xref: /illumos-gate/usr/src/uts/sun4u/opl/sys/drmach.h (revision 4fe85d41)
125cf1a30Sjl /*
225cf1a30Sjl  * CDDL HEADER START
325cf1a30Sjl  *
425cf1a30Sjl  * The contents of this file are subject to the terms of the
525cf1a30Sjl  * Common Development and Distribution License (the "License").
625cf1a30Sjl  * You may not use this file except in compliance with the License.
725cf1a30Sjl  *
825cf1a30Sjl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl  * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl  * See the License for the specific language governing permissions
1125cf1a30Sjl  * and limitations under the License.
1225cf1a30Sjl  *
1325cf1a30Sjl  * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl  * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl  * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl  * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl  *
1925cf1a30Sjl  * CDDL HEADER END
2025cf1a30Sjl  */
2125cf1a30Sjl /*
226534c6f0Swh  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2325cf1a30Sjl  * Use is subject to license terms.
2425cf1a30Sjl  */
2625cf1a30Sjl #ifndef _SYS_DRMACH_H_
2725cf1a30Sjl #define	_SYS_DRMACH_H_
2925cf1a30Sjl #ifdef	__cplusplus
3025cf1a30Sjl extern "C" {
3125cf1a30Sjl #endif
3325cf1a30Sjl #ifndef _ASM
3425cf1a30Sjl #include <sys/types.h>
3525cf1a30Sjl #include <sys/memlist.h>
3625cf1a30Sjl #include <sys/processor.h>
3725cf1a30Sjl #include <sys/cpuvar.h>
3825cf1a30Sjl #include <sys/sbd_ioctl.h>
3925cf1a30Sjl #include <sys/sysevent.h>
4025cf1a30Sjl #include <sys/ddi.h>
4125cf1a30Sjl #include <sys/sunddi.h>
4225cf1a30Sjl #include <sys/sunndi.h>
4325cf1a30Sjl #include <sys/ddi_impldefs.h>
4425cf1a30Sjl #include <sys/pte.h>
4525cf1a30Sjl #include <sys/opl.h>
4625cf1a30Sjl #endif
4925cf1a30Sjl #define	MAX_BOARDS		plat_max_boards()
5025cf1a30Sjl #define	MAX_CPU_UNITS_PER_BOARD	plat_max_cpu_units_per_board()
5125cf1a30Sjl #define	MAX_MEM_UNITS_PER_BOARD	plat_max_mem_units_per_board()
5225cf1a30Sjl #define	MAX_IO_UNITS_PER_BOARD	plat_max_io_units_per_board()
5325cf1a30Sjl #define	MAX_CMP_UNITS_PER_BOARD	plat_max_cmp_units_per_board()
5425cf1a30Sjl /*
5525cf1a30Sjl  * DR uses MAX_CORES_PER_CMP as number of virtual CPU within a CMP
5625cf1a30Sjl  */
6025cf1a30Sjl /* returned with drmach_board_find_devices callback */
6125cf1a30Sjl #define	DRMACH_DEVTYPE_CPU	"cpu"
6225cf1a30Sjl #define	DRMACH_DEVTYPE_MEM	"memory"
6325cf1a30Sjl #define	DRMACH_DEVTYPE_PCI	"pci"
6525cf1a30Sjl #define	FMEM_LOOP_START		1
6625cf1a30Sjl #define	FMEM_LOOP_COPY_READY	2
6725cf1a30Sjl #define	FMEM_LOOP_COPY_DONE	3
6825cf1a30Sjl #define	FMEM_LOOP_FMEM_READY	4
6925cf1a30Sjl #define	FMEM_LOOP_RENAME_DONE	5
7025cf1a30Sjl #define	FMEM_LOOP_DONE		6
7125cf1a30Sjl #define	FMEM_LOOP_EXIT		7
7325cf1a30Sjl #define	SCF_CMD_BUSY		0x8000
7425cf1a30Sjl #define	SCF_STATUS_READY	0x8000
7525cf1a30Sjl #define	SCF_STATUS_SHUTDOWN	0x4000
7625cf1a30Sjl #define	SCF_STATUS_POFF		0x2000
7725cf1a30Sjl #define	SCF_STATUS_EVENT	0x1000
7825cf1a30Sjl #define	SCF_STATUS_TIMER_ADJUST	0x0800
7925cf1a30Sjl #define	SCF_STATUS_ALIVE	0x0400
8025cf1a30Sjl #define	SCF_STATUS_MODE_CHANGED	0x0200
8125cf1a30Sjl #define	SCF_STATUS_CMD_U_PARITY	0x0100
8225cf1a30Sjl #define	SCF_STATUS_CMD_RTN_CODE	0x00f0
8325cf1a30Sjl #define	SCF_STATUS_MODE_SWITCH	0x000c
8425cf1a30Sjl #define	SCF_STATUS_CMD_COMPLETE	0x0002
8525cf1a30Sjl #define	SCF_STATUS_CMD_L_PARITY	0x0001
86*4fe85d41SJames Anderson #define	SCF_STATUS_EX_ONLINE	0x20000000
8825cf1a30Sjl #define	SCF_RETRY_CNT		15
9068ac2337Sjl /*
9168ac2337Sjl  * dynamic memory blocks cannot be added back to phys_install
9268ac2337Sjl  * safely if the alignment is smaller than the largest
9368ac2337Sjl  * physical page size the OS supports.  The VM subsystem
9468ac2337Sjl  * will try to coalesce smaller pages together and
9568ac2337Sjl  * it assumes that the page structures are contiguous.
9668ac2337Sjl  * That assumption does not hold so we have to work around it.
9768ac2337Sjl  * On OPL, the largest page size is 256MB so we can just
9868ac2337Sjl  * add such memory block back.  For everything else,
9968ac2337Sjl  * we round them up to 4MB boundaries and make sure
10068ac2337Sjl  * they are disjoint from phys_install.
10168ac2337Sjl  */
10368ac2337Sjl #define	MH_MPSS_ALIGNMENT	(256 * 1024 * 1024)
10468ac2337Sjl #define	MH_MIN_ALIGNMENT	(4 * 1024 * 1024)
10568ac2337Sjl #define	rounddown(x, y)		((x) & ~(y - 1))
107b307f191Sbm #define	SCF_SB_INFO_OFFSET	0x80020
108b307f191Sbm #define	SCF_SB_INFO_BUSY	0x40
11025cf1a30Sjl #ifndef _ASM
11225cf1a30Sjl /*
11325cf1a30Sjl  * OPL platform specific routines currently only defined
11425cf1a30Sjl  * in opl.c and referenced by DR.
11525cf1a30Sjl  */
11725cf1a30Sjl typedef void *drmachid_t;
11925cf1a30Sjl /*
12068ac2337Sjl  *	There are several requirements to do copy rename:
12168ac2337Sjl  *	1 There should be no subroutine calls/TLBmiss
12268ac2337Sjl  *	  once the copying has begun.
12368ac2337Sjl  *	2 There should be no external memory access by the CPU
12468ac2337Sjl  *	  during the memory rename programming.
12568ac2337Sjl  *
12668ac2337Sjl  *	All data and instruction pages used in the copy rename
12768ac2337Sjl  *	procedure are kept in locked pages to satisfy 1 and 2.
12868ac2337Sjl  *	However that is not enough.  To satisfy 2, we must keep
12968ac2337Sjl  *	all the data and instructions in the 2 assembly routines
13068ac2337Sjl  *	drmach_fmem_loop_script and drmach_fmem_exec_script
13168ac2337Sjl  *	in the same contiguous page.  They are packed into
13268ac2337Sjl  *	the 2nd 8K page of the buffer as shown in the diagram
13368ac2337Sjl  *	below.
13468ac2337Sjl  *
13568ac2337Sjl  *	Note that it is important to keep the "critical"
13668ac2337Sjl  *	data in one 8K page to avoid any cache line
13768ac2337Sjl  *	contention.   The assembly routines read all the
13868ac2337Sjl  *	critical data into the cache so that there is no
13968ac2337Sjl  *	external memory access during FMEM operation.
14025cf1a30Sjl  *
14168ac2337Sjl  *	layout of the FMEM buffers:
14268ac2337Sjl  *	They are all locked in TLB and the critical data
14368ac2337Sjl  *	used in drmach_fmem_xxx assembly code are all
14468ac2337Sjl  *	packed in the second page.
14525cf1a30Sjl  *
14668ac2337Sjl  *	1st 8k page
14768ac2337Sjl  *	+--------------------------------+
14868ac2337Sjl  *	|drmach_copy_rename_program_t    |
14968ac2337Sjl  *	+--------------------------------+
15068ac2337Sjl  *	|drmach_copy_rename_data_t       |
15168ac2337Sjl  *	|                                |
15268ac2337Sjl  *	+--------------------------------+
15368ac2337Sjl  *
15468ac2337Sjl  *	2nd 8k page
15568ac2337Sjl  *	+--------------------------------+
15668ac2337Sjl  *	|drmach_copy_rename_critical_t   |
15768ac2337Sjl  *	|                                |
15868ac2337Sjl  *	+--------------------------------+
15968ac2337Sjl  *	|run (drmach_copy_rename_prog__relocatable)
16068ac2337Sjl  *	|(roundup boundary to 1K)        |
16168ac2337Sjl  *	+--------------------------------+
16268ac2337Sjl  *	| fmem_script                    |
16368ac2337Sjl  *	|(roundup boundary to 1K)        |
16468ac2337Sjl  *	+--------------------------------+
16568ac2337Sjl  *	|loop_script                     |
16668ac2337Sjl  *	|                                |
16768ac2337Sjl  *	+--------------------------------+
16868ac2337Sjl  *	|at least 1K NOP/0's             |
16968ac2337Sjl  *	|                                |
17068ac2337Sjl  *	+--------------------------------+
17168ac2337Sjl  *
17268ac2337Sjl  *	3rd 8k page
17368ac2337Sjl  *	+--------------------------------+
17468ac2337Sjl  *	|memlist_buffer (free_mlist)     |
17568ac2337Sjl  *	|                                |
17668ac2337Sjl  *	+--------------------------------+
17768ac2337Sjl  *
17868ac2337Sjl  *	4th 8k page - drmach_cr_stat_t.
17925cf1a30Sjl  *
18025cf1a30Sjl  */
18225cf1a30Sjl typedef struct {
18325cf1a30Sjl 	int16_t	scf_command;
18425cf1a30Sjl 	int8_t	scf_rsv1[2];
18525cf1a30Sjl 	int16_t	scf_status;
18625cf1a30Sjl 	int8_t	scf_rsv2[2];
18725cf1a30Sjl 	int8_t	scf_version;
18825cf1a30Sjl 	int8_t	scf_rsv3[3];
18925cf1a30Sjl 	int8_t	scf_rsv4[4];
19025cf1a30Sjl 	uint8_t	scf_tdata[16];
19125cf1a30Sjl 	uint8_t	scf_rdata[16];
192*4fe85d41SJames Anderson 	int8_t	scf_rsv5[36];
193*4fe85d41SJames Anderson 	int32_t	scf_status_ex;
19425cf1a30Sjl } drmach_scf_regs_t;
19725cf1a30Sjl typedef struct {
19825cf1a30Sjl 	volatile uint_t	stat;
19925cf1a30Sjl 	volatile uint_t	error;
20025cf1a30Sjl 	int	op;
20125cf1a30Sjl #define	OPL_FMEM_SCF_START 	0x1
20225cf1a30Sjl #define	OPL_FMEM_MC_SUSPEND	0x2
20325cf1a30Sjl } drmach_fmem_mbox_t;
20525cf1a30Sjl typedef struct {
20625cf1a30Sjl 	uint64_t		scf_reg_base;
20725cf1a30Sjl 	uint8_t			scf_td[16];
20825cf1a30Sjl 	uint64_t		save_log[8];
20925cf1a30Sjl 	uint64_t		save_local[8];
21025cf1a30Sjl 	uint64_t		pstate;
21125cf1a30Sjl 	uint64_t		delay;
21225cf1a30Sjl 	int			(*run)(void *arg, int cpuid);
21325cf1a30Sjl 	int			(*fmem)(void *arg, size_t sz);
21425cf1a30Sjl 	int			(*loop)(void *arg1, size_t sz, void *arg2);
21525cf1a30Sjl 	void			(*loop_rtn)(void *arg);
21625cf1a30Sjl 	uint64_t		inst_loop_ret;
21725cf1a30Sjl 	int			fmem_issued;
21825cf1a30Sjl 	volatile uchar_t 	stat[NCPU];
21925cf1a30Sjl } drmach_copy_rename_critical_t;
22125cf1a30Sjl typedef struct {
22225cf1a30Sjl 	uint64_t		s_copybasepa;
22325cf1a30Sjl 	uint64_t		t_copybasepa;
22425cf1a30Sjl 	drmachid_t		s_mem;
22525cf1a30Sjl 	drmachid_t		t_mem;
22625cf1a30Sjl 	cpuset_t		cpu_ready_set;
22725cf1a30Sjl 	cpuset_t		cpu_slave_set;
22825cf1a30Sjl 	cpuset_t		cpu_copy_set;
22925cf1a30Sjl 	processorid_t		cpuid;
23025cf1a30Sjl 	drmach_fmem_mbox_t	fmem_status;
231b307f191Sbm 	volatile ushort_t 	error[NCPU];
23225cf1a30Sjl 	struct memlist		*c_ml;
23325cf1a30Sjl 	struct memlist		*cpu_ml[NCPU];
23425cf1a30Sjl 	void			(*mc_resume)(void);
23525cf1a30Sjl 	int			(*scf_fmem_end)(void);
23625cf1a30Sjl 	int			(*scf_fmem_cancel)(void);
23768ac2337Sjl 	uint64_t		(*scf_get_base_addr)(void);
23825cf1a30Sjl 	uint64_t		copy_delay;
23925cf1a30Sjl 	uint64_t		stick_freq;
24025cf1a30Sjl 	uint64_t		copy_wait_time;
24125cf1a30Sjl 	processorid_t		slowest_cpuid;
2426534c6f0Swh 	int			copy_rename_count;
24325cf1a30Sjl } drmach_copy_rename_data_t;
24525cf1a30Sjl typedef struct {
24625cf1a30Sjl 	uint64_t	nbytes[NCPU];
24725cf1a30Sjl } drmach_cr_stat_t;
24968ac2337Sjl typedef struct drmach_copy_rename_program {
25068ac2337Sjl 	drmach_copy_rename_critical_t		*critical;
25168ac2337Sjl 	struct drmach_copy_rename_program	*locked_prog;
25268ac2337Sjl 	struct drmach_copy_rename_program	*prog;
25368ac2337Sjl 	drmach_copy_rename_data_t		*data;
25468ac2337Sjl 	caddr_t					memlist_buffer;
25568ac2337Sjl 	struct memlist				*free_mlist;
25668ac2337Sjl 	drmach_cr_stat_t			*stat;
25725cf1a30Sjl } drmach_copy_rename_program_t;
25925cf1a30Sjl #define	DRMACH_FMEM_LOCKED_PAGES	4
26025cf1a30Sjl #define	DRMACH_FMEM_DATA_PAGE		0
26125cf1a30Sjl #define	DRMACH_FMEM_CRITICAL_PAGE	1
26225cf1a30Sjl #define	DRMACH_FMEM_MLIST_PAGE		2
26325cf1a30Sjl #define	DRMACH_FMEM_STAT_PAGE		3
26525cf1a30Sjl typedef struct {
26625cf1a30Sjl 	boolean_t	assigned;
26725cf1a30Sjl 	boolean_t	powered;
26825cf1a30Sjl 	boolean_t	configured;
26925cf1a30Sjl 	boolean_t	busy;
27025cf1a30Sjl 	boolean_t	empty;
27125cf1a30Sjl 	sbd_cond_t	cond;
27225cf1a30Sjl 	char		type[MAXNAMELEN];
27325cf1a30Sjl 	char		info[MAXPATHLEN];	/* TODO: what size? */
27425cf1a30Sjl } drmach_status_t;
27625cf1a30Sjl typedef struct {
27725cf1a30Sjl 	int	size;
27825cf1a30Sjl 	char	*copts;
27925cf1a30Sjl } drmach_opts_t;
28125cf1a30Sjl typedef struct {
28225cf1a30Sjl 	uint64_t mi_basepa;
28325cf1a30Sjl 	uint64_t mi_size;
28425cf1a30Sjl 	uint64_t mi_slice_size;
28525cf1a30Sjl 	uint64_t mi_alignment_mask;
28625cf1a30Sjl } drmach_mem_info_t;
28825cf1a30Sjl extern sbd_error_t	*drmach_mem_get_info(drmachid_t, drmach_mem_info_t *);
28925cf1a30Sjl extern int		drmach_board_is_floating(drmachid_t);
29125cf1a30Sjl extern sbd_error_t	*drmach_copy_rename_init(
29225cf1a30Sjl 				drmachid_t dst_id,
29325cf1a30Sjl 				drmachid_t src_id, struct memlist *src_copy_ml,
29425cf1a30Sjl 				drmachid_t *pgm_id);
29525cf1a30Sjl extern sbd_error_t	*drmach_copy_rename_fini(drmachid_t id);
29625cf1a30Sjl extern void		 drmach_copy_rename(drmachid_t id);
29825cf1a30Sjl extern sbd_error_t	*drmach_pre_op(int cmd, drmachid_t id,
29925cf1a30Sjl 						drmach_opts_t *opts);
30025cf1a30Sjl extern sbd_error_t	*drmach_post_op(int cmd, drmachid_t id,
30125cf1a30Sjl 						drmach_opts_t *opts);
30325cf1a30Sjl extern sbd_error_t	*drmach_board_assign(int bnum, drmachid_t *id);
30425cf1a30Sjl extern sbd_error_t	*drmach_board_connect(drmachid_t id,
30525cf1a30Sjl 						drmach_opts_t *opts);
30625cf1a30Sjl extern sbd_error_t	*drmach_board_deprobe(drmachid_t id);
30725cf1a30Sjl extern sbd_error_t	*drmach_board_disconnect(drmachid_t id,
30825cf1a30Sjl 						drmach_opts_t *opts);
30925cf1a30Sjl extern sbd_error_t	*drmach_board_find_devices(drmachid_t id, void *a,
31025cf1a30Sjl 		sbd_error_t *(*found)(void *a, const char *, int, drmachid_t));
31125cf1a30Sjl extern int		drmach_board_lookup(int bnum, drmachid_t *id);
31225cf1a30Sjl extern sbd_error_t	*drmach_passthru(drmachid_t id,
31325cf1a30Sjl 						drmach_opts_t *opts);
31525cf1a30Sjl extern sbd_error_t	*drmach_board_name(int bnum, char *buf, int buflen);
31725cf1a30Sjl extern sbd_error_t	*drmach_board_poweroff(drmachid_t id);
31825cf1a30Sjl extern sbd_error_t	*drmach_board_poweron(drmachid_t id);
31925cf1a30Sjl extern sbd_error_t	*drmach_board_test(drmachid_t id, drmach_opts_t *opts,
32025cf1a30Sjl 				int force);
32225cf1a30Sjl extern sbd_error_t	*drmach_board_unassign(drmachid_t id);
32425cf1a30Sjl extern sbd_error_t	*drmach_configure(drmachid_t id, int flags);
32625cf1a30Sjl extern sbd_error_t	*drmach_cpu_disconnect(drmachid_t id);
32725cf1a30Sjl extern sbd_error_t	*drmach_cpu_get_id(drmachid_t id, processorid_t *cpuid);
32825cf1a30Sjl extern sbd_error_t	*drmach_cpu_get_impl(drmachid_t id, int *ip);
32925cf1a30Sjl extern void		 drmach_cpu_flush_ecache_sync(void);
33125cf1a30Sjl extern sbd_error_t	*drmach_get_dip(drmachid_t id, dev_info_t **dip);
33325cf1a30Sjl extern sbd_error_t	*drmach_io_is_attached(drmachid_t id, int *yes);
33425cf1a30Sjl extern sbd_error_t	*drmach_io_post_attach(drmachid_t id);
33525cf1a30Sjl extern sbd_error_t	*drmach_io_post_release(drmachid_t id);
33625cf1a30Sjl extern sbd_error_t	*drmach_io_pre_release(drmachid_t id);
33725cf1a30Sjl extern sbd_error_t	*drmach_io_unrelease(drmachid_t id);
33925cf1a30Sjl extern sbd_error_t	*drmach_mem_add_span(drmachid_t id,
34025cf1a30Sjl 				uint64_t basepa, uint64_t size);
34125cf1a30Sjl extern sbd_error_t	*drmach_mem_del_span(drmachid_t id,
34225cf1a30Sjl 				uint64_t basepa, uint64_t size);
34325cf1a30Sjl extern sbd_error_t	*drmach_mem_disable(drmachid_t id);
34425cf1a30Sjl extern sbd_error_t	*drmach_mem_enable(drmachid_t id);
34525cf1a30Sjl extern sbd_error_t	*drmach_mem_get_base_physaddr(drmachid_t id,
34625cf1a30Sjl 				uint64_t *pa);
34725cf1a30Sjl extern sbd_error_t	*drmach_mem_get_memlist(drmachid_t id,
34825cf1a30Sjl 				struct memlist **ml);
34925cf1a30Sjl extern sbd_error_t	*drmach_mem_get_slice_size(drmachid_t, uint64_t *);
35125cf1a30Sjl extern sbd_error_t	*drmach_release(drmachid_t id);
35225cf1a30Sjl extern sbd_error_t	*drmach_status(drmachid_t id, drmach_status_t *stat);
35325cf1a30Sjl extern sbd_error_t	*drmach_unconfigure(drmachid_t id, int flags);
35425cf1a30Sjl extern int		drmach_log_sysevent(int board, char *hint, int flag,
35525cf1a30Sjl 					    int verbose);
35725cf1a30Sjl extern int		drmach_verify_sr(dev_info_t *dip, int sflag);
35825cf1a30Sjl extern void		drmach_suspend_last();
35925cf1a30Sjl extern void		drmach_resume_first();
36125cf1a30Sjl #endif
36325cf1a30Sjl #ifdef __cplusplus
36425cf1a30Sjl }
36525cf1a30Sjl #endif
36725cf1a30Sjl #endif /* _SYS_DRMACH_H_ */