125cf1a30Sjl /*
225cf1a30Sjl  * CDDL HEADER START
325cf1a30Sjl  *
425cf1a30Sjl  * The contents of this file are subject to the terms of the
525cf1a30Sjl  * Common Development and Distribution License (the "License").
625cf1a30Sjl  * You may not use this file except in compliance with the License.
725cf1a30Sjl  *
825cf1a30Sjl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl  * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl  * See the License for the specific language governing permissions
1125cf1a30Sjl  * and limitations under the License.
1225cf1a30Sjl  *
1325cf1a30Sjl  * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl  * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl  * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl  * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl  *
1925cf1a30Sjl  * CDDL HEADER END
2025cf1a30Sjl  */
21*07d06da5SSurya Prakki 
2225cf1a30Sjl /*
23*07d06da5SSurya Prakki  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
2425cf1a30Sjl  * Use is subject to license terms.
2525cf1a30Sjl  */
2725cf1a30Sjl /*
2825cf1a30Sjl  * CMU-CH Interrupt Block
2925cf1a30Sjl  */
3125cf1a30Sjl #include <sys/types.h>
3225cf1a30Sjl #include <sys/kmem.h>
3325cf1a30Sjl #include <sys/async.h>
3425cf1a30Sjl #include <sys/systm.h>
3525cf1a30Sjl #include <sys/spl.h>
3625cf1a30Sjl #include <sys/sunddi.h>
3725cf1a30Sjl #include <sys/machsystm.h>
3825cf1a30Sjl #include <sys/ddi_impldefs.h>
3925cf1a30Sjl #include <sys/pcicmu/pcicmu.h>
4125cf1a30Sjl static uint_t pcmu_ib_intr_reset(void *arg);
4325cf1a30Sjl extern uint64_t	xc_tick_jump_limit;
4525cf1a30Sjl void
pcmu_ib_create(pcmu_t * pcmu_p)4625cf1a30Sjl pcmu_ib_create(pcmu_t *pcmu_p)
4725cf1a30Sjl {
4825cf1a30Sjl 	pcmu_ib_t *pib_p;
4925cf1a30Sjl 	uintptr_t a;
5025cf1a30Sjl 	int i;
5225cf1a30Sjl 	/*
5325cf1a30Sjl 	 * Allocate interrupt block state structure and link it to
5425cf1a30Sjl 	 * the pci state structure.
5525cf1a30Sjl 	 */
5625cf1a30Sjl 	pib_p = kmem_zalloc(sizeof (pcmu_ib_t), KM_SLEEP);
5725cf1a30Sjl 	pcmu_p->pcmu_ib_p = pib_p;
5825cf1a30Sjl 	pib_p->pib_pcmu_p = pcmu_p;
6025cf1a30Sjl 	a = pcmu_ib_setup(pib_p);
6225cf1a30Sjl 	/*
6325cf1a30Sjl 	 * Determine virtual addresses of interrupt mapping, clear and diag
6425cf1a30Sjl 	 * registers that have common offsets.
6525cf1a30Sjl 	 */
6625cf1a30Sjl 	pib_p->pib_intr_retry_timer_reg =
67116f7629Sjfrank 	    (uint64_t *)(a + PCMU_IB_INTR_RETRY_TIMER_OFFSET);
6825cf1a30Sjl 	pib_p->pib_obio_intr_state_diag_reg =
69116f7629Sjfrank 	    (uint64_t *)(a + PCMU_IB_OBIO_INTR_STATE_DIAG_REG);
7125cf1a30Sjl 	PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
7225cf1a30Sjl 	    "pcmu_ib_create: obio_imr=%x, obio_cir=%x\n",
7325cf1a30Sjl 	    pib_p->pib_obio_intr_map_regs, pib_p->pib_obio_clear_intr_regs);
7425cf1a30Sjl 	PCMU_DBG2(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
7525cf1a30Sjl 	    "pcmu_ib_create: retry_timer=%x, obio_diag=%x\n",
7625cf1a30Sjl 	    pib_p->pib_intr_retry_timer_reg,
7725cf1a30Sjl 	    pib_p->pib_obio_intr_state_diag_reg);
7925cf1a30Sjl 	pib_p->pib_ino_lst = (pcmu_ib_ino_info_t *)NULL;
8025cf1a30Sjl 	mutex_init(&pib_p->pib_intr_lock, NULL, MUTEX_DRIVER, NULL);
8125cf1a30Sjl 	mutex_init(&pib_p->pib_ino_lst_mutex, NULL, MUTEX_DRIVER, NULL);
8325cf1a30Sjl 	PCMU_DBG1(PCMU_DBG_ATTACH, pcmu_p->pcmu_dip,
8425cf1a30Sjl 	    "pcmu_ib_create: numproxy=%x\n", pcmu_p->pcmu_numproxy);
8525cf1a30Sjl 	for (i = 1; i <= pcmu_p->pcmu_numproxy; i++) {
8625cf1a30Sjl 		set_intr_mapping_reg(pcmu_p->pcmu_id,
87116f7629Sjfrank 		    (uint64_t *)pib_p->pib_upa_imr[i - 1], i);
8825cf1a30Sjl 	}
9025cf1a30Sjl 	pcmu_ib_configure(pib_p);
9125cf1a30Sjl 	bus_func_register(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p);
9225cf1a30Sjl }
9425cf1a30Sjl void
pcmu_ib_destroy(pcmu_t * pcmu_p)9525cf1a30Sjl pcmu_ib_destroy(pcmu_t *pcmu_p)
9625cf1a30Sjl {
9725cf1a30Sjl 	pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
9925cf1a30Sjl 	PCMU_DBG0(PCMU_DBG_IB, pcmu_p->pcmu_dip, "pcmu_ib_destroy\n");
10025cf1a30Sjl 	bus_func_unregister(BF_TYPE_RESINTR, pcmu_ib_intr_reset, pib_p);
10225cf1a30Sjl 	intr_dist_rem_weighted(pcmu_ib_intr_dist_all, pib_p);
10325cf1a30Sjl 	mutex_destroy(&pib_p->pib_ino_lst_mutex);
10425cf1a30Sjl 	mutex_destroy(&pib_p->pib_intr_lock);
10625cf1a30Sjl 	pcmu_ib_free_ino_all(pib_p);
10825cf1a30Sjl 	kmem_free(pib_p, sizeof (pcmu_ib_t));
10925cf1a30Sjl 	pcmu_p->pcmu_ib_p = NULL;
11025cf1a30Sjl }
11225cf1a30Sjl void
pcmu_ib_configure(pcmu_ib_t * pib_p)11325cf1a30Sjl pcmu_ib_configure(pcmu_ib_t *pib_p)
11425cf1a30Sjl {
11525cf1a30Sjl 	*pib_p->pib_intr_retry_timer_reg = pcmu_intr_retry_intv;
11625cf1a30Sjl }
11825cf1a30Sjl /*
11925cf1a30Sjl  * can only used for CMU-CH internal interrupts ue, pbm
12025cf1a30Sjl  */
12125cf1a30Sjl void
pcmu_ib_intr_enable(pcmu_t * pcmu_p,pcmu_ib_ino_t ino)12225cf1a30Sjl pcmu_ib_intr_enable(pcmu_t *pcmu_p, pcmu_ib_ino_t ino)
12325cf1a30Sjl {
12425cf1a30Sjl 	pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
12525cf1a30Sjl 	pcmu_ib_mondo_t mondo = PCMU_IB_INO_TO_MONDO(pib_p, ino);
12625cf1a30Sjl 	volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino);
12725cf1a30Sjl 	uint_t cpu_id;
12925cf1a30Sjl 	/*
13025cf1a30Sjl 	 * Determine the cpu for the interrupt.
13125cf1a30Sjl 	 */
13225cf1a30Sjl 	mutex_enter(&pib_p->pib_intr_lock);
13325cf1a30Sjl 	cpu_id = intr_dist_cpuid();
13425cf1a30Sjl 	cpu_id = u2u_translate_tgtid(pcmu_p, cpu_id, imr_p);
13525cf1a30Sjl 	PCMU_DBG2(PCMU_DBG_IB, pcmu_p->pcmu_dip,
13625cf1a30Sjl 	    "pcmu_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id);
13825cf1a30Sjl 	*imr_p = ib_get_map_reg(mondo, cpu_id);
13925cf1a30Sjl 	PCMU_IB_INO_INTR_CLEAR(ib_clear_intr_reg_addr(pib_p, ino));
14025cf1a30Sjl 	mutex_exit(&pib_p->pib_intr_lock);
14125cf1a30Sjl }
14325cf1a30Sjl /*
14425cf1a30Sjl  * Disable the interrupt via its interrupt mapping register.
14525cf1a30Sjl  * Can only be used for internal interrupts: ue, pbm.
14625cf1a30Sjl  * If called under interrupt context, wait should be set to 0
14725cf1a30Sjl  */
14825cf1a30Sjl void
pcmu_ib_intr_disable(pcmu_ib_t * pib_p,pcmu_ib_ino_t ino,int wait)14925cf1a30Sjl pcmu_ib_intr_disable(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino, int wait)
15025cf1a30Sjl {
15125cf1a30Sjl 	volatile uint64_t *imr_p = ib_intr_map_reg_addr(pib_p, ino);
15225cf1a30Sjl 	volatile uint64_t *state_reg_p = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
15325cf1a30Sjl 	hrtime_t start_time;
15425cf1a30Sjl 	hrtime_t prev, curr, interval, jump;
15525cf1a30Sjl 	hrtime_t intr_timeout;
15725cf1a30Sjl 	/* disable the interrupt */
15825cf1a30Sjl 	mutex_enter(&pib_p->pib_intr_lock);
15925cf1a30Sjl 	PCMU_IB_INO_INTR_OFF(imr_p);
16025cf1a30Sjl 	*imr_p;	/* flush previous write */
16125cf1a30Sjl 	mutex_exit(&pib_p->pib_intr_lock);
16325cf1a30Sjl 	if (!wait)
16425cf1a30Sjl 		goto wait_done;
16625cf1a30Sjl 	intr_timeout = pcmu_intrpend_timeout;
16725cf1a30Sjl 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
16825cf1a30Sjl 	start_time = curr = gethrtime();
16925cf1a30Sjl 	/* busy wait if there is interrupt being processed */
17025cf1a30Sjl 	while (PCMU_IB_INO_INTR_PENDING(state_reg_p, ino) && !panicstr) {
17125cf1a30Sjl 		/*
17225cf1a30Sjl 		 * If we have a really large jump in hrtime, it is most
17325cf1a30Sjl 		 * probably because we entered the debugger (or OBP,
17425cf1a30Sjl 		 * in general). So, we adjust the timeout accordingly
17525cf1a30Sjl 		 * to prevent declaring an interrupt timeout. The
17625cf1a30Sjl 		 * master-interrupt mechanism in OBP should deliver
17725cf1a30Sjl 		 * the interrupts properly.
17825cf1a30Sjl 		 */
17925cf1a30Sjl 		prev = curr;
18025cf1a30Sjl 		curr = gethrtime();
18125cf1a30Sjl 		interval = curr - prev;
18225cf1a30Sjl 		if (interval > jump)
18325cf1a30Sjl 			intr_timeout += interval;
18425cf1a30Sjl 		if (curr - start_time > intr_timeout) {
18525cf1a30Sjl 			pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p;
18625cf1a30Sjl 			cmn_err(CE_WARN,
18725cf1a30Sjl 			    "%s:%s: pcmu_ib_intr_disable timeout %x",
18825cf1a30Sjl 			    pcbm_p->pcbm_nameinst_str,
18925cf1a30Sjl 			    pcbm_p->pcbm_nameaddr_str, ino);
19025cf1a30Sjl 			break;
19125cf1a30Sjl 		}
19225cf1a30Sjl 	}
19325cf1a30Sjl wait_done:
19425cf1a30Sjl 	PCMU_IB_INO_INTR_PEND(ib_clear_intr_reg_addr(pib_p, ino));
19525cf1a30Sjl 	u2u_ittrans_cleanup((u2u_ittrans_data_t *)
19625cf1a30Sjl 	    (PCMU_IB2CB(pib_p)->pcb_ittrans_cookie), imr_p);
19725cf1a30Sjl }
19925cf1a30Sjl /* can only used for CMU-CH internal interrupts ue, pbm */
20025cf1a30Sjl void
pcmu_ib_nintr_clear(pcmu_ib_t * pib_p,pcmu_ib_ino_t ino)20125cf1a30Sjl pcmu_ib_nintr_clear(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino)
20225cf1a30Sjl {
20325cf1a30Sjl 	uint64_t *clr_reg = ib_clear_intr_reg_addr(pib_p, ino);
20425cf1a30Sjl 	PCMU_IB_INO_INTR_CLEAR(clr_reg);
20525cf1a30Sjl }
20725cf1a30Sjl /*
20825cf1a30Sjl  * distribute PBM and UPA interrupts. ino is set to 0 by caller if we
20925cf1a30Sjl  * are dealing with UPA interrupts (without inos).
21025cf1a30Sjl  */
21125cf1a30Sjl void
pcmu_ib_intr_dist_nintr(pcmu_ib_t * pib_p,pcmu_ib_ino_t ino,volatile uint64_t * imr_p)21225cf1a30Sjl pcmu_ib_intr_dist_nintr(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino,
21325cf1a30Sjl     volatile uint64_t *imr_p)
21425cf1a30Sjl {
21525cf1a30Sjl 	volatile uint64_t imr = *imr_p;
21625cf1a30Sjl 	uint32_t cpu_id;
21825cf1a30Sjl 	if (!PCMU_IB_INO_INTR_ISON(imr))
21925cf1a30Sjl 		return;
22125cf1a30Sjl 	cpu_id = intr_dist_cpuid();
22325cf1a30Sjl 	if (ino) {
22425cf1a30Sjl 		cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p);
22525cf1a30Sjl 	}
22725cf1a30Sjl 	if (ib_map_reg_get_cpu(*imr_p) == cpu_id) {
22825cf1a30Sjl 		return;
22925cf1a30Sjl 	}
23025cf1a30Sjl 	*imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id);
23125cf1a30Sjl 	imr = *imr_p;	/* flush previous write */
23225cf1a30Sjl }
23425cf1a30Sjl static void
pcmu_ib_intr_dist(pcmu_ib_t * pib_p,pcmu_ib_ino_info_t * ino_p)23525cf1a30Sjl pcmu_ib_intr_dist(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p)
23625cf1a30Sjl {
23725cf1a30Sjl 	uint32_t cpu_id = ino_p->pino_cpuid;
23825cf1a30Sjl 	pcmu_ib_ino_t ino = ino_p->pino_ino;
23925cf1a30Sjl 	volatile uint64_t imr, *imr_p, *state_reg;
24025cf1a30Sjl 	hrtime_t start_time;
24125cf1a30Sjl 	hrtime_t prev, curr, interval, jump;
24225cf1a30Sjl 	hrtime_t intr_timeout;
24425cf1a30Sjl 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
24525cf1a30Sjl 	imr_p = ib_intr_map_reg_addr(pib_p, ino);
24625cf1a30Sjl 	state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
24825cf1a30Sjl 	/* disable interrupt, this could disrupt devices sharing our slot */
24925cf1a30Sjl 	PCMU_IB_INO_INTR_OFF(imr_p);
25025cf1a30Sjl 	imr = *imr_p;	/* flush previous write */
25225cf1a30Sjl 	/* busy wait if there is interrupt being processed */
25325cf1a30Sjl 	intr_timeout = pcmu_intrpend_timeout;
25425cf1a30Sjl 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
25525cf1a30Sjl 	start_time = curr = gethrtime();
25625cf1a30Sjl 	while (PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
25725cf1a30Sjl 		/*
25825cf1a30Sjl 		 * If we have a really large jump in hrtime, it is most
25925cf1a30Sjl 		 * probably because we entered the debugger (or OBP,
26025cf1a30Sjl 		 * in general). So, we adjust the timeout accordingly
26125cf1a30Sjl 		 * to prevent declaring an interrupt timeout. The
26225cf1a30Sjl 		 * master-interrupt mechanism in OBP should deliver
26325cf1a30Sjl 		 * the interrupts properly.
26425cf1a30Sjl 		 */
26525cf1a30Sjl 		prev = curr;
26625cf1a30Sjl 		curr = gethrtime();
26725cf1a30Sjl 		interval = curr - prev;
26825cf1a30Sjl 		if (interval > jump)
26925cf1a30Sjl 			intr_timeout += interval;
27025cf1a30Sjl 		if (curr - start_time > intr_timeout) {
27125cf1a30Sjl 			pcmu_pbm_t *pcbm_p = pib_p->pib_pcmu_p->pcmu_pcbm_p;
27225cf1a30Sjl 			cmn_err(CE_WARN,
27325cf1a30Sjl 			    "%s:%s: pcmu_ib_intr_dist(%p,%x) timeout",
27425cf1a30Sjl 			    pcbm_p->pcbm_nameinst_str,
27525cf1a30Sjl 			    pcbm_p->pcbm_nameaddr_str,
276*07d06da5SSurya Prakki 			    (void *)imr_p, PCMU_IB_INO_TO_MONDO(pib_p, ino));
27725cf1a30Sjl 			break;
27825cf1a30Sjl 		}
27925cf1a30Sjl 	}
28025cf1a30Sjl 	cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p);
28125cf1a30Sjl 	*imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id);
28225cf1a30Sjl 	imr = *imr_p;	/* flush previous write */
28325cf1a30Sjl }
28525cf1a30Sjl /*
28625cf1a30Sjl  * Redistribute interrupts of the specified weight. The first call has a weight
28725cf1a30Sjl  * of weight_max, which can be used to trigger initialization for
28825cf1a30Sjl  * redistribution. The inos with weight [weight_max, inf.) should be processed
28925cf1a30Sjl  * on the "weight == weight_max" call.  This first call is followed by calls
29025cf1a30Sjl  * of decreasing weights, inos of that weight should be processed.  The final
29125cf1a30Sjl  * call specifies a weight of zero, this can be used to trigger processing of
29225cf1a30Sjl  * stragglers.
29325cf1a30Sjl  */
29425cf1a30Sjl void
pcmu_ib_intr_dist_all(void * arg,int32_t weight_max,int32_t weight)29525cf1a30Sjl pcmu_ib_intr_dist_all(void *arg, int32_t weight_max, int32_t weight)
29625cf1a30Sjl {
29725cf1a30Sjl 	pcmu_ib_t *pib_p = (pcmu_ib_t *)arg;
29825cf1a30Sjl 	pcmu_ib_ino_info_t *ino_p;
29925cf1a30Sjl 	ih_t *ih_lst;
30025cf1a30Sjl 	int32_t dweight;
30125cf1a30Sjl 	int i;
30325cf1a30Sjl 	mutex_enter(&pib_p->pib_ino_lst_mutex);
30525cf1a30Sjl 	/* Perform special processing for first call of a redistribution. */
30625cf1a30Sjl 	if (weight == weight_max) {
30725cf1a30Sjl 		for (ino_p = pib_p->pib_ino_lst; ino_p;
30825cf1a30Sjl 		    ino_p = ino_p->pino_next) {
31025cf1a30Sjl 			/*
31125cf1a30Sjl 			 * Clear pino_established of each ino on first call.
31225cf1a30Sjl 			 * The pino_established field may be used by a pci
31325cf1a30Sjl 			 * nexus driver's pcmu_intr_dist_cpuid implementation
31425cf1a30Sjl 			 * when detection of established pci slot-cpu binding
31525cf1a30Sjl 			 * for multi function pci cards.
31625cf1a30Sjl 			 */
31725cf1a30Sjl 			ino_p->pino_established = 0;
31925cf1a30Sjl 			/*
32025cf1a30Sjl 			 * recompute the pino_intr_weight based on the device
32125cf1a30Sjl 			 * weight of all devinfo nodes sharing the ino (this
32225cf1a30Sjl 			 * will allow us to pick up new weights established by
32325cf1a30Sjl 			 * i_ddi_set_intr_weight()).
32425cf1a30Sjl 			 */
32525cf1a30Sjl 			ino_p->pino_intr_weight = 0;
32625cf1a30Sjl 			for (i = 0, ih_lst = ino_p->pino_ih_head;
32725cf1a30Sjl 			    i < ino_p->pino_ih_size;
32825cf1a30Sjl 			    i++, ih_lst = ih_lst->ih_next) {
32925cf1a30Sjl 				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
33025cf1a30Sjl 				if (dweight > 0)
33125cf1a30Sjl 					ino_p->pino_intr_weight += dweight;
33225cf1a30Sjl 			}
33325cf1a30Sjl 		}
33425cf1a30Sjl 	}
33625cf1a30Sjl 	for (ino_p = pib_p->pib_ino_lst; ino_p; ino_p = ino_p->pino_next) {
33725cf1a30Sjl 		/*
33825cf1a30Sjl 		 * Get the weight of the ino and determine if we are going to
33925cf1a30Sjl 		 * process call.  We wait until an pcmu_ib_intr_dist_all call of
34025cf1a30Sjl 		 * the proper weight occurs to support redistribution of all
34125cf1a30Sjl 		 * heavy weighted interrupts first (across all nexus driver
34225cf1a30Sjl 		 * instances).  This is done to ensure optimal
34325cf1a30Sjl 		 * INTR_WEIGHTED_DIST behavior.
34425cf1a30Sjl 		 */
34525cf1a30Sjl 		if ((weight == ino_p->pino_intr_weight) ||
34625cf1a30Sjl 		    ((weight >= weight_max) &&
34725cf1a30Sjl 		    (ino_p->pino_intr_weight >= weight_max))) {
34825cf1a30Sjl 			/* select cpuid to target and mark ino established */
34925cf1a30Sjl 			ino_p->pino_cpuid = pcmu_intr_dist_cpuid(pib_p, ino_p);
35025cf1a30Sjl 			ino_p->pino_established = 1;
35225cf1a30Sjl 			/* Add device weight of ino devinfos to targeted cpu. */
35325cf1a30Sjl 			for (i = 0, ih_lst = ino_p->pino_ih_head;
35425cf1a30Sjl 			    i < ino_p->pino_ih_size;
35525cf1a30Sjl 			    i++, ih_lst = ih_lst->ih_next) {
35625cf1a30Sjl 				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
35725cf1a30Sjl 				intr_dist_cpuid_add_device_weight(
35825cf1a30Sjl 				    ino_p->pino_cpuid, ih_lst->ih_dip, dweight);
35925cf1a30Sjl 			}
36125cf1a30Sjl 			/* program the hardware */
36225cf1a30Sjl 			pcmu_ib_intr_dist(pib_p, ino_p);
36325cf1a30Sjl 		}
36425cf1a30Sjl 	}
36525cf1a30Sjl 	mutex_exit(&pib_p->pib_ino_lst_mutex);
36625cf1a30Sjl }
36825cf1a30Sjl /*
36925cf1a30Sjl  * Reset interrupts to IDLE.  This function is called during
37025cf1a30Sjl  * panic handling after redistributing interrupts; it's needed to
37125cf1a30Sjl  * support dumping to network devices after 'sync' from OBP.
37225cf1a30Sjl  *
37325cf1a30Sjl  * N.B.  This routine runs in a context where all other threads
37425cf1a30Sjl  * are permanently suspended.
37525cf1a30Sjl  */
37625cf1a30Sjl static uint_t
pcmu_ib_intr_reset(void * arg)37725cf1a30Sjl pcmu_ib_intr_reset(void *arg)
37825cf1a30Sjl {
37925cf1a30Sjl 	pcmu_ib_t *pib_p = (pcmu_ib_t *)arg;
38025cf1a30Sjl 	pcmu_ib_ino_t ino;
38125cf1a30Sjl 	uint64_t *clr_reg;
38325cf1a30Sjl 	/*
38425cf1a30Sjl 	 * Note that we only actually care about interrupts that are
38525cf1a30Sjl 	 * potentially from network devices.
38625cf1a30Sjl 	 */
38725cf1a30Sjl 	for (ino = 0; ino <= pib_p->pib_max_ino; ino++) {
38825cf1a30Sjl 		clr_reg = ib_clear_intr_reg_addr(pib_p, ino);
38925cf1a30Sjl 		PCMU_IB_INO_INTR_CLEAR(clr_reg);
39025cf1a30Sjl 	}
39125cf1a30Sjl 	return (BF_NONE);
39225cf1a30Sjl }
39425cf1a30Sjl void
pcmu_ib_suspend(pcmu_ib_t * pib_p)39525cf1a30Sjl pcmu_ib_suspend(pcmu_ib_t *pib_p)
39625cf1a30Sjl {
39725cf1a30Sjl 	pcmu_ib_ino_info_t *ip;
39925cf1a30Sjl 	/* save ino_lst interrupts' mapping registers content */
40025cf1a30Sjl 	mutex_enter(&pib_p->pib_ino_lst_mutex);
40125cf1a30Sjl 	for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) {
40225cf1a30Sjl 		ip->pino_map_reg_save = *ip->pino_map_reg;
40325cf1a30Sjl 	}
40425cf1a30Sjl 	mutex_exit(&pib_p->pib_ino_lst_mutex);
40525cf1a30Sjl }
40725cf1a30Sjl void
pcmu_ib_resume(pcmu_ib_t * pib_p)40825cf1a30Sjl pcmu_ib_resume(pcmu_ib_t *pib_p)
40925cf1a30Sjl {
41025cf1a30Sjl 	pcmu_ib_ino_info_t *ip;
41225cf1a30Sjl 	/* restore ino_lst interrupts' mapping registers content */
41325cf1a30Sjl 	mutex_enter(&pib_p->pib_ino_lst_mutex);
41425cf1a30Sjl 	for (ip = pib_p->pib_ino_lst; ip; ip = ip->pino_next) {
41525cf1a30Sjl 		PCMU_IB_INO_INTR_CLEAR(ip->pino_clr_reg); /* set intr to idle */
41625cf1a30Sjl 		*ip->pino_map_reg = ip->pino_map_reg_save; /* restore IMR */
41725cf1a30Sjl 	}
41825cf1a30Sjl 	mutex_exit(&pib_p->pib_ino_lst_mutex);
41925cf1a30Sjl }
42125cf1a30Sjl /*
42225cf1a30Sjl  * locate ino_info structure on pib_p->pib_ino_lst according to ino#
42325cf1a30Sjl  * returns NULL if not found.
42425cf1a30Sjl  */
42525cf1a30Sjl pcmu_ib_ino_info_t *
pcmu_ib_locate_ino(pcmu_ib_t * pib_p,pcmu_ib_ino_t ino_num)42625cf1a30Sjl pcmu_ib_locate_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num)
42725cf1a30Sjl {
42825cf1a30Sjl 	pcmu_ib_ino_info_t *ino_p = pib_p->pib_ino_lst;
42925cf1a30Sjl 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
431116f7629Sjfrank 	for (; ino_p && ino_p->pino_ino != ino_num; ino_p = ino_p->pino_next)
432116f7629Sjfrank 		;
43325cf1a30Sjl 	return (ino_p);
43425cf1a30Sjl }
43625cf1a30Sjl #define	PCMU_IB_INO_TO_SLOT(ino)		\
43725cf1a30Sjl 	(PCMU_IB_IS_OBIO_INO(ino) ? 0xff : ((ino) & 0x1f) >> 2)
43925cf1a30Sjl pcmu_ib_ino_info_t *
pcmu_ib_new_ino(pcmu_ib_t * pib_p,pcmu_ib_ino_t ino_num,ih_t * ih_p)44025cf1a30Sjl pcmu_ib_new_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num, ih_t *ih_p)
44125cf1a30Sjl {
44225cf1a30Sjl 	pcmu_ib_ino_info_t *ino_p = kmem_alloc(sizeof (pcmu_ib_ino_info_t),
44325cf1a30Sjl 	    KM_SLEEP);
44425cf1a30Sjl 	ino_p->pino_ino = ino_num;
44525cf1a30Sjl 	ino_p->pino_slot_no = PCMU_IB_INO_TO_SLOT(ino_num);
44625cf1a30Sjl 	ino_p->pino_ib_p = pib_p;
44725cf1a30Sjl 	ino_p->pino_clr_reg = ib_clear_intr_reg_addr(pib_p, ino_num);
44825cf1a30Sjl 	ino_p->pino_map_reg = ib_intr_map_reg_addr(pib_p, ino_num);
44925cf1a30Sjl 	ino_p->pino_unclaimed = 0;
45125cf1a30Sjl 	/*
45225cf1a30Sjl 	 * cannot disable interrupt since we might share slot
45325cf1a30Sjl 	 * PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
45425cf1a30Sjl 	 */
45625cf1a30Sjl 	ih_p->ih_next = ih_p;
45725cf1a30Sjl 	ino_p->pino_ih_head = ih_p;
45825cf1a30Sjl 	ino_p->pino_ih_tail = ih_p;
45925cf1a30Sjl 	ino_p->pino_ih_start = ih_p;
46025cf1a30Sjl 	ino_p->pino_ih_size = 1;
46225cf1a30Sjl 	ino_p->pino_next = pib_p->pib_ino_lst;
46325cf1a30Sjl 	pib_p->pib_ino_lst = ino_p;
46425cf1a30Sjl 	return (ino_p);
46525cf1a30Sjl }
46725cf1a30Sjl /* the ino_p is retrieved by previous call to pcmu_ib_locate_ino() */
46825cf1a30Sjl void
pcmu_ib_delete_ino(pcmu_ib_t * pib_p,pcmu_ib_ino_info_t * ino_p)46925cf1a30Sjl pcmu_ib_delete_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_info_t *ino_p)
47025cf1a30Sjl {
47125cf1a30Sjl 	pcmu_ib_ino_info_t *list = pib_p->pib_ino_lst;
47225cf1a30Sjl 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
47325cf1a30Sjl 	if (list == ino_p) {
47425cf1a30Sjl 		pib_p->pib_ino_lst = list->pino_next;
47525cf1a30Sjl 	} else {
476116f7629Sjfrank 		for (; list->pino_next != ino_p; list = list->pino_next)
477116f7629Sjfrank 			;
47825cf1a30Sjl 		list->pino_next = ino_p->pino_next;
47925cf1a30Sjl 	}
48025cf1a30Sjl }
48225cf1a30Sjl /* free all ino when we are detaching */
48325cf1a30Sjl void
pcmu_ib_free_ino_all(pcmu_ib_t * pib_p)48425cf1a30Sjl pcmu_ib_free_ino_all(pcmu_ib_t *pib_p)
48525cf1a30Sjl {
48625cf1a30Sjl 	pcmu_ib_ino_info_t *tmp = pib_p->pib_ino_lst;
48725cf1a30Sjl 	pcmu_ib_ino_info_t *next = NULL;
48825cf1a30Sjl 	while (tmp) {
48925cf1a30Sjl 		next = tmp->pino_next;
49025cf1a30Sjl 		kmem_free(tmp, sizeof (pcmu_ib_ino_info_t));
49125cf1a30Sjl 		tmp = next;
49225cf1a30Sjl 	}
49325cf1a30Sjl }
49525cf1a30Sjl void
pcmu_ib_ino_add_intr(pcmu_t * pcmu_p,pcmu_ib_ino_info_t * ino_p,ih_t * ih_p)49625cf1a30Sjl pcmu_ib_ino_add_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p)
49725cf1a30Sjl {
49825cf1a30Sjl 	pcmu_ib_ino_t ino = ino_p->pino_ino;
49925cf1a30Sjl 	pcmu_ib_t *pib_p = ino_p->pino_ib_p;
50025cf1a30Sjl 	volatile uint64_t *state_reg = PCMU_IB_INO_INTR_STATE_REG(pib_p, ino);
50125cf1a30Sjl 	hrtime_t start_time;
50225cf1a30Sjl 	hrtime_t prev, curr, interval, jump;
50325cf1a30Sjl 	hrtime_t intr_timeout;
50525cf1a30Sjl 	ASSERT(pib_p == pcmu_p->pcmu_ib_p);
50625cf1a30Sjl 	ASSERT(MUTEX_HELD(&pib_p->pib_ino_lst_mutex));
50825cf1a30Sjl 	/* disable interrupt, this could disrupt devices sharing our slot */
50925cf1a30Sjl 	PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
51025cf1a30Sjl 	*ino_p->pino_map_reg;
51225cf1a30Sjl 	/* do NOT modify the link list until after the busy wait */
51425cf1a30Sjl 	/*
51525cf1a30Sjl 	 * busy wait if there is interrupt being processed.
51625cf1a30Sjl 	 * either the pending state will be cleared by the interrupt wrapper
51725cf1a30Sjl 	 * or the interrupt will be marked as blocked indicating that it was
51825cf1a30Sjl 	 * jabbering.
51925cf1a30Sjl 	 */
52025cf1a30Sjl 	intr_timeout = pcmu_intrpend_timeout;
52125cf1a30Sjl 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
52225cf1a30Sjl 	start_time = curr = gethrtime();
52325cf1a30Sjl 	while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) &&
524116f7629Sjfrank 	    PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
52525cf1a30Sjl 		/*
52625cf1a30Sjl 		 * If we have a really large jump in hrtime, it is most
52725cf1a30Sjl 		 * probably because we entered the debugger (or OBP,
52825cf1a30Sjl 		 * in general). So, we adjust the timeout accordingly
52925cf1a30Sjl 		 * to prevent declaring an interrupt timeout. The
53025cf1a30Sjl 		 * master-interrupt mechanism in OBP should deliver
53125cf1a30Sjl 		 * the interrupts properly.
53225cf1a30Sjl 		 */
53325cf1a30Sjl 		prev = curr;
53425cf1a30Sjl 		curr = gethrtime();
53525cf1a30Sjl 		interval = curr - prev;
53625cf1a30Sjl 		if (interval > jump)
53725cf1a30Sjl 			intr_timeout += interval;
53825cf1a30Sjl 		if (curr - start_time > intr_timeout) {
53925cf1a30Sjl 			pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
54025cf1a30Sjl 			cmn_err(CE_WARN,
54125cf1a30Sjl 			    "%s:%s: pcmu_ib_ino_add_intr %x timeout",
54225cf1a30Sjl 			    pcbm_p->pcbm_nameinst_str,
54325cf1a30Sjl 			    pcbm_p->pcbm_nameaddr_str, ino);
54425cf1a30Sjl 			break;
54525cf1a30Sjl 		}
54625cf1a30Sjl 	}
54825cf1a30Sjl 	/* link up pcmu_ispec_t portion of the ppd */
54925cf1a30Sjl 	ih_p->ih_next = ino_p->pino_ih_head;
55025cf1a30Sjl 	ino_p->pino_ih_tail->ih_next = ih_p;
55125cf1a30Sjl 	ino_p->pino_ih_tail = ih_p;
55325cf1a30Sjl 	ino_p->pino_ih_start = ino_p->pino_ih_head;
55425cf1a30Sjl 	ino_p->pino_ih_size++;
55625cf1a30Sjl 	/*
55725cf1a30Sjl 	 * if the interrupt was previously blocked (left in pending state)
55825cf1a30Sjl 	 * because of jabber we need to clear the pending state in case the
55925cf1a30Sjl 	 * jabber has gone away.
56025cf1a30Sjl 	 */
56125cf1a30Sjl 	if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) {
56225cf1a30Sjl 		cmn_err(CE_WARN,
56325cf1a30Sjl 		    "%s%d: pcmu_ib_ino_add_intr: ino 0x%x has been unblocked",
56425cf1a30Sjl 		    ddi_driver_name(pcmu_p->pcmu_dip),
56525cf1a30Sjl 		    ddi_get_instance(pcmu_p->pcmu_dip),
56625cf1a30Sjl 		    ino_p->pino_ino);
56725cf1a30Sjl 		ino_p->pino_unclaimed = 0;
56825cf1a30Sjl 		PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg);
56925cf1a30Sjl 	}
57125cf1a30Sjl 	/* re-enable interrupt */
57225cf1a30Sjl 	PCMU_IB_INO_INTR_ON(ino_p->pino_map_reg);
57325cf1a30Sjl 	*ino_p->pino_map_reg;
57425cf1a30Sjl }
57625cf1a30Sjl /*
57725cf1a30Sjl  * removes pcmu_ispec_t from the ino's link list.
57825cf1a30Sjl  * uses hardware mutex to lock out interrupt threads.
57925cf1a30Sjl  * Side effects: interrupt belongs to that ino is turned off on return.
58025cf1a30Sjl  * if we are sharing PCI slot with other inos, the caller needs
58125cf1a30Sjl  * to turn it back on.
58225cf1a30Sjl  */
583116f7629Sjfrank int
pcmu_ib_ino_rem_intr(pcmu_t * pcmu_p,pcmu_ib_ino_info_t * ino_p,ih_t * ih_p)58425cf1a30Sjl pcmu_ib_ino_rem_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p)
58525cf1a30Sjl {
58625cf1a30Sjl 	int i;
58725cf1a30Sjl 	pcmu_ib_ino_t ino = ino_p->pino_ino;
58825cf1a30Sjl 	ih_t *ih_lst = ino_p->pino_ih_head;
58925cf1a30Sjl 	volatile uint64_t *state_reg =
590116f7629Sjfrank 	    PCMU_IB_INO_INTR_STATE_REG(ino_p->pino_ib_p, ino);
59125cf1a30Sjl 	hrtime_t start_time;
59225cf1a30Sjl 	hrtime_t prev, curr, interval, jump;
59325cf1a30Sjl 	hrtime_t intr_timeout;
59525cf1a30Sjl 	ASSERT(MUTEX_HELD(&ino_p->pino_ib_p->pib_ino_lst_mutex));
59625cf1a30Sjl 	/* disable interrupt, this could disrupt devices sharing our slot */
59725cf1a30Sjl 	PCMU_IB_INO_INTR_OFF(ino_p->pino_map_reg);
59825cf1a30Sjl 	*ino_p->pino_map_reg;
60025cf1a30Sjl 	/* do NOT modify the link list until after the busy wait */
60225cf1a30Sjl 	/*
60325cf1a30Sjl 	 * busy wait if there is interrupt being processed.
60425cf1a30Sjl 	 * either the pending state will be cleared by the interrupt wrapper
60525cf1a30Sjl 	 * or the interrupt will be marked as blocked indicating that it was
60625cf1a30Sjl 	 * jabbering.
60725cf1a30Sjl 	 */
60825cf1a30Sjl 	intr_timeout = pcmu_intrpend_timeout;
60925cf1a30Sjl 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
61025cf1a30Sjl 	start_time = curr = gethrtime();
61125cf1a30Sjl 	while ((ino_p->pino_unclaimed <= pcmu_unclaimed_intr_max) &&
612116f7629Sjfrank 	    PCMU_IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
61325cf1a30Sjl 		/*
61425cf1a30Sjl 		 * If we have a really large jump in hrtime, it is most
61525cf1a30Sjl 		 * probably because we entered the debugger (or OBP,
61625cf1a30Sjl 		 * in general). So, we adjust the timeout accordingly
61725cf1a30Sjl 		 * to prevent declaring an interrupt timeout. The
61825cf1a30Sjl 		 * master-interrupt mechanism in OBP should deliver
61925cf1a30Sjl 		 * the interrupts properly.
62025cf1a30Sjl 		 */
62125cf1a30Sjl 		prev = curr;
62225cf1a30Sjl 		curr = gethrtime();
62325cf1a30Sjl 		interval = curr - prev;
62425cf1a30Sjl 		if (interval > jump)
62525cf1a30Sjl 			intr_timeout += interval;
62625cf1a30Sjl 		if (curr - start_time > intr_timeout) {
62725cf1a30Sjl 			pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
62825cf1a30Sjl 			cmn_err(CE_WARN,
62925cf1a30Sjl 			    "%s:%s: pcmu_ib_ino_rem_intr %x timeout",
63025cf1a30Sjl 			    pcbm_p->pcbm_nameinst_str,
63125cf1a30Sjl 			    pcbm_p->pcbm_nameaddr_str, ino);
632116f7629Sjfrank 			PCMU_IB_INO_INTR_ON(ino_p->pino_map_reg);
633116f7629Sjfrank 			*ino_p->pino_map_reg;
634116f7629Sjfrank 			return (DDI_FAILURE);
63525cf1a30Sjl 		}
63625cf1a30Sjl 	}
63825cf1a30Sjl 	if (ino_p->pino_ih_size == 1) {
63925cf1a30Sjl 		if (ih_lst != ih_p)
64025cf1a30Sjl 			goto not_found;
64125cf1a30Sjl 		/* no need to set head/tail as ino_p will be freed */
64225cf1a30Sjl 		goto reset;
64325cf1a30Sjl 	}
64525cf1a30Sjl 	/*
64625cf1a30Sjl 	 * if the interrupt was previously blocked (left in pending state)
64725cf1a30Sjl 	 * because of jabber we need to clear the pending state in case the
64825cf1a30Sjl 	 * jabber has gone away.
64925cf1a30Sjl 	 */
65025cf1a30Sjl 	if (ino_p->pino_unclaimed > pcmu_unclaimed_intr_max) {
65125cf1a30Sjl 		cmn_err(CE_WARN,
65225cf1a30Sjl 		    "%s%d: pcmu_ib_ino_rem_intr: ino 0x%x has been unblocked",
65325cf1a30Sjl 		    ddi_driver_name(pcmu_p->pcmu_dip),
65425cf1a30Sjl 		    ddi_get_instance(pcmu_p->pcmu_dip),
65525cf1a30Sjl 		    ino_p->pino_ino);
65625cf1a30Sjl 		ino_p->pino_unclaimed = 0;
65725cf1a30Sjl 		PCMU_IB_INO_INTR_CLEAR(ino_p->pino_clr_reg);
65825cf1a30Sjl 	}
66025cf1a30Sjl 	/* search the link list for ih_p */
66125cf1a30Sjl 	for (i = 0; (i < ino_p->pino_ih_size) && (ih_lst->ih_next != ih_p);
662116f7629Sjfrank 	    i++, ih_lst = ih_lst->ih_next)
663116f7629Sjfrank 		;
66425cf1a30Sjl 	if (ih_lst->ih_next != ih_p) {
66525cf1a30Sjl 		goto not_found;
66625cf1a30Sjl 	}
66825cf1a30Sjl 	/* remove ih_p from the link list and maintain the head/tail */
66925cf1a30Sjl 	ih_lst->ih_next = ih_p->ih_next;
67025cf1a30Sjl 	if (ino_p->pino_ih_head == ih_p) {
67125cf1a30Sjl 		ino_p->pino_ih_head = ih_p->ih_next;
67225cf1a30Sjl 	}
67325cf1a30Sjl 	if (ino_p->pino_ih_tail == ih_p) {
67425cf1a30Sjl 		ino_p->pino_ih_tail = ih_lst;
67525cf1a30Sjl 	}
67625cf1a30Sjl 	ino_p->pino_ih_start = ino_p->pino_ih_head;
67725cf1a30Sjl reset:
67825cf1a30Sjl 	if (ih_p->ih_config_handle) {
67925cf1a30Sjl 		pci_config_teardown(&ih_p->ih_config_handle);
68025cf1a30Sjl 	}
68125cf1a30Sjl 	kmem_free(ih_p, sizeof (ih_t));
68225cf1a30Sjl 	ino_p->pino_ih_size--;
684116f7629Sjfrank 	return (DDI_SUCCESS);
68525cf1a30Sjl not_found:
68625cf1a30Sjl 	PCMU_DBG2(PCMU_DBG_R_INTX, ino_p->pino_ib_p->pib_pcmu_p->pcmu_dip,
68725cf1a30Sjl 	    "ino_p=%x does not have ih_p=%x\n", ino_p, ih_p);
688116f7629Sjfrank 	return (DDI_SUCCESS);
68925cf1a30Sjl }
69125cf1a30Sjl ih_t *
pcmu_ib_ino_locate_intr(pcmu_ib_ino_info_t * ino_p,dev_info_t * rdip,uint32_t inum)69225cf1a30Sjl pcmu_ib_ino_locate_intr(pcmu_ib_ino_info_t *ino_p,
69325cf1a30Sjl     dev_info_t *rdip, uint32_t inum)
69425cf1a30Sjl {
69525cf1a30Sjl 	ih_t *ih_lst = ino_p->pino_ih_head;
69625cf1a30Sjl 	int i;
69725cf1a30Sjl 	for (i = 0; i < ino_p->pino_ih_size; i++, ih_lst = ih_lst->ih_next) {
69825cf1a30Sjl 		if (ih_lst->ih_dip == rdip && ih_lst->ih_inum == inum) {
69925cf1a30Sjl 			return (ih_lst);
70025cf1a30Sjl 		}
70125cf1a30Sjl 	}
70225cf1a30Sjl 	return ((ih_t *)NULL);
70325cf1a30Sjl }
70525cf1a30Sjl ih_t *
pcmu_ib_alloc_ih(dev_info_t * rdip,uint32_t inum,uint_t (* int_handler)(caddr_t int_handler_arg1,caddr_t int_handler_arg2),caddr_t int_handler_arg1,caddr_t int_handler_arg2)70625cf1a30Sjl pcmu_ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
70725cf1a30Sjl     uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
70825cf1a30Sjl     caddr_t int_handler_arg1,
70925cf1a30Sjl     caddr_t int_handler_arg2)
71025cf1a30Sjl {
71125cf1a30Sjl 	ih_t *ih_p;
71325cf1a30Sjl 	ih_p = kmem_alloc(sizeof (ih_t), KM_SLEEP);
71425cf1a30Sjl 	ih_p->ih_dip = rdip;
71525cf1a30Sjl 	ih_p->ih_inum = inum;
71625cf1a30Sjl 	ih_p->ih_intr_state = PCMU_INTR_STATE_DISABLE;
71725cf1a30Sjl 	ih_p->ih_handler = int_handler;
71825cf1a30Sjl 	ih_p->ih_handler_arg1 = int_handler_arg1;
71925cf1a30Sjl 	ih_p->ih_handler_arg2 = int_handler_arg2;
72025cf1a30Sjl 	ih_p->ih_config_handle = NULL;
72125cf1a30Sjl 	return (ih_p);
72225cf1a30Sjl }
72425cf1a30Sjl int
pcmu_ib_update_intr_state(pcmu_t * pcmu_p,dev_info_t * rdip,ddi_intr_handle_impl_t * hdlp,uint_t new_intr_state)72525cf1a30Sjl pcmu_ib_update_intr_state(pcmu_t *pcmu_p, dev_info_t *rdip,
72625cf1a30Sjl     ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state)
72725cf1a30Sjl {
72825cf1a30Sjl 	pcmu_ib_t		*pib_p = pcmu_p->pcmu_ib_p;
72925cf1a30Sjl 	pcmu_ib_ino_info_t	*ino_p;
73025cf1a30Sjl 	pcmu_ib_mondo_t	mondo;
73125cf1a30Sjl 	ih_t		*ih_p;
73225cf1a30Sjl 	int		ret = DDI_FAILURE;
73425cf1a30Sjl 	mutex_enter(&pib_p->pib_ino_lst_mutex);
73625cf1a30Sjl 	if ((mondo = PCMU_IB_INO_TO_MONDO(pcmu_p->pcmu_ib_p,
73725cf1a30Sjl 	    PCMU_IB_MONDO_TO_INO((int32_t)hdlp->ih_vector))) == 0) {
73825cf1a30Sjl 		mutex_exit(&pib_p->pib_ino_lst_mutex);
73925cf1a30Sjl 		return (ret);
74025cf1a30Sjl 	}
74225cf1a30Sjl 	if (ino_p = pcmu_ib_locate_ino(pib_p, PCMU_IB_MONDO_TO_INO(mondo))) {
74325cf1a30Sjl 		if (ih_p = pcmu_ib_ino_locate_intr(ino_p,
74425cf1a30Sjl 		    rdip, hdlp->ih_inum)) {
74525cf1a30Sjl 			ih_p->ih_intr_state = new_intr_state;
74625cf1a30Sjl 			ret = DDI_SUCCESS;
74725cf1a30Sjl 		}
74825cf1a30Sjl 	}
74925cf1a30Sjl 	mutex_exit(&pib_p->pib_ino_lst_mutex);
75025cf1a30Sjl 	return (ret);
75125cf1a30Sjl }