xref: /illumos-gate/usr/src/uts/sun4u/opl/io/mc-opl.c (revision aeb241b2)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * All Rights Reserved, Copyright (c) FUJITSU LIMITED 2006
27  */
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #include <sys/types.h>
32 #include <sys/sysmacros.h>
33 #include <sys/conf.h>
34 #include <sys/modctl.h>
35 #include <sys/stat.h>
36 #include <sys/async.h>
37 #include <sys/machcpuvar.h>
38 #include <sys/machsystm.h>
39 #include <sys/promif.h>
40 #include <sys/ksynch.h>
41 #include <sys/ddi.h>
42 #include <sys/sunddi.h>
43 #include <sys/ddifm.h>
44 #include <sys/fm/protocol.h>
45 #include <sys/fm/util.h>
46 #include <sys/kmem.h>
47 #include <sys/fm/io/opl_mc_fm.h>
48 #include <sys/memlist.h>
49 #include <sys/param.h>
50 #include <sys/disp.h>
51 #include <vm/page.h>
52 #include <sys/mc-opl.h>
53 #include <sys/opl.h>
54 #include <sys/opl_dimm.h>
55 #include <sys/scfd/scfostoescf.h>
56 #include <sys/cpu_module.h>
57 #include <vm/seg_kmem.h>
58 #include <sys/vmem.h>
59 #include <vm/hat_sfmmu.h>
60 #include <sys/vmsystm.h>
61 #include <sys/membar.h>
62 
63 /*
64  * Function prototypes
65  */
66 static int mc_open(dev_t *, int, int, cred_t *);
67 static int mc_close(dev_t, int, int, cred_t *);
68 static int mc_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
69 static int mc_attach(dev_info_t *, ddi_attach_cmd_t);
70 static int mc_detach(dev_info_t *, ddi_detach_cmd_t);
71 
72 static int mc_poll_init(void);
73 static void mc_poll_fini(void);
74 static int mc_board_add(mc_opl_t *mcp);
75 static int mc_board_del(mc_opl_t *mcp);
76 static int mc_suspend(mc_opl_t *mcp, uint32_t flag);
77 static int mc_resume(mc_opl_t *mcp, uint32_t flag);
78 int opl_mc_suspend(void);
79 int opl_mc_resume(void);
80 
81 static void insert_mcp(mc_opl_t *mcp);
82 static void delete_mcp(mc_opl_t *mcp);
83 
84 static int pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr);
85 
86 static int mc_rangecheck_pa(mc_opl_t *mcp, uint64_t pa);
87 
88 int mc_get_mem_unum(int, uint64_t, char *, int, int *);
89 int mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr);
90 int mc_get_mem_offset(uint64_t paddr, uint64_t *offp);
91 int mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp);
92 int mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf,
93     int buflen, int *lenp);
94 mc_dimm_info_t *mc_get_dimm_list(mc_opl_t *mcp);
95 mc_dimm_info_t *mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp);
96 int mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, int bank,
97     uint32_t mf_type, uint32_t d_slot);
98 static void mc_free_dimm_list(mc_dimm_info_t *d);
99 static void mc_get_mlist(mc_opl_t *);
100 static void mc_polling(void);
101 static int mc_opl_get_physical_board(int);
102 
103 #ifdef	DEBUG
104 static int mc_ioctl_debug(dev_t, int, intptr_t, int, cred_t *, int *);
105 void mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz);
106 void mc_dump_dimm_info(board_dimm_info_t *bd_dimmp);
107 #endif
108 
109 #pragma weak opl_get_physical_board
110 extern int opl_get_physical_board(int);
111 extern int plat_max_boards(void);
112 
113 /*
114  * Configuration data structures
115  */
116 static struct cb_ops mc_cb_ops = {
117 	mc_open,			/* open */
118 	mc_close,			/* close */
119 	nulldev,			/* strategy */
120 	nulldev,			/* print */
121 	nodev,				/* dump */
122 	nulldev,			/* read */
123 	nulldev,			/* write */
124 	mc_ioctl,			/* ioctl */
125 	nodev,				/* devmap */
126 	nodev,				/* mmap */
127 	nodev,				/* segmap */
128 	nochpoll,			/* poll */
129 	ddi_prop_op,			/* cb_prop_op */
130 	0,				/* streamtab */
131 	D_MP | D_NEW | D_HOTPLUG,	/* Driver compatibility flag */
132 	CB_REV,				/* rev */
133 	nodev,				/* cb_aread */
134 	nodev				/* cb_awrite */
135 };
136 
137 static struct dev_ops mc_ops = {
138 	DEVO_REV,			/* rev */
139 	0,				/* refcnt  */
140 	ddi_getinfo_1to1,		/* getinfo */
141 	nulldev,			/* identify */
142 	nulldev,			/* probe */
143 	mc_attach,			/* attach */
144 	mc_detach,			/* detach */
145 	nulldev,			/* reset */
146 	&mc_cb_ops,			/* cb_ops */
147 	(struct bus_ops *)0,		/* bus_ops */
148 	nulldev				/* power */
149 };
150 
151 /*
152  * Driver globals
153  */
154 
155 static enum {
156 	MODEL_FF1 = 0,
157 	MODEL_FF2 = 1,
158 	MODEL_DC = 2
159 } plat_model = MODEL_DC;	/* The default behaviour is DC */
160 
161 static struct plat_model_names {
162 	const char *unit_name;
163 	const char *mem_name;
164 } model_names[] = {
165 	{ "MBU_A", "MEMB" },
166 	{ "MBU_B", "MEMB" },
167 	{ "CMU", "" }
168 };
169 
170 /*
171  * The DIMM Names for DC platform.
172  * The index into this table is made up of (bank, dslot),
173  * Where dslot occupies bits 0-1 and bank occupies 2-4.
174  */
175 static char *mc_dc_dimm_unum_table[OPL_MAX_DIMMS] = {
176 	/* --------CMUnn----------- */
177 	/* --CS0-----|--CS1------ */
178 	/* -H-|--L-- | -H- | -L-- */
179 	"03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */
180 	"13A", "12A", "13B", "12B", /* Bank 1 (MAC 0 bank 1) */
181 	"23A", "22A", "23B", "22B", /* Bank 2 (MAC 1 bank 0) */
182 	"33A", "32A", "33B", "32B", /* Bank 3 (MAC 1 bank 1) */
183 	"01A", "00A", "01B", "00B", /* Bank 4 (MAC 2 bank 0) */
184 	"11A", "10A", "11B", "10B", /* Bank 5 (MAC 2 bank 1) */
185 	"21A", "20A", "21B", "20B", /* Bank 6 (MAC 3 bank 0) */
186 	"31A", "30A", "31B", "30B"  /* Bank 7 (MAC 3 bank 1) */
187 };
188 
189 /*
190  * The DIMM Names for FF1/FF2 platforms.
191  * The index into this table is made up of (board, bank, dslot),
192  * Where dslot occupies bits 0-1, bank occupies 2-4 and
193  * board occupies the bit 5.
194  */
195 static char *mc_ff_dimm_unum_table[2 * OPL_MAX_DIMMS] = {
196 	/* --------CMU0---------- */
197 	/* --CS0-----|--CS1------ */
198 	/* -H-|--L-- | -H- | -L-- */
199 	"03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */
200 	"01A", "00A", "01B", "00B", /* Bank 1 (MAC 0 bank 1) */
201 	"13A", "12A", "13B", "12B", /* Bank 2 (MAC 1 bank 0) */
202 	"11A", "10A", "11B", "10B", /* Bank 3 (MAC 1 bank 1) */
203 	"23A", "22A", "23B", "22B", /* Bank 4 (MAC 2 bank 0) */
204 	"21A", "20A", "21B", "20B", /* Bank 5 (MAC 2 bank 1) */
205 	"33A", "32A", "33B", "32B", /* Bank 6 (MAC 3 bank 0) */
206 	"31A", "30A", "31B", "30B", /* Bank 7 (MAC 3 bank 1) */
207 	/* --------CMU1---------- */
208 	/* --CS0-----|--CS1------ */
209 	/* -H-|--L-- | -H- | -L-- */
210 	"43A", "42A", "43B", "42B", /* Bank 0 (MAC 0 bank 0) */
211 	"41A", "40A", "41B", "40B", /* Bank 1 (MAC 0 bank 1) */
212 	"53A", "52A", "53B", "52B", /* Bank 2 (MAC 1 bank 0) */
213 	"51A", "50A", "51B", "50B", /* Bank 3 (MAC 1 bank 1) */
214 	"63A", "62A", "63B", "62B", /* Bank 4 (MAC 2 bank 0) */
215 	"61A", "60A", "61B", "60B", /* Bank 5 (MAC 2 bank 1) */
216 	"73A", "72A", "73B", "72B", /* Bank 6 (MAC 3 bank 0) */
217 	"71A", "70A", "71B", "70B"  /* Bank 7 (MAC 3 bank 1) */
218 };
219 
220 #define	BD_BK_SLOT_TO_INDEX(bd, bk, s)			\
221 	(((bd & 0x01) << 5) | ((bk & 0x07) << 2) | (s & 0x03))
222 
223 #define	INDEX_TO_BANK(i)			(((i) & 0x1C) >> 2)
224 #define	INDEX_TO_SLOT(i)			((i) & 0x03)
225 
226 #define	SLOT_TO_CS(slot)	((slot & 0x3) >> 1)
227 
228 /* Isolation unit size is 64 MB */
229 #define	MC_ISOLATION_BSIZE	(64 * 1024 * 1024)
230 
231 #define	MC_MAX_SPEEDS 7
232 
233 typedef struct {
234 	uint32_t mc_speeds;
235 	uint32_t mc_period;
236 } mc_scan_speed_t;
237 
238 #define	MC_CNTL_SPEED_SHIFT 26
239 
240 /*
241  * In mirror mode, we normalized the bank idx to "even" since
242  * the HW treats them as one unit w.r.t programming.
243  * This bank index will be the "effective" bank index.
244  * All mirrored bank state info on mc_period, mc_speedup_period
245  * will be stored in the even bank structure to avoid code duplication.
246  */
247 #define	MIRROR_IDX(bankidx)	(bankidx & ~1)
248 
249 static mc_scan_speed_t	mc_scan_speeds[MC_MAX_SPEEDS] = {
250 	{0x6 << MC_CNTL_SPEED_SHIFT, 0},
251 	{0x5 << MC_CNTL_SPEED_SHIFT, 32},
252 	{0x4 << MC_CNTL_SPEED_SHIFT, 64},
253 	{0x3 << MC_CNTL_SPEED_SHIFT, 128},
254 	{0x2 << MC_CNTL_SPEED_SHIFT, 256},
255 	{0x1 << MC_CNTL_SPEED_SHIFT, 512},
256 	{0x0 << MC_CNTL_SPEED_SHIFT, 1024}
257 };
258 
259 static uint32_t	mc_max_speed = (0x6 << 26);
260 
261 int mc_isolation_bsize = MC_ISOLATION_BSIZE;
262 int mc_patrol_interval_sec = MC_PATROL_INTERVAL_SEC;
263 int mc_max_scf_retry = 16;
264 int mc_max_scf_logs = 64;
265 int mc_max_errlog_processed = BANKNUM_PER_SB*2;
266 int mc_scan_period = 12 * 60 * 60;	/* 12 hours period */
267 int mc_max_rewrite_loop = 100;
268 int mc_rewrite_delay = 10;
269 /*
270  * it takes SCF about 300 m.s. to process a requst.  We can bail out
271  * if it is busy.  It does not pay to wait for it too long.
272  */
273 int mc_max_scf_loop = 2;
274 int mc_scf_delay = 100;
275 int mc_pce_dropped = 0;
276 int mc_poll_priority = MINCLSYSPRI;
277 
278 
279 /*
280  * Mutex heierachy in mc-opl
281  * If both mcmutex and mc_lock must be held,
282  * mcmutex must be acquired first, and then mc_lock.
283  */
284 
285 static kmutex_t mcmutex;
286 mc_opl_t *mc_instances[OPL_MAX_BOARDS];
287 
288 static kmutex_t mc_polling_lock;
289 static kcondvar_t mc_polling_cv;
290 static kcondvar_t mc_poll_exit_cv;
291 static int mc_poll_cmd = 0;
292 static int mc_pollthr_running = 0;
293 int mc_timeout_period = 0; /* this is in m.s. */
294 void *mc_statep;
295 
296 #ifdef	DEBUG
297 int oplmc_debug = 0;
298 #endif
299 
300 static int mc_debug_show_all = 0;
301 
302 extern struct mod_ops mod_driverops;
303 
304 static struct modldrv modldrv = {
305 	&mod_driverops,			/* module type, this one is a driver */
306 	"OPL Memory-controller %I%",	/* module name */
307 	&mc_ops,			/* driver ops */
308 };
309 
310 static struct modlinkage modlinkage = {
311 	MODREV_1,		/* rev */
312 	(void *)&modldrv,
313 	NULL
314 };
315 
316 #pragma weak opl_get_mem_unum
317 #pragma weak opl_get_mem_sid
318 #pragma weak opl_get_mem_offset
319 #pragma weak opl_get_mem_addr
320 
321 extern int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *);
322 extern int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp);
323 extern int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp);
324 extern int (*opl_get_mem_addr)(char *unum, char *sid, uint64_t offset,
325     uint64_t *paddr);
326 
327 
328 /*
329  * pseudo-mc node portid format
330  *
331  *		[10]   = 0
332  *		[9]    = 1
333  *		[8]    = LSB_ID[4] = 0
334  *		[7:4]  = LSB_ID[3:0]
335  *		[3:0]  = 0
336  *
337  */
338 
339 /*
340  * These are the module initialization routines.
341  */
342 int
343 _init(void)
344 {
345 	int	error;
346 	int	plen;
347 	char	model[20];
348 	pnode_t	node;
349 
350 
351 	if ((error = ddi_soft_state_init(&mc_statep,
352 	    sizeof (mc_opl_t), 1)) != 0)
353 		return (error);
354 
355 	if ((error = mc_poll_init()) != 0) {
356 		ddi_soft_state_fini(&mc_statep);
357 		return (error);
358 	}
359 
360 	mutex_init(&mcmutex, NULL, MUTEX_DRIVER, NULL);
361 	if (&opl_get_mem_unum)
362 		opl_get_mem_unum = mc_get_mem_unum;
363 	if (&opl_get_mem_sid)
364 		opl_get_mem_sid = mc_get_mem_sid;
365 	if (&opl_get_mem_offset)
366 		opl_get_mem_offset = mc_get_mem_offset;
367 	if (&opl_get_mem_addr)
368 		opl_get_mem_addr = mc_get_mem_addr;
369 
370 	node = prom_rootnode();
371 	plen = prom_getproplen(node, "model");
372 
373 	if (plen > 0 && plen < sizeof (model)) {
374 		(void) prom_getprop(node, "model", model);
375 		model[plen] = '\0';
376 		if (strcmp(model, "FF1") == 0)
377 			plat_model = MODEL_FF1;
378 		else if (strcmp(model, "FF2") == 0)
379 			plat_model = MODEL_FF2;
380 		else if (strncmp(model, "DC", 2) == 0)
381 			plat_model = MODEL_DC;
382 	}
383 
384 	error =  mod_install(&modlinkage);
385 	if (error != 0) {
386 		if (&opl_get_mem_unum)
387 			opl_get_mem_unum = NULL;
388 		if (&opl_get_mem_sid)
389 			opl_get_mem_sid = NULL;
390 		if (&opl_get_mem_offset)
391 			opl_get_mem_offset = NULL;
392 		if (&opl_get_mem_addr)
393 			opl_get_mem_addr = NULL;
394 		mutex_destroy(&mcmutex);
395 		mc_poll_fini();
396 		ddi_soft_state_fini(&mc_statep);
397 	}
398 	return (error);
399 }
400 
401 int
402 _fini(void)
403 {
404 	int error;
405 
406 	if ((error = mod_remove(&modlinkage)) != 0)
407 		return (error);
408 
409 	if (&opl_get_mem_unum)
410 		opl_get_mem_unum = NULL;
411 	if (&opl_get_mem_sid)
412 		opl_get_mem_sid = NULL;
413 	if (&opl_get_mem_offset)
414 		opl_get_mem_offset = NULL;
415 	if (&opl_get_mem_addr)
416 		opl_get_mem_addr = NULL;
417 
418 	mutex_destroy(&mcmutex);
419 	mc_poll_fini();
420 	ddi_soft_state_fini(&mc_statep);
421 
422 	return (0);
423 }
424 
425 int
426 _info(struct modinfo *modinfop)
427 {
428 	return (mod_info(&modlinkage, modinfop));
429 }
430 
431 static void
432 mc_polling_thread()
433 {
434 	mutex_enter(&mc_polling_lock);
435 	mc_pollthr_running = 1;
436 	while (!(mc_poll_cmd & MC_POLL_EXIT)) {
437 		mc_polling();
438 		cv_timedwait(&mc_polling_cv, &mc_polling_lock,
439 		    ddi_get_lbolt() + mc_timeout_period);
440 	}
441 	mc_pollthr_running = 0;
442 
443 	/*
444 	 * signal if any one is waiting for this thread to exit.
445 	 */
446 	cv_signal(&mc_poll_exit_cv);
447 	mutex_exit(&mc_polling_lock);
448 	thread_exit();
449 	/* NOTREACHED */
450 }
451 
452 static int
453 mc_poll_init()
454 {
455 	mutex_init(&mc_polling_lock, NULL, MUTEX_DRIVER, NULL);
456 	cv_init(&mc_polling_cv, NULL, CV_DRIVER, NULL);
457 	cv_init(&mc_poll_exit_cv, NULL, CV_DRIVER, NULL);
458 	return (0);
459 }
460 
461 static void
462 mc_poll_fini()
463 {
464 	mutex_enter(&mc_polling_lock);
465 	if (mc_pollthr_running) {
466 		mc_poll_cmd = MC_POLL_EXIT;
467 		cv_signal(&mc_polling_cv);
468 		while (mc_pollthr_running) {
469 			cv_wait(&mc_poll_exit_cv, &mc_polling_lock);
470 		}
471 	}
472 	mutex_exit(&mc_polling_lock);
473 	mutex_destroy(&mc_polling_lock);
474 	cv_destroy(&mc_polling_cv);
475 	cv_destroy(&mc_poll_exit_cv);
476 }
477 
478 static int
479 mc_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
480 {
481 	mc_opl_t *mcp;
482 	int instance;
483 	int rv;
484 
485 	/* get the instance of this devi */
486 	instance = ddi_get_instance(devi);
487 
488 	switch (cmd) {
489 	case DDI_ATTACH:
490 		break;
491 	case DDI_RESUME:
492 		mcp = ddi_get_soft_state(mc_statep, instance);
493 		rv = mc_resume(mcp, MC_DRIVER_SUSPENDED);
494 		return (rv);
495 	default:
496 		return (DDI_FAILURE);
497 	}
498 
499 	if (ddi_soft_state_zalloc(mc_statep, instance) != DDI_SUCCESS)
500 		return (DDI_FAILURE);
501 
502 	if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) {
503 		goto bad;
504 	}
505 
506 	if (mc_timeout_period == 0) {
507 		mc_patrol_interval_sec = (int)ddi_getprop(DDI_DEV_T_ANY, devi,
508 			DDI_PROP_DONTPASS, "mc-timeout-interval-sec",
509 			mc_patrol_interval_sec);
510 		mc_timeout_period = drv_usectohz(
511 			1000000 * mc_patrol_interval_sec / OPL_MAX_BOARDS);
512 	}
513 
514 	/* set informations in mc state */
515 	mcp->mc_dip = devi;
516 
517 	if (mc_board_add(mcp))
518 		goto bad;
519 
520 	insert_mcp(mcp);
521 
522 	/*
523 	 * Start the polling thread if it is not running already.
524 	 */
525 	mutex_enter(&mc_polling_lock);
526 	if (!mc_pollthr_running) {
527 		(void) thread_create(NULL, 0, (void (*)())mc_polling_thread,
528 			NULL, 0, &p0, TS_RUN, mc_poll_priority);
529 	}
530 	mutex_exit(&mc_polling_lock);
531 	ddi_report_dev(devi);
532 
533 	return (DDI_SUCCESS);
534 
535 bad:
536 	ddi_soft_state_free(mc_statep, instance);
537 	return (DDI_FAILURE);
538 }
539 
540 /* ARGSUSED */
541 static int
542 mc_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
543 {
544 	int rv;
545 	int instance;
546 	mc_opl_t *mcp;
547 
548 	/* get the instance of this devi */
549 	instance = ddi_get_instance(devi);
550 	if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) {
551 		return (DDI_FAILURE);
552 	}
553 
554 	switch (cmd) {
555 	case DDI_SUSPEND:
556 		rv = mc_suspend(mcp, MC_DRIVER_SUSPENDED);
557 		return (rv);
558 	case DDI_DETACH:
559 		break;
560 	default:
561 		return (DDI_FAILURE);
562 	}
563 
564 	delete_mcp(mcp);
565 	if (mc_board_del(mcp) != DDI_SUCCESS) {
566 		return (DDI_FAILURE);
567 	}
568 
569 	/* free up the soft state */
570 	ddi_soft_state_free(mc_statep, instance);
571 
572 	return (DDI_SUCCESS);
573 }
574 
575 /* ARGSUSED */
576 static int
577 mc_open(dev_t *devp, int flag, int otyp, cred_t *credp)
578 {
579 	return (0);
580 }
581 
582 /* ARGSUSED */
583 static int
584 mc_close(dev_t devp, int flag, int otyp, cred_t *credp)
585 {
586 	return (0);
587 }
588 
589 /* ARGSUSED */
590 static int
591 mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
592 	int *rvalp)
593 {
594 #ifdef DEBUG
595 	return (mc_ioctl_debug(dev, cmd, arg, mode, credp, rvalp));
596 #else
597 	return (ENXIO);
598 #endif
599 }
600 
601 /*
602  * PA validity check:
603  * This function return 1 if the PA is a valid PA
604  * in the running Solaris instance i.e. in physinstall
605  * Otherwise, return 0.
606  */
607 
608 /* ARGSUSED */
609 static int
610 pa_is_valid(mc_opl_t *mcp, uint64_t addr)
611 {
612 	if (mcp->mlist == NULL)
613 		mc_get_mlist(mcp);
614 
615 	if (mcp->mlist && address_in_memlist(mcp->mlist, addr, 0)) {
616 		return (1);
617 	}
618 	return (0);
619 }
620 
621 /*
622  * mac-pa translation routines.
623  *
624  *    Input: mc driver state, (LSB#, Bank#, DIMM address)
625  *    Output: physical address
626  *
627  *    Valid   - return value:  0
628  *    Invalid - return value: -1
629  */
630 static int
631 mcaddr_to_pa(mc_opl_t *mcp, mc_addr_t *maddr, uint64_t *pa)
632 {
633 	int i;
634 	uint64_t pa_offset = 0;
635 	int cs = (maddr->ma_dimm_addr >> CS_SHIFT) & 1;
636 	int bank = maddr->ma_bank;
637 	mc_addr_t maddr1;
638 	int bank0, bank1;
639 
640 	MC_LOG("mcaddr /LSB%d/B%d/%x\n", maddr->ma_bd, bank,
641 		maddr->ma_dimm_addr);
642 
643 	/* loc validity check */
644 	ASSERT(maddr->ma_bd >= 0 && OPL_BOARD_MAX > maddr->ma_bd);
645 	ASSERT(bank >= 0 && OPL_BANK_MAX > bank);
646 
647 	/* Do translation */
648 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
649 		int pa_bit = 0;
650 		int mc_bit = mcp->mc_trans_table[cs][i];
651 		if (mc_bit < MC_ADDRESS_BITS) {
652 			pa_bit = (maddr->ma_dimm_addr >> mc_bit) & 1;
653 		} else if (mc_bit == MP_NONE) {
654 			pa_bit = 0;
655 		} else if (mc_bit == MP_BANK_0) {
656 			pa_bit = bank & 1;
657 		} else if (mc_bit == MP_BANK_1) {
658 			pa_bit = (bank >> 1) & 1;
659 		} else if (mc_bit == MP_BANK_2) {
660 			pa_bit = (bank >> 2) & 1;
661 		}
662 		pa_offset |= ((uint64_t)pa_bit) << i;
663 	}
664 	*pa = mcp->mc_start_address + pa_offset;
665 	MC_LOG("pa = %lx\n", *pa);
666 
667 	if (pa_to_maddr(mcp, *pa, &maddr1) == -1) {
668 		cmn_err(CE_WARN, "mcaddr_to_pa: /LSB%d/B%d/%x failed to "
669 		    "convert PA %lx\n", maddr->ma_bd, bank,
670 		    maddr->ma_dimm_addr, *pa);
671 		return (-1);
672 	}
673 
674 	/*
675 	 * In mirror mode, PA is always translated to the even bank.
676 	 */
677 	if (IS_MIRROR(mcp, maddr->ma_bank)) {
678 		bank0 = maddr->ma_bank & ~(1);
679 		bank1 = maddr1.ma_bank & ~(1);
680 	} else {
681 		bank0 = maddr->ma_bank;
682 		bank1 = maddr1.ma_bank;
683 	}
684 	/*
685 	 * there is no need to check ma_bd because it is generated from
686 	 * mcp.  They are the same.
687 	 */
688 	if ((bank0 == bank1) &&
689 		(maddr->ma_dimm_addr == maddr1.ma_dimm_addr)) {
690 		return (0);
691 	} else {
692 		cmn_err(CE_WARN, "Translation error source /LSB%d/B%d/%x, "
693 			"PA %lx, target /LSB%d/B%d/%x\n",
694 			maddr->ma_bd, bank, maddr->ma_dimm_addr,
695 			*pa, maddr1.ma_bd, maddr1.ma_bank,
696 			maddr1.ma_dimm_addr);
697 		return (-1);
698 	}
699 }
700 
701 /*
702  * PA to CS (used by pa_to_maddr).
703  */
704 static int
705 pa_to_cs(mc_opl_t *mcp, uint64_t pa_offset)
706 {
707 	int i;
708 	int cs = 1;
709 
710 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
711 		/* MAC address bit<29> is arranged on the same PA bit */
712 		/* on both table. So we may use any table. */
713 		if (mcp->mc_trans_table[0][i] == CS_SHIFT) {
714 			cs = (pa_offset >> i) & 1;
715 			break;
716 		}
717 	}
718 	return (cs);
719 }
720 
721 /*
722  * PA to DIMM (used by pa_to_maddr).
723  */
724 /* ARGSUSED */
725 static uint32_t
726 pa_to_dimm(mc_opl_t *mcp, uint64_t pa_offset)
727 {
728 	int i;
729 	int cs = pa_to_cs(mcp, pa_offset);
730 	uint32_t dimm_addr = 0;
731 
732 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
733 		int pa_bit_value = (pa_offset >> i) & 1;
734 		int mc_bit = mcp->mc_trans_table[cs][i];
735 		if (mc_bit < MC_ADDRESS_BITS) {
736 			dimm_addr |= pa_bit_value << mc_bit;
737 		}
738 	}
739 	dimm_addr |= cs << CS_SHIFT;
740 	return (dimm_addr);
741 }
742 
743 /*
744  * PA to Bank (used by pa_to_maddr).
745  */
746 static int
747 pa_to_bank(mc_opl_t *mcp, uint64_t pa_offset)
748 {
749 	int i;
750 	int cs = pa_to_cs(mcp, pa_offset);
751 	int bankno = mcp->mc_trans_table[cs][INDEX_OF_BANK_SUPPLEMENT_BIT];
752 
753 
754 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
755 		int pa_bit_value = (pa_offset >> i) & 1;
756 		int mc_bit = mcp->mc_trans_table[cs][i];
757 		switch (mc_bit) {
758 		case MP_BANK_0:
759 			bankno |= pa_bit_value;
760 			break;
761 		case MP_BANK_1:
762 			bankno |= pa_bit_value << 1;
763 			break;
764 		case MP_BANK_2:
765 			bankno |= pa_bit_value << 2;
766 			break;
767 		}
768 	}
769 
770 	return (bankno);
771 }
772 
773 /*
774  * PA to MAC address translation
775  *
776  *   Input: MAC driver state, physicall adress
777  *   Output: LSB#, Bank id, mac address
778  *
779  *    Valid   - return value:  0
780  *    Invalid - return value: -1
781  */
782 
783 int
784 pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr)
785 {
786 	uint64_t pa_offset;
787 
788 	if (!mc_rangecheck_pa(mcp, pa))
789 		return (-1);
790 
791 	/* Do translation */
792 	pa_offset = pa - mcp->mc_start_address;
793 
794 	maddr->ma_bd = mcp->mc_board_num;
795 	maddr->ma_phys_bd = mcp->mc_phys_board_num;
796 	maddr->ma_bank = pa_to_bank(mcp, pa_offset);
797 	maddr->ma_dimm_addr = pa_to_dimm(mcp, pa_offset);
798 	MC_LOG("pa %lx -> mcaddr /LSB%d/B%d/%x\n",
799 		pa_offset, maddr->ma_bd, maddr->ma_bank, maddr->ma_dimm_addr);
800 	return (0);
801 }
802 
803 /*
804  * UNUM format for DC is "/CMUnn/MEMxyZ", where
805  *	nn = 00..03 for DC1 and 00..07 for DC2 and 00..15 for DC3.
806  *	x = MAC 0..3
807  *	y = 0..3 (slot info).
808  *	Z = 'A' or 'B'
809  *
810  * UNUM format for FF1 is "/MBU_A/MEMBx/MEMyZ", where
811  *	x = 0..3 (MEMB number)
812  *	y = 0..3 (slot info).
813  *	Z = 'A' or 'B'
814  *
815  * UNUM format for FF2 is "/MBU_B/MEMBx/MEMyZ"
816  *	x = 0..7 (MEMB number)
817  *	y = 0..3 (slot info).
818  *	Z = 'A' or 'B'
819  */
820 int
821 mc_set_mem_unum(char *buf, int buflen, int sb, int bank,
822     uint32_t mf_type, uint32_t d_slot)
823 {
824 	char *dimmnm;
825 	char memb_num;
826 	int cs;
827 	int i;
828 	int j;
829 
830 	cs = SLOT_TO_CS(d_slot);
831 
832 	if (plat_model == MODEL_DC) {
833 		if (mf_type == FLT_TYPE_PERMANENT_CE) {
834 			i = BD_BK_SLOT_TO_INDEX(0, bank, d_slot);
835 			dimmnm = mc_dc_dimm_unum_table[i];
836 			snprintf(buf, buflen, "/%s%02d/MEM%s",
837 			    model_names[plat_model].unit_name, sb, dimmnm);
838 		} else {
839 			i = BD_BK_SLOT_TO_INDEX(0, bank, 0);
840 			j = (cs == 0) ?  i : i + 2;
841 			snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s",
842 			    model_names[plat_model].unit_name, sb,
843 			    mc_dc_dimm_unum_table[j],
844 			    mc_dc_dimm_unum_table[j + 1]);
845 		}
846 	} else {
847 		if (mf_type == FLT_TYPE_PERMANENT_CE) {
848 			i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot);
849 			dimmnm = mc_ff_dimm_unum_table[i];
850 			memb_num = dimmnm[0];
851 			snprintf(buf, buflen, "/%s/%s%c/MEM%s",
852 			    model_names[plat_model].unit_name,
853 			    model_names[plat_model].mem_name,
854 			    memb_num, &dimmnm[1]);
855 		} else {
856 			i = BD_BK_SLOT_TO_INDEX(sb, bank, 0);
857 			j = (cs == 0) ?  i : i + 2;
858 			memb_num = mc_ff_dimm_unum_table[i][0],
859 			snprintf(buf, buflen,
860 			    "/%s/%s%c/MEM%s MEM%s",
861 			    model_names[plat_model].unit_name,
862 			    model_names[plat_model].mem_name, memb_num,
863 			    &mc_ff_dimm_unum_table[j][1],
864 			    &mc_ff_dimm_unum_table[j + 1][1]);
865 		}
866 	}
867 	return (0);
868 }
869 
870 static void
871 mc_ereport_post(mc_aflt_t *mc_aflt)
872 {
873 	char buf[FM_MAX_CLASS];
874 	char device_path[MAXPATHLEN];
875 	char sid[MAXPATHLEN];
876 	nv_alloc_t *nva = NULL;
877 	nvlist_t *ereport, *detector, *resource;
878 	errorq_elem_t *eqep;
879 	int nflts;
880 	mc_flt_stat_t *flt_stat;
881 	int i, n;
882 	int blen = MAXPATHLEN;
883 	char *p, *s = NULL;
884 	uint32_t values[2], synd[2], dslot[2];
885 	uint64_t offset = (uint64_t)-1;
886 	int ret = -1;
887 
888 	if (panicstr) {
889 		eqep = errorq_reserve(ereport_errorq);
890 		if (eqep == NULL)
891 			return;
892 		ereport = errorq_elem_nvl(ereport_errorq, eqep);
893 		nva = errorq_elem_nva(ereport_errorq, eqep);
894 	} else {
895 		ereport = fm_nvlist_create(nva);
896 	}
897 
898 	/*
899 	 * Create the scheme "dev" FMRI.
900 	 */
901 	detector = fm_nvlist_create(nva);
902 	resource = fm_nvlist_create(nva);
903 
904 	nflts = mc_aflt->mflt_nflts;
905 
906 	ASSERT(nflts >= 1 && nflts <= 2);
907 
908 	flt_stat = mc_aflt->mflt_stat[0];
909 	(void) ddi_pathname(mc_aflt->mflt_mcp->mc_dip, device_path);
910 	(void) fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL,
911 	    device_path, NULL);
912 
913 	/*
914 	 * Encode all the common data into the ereport.
915 	 */
916 	(void) snprintf(buf, FM_MAX_CLASS, "%s.%s-%s",
917 		MC_OPL_ERROR_CLASS,
918 		mc_aflt->mflt_is_ptrl ? MC_OPL_PTRL_SUBCLASS :
919 		MC_OPL_MI_SUBCLASS,
920 		mc_aflt->mflt_erpt_class);
921 
922 	MC_LOG("mc_ereport_post: ereport %s\n", buf);
923 
924 
925 	fm_ereport_set(ereport, FM_EREPORT_VERSION, buf,
926 		fm_ena_generate(mc_aflt->mflt_id, FM_ENA_FMT1),
927 		detector, NULL);
928 
929 	/*
930 	 * Set payload.
931 	 */
932 	fm_payload_set(ereport, MC_OPL_BOARD, DATA_TYPE_UINT32,
933 		flt_stat->mf_flt_maddr.ma_bd, NULL);
934 
935 	fm_payload_set(ereport, MC_OPL_PA, DATA_TYPE_UINT64,
936 		flt_stat->mf_flt_paddr, NULL);
937 
938 	if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) {
939 		fm_payload_set(ereport, MC_OPL_FLT_TYPE,
940 			DATA_TYPE_UINT8, ECC_STICKY, NULL);
941 	}
942 
943 	for (i = 0; i < nflts; i++)
944 		values[i] = mc_aflt->mflt_stat[i]->mf_flt_maddr.ma_bank;
945 
946 	fm_payload_set(ereport, MC_OPL_BANK, DATA_TYPE_UINT32_ARRAY,
947 		nflts, values, NULL);
948 
949 	for (i = 0; i < nflts; i++)
950 		values[i] = mc_aflt->mflt_stat[i]->mf_cntl;
951 
952 	fm_payload_set(ereport, MC_OPL_STATUS, DATA_TYPE_UINT32_ARRAY,
953 		nflts, values, NULL);
954 
955 	for (i = 0; i < nflts; i++)
956 		values[i] = mc_aflt->mflt_stat[i]->mf_err_add;
957 
958 	/* offset is set only for PCE */
959 	if (mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_PERMANENT_CE) {
960 		offset = values[0];
961 
962 	}
963 	fm_payload_set(ereport, MC_OPL_ERR_ADD, DATA_TYPE_UINT32_ARRAY,
964 		nflts, values, NULL);
965 
966 	for (i = 0; i < nflts; i++)
967 		values[i] = mc_aflt->mflt_stat[i]->mf_err_log;
968 
969 	fm_payload_set(ereport, MC_OPL_ERR_LOG, DATA_TYPE_UINT32_ARRAY,
970 		nflts, values, NULL);
971 
972 	for (i = 0; i < nflts; i++) {
973 		flt_stat = mc_aflt->mflt_stat[i];
974 		if (flt_stat->mf_errlog_valid) {
975 			synd[i] = flt_stat->mf_synd;
976 			dslot[i] = flt_stat->mf_dimm_slot;
977 			values[i] = flt_stat->mf_dram_place;
978 		} else {
979 			synd[i] = 0;
980 			dslot[i] = 0;
981 			values[i] = 0;
982 		}
983 	}
984 
985 	fm_payload_set(ereport, MC_OPL_ERR_SYND,
986 		DATA_TYPE_UINT32_ARRAY, nflts, synd, NULL);
987 
988 	fm_payload_set(ereport, MC_OPL_ERR_DIMMSLOT,
989 		DATA_TYPE_UINT32_ARRAY, nflts, dslot, NULL);
990 
991 	fm_payload_set(ereport, MC_OPL_ERR_DRAM,
992 		DATA_TYPE_UINT32_ARRAY, nflts, values, NULL);
993 
994 	device_path[0] = 0;
995 	p = &device_path[0];
996 	sid[0] = 0;
997 	s = &sid[0];
998 	ret = 0;
999 
1000 	for (i = 0; i < nflts; i++) {
1001 		int bank;
1002 
1003 		flt_stat = mc_aflt->mflt_stat[i];
1004 		bank = flt_stat->mf_flt_maddr.ma_bank;
1005 		ret =  mc_set_mem_unum(p + strlen(p), blen,
1006 			flt_stat->mf_flt_maddr.ma_phys_bd, bank,
1007 			flt_stat->mf_type, flt_stat->mf_dimm_slot);
1008 
1009 		if (ret != 0) {
1010 			cmn_err(CE_WARN,
1011 			    "mc_ereport_post: Failed to determine the unum "
1012 			    "for board=%d bank=%d type=0x%x slot=0x%x",
1013 			    flt_stat->mf_flt_maddr.ma_bd, bank,
1014 			    flt_stat->mf_type, flt_stat->mf_dimm_slot);
1015 			continue;
1016 		}
1017 		n = strlen(device_path);
1018 		blen = MAXPATHLEN - n;
1019 		p = &device_path[n];
1020 		if (i < (nflts - 1)) {
1021 			snprintf(p, blen, " ");
1022 			blen--;
1023 			p++;
1024 		}
1025 
1026 		if (ret == 0) {
1027 			ret = mc_set_mem_sid(mc_aflt->mflt_mcp, s + strlen(s),
1028 			    blen, flt_stat->mf_flt_maddr.ma_phys_bd, bank,
1029 			    flt_stat->mf_type, flt_stat->mf_dimm_slot);
1030 
1031 		}
1032 	}
1033 
1034 	(void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION,
1035 		NULL, device_path, (ret == 0) ? sid : NULL,
1036 		(ret == 0) ? offset : (uint64_t)-1);
1037 
1038 	fm_payload_set(ereport, MC_OPL_RESOURCE, DATA_TYPE_NVLIST,
1039 		resource, NULL);
1040 
1041 	if (panicstr) {
1042 		errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC);
1043 	} else {
1044 		(void) fm_ereport_post(ereport, EVCH_TRYHARD);
1045 		fm_nvlist_destroy(ereport, FM_NVA_FREE);
1046 		fm_nvlist_destroy(detector, FM_NVA_FREE);
1047 		fm_nvlist_destroy(resource, FM_NVA_FREE);
1048 	}
1049 }
1050 
1051 
1052 static void
1053 mc_err_drain(mc_aflt_t *mc_aflt)
1054 {
1055 	int rv;
1056 	uint64_t pa = (uint64_t)(-1);
1057 	int i;
1058 
1059 	MC_LOG("mc_err_drain: %s\n",
1060 		mc_aflt->mflt_erpt_class);
1061 	/*
1062 	 * we come here only when we have:
1063 	 * In mirror mode: CMPE, MUE, SUE
1064 	 * In normal mode: UE, Permanent CE
1065 	 */
1066 	for (i = 0; i < mc_aflt->mflt_nflts; i++) {
1067 		rv = mcaddr_to_pa(mc_aflt->mflt_mcp,
1068 			&(mc_aflt->mflt_stat[i]->mf_flt_maddr), &pa);
1069 
1070 		/* Ensure the pa is valid (not in isolated memory block) */
1071 		if (rv == 0 && pa_is_valid(mc_aflt->mflt_mcp, pa))
1072 			mc_aflt->mflt_stat[i]->mf_flt_paddr = pa;
1073 		else
1074 			mc_aflt->mflt_stat[i]->mf_flt_paddr = (uint64_t)-1;
1075 	}
1076 
1077 	MC_LOG("mc_err_drain:pa = %lx\n", pa);
1078 
1079 	switch (page_retire_check(pa, NULL)) {
1080 	case 0:
1081 	case EAGAIN:
1082 		MC_LOG("Page retired or pending\n");
1083 		return;
1084 	case EIO:
1085 		/*
1086 		 * Do page retirement except for the PCE case.
1087 		 * This is taken care by the OPL DE
1088 		 */
1089 		if (mc_aflt->mflt_stat[0]->mf_type != FLT_TYPE_PERMANENT_CE) {
1090 			MC_LOG("offline page at pa %lx error %x\n", pa,
1091 				mc_aflt->mflt_pr);
1092 			(void) page_retire(pa, mc_aflt->mflt_pr);
1093 		}
1094 		break;
1095 	case EINVAL:
1096 	default:
1097 		/*
1098 		 * Some memory do not have page structure so
1099 		 * we keep going in case of EINVAL.
1100 		 */
1101 		break;
1102 	}
1103 
1104 	for (i = 0; i < mc_aflt->mflt_nflts; i++) {
1105 		mc_aflt_t mc_aflt0;
1106 		if (mc_aflt->mflt_stat[i]->mf_flt_paddr != (uint64_t)-1) {
1107 			mc_aflt0 = *mc_aflt;
1108 			mc_aflt0.mflt_nflts = 1;
1109 			mc_aflt0.mflt_stat[0] = mc_aflt->mflt_stat[i];
1110 			mc_ereport_post(&mc_aflt0);
1111 		}
1112 	}
1113 }
1114 
1115 /*
1116  * The restart address is actually defined in unit of PA[37:6]
1117  * the mac patrol will convert that to dimm offset.  If the
1118  * address is not in the bank, it will continue to search for
1119  * the next PA that is within the bank.
1120  *
1121  * Also the mac patrol scans the dimms based on PA, not
1122  * dimm offset.
1123  */
1124 static int
1125 restart_patrol(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr_info)
1126 {
1127 	uint64_t pa;
1128 	int rv;
1129 
1130 	if (rsaddr_info == NULL || (rsaddr_info->mi_valid == 0)) {
1131 		MAC_PTRL_START(mcp, bank);
1132 		return (0);
1133 	}
1134 
1135 	rv = mcaddr_to_pa(mcp, &rsaddr_info->mi_restartaddr, &pa);
1136 	if (rv != 0) {
1137 		MC_LOG("cannot convert mcaddr to pa. use auto restart\n");
1138 		MAC_PTRL_START(mcp, bank);
1139 		return (0);
1140 	}
1141 
1142 	if (!mc_rangecheck_pa(mcp, pa)) {
1143 		/* pa is not on this board, just retry */
1144 		cmn_err(CE_WARN, "restart_patrol: invalid address %lx "
1145 			"on board %d\n", pa, mcp->mc_board_num);
1146 		MAC_PTRL_START(mcp, bank);
1147 		return (0);
1148 	}
1149 
1150 	MC_LOG("restart_patrol: pa = %lx\n", pa);
1151 
1152 	if (!rsaddr_info->mi_injectrestart) {
1153 		/*
1154 		 * For non-errorinjection restart we need to
1155 		 * determine if the current restart pa/page is
1156 		 * a "good" page. A "good" page is a page that
1157 		 * has not been page retired. If the current
1158 		 * page that contains the pa is "good", we will
1159 		 * do a HW auto restart and let HW patrol continue
1160 		 * where it last stopped. Most desired scenario.
1161 		 *
1162 		 * If the current page is not "good", we will advance
1163 		 * to the next page to find the next "good" page and
1164 		 * restart the patrol from there.
1165 		 */
1166 		int wrapcount = 0;
1167 		uint64_t origpa = pa;
1168 		while (wrapcount < 2) {
1169 		    if (!pa_is_valid(mcp, pa)) {
1170 			/*
1171 			 * Not in physinstall - advance to the
1172 			 * next memory isolation blocksize
1173 			 */
1174 			MC_LOG("Invalid PA\n");
1175 			pa = roundup(pa + 1, mc_isolation_bsize);
1176 		    } else {
1177 			int rv;
1178 			if ((rv = page_retire_check(pa, NULL)) != 0 &&
1179 			    rv != EAGAIN) {
1180 				/*
1181 				 * The page is "good" (not retired), we will
1182 				 * use automatic HW restart algorithm if
1183 				 * this is the original current starting page
1184 				 */
1185 				if (pa == origpa) {
1186 				    MC_LOG("Page has no error. Auto restart\n");
1187 				    MAC_PTRL_START(mcp, bank);
1188 				    return (0);
1189 				} else {
1190 				    /* found a subsequent good page */
1191 				    break;
1192 				}
1193 			}
1194 
1195 			/*
1196 			 * Skip to the next page
1197 			 */
1198 			pa = roundup(pa + 1, PAGESIZE);
1199 			MC_LOG("Skipping bad page to %lx\n", pa);
1200 		    }
1201 
1202 		    /* Check to see if we hit the end of the memory range */
1203 		    if (pa >= (mcp->mc_start_address + mcp->mc_size)) {
1204 			MC_LOG("Wrap around\n");
1205 			pa = mcp->mc_start_address;
1206 			wrapcount++;
1207 		    }
1208 		}
1209 
1210 		if (wrapcount > 1) {
1211 		    MC_LOG("Failed to find a good page. Just restart\n");
1212 		    MAC_PTRL_START(mcp, bank);
1213 		    return (0);
1214 		}
1215 	}
1216 
1217 	/*
1218 	 * We reached here either:
1219 	 * 1. We are doing an error injection restart that specify
1220 	 *    the exact pa/page to restart. OR
1221 	 * 2. We found a subsequent good page different from the
1222 	 *    original restart pa/page.
1223 	 * Restart MAC patrol: PA[37:6]
1224 	 */
1225 	MC_LOG("restart at pa = %lx\n", pa);
1226 	ST_MAC_REG(MAC_RESTART_ADD(mcp, bank), MAC_RESTART_PA(pa));
1227 	MAC_PTRL_START_ADD(mcp, bank);
1228 
1229 	return (0);
1230 }
1231 
1232 /*
1233  * Rewriting is used for two purposes.
1234  *  - to correct the error in memory.
1235  *  - to determine whether the error is permanent or intermittent.
1236  * It's done by writing the address in MAC_BANKm_REWRITE_ADD
1237  * and issuing REW_REQ command in MAC_BANKm_PTRL_CNRL. After that,
1238  * REW_END (and REW_CE/REW_UE if some error detected) is set when
1239  * rewrite operation is done. See 4.7.3 and 4.7.11 in Columbus2 PRM.
1240  *
1241  * Note that rewrite operation doesn't change RAW_UE to Marked UE.
1242  * Therefore, we use it only CE case.
1243  */
1244 static uint32_t
1245 do_rewrite(mc_opl_t *mcp, int bank, uint32_t dimm_addr)
1246 {
1247 	uint32_t cntl;
1248 	int count = 0;
1249 
1250 	/* first wait to make sure PTRL_STATUS is 0 */
1251 	while (count++ < mc_max_rewrite_loop) {
1252 		cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank));
1253 		if (!(cntl & MAC_CNTL_PTRL_STATUS))
1254 			break;
1255 		drv_usecwait(mc_rewrite_delay);
1256 	}
1257 	if (count >= mc_max_rewrite_loop)
1258 		goto bad;
1259 
1260 	count = 0;
1261 
1262 	ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), dimm_addr);
1263 	MAC_REW_REQ(mcp, bank);
1264 
1265 	do {
1266 		cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank));
1267 		if (count++ >= mc_max_rewrite_loop) {
1268 			goto bad;
1269 		} else {
1270 			drv_usecwait(mc_rewrite_delay);
1271 		}
1272 	/*
1273 	 * If there are other MEMORY or PCI activities, this
1274 	 * will be BUSY, else it should be set immediately
1275 	 */
1276 	} while (!(cntl & MAC_CNTL_REW_END));
1277 
1278 	MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS);
1279 	return (cntl);
1280 bad:
1281 	/* This is bad.  Just reset the circuit */
1282 	cmn_err(CE_WARN, "mc-opl rewrite timeout on /LSB%d/B%d\n",
1283 		mcp->mc_board_num, bank);
1284 	cntl = MAC_CNTL_REW_END;
1285 	MAC_CMD(mcp, bank, MAC_CNTL_PTRL_RESET);
1286 	MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS);
1287 	return (cntl);
1288 }
1289 void
1290 mc_process_scf_log(mc_opl_t *mcp)
1291 {
1292 	int count;
1293 	int n = 0;
1294 	scf_log_t *p;
1295 	int bank;
1296 
1297 	for (bank = 0; bank < BANKNUM_PER_SB; bank++) {
1298 	    while ((p = mcp->mc_scf_log[bank]) != NULL &&
1299 		(n < mc_max_errlog_processed)) {
1300 		ASSERT(bank == p->sl_bank);
1301 		count = 0;
1302 		while ((LD_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank))
1303 			& MAC_STATIC_ERR_VLD)) {
1304 			if (count++ >= (mc_max_scf_loop)) {
1305 				break;
1306 			}
1307 			drv_usecwait(mc_scf_delay);
1308 		}
1309 
1310 		if (count < mc_max_scf_loop) {
1311 			ST_MAC_REG(MAC_STATIC_ERR_LOG(mcp, p->sl_bank),
1312 				p->sl_err_log);
1313 
1314 			ST_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank),
1315 				p->sl_err_add|MAC_STATIC_ERR_VLD);
1316 			mcp->mc_scf_retry[bank] = 0;
1317 		} else {
1318 			/* if we try too many times, just drop the req */
1319 			if (mcp->mc_scf_retry[bank]++ <= mc_max_scf_retry) {
1320 				return;
1321 			} else {
1322 			    if ((++mc_pce_dropped & 0xff) == 0) {
1323 				cmn_err(CE_WARN,
1324 				    "Cannot report Permanent CE to SCF\n");
1325 			    }
1326 			}
1327 		}
1328 		n++;
1329 		mcp->mc_scf_log[bank] = p->sl_next;
1330 		mcp->mc_scf_total[bank]--;
1331 		ASSERT(mcp->mc_scf_total[bank] >= 0);
1332 		kmem_free(p, sizeof (scf_log_t));
1333 	    }
1334 	}
1335 }
1336 void
1337 mc_queue_scf_log(mc_opl_t *mcp, mc_flt_stat_t *flt_stat, int bank)
1338 {
1339 	scf_log_t *p;
1340 
1341 	if (mcp->mc_scf_total[bank] >= mc_max_scf_logs) {
1342 		if ((++mc_pce_dropped & 0xff) == 0) {
1343 		    cmn_err(CE_WARN, "Too many Permanent CE requests.\n");
1344 		}
1345 		return;
1346 	}
1347 	p = kmem_zalloc(sizeof (scf_log_t), KM_SLEEP);
1348 	p->sl_next = 0;
1349 	p->sl_err_add = flt_stat->mf_err_add;
1350 	p->sl_err_log = flt_stat->mf_err_log;
1351 	p->sl_bank = bank;
1352 
1353 	if (mcp->mc_scf_log[bank] == NULL) {
1354 		/*
1355 		 * we rely on mc_scf_log to detect NULL queue.
1356 		 * mc_scf_log_tail is irrelevant is such case.
1357 		 */
1358 		mcp->mc_scf_log_tail[bank] = mcp->mc_scf_log[bank] = p;
1359 	} else {
1360 		mcp->mc_scf_log_tail[bank]->sl_next = p;
1361 		mcp->mc_scf_log_tail[bank] = p;
1362 	}
1363 	mcp->mc_scf_total[bank]++;
1364 }
1365 /*
1366  * This routine determines what kind of CE happens, intermittent
1367  * or permanent as follows. (See 4.7.3 in Columbus2 PRM.)
1368  * - Do rewrite by issuing REW_REQ command to MAC_PTRL_CNTL register.
1369  * - If CE is still detected on the same address even after doing
1370  *   rewrite operation twice, it is determined as permanent error.
1371  * - If error is not detected anymore, it is determined as intermittent
1372  *   error.
1373  * - If UE is detected due to rewrite operation, it should be treated
1374  *   as UE.
1375  */
1376 
1377 /* ARGSUSED */
1378 static void
1379 mc_scrub_ce(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat, int ptrl_error)
1380 {
1381 	uint32_t cntl;
1382 	int i;
1383 
1384 	flt_stat->mf_type = FLT_TYPE_PERMANENT_CE;
1385 	/*
1386 	 * rewrite request 1st time reads and correct error data
1387 	 * and write to DIMM.  2nd rewrite request must be issued
1388 	 * after REW_CE/UE/END is 0.  When the 2nd request is completed,
1389 	 * if REW_CE = 1, then it is permanent CE.
1390 	 */
1391 	for (i = 0; i < 2; i++) {
1392 		cntl = do_rewrite(mcp, bank, flt_stat->mf_err_add);
1393 		/*
1394 		 * If the error becomes UE or CMPE
1395 		 * we return to the caller immediately.
1396 		 */
1397 		if (cntl & MAC_CNTL_REW_UE) {
1398 			if (ptrl_error)
1399 				flt_stat->mf_cntl |= MAC_CNTL_PTRL_UE;
1400 			else
1401 				flt_stat->mf_cntl |= MAC_CNTL_MI_UE;
1402 			flt_stat->mf_type = FLT_TYPE_UE;
1403 			return;
1404 		}
1405 		if (cntl & MAC_CNTL_REW_CMPE) {
1406 			if (ptrl_error)
1407 				flt_stat->mf_cntl |= MAC_CNTL_PTRL_CMPE;
1408 			else
1409 				flt_stat->mf_cntl |= MAC_CNTL_MI_CMPE;
1410 			flt_stat->mf_type = FLT_TYPE_CMPE;
1411 			return;
1412 		}
1413 	}
1414 	if (!(cntl & MAC_CNTL_REW_CE)) {
1415 		flt_stat->mf_type = FLT_TYPE_INTERMITTENT_CE;
1416 	}
1417 
1418 	if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) {
1419 		/* report PERMANENT_CE to SP via SCF */
1420 		if (!(flt_stat->mf_err_log & MAC_ERR_LOG_INVALID)) {
1421 			mc_queue_scf_log(mcp, flt_stat, bank);
1422 		}
1423 	}
1424 }
1425 
1426 #define	IS_CMPE(cntl, f)	((cntl) & ((f) ? MAC_CNTL_PTRL_CMPE :\
1427 				MAC_CNTL_MI_CMPE))
1428 #define	IS_UE(cntl, f)	((cntl) & ((f) ? MAC_CNTL_PTRL_UE : MAC_CNTL_MI_UE))
1429 #define	IS_CE(cntl, f)	((cntl) & ((f) ? MAC_CNTL_PTRL_CE : MAC_CNTL_MI_CE))
1430 #define	IS_OK(cntl, f)	(!((cntl) & ((f) ? MAC_CNTL_PTRL_ERRS : \
1431 			MAC_CNTL_MI_ERRS)))
1432 
1433 
1434 static int
1435 IS_CE_ONLY(uint32_t cntl, int ptrl_error)
1436 {
1437 	if (ptrl_error) {
1438 		return ((cntl & MAC_CNTL_PTRL_ERRS) == MAC_CNTL_PTRL_CE);
1439 	} else {
1440 		return ((cntl & MAC_CNTL_MI_ERRS) == MAC_CNTL_MI_CE);
1441 	}
1442 }
1443 
1444 void
1445 mc_write_cntl(mc_opl_t *mcp, int bank, uint32_t value)
1446 {
1447 	int ebank = (IS_MIRROR(mcp, bank)) ? MIRROR_IDX(bank) : bank;
1448 
1449 	if (mcp->mc_speedup_period[ebank] > 0)
1450 		value |= mc_max_speed;
1451 	else
1452 		value |= mcp->mc_speed;
1453 	ST_MAC_REG(MAC_PTRL_CNTL(mcp, bank), value);
1454 }
1455 
1456 static void
1457 mc_read_ptrl_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat)
1458 {
1459 	flt_stat->mf_cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) &
1460 		MAC_CNTL_PTRL_ERRS;
1461 	flt_stat->mf_err_add = LD_MAC_REG(MAC_PTRL_ERR_ADD(mcp, bank));
1462 	flt_stat->mf_err_log = LD_MAC_REG(MAC_PTRL_ERR_LOG(mcp, bank));
1463 	flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num;
1464 	flt_stat->mf_flt_maddr.ma_phys_bd = mcp->mc_phys_board_num;
1465 	flt_stat->mf_flt_maddr.ma_bank = bank;
1466 	flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add;
1467 }
1468 
1469 static void
1470 mc_read_mi_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat)
1471 {
1472 	uint32_t status, old_status;
1473 
1474 	status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) &
1475 		MAC_CNTL_MI_ERRS;
1476 	old_status = 0;
1477 
1478 	/* we keep reading until the status is stable */
1479 	while (old_status != status) {
1480 		old_status = status;
1481 		flt_stat->mf_err_add =
1482 			LD_MAC_REG(MAC_MI_ERR_ADD(mcp, bank));
1483 		flt_stat->mf_err_log =
1484 			LD_MAC_REG(MAC_MI_ERR_LOG(mcp, bank));
1485 		status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) &
1486 			MAC_CNTL_MI_ERRS;
1487 		if (status == old_status) {
1488 			break;
1489 		}
1490 	}
1491 
1492 	flt_stat->mf_cntl = status;
1493 	flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num;
1494 	flt_stat->mf_flt_maddr.ma_phys_bd = mcp->mc_phys_board_num;
1495 	flt_stat->mf_flt_maddr.ma_bank = bank;
1496 	flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add;
1497 }
1498 
1499 
1500 /*
1501  * Error philosophy for mirror mode:
1502  *
1503  * PTRL (The error address for both banks are same, since ptrl stops if it
1504  * detects error.)
1505  * - Compaire error  Report CMPE.
1506  *
1507  * - UE-UE           Report MUE.  No rewrite.
1508  *
1509  * - UE-*	     UE-(CE/OK). Rewrite to scrub UE.  Report SUE.
1510  *
1511  * - CE-*            CE-(CE/OK). Scrub to determine if CE is permanent.
1512  *                   If CE is permanent, inform SCF.  Once for each
1513  *		     Dimm.  If CE becomes UE or CMPE, go back to above.
1514  *
1515  *
1516  * MI (The error addresses for each bank are the same or different.)
1517  * - Compair  error  If addresses are the same.  Just CMPE.
1518  *		     If addresses are different (this could happen
1519  *		     as a result of scrubbing.  Report each seperately.
1520  *		     Only report error info on each side.
1521  *
1522  * - UE-UE           Addresses are the same.  Report MUE.
1523  *		     Addresses are different.  Report SUE on each bank.
1524  *		     Rewrite to clear UE.
1525  *
1526  * - UE-*	     UE-(CE/OK)
1527  *		     Rewrite to clear UE.  Report SUE for the bank.
1528  *
1529  * - CE-*            CE-(CE/OK).  Scrub to determine if CE is permanent.
1530  *                   If CE becomes UE or CMPE, go back to above.
1531  *
1532  */
1533 
1534 static int
1535 mc_process_error_mir(mc_opl_t *mcp, mc_aflt_t *mc_aflt, mc_flt_stat_t *flt_stat)
1536 {
1537 	int ptrl_error = mc_aflt->mflt_is_ptrl;
1538 	int i;
1539 	int rv = 0;
1540 
1541 	MC_LOG("process mirror errors cntl[0] = %x, cntl[1] = %x\n",
1542 		flt_stat[0].mf_cntl, flt_stat[1].mf_cntl);
1543 
1544 	if (ptrl_error) {
1545 		if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl)
1546 			& MAC_CNTL_PTRL_ERRS) == 0)
1547 			return (0);
1548 	} else {
1549 		if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl)
1550 			& MAC_CNTL_MI_ERRS) == 0)
1551 			return (0);
1552 	}
1553 
1554 	/*
1555 	 * First we take care of the case of CE
1556 	 * because they can become UE or CMPE
1557 	 */
1558 	for (i = 0; i < 2; i++) {
1559 		if (IS_CE_ONLY(flt_stat[i].mf_cntl, ptrl_error)) {
1560 			MC_LOG("CE detected on bank %d\n",
1561 				flt_stat[i].mf_flt_maddr.ma_bank);
1562 			mc_scrub_ce(mcp, flt_stat[i].mf_flt_maddr.ma_bank,
1563 				&flt_stat[i], ptrl_error);
1564 			rv = 1;
1565 		}
1566 	}
1567 
1568 	/* The above scrubbing can turn CE into UE or CMPE */
1569 
1570 	/*
1571 	 * Now we distinguish two cases: same address or not
1572 	 * the same address.  It might seem more intuitive to
1573 	 * distinguish PTRL v.s. MI error but it is more
1574 	 * complicated that way.
1575 	 */
1576 
1577 	if (flt_stat[0].mf_err_add == flt_stat[1].mf_err_add) {
1578 
1579 		if (IS_CMPE(flt_stat[0].mf_cntl, ptrl_error) ||
1580 		    IS_CMPE(flt_stat[1].mf_cntl, ptrl_error)) {
1581 			flt_stat[0].mf_type = FLT_TYPE_CMPE;
1582 			flt_stat[1].mf_type = FLT_TYPE_CMPE;
1583 			mc_aflt->mflt_erpt_class = MC_OPL_CMPE;
1584 			MC_LOG("cmpe error detected\n");
1585 			mc_aflt->mflt_nflts = 2;
1586 			mc_aflt->mflt_stat[0] = &flt_stat[0];
1587 			mc_aflt->mflt_stat[1] = &flt_stat[1];
1588 			mc_aflt->mflt_pr = PR_UE;
1589 			mc_err_drain(mc_aflt);
1590 			return (1);
1591 		}
1592 
1593 		if (IS_UE(flt_stat[0].mf_cntl, ptrl_error) &&
1594 			IS_UE(flt_stat[1].mf_cntl, ptrl_error)) {
1595 			/* Both side are UE's */
1596 
1597 			MAC_SET_ERRLOG_INFO(&flt_stat[0]);
1598 			MAC_SET_ERRLOG_INFO(&flt_stat[1]);
1599 			MC_LOG("MUE detected\n");
1600 			flt_stat[0].mf_type = FLT_TYPE_MUE;
1601 			flt_stat[1].mf_type = FLT_TYPE_MUE;
1602 			mc_aflt->mflt_erpt_class = MC_OPL_MUE;
1603 			mc_aflt->mflt_nflts = 2;
1604 			mc_aflt->mflt_stat[0] = &flt_stat[0];
1605 			mc_aflt->mflt_stat[1] = &flt_stat[1];
1606 			mc_aflt->mflt_pr = PR_UE;
1607 			mc_err_drain(mc_aflt);
1608 			return (1);
1609 		}
1610 
1611 		/* Now the only case is UE/CE, UE/OK, or don't care */
1612 		for (i = 0; i < 2; i++) {
1613 		    if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) {
1614 
1615 			/* rewrite can clear the one side UE error */
1616 
1617 			if (IS_OK(flt_stat[i^1].mf_cntl, ptrl_error)) {
1618 				(void) do_rewrite(mcp,
1619 				    flt_stat[i].mf_flt_maddr.ma_bank,
1620 				    flt_stat[i].mf_flt_maddr.ma_dimm_addr);
1621 			}
1622 			flt_stat[i].mf_type = FLT_TYPE_UE;
1623 			MAC_SET_ERRLOG_INFO(&flt_stat[i]);
1624 			mc_aflt->mflt_erpt_class = MC_OPL_SUE;
1625 			mc_aflt->mflt_stat[0] = &flt_stat[i];
1626 			mc_aflt->mflt_nflts = 1;
1627 			mc_aflt->mflt_pr = PR_MCE;
1628 			mc_err_drain(mc_aflt);
1629 			/* Once we hit a UE/CE or UE/OK case, done */
1630 			return (1);
1631 		    }
1632 		}
1633 
1634 	} else {
1635 		/*
1636 		 * addresses are different. That means errors
1637 		 * on the 2 banks are not related at all.
1638 		 */
1639 		for (i = 0; i < 2; i++) {
1640 		    if (IS_CMPE(flt_stat[i].mf_cntl, ptrl_error)) {
1641 			flt_stat[i].mf_type = FLT_TYPE_CMPE;
1642 			mc_aflt->mflt_erpt_class = MC_OPL_CMPE;
1643 			MC_LOG("cmpe error detected\n");
1644 			mc_aflt->mflt_nflts = 1;
1645 			mc_aflt->mflt_stat[0] = &flt_stat[i];
1646 			mc_aflt->mflt_pr = PR_UE;
1647 			mc_err_drain(mc_aflt);
1648 			/* no more report on this bank */
1649 			flt_stat[i].mf_cntl = 0;
1650 			rv = 1;
1651 		    }
1652 		}
1653 
1654 		/* rewrite can clear the one side UE error */
1655 
1656 		for (i = 0; i < 2; i++) {
1657 		    if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) {
1658 			(void) do_rewrite(mcp,
1659 				flt_stat[i].mf_flt_maddr.ma_bank,
1660 				flt_stat[i].mf_flt_maddr.ma_dimm_addr);
1661 			flt_stat[i].mf_type = FLT_TYPE_UE;
1662 			MAC_SET_ERRLOG_INFO(&flt_stat[i]);
1663 			mc_aflt->mflt_erpt_class = MC_OPL_SUE;
1664 			mc_aflt->mflt_stat[0] = &flt_stat[i];
1665 			mc_aflt->mflt_nflts = 1;
1666 			mc_aflt->mflt_pr = PR_MCE;
1667 			mc_err_drain(mc_aflt);
1668 			rv = 1;
1669 		    }
1670 		}
1671 	}
1672 	return (rv);
1673 }
1674 static void
1675 mc_error_handler_mir(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr)
1676 {
1677 	mc_aflt_t mc_aflt;
1678 	mc_flt_stat_t flt_stat[2], mi_flt_stat[2];
1679 	int i;
1680 	int mi_valid;
1681 
1682 	ASSERT(rsaddr);
1683 
1684 	bzero(&mc_aflt, sizeof (mc_aflt_t));
1685 	bzero(&flt_stat, 2 * sizeof (mc_flt_stat_t));
1686 	bzero(&mi_flt_stat, 2 * sizeof (mc_flt_stat_t));
1687 
1688 	mc_aflt.mflt_mcp = mcp;
1689 	mc_aflt.mflt_id = gethrtime();
1690 
1691 	/* Now read all the registers into flt_stat */
1692 
1693 	for (i = 0; i < 2; i++) {
1694 		MC_LOG("Reading registers of bank %d\n", bank);
1695 		/* patrol registers */
1696 		mc_read_ptrl_reg(mcp, bank, &flt_stat[i]);
1697 
1698 		/*
1699 		 * In mirror mode, it is possible that only one bank
1700 		 * may report the error. We need to check for it to
1701 		 * ensure we pick the right addr value for patrol restart.
1702 		 * Note that if both banks reported errors, we pick the
1703 		 * 2nd one. Both banks should reported the same error address.
1704 		 */
1705 		if (flt_stat[i].mf_cntl & MAC_CNTL_PTRL_ERRS)
1706 			rsaddr->mi_restartaddr = flt_stat[i].mf_flt_maddr;
1707 
1708 		MC_LOG("ptrl registers cntl %x add %x log %x\n",
1709 			flt_stat[i].mf_cntl,
1710 			flt_stat[i].mf_err_add,
1711 			flt_stat[i].mf_err_log);
1712 
1713 		/* MI registers */
1714 		mc_read_mi_reg(mcp, bank, &mi_flt_stat[i]);
1715 
1716 		MC_LOG("MI registers cntl %x add %x log %x\n",
1717 			mi_flt_stat[i].mf_cntl,
1718 			mi_flt_stat[i].mf_err_add,
1719 			mi_flt_stat[i].mf_err_log);
1720 
1721 		bank = bank^1;
1722 	}
1723 
1724 	/* clear errors once we read all the registers */
1725 	MAC_CLEAR_ERRS(mcp, bank,
1726 		(MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS));
1727 
1728 	MAC_CLEAR_ERRS(mcp, bank ^ 1, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS));
1729 
1730 	/* Process MI errors first */
1731 
1732 	/* if not error mode, cntl1 is 0 */
1733 	if ((mi_flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) ||
1734 		(mi_flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID))
1735 		mi_flt_stat[0].mf_cntl = 0;
1736 
1737 	if ((mi_flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) ||
1738 		(mi_flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID))
1739 		mi_flt_stat[1].mf_cntl = 0;
1740 
1741 	mc_aflt.mflt_is_ptrl = 0;
1742 	mi_valid = mc_process_error_mir(mcp, &mc_aflt, &mi_flt_stat[0]);
1743 
1744 	if ((((flt_stat[0].mf_cntl & MAC_CNTL_PTRL_ERRS) >>
1745 		MAC_CNTL_PTRL_ERR_SHIFT) ==
1746 		((mi_flt_stat[0].mf_cntl & MAC_CNTL_MI_ERRS) >>
1747 		MAC_CNTL_MI_ERR_SHIFT)) &&
1748 		(flt_stat[0].mf_err_add == mi_flt_stat[0].mf_err_add) &&
1749 		(((flt_stat[1].mf_cntl & MAC_CNTL_PTRL_ERRS) >>
1750 		MAC_CNTL_PTRL_ERR_SHIFT) ==
1751 		((mi_flt_stat[1].mf_cntl & MAC_CNTL_MI_ERRS) >>
1752 		MAC_CNTL_MI_ERR_SHIFT)) &&
1753 		(flt_stat[1].mf_err_add == mi_flt_stat[1].mf_err_add)) {
1754 #ifdef DEBUG
1755 		MC_LOG("discarding PTRL error because "
1756 		    "it is the same as MI\n");
1757 #endif
1758 		rsaddr->mi_valid = mi_valid;
1759 		return;
1760 	}
1761 	/* if not error mode, cntl1 is 0 */
1762 	if ((flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) ||
1763 		(flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID))
1764 		flt_stat[0].mf_cntl = 0;
1765 
1766 	if ((flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) ||
1767 		(flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID))
1768 		flt_stat[1].mf_cntl = 0;
1769 
1770 	mc_aflt.mflt_is_ptrl = 1;
1771 	rsaddr->mi_valid = mc_process_error_mir(mcp, &mc_aflt, &flt_stat[0]);
1772 }
1773 static int
1774 mc_process_error(mc_opl_t *mcp, int bank, mc_aflt_t *mc_aflt,
1775 	mc_flt_stat_t *flt_stat)
1776 {
1777 	int ptrl_error = mc_aflt->mflt_is_ptrl;
1778 	int rv = 0;
1779 
1780 	mc_aflt->mflt_erpt_class = NULL;
1781 	if (IS_UE(flt_stat->mf_cntl, ptrl_error)) {
1782 		MC_LOG("UE deteceted\n");
1783 		flt_stat->mf_type = FLT_TYPE_UE;
1784 		mc_aflt->mflt_erpt_class = MC_OPL_UE;
1785 		mc_aflt->mflt_pr = PR_UE;
1786 		MAC_SET_ERRLOG_INFO(flt_stat);
1787 		rv = 1;
1788 	} else if (IS_CE(flt_stat->mf_cntl, ptrl_error)) {
1789 		MC_LOG("CE deteceted\n");
1790 		MAC_SET_ERRLOG_INFO(flt_stat);
1791 
1792 		/* Error type can change after scrubing */
1793 		mc_scrub_ce(mcp, bank, flt_stat, ptrl_error);
1794 
1795 		if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) {
1796 			mc_aflt->mflt_erpt_class = MC_OPL_CE;
1797 			mc_aflt->mflt_pr = PR_MCE;
1798 		} else if (flt_stat->mf_type == FLT_TYPE_UE) {
1799 			mc_aflt->mflt_erpt_class = MC_OPL_UE;
1800 			mc_aflt->mflt_pr = PR_UE;
1801 		}
1802 		rv = 1;
1803 	}
1804 	MC_LOG("mc_process_error: fault type %x erpt %s\n",
1805 		flt_stat->mf_type,
1806 		mc_aflt->mflt_erpt_class);
1807 	if (mc_aflt->mflt_erpt_class) {
1808 		mc_aflt->mflt_stat[0] = flt_stat;
1809 		mc_aflt->mflt_nflts = 1;
1810 		mc_err_drain(mc_aflt);
1811 	}
1812 	return (rv);
1813 }
1814 
1815 static void
1816 mc_error_handler(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr)
1817 {
1818 	mc_aflt_t mc_aflt;
1819 	mc_flt_stat_t flt_stat, mi_flt_stat;
1820 	int mi_valid;
1821 
1822 	bzero(&mc_aflt, sizeof (mc_aflt_t));
1823 	bzero(&flt_stat, sizeof (mc_flt_stat_t));
1824 	bzero(&mi_flt_stat, sizeof (mc_flt_stat_t));
1825 
1826 	mc_aflt.mflt_mcp = mcp;
1827 	mc_aflt.mflt_id = gethrtime();
1828 
1829 	/* patrol registers */
1830 	mc_read_ptrl_reg(mcp, bank, &flt_stat);
1831 
1832 	ASSERT(rsaddr);
1833 	rsaddr->mi_restartaddr = flt_stat.mf_flt_maddr;
1834 
1835 	MC_LOG("ptrl registers cntl %x add %x log %x\n",
1836 		flt_stat.mf_cntl,
1837 		flt_stat.mf_err_add,
1838 		flt_stat.mf_err_log);
1839 
1840 	/* MI registers */
1841 	mc_read_mi_reg(mcp, bank, &mi_flt_stat);
1842 
1843 
1844 	MC_LOG("MI registers cntl %x add %x log %x\n",
1845 		mi_flt_stat.mf_cntl,
1846 		mi_flt_stat.mf_err_add,
1847 		mi_flt_stat.mf_err_log);
1848 
1849 	/* clear errors once we read all the registers */
1850 	MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS));
1851 
1852 	mc_aflt.mflt_is_ptrl = 0;
1853 	if ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) &&
1854 		((mi_flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) &&
1855 		((mi_flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) {
1856 		mi_valid = mc_process_error(mcp, bank, &mc_aflt, &mi_flt_stat);
1857 	}
1858 
1859 	if ((((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) >>
1860 		MAC_CNTL_PTRL_ERR_SHIFT) ==
1861 		((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) >>
1862 		MAC_CNTL_MI_ERR_SHIFT)) &&
1863 		(flt_stat.mf_err_add == mi_flt_stat.mf_err_add)) {
1864 #ifdef DEBUG
1865 		MC_LOG("discarding PTRL error because "
1866 		    "it is the same as MI\n");
1867 #endif
1868 		rsaddr->mi_valid = mi_valid;
1869 		return;
1870 	}
1871 
1872 	mc_aflt.mflt_is_ptrl = 1;
1873 	if ((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) &&
1874 		((flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) &&
1875 		((flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) {
1876 		rsaddr->mi_valid = mc_process_error(mcp, bank,
1877 			&mc_aflt, &flt_stat);
1878 	}
1879 }
1880 /*
1881  *	memory patrol error handling algorithm:
1882  *	timeout() is used to do periodic polling
1883  *	This is the flow chart.
1884  *	timeout ->
1885  *	mc_check_errors()
1886  *	    if memory bank is installed, read the status register
1887  *	    if any error bit is set,
1888  *	    -> mc_error_handler()
1889  *		-> read all error regsiters
1890  *	        -> mc_process_error()
1891  *	            determine error type
1892  *	            rewrite to clear error or scrub to determine CE type
1893  *	            inform SCF on permanent CE
1894  *	        -> mc_err_drain
1895  *	            page offline processing
1896  *	            -> mc_ereport_post()
1897  */
1898 
1899 static void
1900 mc_check_errors_func(mc_opl_t *mcp)
1901 {
1902 	mc_rsaddr_info_t rsaddr_info;
1903 	int i, error_count = 0;
1904 	uint32_t stat, cntl;
1905 	int running;
1906 	int wrapped;
1907 	int ebk;
1908 
1909 	/*
1910 	 * scan errors.
1911 	 */
1912 	if (mcp->mc_status & MC_MEMORYLESS)
1913 		return;
1914 
1915 	for (i = 0; i < BANKNUM_PER_SB; i++) {
1916 		if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) {
1917 			stat = ldphysio(MAC_PTRL_STAT(mcp, i));
1918 			cntl = ldphysio(MAC_PTRL_CNTL(mcp, i));
1919 			running = cntl & MAC_CNTL_PTRL_START;
1920 			wrapped = cntl & MAC_CNTL_PTRL_ADD_MAX;
1921 
1922 			/* Compute the effective bank idx */
1923 			ebk = (IS_MIRROR(mcp, i)) ? MIRROR_IDX(i) : i;
1924 
1925 			if (mc_debug_show_all || stat) {
1926 				MC_LOG("/LSB%d/B%d stat %x cntl %x\n",
1927 					mcp->mc_board_num, i,
1928 					stat, cntl);
1929 			}
1930 
1931 			/*
1932 			 * Update stats and reset flag if the HW patrol
1933 			 * wrapped around in its scan.
1934 			 */
1935 			if (wrapped) {
1936 				MAC_CLEAR_MAX(mcp, i);
1937 				mcp->mc_period[ebk]++;
1938 				if (IS_MIRROR(mcp, i))
1939 				    MC_LOG("mirror mc period %ld on "
1940 					"/LSB%d/B%d\n", mcp->mc_period[ebk],
1941 					mcp->mc_board_num, i);
1942 				else {
1943 				    MC_LOG("mc period %ld on "
1944 					"/LSB%d/B%d\n", mcp->mc_period[ebk],
1945 					mcp->mc_board_num, i);
1946 				}
1947 			}
1948 
1949 			if (running) {
1950 				/*
1951 				 * Mac patrol HW is still running.
1952 				 * Normally when an error is detected,
1953 				 * the HW patrol will stop so that we
1954 				 * can collect error data for reporting.
1955 				 * Certain errors (MI errors) detected may not
1956 				 * cause the HW patrol to stop which is a
1957 				 * problem since we cannot read error data while
1958 				 * the HW patrol is running. SW is not allowed
1959 				 * to stop the HW patrol while it is running
1960 				 * as it may cause HW inconsistency. This is
1961 				 * described in a HW errata.
1962 				 * In situations where we detected errors
1963 				 * that may not cause the HW patrol to stop.
1964 				 * We speed up the HW patrol scanning in
1965 				 * the hope that it will find the 'real' PTRL
1966 				 * errors associated with the previous errors
1967 				 * causing the HW to finally stop so that we
1968 				 * can do the reporting.
1969 				 */
1970 				/*
1971 				 * Check to see if we did speed up
1972 				 * the HW patrol due to previous errors
1973 				 * detected that did not cause the patrol
1974 				 * to stop. We only do it if HW patrol scan
1975 				 * wrapped (counted as completing a 'period').
1976 				 */
1977 				if (mcp->mc_speedup_period[ebk] > 0) {
1978 				    if (wrapped &&
1979 					(--mcp->mc_speedup_period[ebk] == 0)) {
1980 					/*
1981 					 * We did try to speed up.
1982 					 * The speed up period has expired
1983 					 * and the HW patrol is still running.
1984 					 * The errors must be intermittent.
1985 					 * We have no choice but to ignore
1986 					 * them, reset the scan speed to normal
1987 					 * and clear the MI error bits. For
1988 					 * mirror mode, we need to clear errors
1989 					 * on both banks.
1990 					 */
1991 					MC_LOG("Clearing MI errors\n");
1992 					MAC_CLEAR_ERRS(mcp, i,
1993 					    MAC_CNTL_MI_ERRS);
1994 
1995 					if (IS_MIRROR(mcp, i)) {
1996 					    MC_LOG("Clearing Mirror MI errs\n");
1997 					    MAC_CLEAR_ERRS(mcp, i^1,
1998 						MAC_CNTL_MI_ERRS);
1999 					}
2000 				    }
2001 				} else if (stat & MAC_STAT_MI_ERRS) {
2002 					/*
2003 					 * MI errors detected but we cannot
2004 					 * report them since the HW patrol
2005 					 * is still running.
2006 					 * We will attempt to speed up the
2007 					 * scanning and hopefully the HW
2008 					 * can detect PRTL errors at the same
2009 					 * location that cause the HW patrol
2010 					 * to stop.
2011 					 */
2012 					mcp->mc_speedup_period[ebk] = 2;
2013 					MAC_CMD(mcp, i, 0);
2014 				}
2015 			} else if (stat & (MAC_STAT_PTRL_ERRS |
2016 			    MAC_STAT_MI_ERRS)) {
2017 				/*
2018 				 * HW Patrol has stopped and we found errors.
2019 				 * Proceed to collect and report error info.
2020 				 */
2021 				mcp->mc_speedup_period[ebk] = 0;
2022 				rsaddr_info.mi_valid = 0;
2023 				rsaddr_info.mi_injectrestart = 0;
2024 				if (IS_MIRROR(mcp, i)) {
2025 				    mc_error_handler_mir(mcp, i, &rsaddr_info);
2026 				} else {
2027 				    mc_error_handler(mcp, i, &rsaddr_info);
2028 				}
2029 
2030 				error_count++;
2031 				restart_patrol(mcp, i, &rsaddr_info);
2032 			} else {
2033 				/*
2034 				 * HW patrol scan has apparently stopped
2035 				 * but no errors detected/flagged.
2036 				 * Restart the HW patrol just to be sure.
2037 				 * In mirror mode, the odd bank might have
2038 				 * reported errors that caused the patrol to
2039 				 * stop. We'll defer the restart to the odd
2040 				 * bank in this case.
2041 				 */
2042 				if (!IS_MIRROR(mcp, i) || (i & 0x1))
2043 					restart_patrol(mcp, i, NULL);
2044 			}
2045 		}
2046 	}
2047 	if (error_count > 0)
2048 		mcp->mc_last_error += error_count;
2049 	else
2050 		mcp->mc_last_error = 0;
2051 }
2052 
2053 /*
2054  * mc_polling -- Check errors for only one instance,
2055  * but process errors for all instances to make sure we drain the errors
2056  * faster than they can be accumulated.
2057  *
2058  * Polling on each board should be done only once per each
2059  * mc_patrol_interval_sec.  This is equivalent to setting mc_tick_left
2060  * to OPL_MAX_BOARDS and decrement by 1 on each timeout.
2061  * Once mc_tick_left becomes negative, the board becomes a candidate
2062  * for polling because it has waited for at least
2063  * mc_patrol_interval_sec's long.    If mc_timeout_period is calculated
2064  * differently, this has to beupdated accordingly.
2065  */
2066 
2067 static void
2068 mc_polling(void)
2069 {
2070 	int i, scan_error;
2071 	mc_opl_t *mcp;
2072 
2073 
2074 	scan_error = 1;
2075 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
2076 		mutex_enter(&mcmutex);
2077 		if ((mcp = mc_instances[i]) == NULL) {
2078 			mutex_exit(&mcmutex);
2079 			continue;
2080 		}
2081 		mutex_enter(&mcp->mc_lock);
2082 		mutex_exit(&mcmutex);
2083 		if (!(mcp->mc_status & MC_POLL_RUNNING)) {
2084 			mutex_exit(&mcp->mc_lock);
2085 			continue;
2086 		}
2087 		if (scan_error && mcp->mc_tick_left <= 0) {
2088 			mc_check_errors_func((void *)mcp);
2089 			mcp->mc_tick_left = OPL_MAX_BOARDS;
2090 			scan_error = 0;
2091 		} else {
2092 			mcp->mc_tick_left--;
2093 		}
2094 		mc_process_scf_log(mcp);
2095 		mutex_exit(&mcp->mc_lock);
2096 	}
2097 }
2098 
2099 static void
2100 get_ptrl_start_address(mc_opl_t *mcp, int bank, mc_addr_t *maddr)
2101 {
2102 	maddr->ma_bd = mcp->mc_board_num;
2103 	maddr->ma_bank = bank;
2104 	maddr->ma_dimm_addr = 0;
2105 }
2106 
2107 typedef struct mc_mem_range {
2108 	uint64_t	addr;
2109 	uint64_t	size;
2110 } mc_mem_range_t;
2111 
2112 static int
2113 get_base_address(mc_opl_t *mcp)
2114 {
2115 	mc_mem_range_t *mem_range;
2116 	int len;
2117 
2118 	if (ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS,
2119 		"sb-mem-ranges", (caddr_t)&mem_range, &len) != DDI_SUCCESS) {
2120 		return (DDI_FAILURE);
2121 	}
2122 
2123 	mcp->mc_start_address = mem_range->addr;
2124 	mcp->mc_size = mem_range->size;
2125 
2126 	kmem_free(mem_range, len);
2127 	return (DDI_SUCCESS);
2128 }
2129 
2130 struct mc_addr_spec {
2131 	uint32_t bank;
2132 	uint32_t phys_hi;
2133 	uint32_t phys_lo;
2134 };
2135 
2136 #define	REGS_PA(m, i) ((((uint64_t)m[i].phys_hi)<<32) | m[i].phys_lo)
2137 
2138 static char *mc_tbl_name[] = {
2139 	"cs0-mc-pa-trans-table",
2140 	"cs1-mc-pa-trans-table"
2141 };
2142 
2143 /*
2144  * This routine performs a rangecheck for a given PA
2145  * to see if it belongs to the memory range for this board.
2146  * Return 1 if it is valid (within the range) and 0 otherwise
2147  */
2148 static int
2149 mc_rangecheck_pa(mc_opl_t *mcp, uint64_t pa)
2150 {
2151 	if ((pa < mcp->mc_start_address) ||
2152 		(mcp->mc_start_address + mcp->mc_size <= pa))
2153 		return (0);
2154 	else
2155 		return (1);
2156 }
2157 
2158 static void
2159 mc_memlist_delete(struct memlist *mlist)
2160 {
2161 	struct memlist *ml;
2162 
2163 	for (ml = mlist; ml; ml = mlist) {
2164 		mlist = ml->next;
2165 		kmem_free(ml, sizeof (struct memlist));
2166 	}
2167 }
2168 
2169 static struct memlist *
2170 mc_memlist_dup(struct memlist *mlist)
2171 {
2172 	struct memlist *hl = NULL, *tl, **mlp;
2173 
2174 	if (mlist == NULL)
2175 		return (NULL);
2176 
2177 	mlp = &hl;
2178 	tl = *mlp;
2179 	for (; mlist; mlist = mlist->next) {
2180 		*mlp = kmem_alloc(sizeof (struct memlist), KM_SLEEP);
2181 		(*mlp)->address = mlist->address;
2182 		(*mlp)->size = mlist->size;
2183 		(*mlp)->prev = tl;
2184 		tl = *mlp;
2185 		mlp = &((*mlp)->next);
2186 	}
2187 	*mlp = NULL;
2188 
2189 	return (hl);
2190 }
2191 
2192 
2193 static struct memlist *
2194 mc_memlist_del_span(struct memlist *mlist, uint64_t base, uint64_t len)
2195 {
2196 	uint64_t	end;
2197 	struct memlist	*ml, *tl, *nlp;
2198 
2199 	if (mlist == NULL)
2200 		return (NULL);
2201 
2202 	end = base + len;
2203 	if ((end <= mlist->address) || (base == end))
2204 		return (mlist);
2205 
2206 	for (tl = ml = mlist; ml; tl = ml, ml = nlp) {
2207 		uint64_t	mend;
2208 
2209 		nlp = ml->next;
2210 
2211 		if (end <= ml->address)
2212 			break;
2213 
2214 		mend = ml->address + ml->size;
2215 		if (base < mend) {
2216 			if (base <= ml->address) {
2217 				ml->address = end;
2218 				if (end >= mend)
2219 					ml->size = 0ull;
2220 				else
2221 					ml->size = mend - ml->address;
2222 			} else {
2223 				ml->size = base - ml->address;
2224 				if (end < mend) {
2225 					struct memlist	*nl;
2226 					/*
2227 					 * splitting an memlist entry.
2228 					 */
2229 					nl = kmem_alloc(sizeof (struct memlist),
2230 						KM_SLEEP);
2231 					nl->address = end;
2232 					nl->size = mend - nl->address;
2233 					if ((nl->next = nlp) != NULL)
2234 						nlp->prev = nl;
2235 					nl->prev = ml;
2236 					ml->next = nl;
2237 					nlp = nl;
2238 				}
2239 			}
2240 			if (ml->size == 0ull) {
2241 				if (ml == mlist) {
2242 					if ((mlist = nlp) != NULL)
2243 						nlp->prev = NULL;
2244 					kmem_free(ml, sizeof (struct memlist));
2245 					if (mlist == NULL)
2246 						break;
2247 					ml = nlp;
2248 				} else {
2249 					if ((tl->next = nlp) != NULL)
2250 						nlp->prev = tl;
2251 					kmem_free(ml, sizeof (struct memlist));
2252 					ml = tl;
2253 				}
2254 			}
2255 		}
2256 	}
2257 
2258 	return (mlist);
2259 }
2260 
2261 static void
2262 mc_get_mlist(mc_opl_t *mcp)
2263 {
2264 	struct memlist *mlist;
2265 
2266 	memlist_read_lock();
2267 	mlist = mc_memlist_dup(phys_install);
2268 	memlist_read_unlock();
2269 
2270 	if (mlist) {
2271 		mlist = mc_memlist_del_span(mlist, 0ull, mcp->mc_start_address);
2272 	}
2273 
2274 	if (mlist) {
2275 		uint64_t startpa, endpa;
2276 
2277 		startpa = mcp->mc_start_address + mcp->mc_size;
2278 		endpa = ptob(physmax + 1);
2279 		if (endpa > startpa) {
2280 			mlist = mc_memlist_del_span(mlist,
2281 				startpa, endpa - startpa);
2282 		}
2283 	}
2284 
2285 	if (mlist) {
2286 		mcp->mlist = mlist;
2287 	}
2288 }
2289 
2290 int
2291 mc_board_add(mc_opl_t *mcp)
2292 {
2293 	struct mc_addr_spec *macaddr;
2294 	cs_status_t *cs_status;
2295 	int len, len1, i, bk, cc;
2296 	mc_rsaddr_info_t rsaddr;
2297 	uint32_t mirr;
2298 	int nbanks = 0;
2299 	uint64_t nbytes = 0;
2300 
2301 	/*
2302 	 * Get configurations from "pseudo-mc" node which includes:
2303 	 * board# : LSB number
2304 	 * mac-addr : physical base address of MAC registers
2305 	 * csX-mac-pa-trans-table: translation table from DIMM address
2306 	 *			to physical address or vice versa.
2307 	 */
2308 	mcp->mc_board_num = (int)ddi_getprop(DDI_DEV_T_ANY, mcp->mc_dip,
2309 		DDI_PROP_DONTPASS, "board#", -1);
2310 
2311 	if (mcp->mc_board_num == -1) {
2312 		return (DDI_FAILURE);
2313 	}
2314 
2315 	/*
2316 	 * Get start address in this CAB. It can be gotten from
2317 	 * "sb-mem-ranges" property.
2318 	 */
2319 
2320 	if (get_base_address(mcp) == DDI_FAILURE) {
2321 		return (DDI_FAILURE);
2322 	}
2323 	/* get mac-pa trans tables */
2324 	for (i = 0; i < MC_TT_CS; i++) {
2325 		len = MC_TT_ENTRIES;
2326 		cc = ddi_getlongprop_buf(DDI_DEV_T_ANY, mcp->mc_dip,
2327 			DDI_PROP_DONTPASS, mc_tbl_name[i],
2328 			(caddr_t)mcp->mc_trans_table[i], &len);
2329 
2330 		if (cc != DDI_SUCCESS) {
2331 			bzero(mcp->mc_trans_table[i], MC_TT_ENTRIES);
2332 		}
2333 	}
2334 	mcp->mlist = NULL;
2335 
2336 	mc_get_mlist(mcp);
2337 
2338 	/* initialize bank informations */
2339 	cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS,
2340 		"mc-addr", (caddr_t)&macaddr, &len);
2341 	if (cc != DDI_SUCCESS) {
2342 		cmn_err(CE_WARN, "Cannot get mc-addr. err=%d\n", cc);
2343 		return (DDI_FAILURE);
2344 	}
2345 
2346 	cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS,
2347 		"cs-status", (caddr_t)&cs_status, &len1);
2348 
2349 	if (cc != DDI_SUCCESS) {
2350 		if (len > 0)
2351 			kmem_free(macaddr, len);
2352 		cmn_err(CE_WARN, "Cannot get cs-status. err=%d\n", cc);
2353 		return (DDI_FAILURE);
2354 	}
2355 	/* get the physical board number for a given logical board number */
2356 	mcp->mc_phys_board_num = mc_opl_get_physical_board(mcp->mc_board_num);
2357 
2358 	if (mcp->mc_phys_board_num < 0) {
2359 		if (len > 0)
2360 			kmem_free(macaddr, len);
2361 		cmn_err(CE_WARN, "Unable to obtain the physical board number");
2362 		return (DDI_FAILURE);
2363 	}
2364 
2365 	mutex_init(&mcp->mc_lock, NULL, MUTEX_DRIVER, NULL);
2366 
2367 	for (i = 0; i < len1 / sizeof (cs_status_t); i++) {
2368 		nbytes += ((uint64_t)cs_status[i].cs_avail_hi << 32) |
2369 			((uint64_t)cs_status[i].cs_avail_low);
2370 	}
2371 	if (len1 > 0)
2372 		kmem_free(cs_status, len1);
2373 	nbanks = len / sizeof (struct mc_addr_spec);
2374 
2375 	if (nbanks > 0)
2376 		nbytes /= nbanks;
2377 	else {
2378 		/* No need to free macaddr because len must be 0 */
2379 		mcp->mc_status |= MC_MEMORYLESS;
2380 		return (DDI_SUCCESS);
2381 	}
2382 
2383 	for (i = 0; i < BANKNUM_PER_SB; i++) {
2384 		mcp->mc_scf_retry[i] = 0;
2385 		mcp->mc_period[i] = 0;
2386 		mcp->mc_speedup_period[i] = 0;
2387 	}
2388 
2389 	/*
2390 	 * Get the memory size here. Let it be B (bytes).
2391 	 * Let T be the time in u.s. to scan 64 bytes.
2392 	 * If we want to complete 1 round of scanning in P seconds.
2393 	 *
2394 	 *	B * T * 10^(-6)	= P
2395 	 *	---------------
2396 	 *		64
2397 	 *
2398 	 *	T = P * 64 * 10^6
2399 	 *	    -------------
2400 	 *		B
2401 	 *
2402 	 *	  = P * 64 * 10^6
2403 	 *	    -------------
2404 	 *		B
2405 	 *
2406 	 *	The timing bits are set in PTRL_CNTL[28:26] where
2407 	 *
2408 	 *	0	- 1 m.s
2409 	 *	1	- 512 u.s.
2410 	 *	10	- 256 u.s.
2411 	 *	11	- 128 u.s.
2412 	 *	100	- 64 u.s.
2413 	 *	101	- 32 u.s.
2414 	 *	110	- 0 u.s.
2415 	 *	111	- reserved.
2416 	 *
2417 	 *
2418 	 *	a[0] = 110, a[1] = 101, ... a[6] = 0
2419 	 *
2420 	 *	cs-status property is int x 7
2421 	 *	0 - cs#
2422 	 *	1 - cs-status
2423 	 *	2 - cs-avail.hi
2424 	 *	3 - cs-avail.lo
2425 	 *	4 - dimm-capa.hi
2426 	 *	5 - dimm-capa.lo
2427 	 *	6 - #of dimms
2428 	 */
2429 
2430 	if (nbytes > 0) {
2431 		int i;
2432 		uint64_t ms;
2433 		ms = ((uint64_t)mc_scan_period * 64 * 1000000)/nbytes;
2434 		mcp->mc_speed = mc_scan_speeds[MC_MAX_SPEEDS - 1].mc_speeds;
2435 		for (i = 0; i < MC_MAX_SPEEDS - 1; i++) {
2436 			if (ms < mc_scan_speeds[i + 1].mc_period) {
2437 				mcp->mc_speed = mc_scan_speeds[i].mc_speeds;
2438 				break;
2439 			}
2440 		}
2441 	} else
2442 		mcp->mc_speed = 0;
2443 
2444 
2445 	for (i = 0; i < len / sizeof (struct mc_addr_spec); i++) {
2446 		struct mc_bank *bankp;
2447 		uint32_t reg;
2448 
2449 		/*
2450 		 * setup bank
2451 		 */
2452 		bk = macaddr[i].bank;
2453 		bankp = &(mcp->mc_bank[bk]);
2454 		bankp->mcb_status = BANK_INSTALLED;
2455 		bankp->mcb_reg_base = REGS_PA(macaddr, i);
2456 
2457 		reg = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bk));
2458 		bankp->mcb_ptrl_cntl = (reg & MAC_CNTL_PTRL_PRESERVE_BITS);
2459 
2460 		/*
2461 		 * check if mirror mode
2462 		 */
2463 		mirr = LD_MAC_REG(MAC_MIRR(mcp, bk));
2464 
2465 		if (mirr & MAC_MIRR_MIRROR_MODE) {
2466 			MC_LOG("Mirror -> /LSB%d/B%d\n",
2467 				mcp->mc_board_num, bk);
2468 			bankp->mcb_status |= BANK_MIRROR_MODE;
2469 			/*
2470 			 * The following bit is only used for
2471 			 * error injection.  We should clear it
2472 			 */
2473 			if (mirr & MAC_MIRR_BANK_EXCLUSIVE)
2474 				ST_MAC_REG(MAC_MIRR(mcp, bk),
2475 					0);
2476 		}
2477 
2478 		/*
2479 		 * restart if not mirror mode or the other bank
2480 		 * of the mirror is not running
2481 		 */
2482 		if (!(mirr & MAC_MIRR_MIRROR_MODE) ||
2483 			!(mcp->mc_bank[bk^1].mcb_status &
2484 			BANK_PTRL_RUNNING)) {
2485 			MC_LOG("Starting up /LSB%d/B%d\n",
2486 				mcp->mc_board_num, bk);
2487 			get_ptrl_start_address(mcp, bk, &rsaddr.mi_restartaddr);
2488 			rsaddr.mi_valid = 0;
2489 			rsaddr.mi_injectrestart = 0;
2490 			restart_patrol(mcp, bk, &rsaddr);
2491 		} else {
2492 			MC_LOG("Not starting up /LSB%d/B%d\n",
2493 				mcp->mc_board_num, bk);
2494 		}
2495 		bankp->mcb_status |= BANK_PTRL_RUNNING;
2496 	}
2497 	if (len > 0)
2498 		kmem_free(macaddr, len);
2499 
2500 	mcp->mc_dimm_list = mc_get_dimm_list(mcp);
2501 
2502 	/*
2503 	 * set interval in HZ.
2504 	 */
2505 	mcp->mc_last_error = 0;
2506 
2507 	/* restart memory patrol checking */
2508 	mcp->mc_status |= MC_POLL_RUNNING;
2509 
2510 	return (DDI_SUCCESS);
2511 }
2512 
2513 int
2514 mc_board_del(mc_opl_t *mcp)
2515 {
2516 	int i;
2517 	scf_log_t *p;
2518 
2519 	/*
2520 	 * cleanup mac state
2521 	 */
2522 	mutex_enter(&mcp->mc_lock);
2523 	if (mcp->mc_status & MC_MEMORYLESS) {
2524 		mutex_exit(&mcp->mc_lock);
2525 		mutex_destroy(&mcp->mc_lock);
2526 		return (DDI_SUCCESS);
2527 	}
2528 	for (i = 0; i < BANKNUM_PER_SB; i++) {
2529 		if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) {
2530 			mcp->mc_bank[i].mcb_status &= ~BANK_INSTALLED;
2531 		}
2532 	}
2533 
2534 	/* stop memory patrol checking */
2535 	mcp->mc_status &= ~MC_POLL_RUNNING;
2536 
2537 	/* just throw away all the scf logs */
2538 	for (i = 0; i < BANKNUM_PER_SB; i++) {
2539 	    while ((p = mcp->mc_scf_log[i]) != NULL) {
2540 		mcp->mc_scf_log[i] = p->sl_next;
2541 		mcp->mc_scf_total[i]--;
2542 		kmem_free(p, sizeof (scf_log_t));
2543 	    }
2544 	}
2545 
2546 	if (mcp->mlist)
2547 		mc_memlist_delete(mcp->mlist);
2548 
2549 	if (mcp->mc_dimm_list)
2550 		mc_free_dimm_list(mcp->mc_dimm_list);
2551 
2552 	mutex_exit(&mcp->mc_lock);
2553 
2554 	mutex_destroy(&mcp->mc_lock);
2555 	return (DDI_SUCCESS);
2556 }
2557 
2558 int
2559 mc_suspend(mc_opl_t *mcp, uint32_t flag)
2560 {
2561 	/* stop memory patrol checking */
2562 	mutex_enter(&mcp->mc_lock);
2563 	if (mcp->mc_status & MC_MEMORYLESS) {
2564 		mutex_exit(&mcp->mc_lock);
2565 		return (DDI_SUCCESS);
2566 	}
2567 
2568 	mcp->mc_status &= ~MC_POLL_RUNNING;
2569 
2570 	mcp->mc_status |= flag;
2571 	mutex_exit(&mcp->mc_lock);
2572 
2573 	return (DDI_SUCCESS);
2574 }
2575 
2576 /* caller must clear the SUSPEND bits or this will do nothing */
2577 
2578 int
2579 mc_resume(mc_opl_t *mcp, uint32_t flag)
2580 {
2581 	int i;
2582 	uint64_t basepa;
2583 
2584 	mutex_enter(&mcp->mc_lock);
2585 	if (mcp->mc_status & MC_MEMORYLESS) {
2586 		mutex_exit(&mcp->mc_lock);
2587 		return (DDI_SUCCESS);
2588 	}
2589 	basepa = mcp->mc_start_address;
2590 	if (get_base_address(mcp) == DDI_FAILURE) {
2591 		mutex_exit(&mcp->mc_lock);
2592 		return (DDI_FAILURE);
2593 	}
2594 
2595 	if (basepa != mcp->mc_start_address) {
2596 		if (mcp->mlist)
2597 			mc_memlist_delete(mcp->mlist);
2598 		mcp->mlist = NULL;
2599 		mc_get_mlist(mcp);
2600 	}
2601 
2602 	mcp->mc_status &= ~flag;
2603 
2604 	if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) {
2605 		mutex_exit(&mcp->mc_lock);
2606 		return (DDI_SUCCESS);
2607 	}
2608 
2609 	if (!(mcp->mc_status & MC_POLL_RUNNING)) {
2610 		/* restart memory patrol checking */
2611 		mcp->mc_status |= MC_POLL_RUNNING;
2612 		for (i = 0; i < BANKNUM_PER_SB; i++) {
2613 			if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) {
2614 				restart_patrol(mcp, i, NULL);
2615 			}
2616 		}
2617 	}
2618 	mutex_exit(&mcp->mc_lock);
2619 
2620 	return (DDI_SUCCESS);
2621 }
2622 
2623 static mc_opl_t *
2624 mc_pa_to_mcp(uint64_t pa)
2625 {
2626 	mc_opl_t *mcp;
2627 	int i;
2628 
2629 	ASSERT(MUTEX_HELD(&mcmutex));
2630 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
2631 		if ((mcp = mc_instances[i]) == NULL)
2632 			continue;
2633 		/* if mac patrol is suspended, we cannot rely on it */
2634 		if (!(mcp->mc_status & MC_POLL_RUNNING) ||
2635 			(mcp->mc_status & MC_SOFT_SUSPENDED))
2636 			continue;
2637 		if (mc_rangecheck_pa(mcp, pa)) {
2638 			return (mcp);
2639 		}
2640 	}
2641 	return (NULL);
2642 }
2643 
2644 /*
2645  * Get Physical Board number from Logical one.
2646  */
2647 static int
2648 mc_opl_get_physical_board(int sb)
2649 {
2650 	if (&opl_get_physical_board) {
2651 		return (opl_get_physical_board(sb));
2652 	}
2653 
2654 	cmn_err(CE_NOTE, "!opl_get_physical_board() not loaded\n");
2655 	return (-1);
2656 }
2657 
2658 /* ARGSUSED */
2659 int
2660 mc_get_mem_unum(int synd_code, uint64_t flt_addr, char *buf, int buflen,
2661 	int *lenp)
2662 {
2663 	int i;
2664 	int j;
2665 	int sb;
2666 	int bank;
2667 	int cs;
2668 	mc_opl_t *mcp;
2669 	char memb_num;
2670 
2671 	mutex_enter(&mcmutex);
2672 
2673 	if (((mcp = mc_pa_to_mcp(flt_addr)) == NULL) ||
2674 		(!pa_is_valid(mcp, flt_addr))) {
2675 		mutex_exit(&mcmutex);
2676 		if (snprintf(buf, buflen, "UNKNOWN") >= buflen) {
2677 			return (ENOSPC);
2678 		} else {
2679 			if (lenp)
2680 				*lenp = strlen(buf);
2681 		}
2682 		return (0);
2683 	}
2684 
2685 	bank = pa_to_bank(mcp, flt_addr - mcp->mc_start_address);
2686 	sb = mcp->mc_phys_board_num;
2687 	cs = pa_to_cs(mcp, flt_addr - mcp->mc_start_address);
2688 
2689 	if (sb == -1) {
2690 		mutex_exit(&mcmutex);
2691 		return (ENXIO);
2692 	}
2693 
2694 	if (plat_model == MODEL_DC) {
2695 		i = BD_BK_SLOT_TO_INDEX(0, bank, 0);
2696 		j = (cs == 0) ? i : i + 2;
2697 		snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s",
2698 		    model_names[plat_model].unit_name, sb,
2699 		    mc_dc_dimm_unum_table[j],
2700 		    mc_dc_dimm_unum_table[j + 1]);
2701 	} else {
2702 		i = BD_BK_SLOT_TO_INDEX(sb, bank, 0);
2703 		j = (cs == 0) ? i : i + 2;
2704 		memb_num = mc_ff_dimm_unum_table[i][0];
2705 		snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s",
2706 		    model_names[plat_model].unit_name,
2707 		    model_names[plat_model].mem_name, memb_num,
2708 		    &mc_ff_dimm_unum_table[j][1],
2709 		    &mc_ff_dimm_unum_table[j + 1][1]);
2710 	}
2711 	if (lenp) {
2712 		*lenp = strlen(buf);
2713 	}
2714 	mutex_exit(&mcmutex);
2715 	return (0);
2716 }
2717 
2718 int
2719 opl_mc_suspend(void)
2720 {
2721 	mc_opl_t *mcp;
2722 	int i;
2723 
2724 	mutex_enter(&mcmutex);
2725 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
2726 		if ((mcp = mc_instances[i]) == NULL)
2727 			continue;
2728 		mc_suspend(mcp, MC_SOFT_SUSPENDED);
2729 	}
2730 	mutex_exit(&mcmutex);
2731 
2732 	return (0);
2733 }
2734 
2735 int
2736 opl_mc_resume(void)
2737 {
2738 	mc_opl_t *mcp;
2739 	int i;
2740 
2741 	mutex_enter(&mcmutex);
2742 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
2743 		if ((mcp = mc_instances[i]) == NULL)
2744 			continue;
2745 		mc_resume(mcp, MC_SOFT_SUSPENDED);
2746 	}
2747 	mutex_exit(&mcmutex);
2748 
2749 	return (0);
2750 }
2751 static void
2752 insert_mcp(mc_opl_t *mcp)
2753 {
2754 	mutex_enter(&mcmutex);
2755 	if (mc_instances[mcp->mc_board_num] != NULL) {
2756 		MC_LOG("mc-opl instance for board# %d already exists\n",
2757 			mcp->mc_board_num);
2758 	}
2759 	mc_instances[mcp->mc_board_num] = mcp;
2760 	mutex_exit(&mcmutex);
2761 }
2762 
2763 static void
2764 delete_mcp(mc_opl_t *mcp)
2765 {
2766 	mutex_enter(&mcmutex);
2767 	mc_instances[mcp->mc_board_num] = 0;
2768 	mutex_exit(&mcmutex);
2769 }
2770 
2771 /* Error injection interface */
2772 
2773 static void
2774 mc_lock_va(uint64_t pa, caddr_t new_va)
2775 {
2776 	tte_t tte;
2777 
2778 	vtag_flushpage(new_va, (uint64_t)ksfmmup);
2779 	sfmmu_memtte(&tte, pa >> PAGESHIFT,
2780 		PROC_DATA|HAT_NOSYNC, TTE8K);
2781 	tte.tte_intlo |= TTE_LCK_INT;
2782 	sfmmu_dtlb_ld_kva(new_va, &tte);
2783 }
2784 
2785 static void
2786 mc_unlock_va(caddr_t va)
2787 {
2788 	vtag_flushpage(va, (uint64_t)ksfmmup);
2789 }
2790 
2791 /* ARGSUSED */
2792 int
2793 mc_inject_error(int error_type, uint64_t pa, uint32_t flags)
2794 {
2795 	mc_opl_t *mcp;
2796 	int bank;
2797 	uint32_t dimm_addr;
2798 	uint32_t cntl;
2799 	mc_rsaddr_info_t rsaddr;
2800 	uint32_t data, stat;
2801 	int both_sides = 0;
2802 	uint64_t pa0;
2803 	int extra_injection_needed = 0;
2804 	extern void cpu_flush_ecache(void);
2805 
2806 	MC_LOG("HW mc_inject_error(%x, %lx, %x)\n", error_type, pa, flags);
2807 
2808 	mutex_enter(&mcmutex);
2809 	if ((mcp = mc_pa_to_mcp(pa)) == NULL) {
2810 		mutex_exit(&mcmutex);
2811 		MC_LOG("mc_inject_error: invalid pa\n");
2812 		return (ENOTSUP);
2813 	}
2814 
2815 	mutex_enter(&mcp->mc_lock);
2816 	mutex_exit(&mcmutex);
2817 
2818 	if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) {
2819 		mutex_exit(&mcp->mc_lock);
2820 		MC_LOG("mc-opl has been suspended.  No error injection.\n");
2821 		return (EBUSY);
2822 	}
2823 
2824 	/* convert pa to offset within the board */
2825 	MC_LOG("pa %lx, offset %lx\n", pa, pa - mcp->mc_start_address);
2826 
2827 	if (!pa_is_valid(mcp, pa)) {
2828 		mutex_exit(&mcp->mc_lock);
2829 		return (EINVAL);
2830 	}
2831 
2832 	pa0 = pa - mcp->mc_start_address;
2833 
2834 	bank = pa_to_bank(mcp, pa0);
2835 
2836 	if (flags & MC_INJECT_FLAG_OTHER)
2837 		bank = bank ^ 1;
2838 
2839 	if (MC_INJECT_MIRROR(error_type) && !IS_MIRROR(mcp, bank)) {
2840 		mutex_exit(&mcp->mc_lock);
2841 		MC_LOG("Not mirror mode\n");
2842 		return (EINVAL);
2843 	}
2844 
2845 	dimm_addr = pa_to_dimm(mcp, pa0);
2846 
2847 	MC_LOG("injecting error to /LSB%d/B%d/%x\n",
2848 		mcp->mc_board_num, bank, dimm_addr);
2849 
2850 
2851 	switch (error_type) {
2852 	case MC_INJECT_INTERMITTENT_MCE:
2853 	case MC_INJECT_PERMANENT_MCE:
2854 	case MC_INJECT_MUE:
2855 		both_sides = 1;
2856 	}
2857 
2858 	if (flags & MC_INJECT_FLAG_RESET)
2859 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 0);
2860 
2861 	ST_MAC_REG(MAC_EG_ADD(mcp, bank), dimm_addr & MAC_EG_ADD_MASK);
2862 
2863 	if (both_sides) {
2864 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), 0);
2865 		ST_MAC_REG(MAC_EG_ADD(mcp, bank^1),
2866 			dimm_addr & MAC_EG_ADD_MASK);
2867 	}
2868 
2869 	switch (error_type) {
2870 	case MC_INJECT_SUE:
2871 		extra_injection_needed = 1;
2872 		/*FALLTHROUGH*/
2873 	case MC_INJECT_UE:
2874 	case MC_INJECT_MUE:
2875 		if (flags & MC_INJECT_FLAG_PATH) {
2876 			cntl = MAC_EG_ADD_FIX
2877 				|MAC_EG_FORCE_READ00|MAC_EG_FORCE_READ16
2878 				|MAC_EG_RDERR_ONCE;
2879 		} else {
2880 			cntl = MAC_EG_ADD_FIX|MAC_EG_FORCE_DERR00
2881 				|MAC_EG_FORCE_DERR16|MAC_EG_DERR_ONCE;
2882 		}
2883 		flags |= MC_INJECT_FLAG_ST;
2884 		break;
2885 	case MC_INJECT_INTERMITTENT_CE:
2886 	case MC_INJECT_INTERMITTENT_MCE:
2887 		if (flags & MC_INJECT_FLAG_PATH) {
2888 			cntl = MAC_EG_ADD_FIX
2889 				|MAC_EG_FORCE_READ00
2890 				|MAC_EG_RDERR_ONCE;
2891 		} else {
2892 			cntl = MAC_EG_ADD_FIX
2893 				|MAC_EG_FORCE_DERR16
2894 				|MAC_EG_DERR_ONCE;
2895 		}
2896 		extra_injection_needed = 1;
2897 		flags |= MC_INJECT_FLAG_ST;
2898 		break;
2899 	case MC_INJECT_PERMANENT_CE:
2900 	case MC_INJECT_PERMANENT_MCE:
2901 		if (flags & MC_INJECT_FLAG_PATH) {
2902 			cntl = MAC_EG_ADD_FIX
2903 				|MAC_EG_FORCE_READ00
2904 				|MAC_EG_RDERR_ALWAYS;
2905 		} else {
2906 			cntl = MAC_EG_ADD_FIX
2907 				|MAC_EG_FORCE_DERR16
2908 				|MAC_EG_DERR_ALWAYS;
2909 		}
2910 		flags |= MC_INJECT_FLAG_ST;
2911 		break;
2912 	case MC_INJECT_CMPE:
2913 		data = 0xabcdefab;
2914 		stphys(pa, data);
2915 		cpu_flush_ecache();
2916 		MC_LOG("CMPE: writing data %x to %lx\n", data, pa);
2917 		ST_MAC_REG(MAC_MIRR(mcp, bank), MAC_MIRR_BANK_EXCLUSIVE);
2918 		stphys(pa, data ^ 0xffffffff);
2919 		membar_sync();
2920 		cpu_flush_ecache();
2921 		ST_MAC_REG(MAC_MIRR(mcp, bank), 0);
2922 		MC_LOG("CMPE: write new data %xto %lx\n", data, pa);
2923 		cntl = 0;
2924 		break;
2925 	case MC_INJECT_NOP:
2926 		cntl = 0;
2927 		break;
2928 	default:
2929 		MC_LOG("mc_inject_error: invalid option\n");
2930 		cntl = 0;
2931 	}
2932 
2933 	if (cntl) {
2934 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl & MAC_EG_SETUP_MASK);
2935 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl);
2936 
2937 		if (both_sides) {
2938 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl &
2939 				MAC_EG_SETUP_MASK);
2940 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl);
2941 		}
2942 	}
2943 
2944 	/*
2945 	 * For all injection cases except compare error, we
2946 	 * must write to the PA to trigger the error.
2947 	 */
2948 
2949 	if (flags & MC_INJECT_FLAG_ST) {
2950 		data = 0xf0e0d0c0;
2951 		MC_LOG("Writing %x to %lx\n", data, pa);
2952 		stphys(pa, data);
2953 		cpu_flush_ecache();
2954 	}
2955 
2956 
2957 	if (flags & MC_INJECT_FLAG_LD) {
2958 		if (flags & MC_INJECT_FLAG_PREFETCH) {
2959 			/*
2960 			 * Use strong prefetch operation to
2961 			 * inject MI errors.
2962 			 */
2963 			page_t *pp;
2964 			extern void mc_prefetch(caddr_t);
2965 
2966 			MC_LOG("prefetch\n");
2967 
2968 			pp = page_numtopp_nolock(pa >> PAGESHIFT);
2969 			if (pp != NULL) {
2970 				caddr_t	va, va1;
2971 
2972 				va = ppmapin(pp, PROT_READ|PROT_WRITE,
2973 					(caddr_t)-1);
2974 				kpreempt_disable();
2975 				mc_lock_va((uint64_t)pa, va);
2976 				va1 = va + (pa & (PAGESIZE - 1));
2977 				mc_prefetch(va1);
2978 				mc_unlock_va(va);
2979 				kpreempt_enable();
2980 				ppmapout(va);
2981 
2982 				/*
2983 				 * For MI errors, we need one extra
2984 				 * injection for HW patrol to stop.
2985 				 */
2986 				extra_injection_needed = 1;
2987 			} else {
2988 				cmn_err(CE_WARN, "Cannot find page structure"
2989 					" for PA %lx\n", pa);
2990 			}
2991 		} else {
2992 			MC_LOG("Reading from %lx\n", pa);
2993 			data = ldphys(pa);
2994 			MC_LOG("data = %x\n", data);
2995 		}
2996 
2997 		if (extra_injection_needed) {
2998 			/*
2999 			 * These are the injection cases where the
3000 			 * requested injected errors will not cause the HW
3001 			 * patrol to stop. For these cases, we need to inject
3002 			 * an extra 'real' PTRL error to force the
3003 			 * HW patrol to stop so that we can report the
3004 			 * errors injected. Note that we cannot read
3005 			 * and report error status while the HW patrol
3006 			 * is running.
3007 			 */
3008 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank),
3009 				cntl & MAC_EG_SETUP_MASK);
3010 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl);
3011 
3012 			if (both_sides) {
3013 			    ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl &
3014 				MAC_EG_SETUP_MASK);
3015 			    ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl);
3016 			}
3017 			data = 0xf0e0d0c0;
3018 			MC_LOG("Writing %x to %lx\n", data, pa);
3019 			stphys(pa, data);
3020 			cpu_flush_ecache();
3021 		}
3022 	}
3023 
3024 	if (flags & MC_INJECT_FLAG_RESTART) {
3025 		MC_LOG("Restart patrol\n");
3026 		rsaddr.mi_restartaddr.ma_bd = mcp->mc_board_num;
3027 		rsaddr.mi_restartaddr.ma_bank = bank;
3028 		rsaddr.mi_restartaddr.ma_dimm_addr = dimm_addr;
3029 		rsaddr.mi_valid = 1;
3030 		rsaddr.mi_injectrestart = 1;
3031 		restart_patrol(mcp, bank, &rsaddr);
3032 	}
3033 
3034 	if (flags & MC_INJECT_FLAG_POLL) {
3035 		int running;
3036 		int ebank = (IS_MIRROR(mcp, bank)) ? MIRROR_IDX(bank) : bank;
3037 
3038 		MC_LOG("Poll patrol error\n");
3039 		stat = LD_MAC_REG(MAC_PTRL_STAT(mcp, bank));
3040 		cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank));
3041 		running = cntl & MAC_CNTL_PTRL_START;
3042 
3043 		if (!running &&
3044 		    (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS))) {
3045 			/*
3046 			 * HW patrol stopped and we have errors to
3047 			 * report. Do it.
3048 			 */
3049 			mcp->mc_speedup_period[ebank] = 0;
3050 			rsaddr.mi_valid = 0;
3051 			rsaddr.mi_injectrestart = 0;
3052 			if (IS_MIRROR(mcp, bank)) {
3053 				mc_error_handler_mir(mcp, bank, &rsaddr);
3054 			} else {
3055 				mc_error_handler(mcp, bank, &rsaddr);
3056 			}
3057 
3058 			restart_patrol(mcp, bank, &rsaddr);
3059 		} else {
3060 			/*
3061 			 * We are expecting to report injected
3062 			 * errors but the HW patrol is still running.
3063 			 * Speed up the scanning
3064 			 */
3065 			mcp->mc_speedup_period[ebank] = 2;
3066 			MAC_CMD(mcp, bank, 0);
3067 			restart_patrol(mcp, bank, NULL);
3068 		}
3069 	}
3070 
3071 	mutex_exit(&mcp->mc_lock);
3072 	return (0);
3073 }
3074 
3075 void
3076 mc_stphysio(uint64_t pa, uint32_t data)
3077 {
3078 	MC_LOG("0x%x -> pa(%lx)\n", data, pa);
3079 	stphysio(pa, data);
3080 
3081 	/* force the above write to be processed by mac patrol */
3082 	data = ldphysio(pa);
3083 	MC_LOG("pa(%lx) = 0x%x\n", pa, data);
3084 }
3085 
3086 uint32_t
3087 mc_ldphysio(uint64_t pa)
3088 {
3089 	uint32_t rv;
3090 
3091 	rv = ldphysio(pa);
3092 	MC_LOG("pa(%lx) = 0x%x\n", pa, rv);
3093 	return (rv);
3094 }
3095 
3096 #define	isdigit(ch)	((ch) >= '0' && (ch) <= '9')
3097 
3098 /*
3099  * parse_unum_memory -- extract the board number and the DIMM name from
3100  * the unum.
3101  *
3102  * Return 0 for success and non-zero for a failure.
3103  */
3104 int
3105 parse_unum_memory(char *unum, int *board, char *dname)
3106 {
3107 	char *c;
3108 	char x, y, z;
3109 
3110 	if ((c = strstr(unum, "CMU")) != NULL) {
3111 		/* DC Model */
3112 		c += 3;
3113 		*board = (uint8_t)stoi(&c);
3114 		if ((c = strstr(c, "MEM")) == NULL) {
3115 			return (1);
3116 		}
3117 		c += 3;
3118 		if (strlen(c) < 3) {
3119 			return (2);
3120 		}
3121 		if ((!isdigit(c[0])) || (!(isdigit(c[1]))) ||
3122 		    ((c[2] != 'A') && (c[2] != 'B'))) {
3123 			return (3);
3124 		}
3125 		x = c[0];
3126 		y = c[1];
3127 		z = c[2];
3128 	} else if ((c = strstr(unum, "MBU_")) != NULL) {
3129 		/*  FF1/FF2 Model */
3130 		c += 4;
3131 		if ((c[0] != 'A') && (c[0] != 'B')) {
3132 			return (4);
3133 		}
3134 		if ((c = strstr(c, "MEMB")) == NULL) {
3135 			return (5);
3136 		}
3137 		c += 4;
3138 
3139 		x = c[0];
3140 		*board =  ((uint8_t)stoi(&c)) / 4;
3141 		if ((c = strstr(c, "MEM")) == NULL) {
3142 			return (6);
3143 		}
3144 		c += 3;
3145 		if (strlen(c) < 2) {
3146 			return (7);
3147 		}
3148 		if ((!isdigit(c[0])) || ((c[1] != 'A') && (c[1] != 'B'))) {
3149 			return (8);
3150 		}
3151 		y = c[0];
3152 		z = c[1];
3153 	} else {
3154 		return (9);
3155 	}
3156 	if (*board < 0) {
3157 		return (10);
3158 	}
3159 	dname[0] = x;
3160 	dname[1] = y;
3161 	dname[2] = z;
3162 	dname[3] = '\0';
3163 	return (0);
3164 }
3165 
3166 /*
3167  * mc_get_mem_sid_dimm -- Get the serial-ID for a given board and
3168  * the DIMM name.
3169  */
3170 int
3171 mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf,
3172     int buflen, int *lenp)
3173 {
3174 	int		ret = ENODEV;
3175 	mc_dimm_info_t	*d = NULL;
3176 
3177 	if ((d = mcp->mc_dimm_list) == NULL)
3178 		return (ENOTSUP);
3179 
3180 	for (; d != NULL; d = d->md_next) {
3181 		if (strcmp(d->md_dimmname, dname) == 0) {
3182 			break;
3183 		}
3184 	}
3185 	if (d != NULL) {
3186 		*lenp = strlen(d->md_serial) + strlen(d->md_partnum);
3187 		if (buflen <=  *lenp) {
3188 			cmn_err(CE_WARN, "mc_get_mem_sid_dimm: "
3189 			    "buflen is smaller than %d\n", *lenp);
3190 			ret = ENOSPC;
3191 		} else {
3192 			snprintf(buf, buflen, "%s:%s",
3193 			    d->md_serial, d->md_partnum);
3194 			ret = 0;
3195 		}
3196 	}
3197 	MC_LOG("mc_get_mem_sid_dimm: Ret=%d Name=%s Serial-ID=%s\n",
3198 	    ret, dname, (ret == 0) ? buf : "");
3199 	return (ret);
3200 }
3201 
3202 int
3203 mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int sb,
3204     int bank, uint32_t mf_type, uint32_t d_slot)
3205 {
3206 	int	lenp = buflen;
3207 	int	id;
3208 	int	ret;
3209 	char	*dimmnm;
3210 
3211 	if (mf_type == FLT_TYPE_PERMANENT_CE) {
3212 		if (plat_model == MODEL_DC) {
3213 			id = BD_BK_SLOT_TO_INDEX(0, bank, d_slot);
3214 			dimmnm = mc_dc_dimm_unum_table[id];
3215 		} else {
3216 			id = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot);
3217 			dimmnm = mc_ff_dimm_unum_table[id];
3218 		}
3219 		if ((ret = mc_get_mem_sid_dimm(mcp, dimmnm, buf, buflen,
3220 		    &lenp)) != 0) {
3221 			return (ret);
3222 		}
3223 	} else {
3224 		return (1);
3225 	}
3226 
3227 	return (0);
3228 }
3229 
3230 /*
3231  * mc_get_mem_sid -- get the DIMM serial-ID corresponding to the unum.
3232  */
3233 int
3234 mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp)
3235 {
3236 	int	i;
3237 	int	ret = ENODEV;
3238 	int	board;
3239 	char	dname[MCOPL_MAX_DIMMNAME + 1];
3240 	mc_opl_t *mcp;
3241 
3242 	MC_LOG("mc_get_mem_sid: unum=%s buflen=%d\n", unum, buflen);
3243 	if ((ret = parse_unum_memory(unum, &board, dname)) != 0) {
3244 		MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n",
3245 		    unum, ret);
3246 		return (EINVAL);
3247 	}
3248 
3249 	if (board < 0) {
3250 		MC_LOG("mc_get_mem_sid: Invalid board=%d dimm=%s\n",
3251 		    board, dname);
3252 		return (EINVAL);
3253 	}
3254 
3255 	mutex_enter(&mcmutex);
3256 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
3257 		if ((mcp = mc_instances[i]) == NULL)
3258 			continue;
3259 		mutex_enter(&mcp->mc_lock);
3260 		if (mcp->mc_phys_board_num != board) {
3261 			mutex_exit(&mcp->mc_lock);
3262 			continue;
3263 		}
3264 		ret = mc_get_mem_sid_dimm(mcp, dname, buf, buflen, lenp);
3265 		if (ret == 0) {
3266 			mutex_exit(&mcp->mc_lock);
3267 			break;
3268 		}
3269 		mutex_exit(&mcp->mc_lock);
3270 	}
3271 	mutex_exit(&mcmutex);
3272 	return (ret);
3273 }
3274 
3275 /*
3276  * mc_get_mem_offset -- get the offset in a DIMM for a given physical address.
3277  */
3278 int
3279 mc_get_mem_offset(uint64_t paddr, uint64_t *offp)
3280 {
3281 	int		i;
3282 	int		ret = ENODEV;
3283 	mc_addr_t	maddr;
3284 	mc_opl_t	*mcp;
3285 
3286 	mutex_enter(&mcmutex);
3287 	for (i = 0; ((i < OPL_MAX_BOARDS) && (ret != 0)); i++) {
3288 		if ((mcp = mc_instances[i]) == NULL)
3289 			continue;
3290 		mutex_enter(&mcp->mc_lock);
3291 		if (!pa_is_valid(mcp, paddr)) {
3292 			mutex_exit(&mcp->mc_lock);
3293 			continue;
3294 		}
3295 		if (pa_to_maddr(mcp, paddr, &maddr) == 0) {
3296 			*offp = maddr.ma_dimm_addr;
3297 			ret = 0;
3298 		}
3299 		mutex_exit(&mcp->mc_lock);
3300 	}
3301 	mutex_exit(&mcmutex);
3302 	MC_LOG("mc_get_mem_offset: Ret=%d paddr=0x%lx offset=0x%lx\n",
3303 	    ret, paddr, *offp);
3304 	return (ret);
3305 }
3306 
3307 /*
3308  * dname_to_bankslot - Get the bank and slot number from the DIMM name.
3309  */
3310 int
3311 dname_to_bankslot(char *dname, int *bank, int *slot)
3312 {
3313 	int i;
3314 	int tsz;
3315 	char **tbl;
3316 
3317 	if (plat_model == MODEL_DC) { /* DC */
3318 		tbl = mc_dc_dimm_unum_table;
3319 		tsz = OPL_MAX_DIMMS;
3320 	} else {
3321 		tbl = mc_ff_dimm_unum_table;
3322 		tsz = 2 * OPL_MAX_DIMMS;
3323 	}
3324 
3325 	for (i = 0; i < tsz; i++) {
3326 		if (strcmp(dname,  tbl[i]) == 0) {
3327 			break;
3328 		}
3329 	}
3330 	if (i == tsz) {
3331 		return (1);
3332 	}
3333 	*bank = INDEX_TO_BANK(i);
3334 	*slot = INDEX_TO_SLOT(i);
3335 	return (0);
3336 }
3337 
3338 /*
3339  * mc_get_mem_addr -- get the physical address of a DIMM corresponding
3340  * to the unum and sid.
3341  */
3342 int
3343 mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr)
3344 {
3345 	int	board;
3346 	int	bank;
3347 	int	slot;
3348 	int	i;
3349 	int	ret = ENODEV;
3350 	char	dname[MCOPL_MAX_DIMMNAME + 1];
3351 	mc_addr_t maddr;
3352 	mc_opl_t *mcp;
3353 
3354 	MC_LOG("mc_get_mem_addr: unum=%s sid=%s offset=0x%lx\n",
3355 	    unum, sid, offset);
3356 	if (parse_unum_memory(unum, &board, dname) != 0) {
3357 		MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n",
3358 		    unum, ret);
3359 		return (EINVAL);
3360 	}
3361 
3362 	if (board < 0) {
3363 		MC_LOG("mc_get_mem_addr: Invalid board=%d dimm=%s\n",
3364 		    board, dname);
3365 		return (EINVAL);
3366 	}
3367 
3368 	mutex_enter(&mcmutex);
3369 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
3370 		if ((mcp = mc_instances[i]) == NULL)
3371 			continue;
3372 		mutex_enter(&mcp->mc_lock);
3373 		if (mcp->mc_phys_board_num != board) {
3374 			mutex_exit(&mcp->mc_lock);
3375 			continue;
3376 		}
3377 
3378 		ret = dname_to_bankslot(dname, &bank, &slot);
3379 		MC_LOG("mc_get_mem_addr: bank=%d slot=%d\n", bank, slot);
3380 		if (ret != 0) {
3381 			MC_LOG("mc_get_mem_addr: dname_to_bankslot failed\n");
3382 			ret = ENODEV;
3383 		} else {
3384 			maddr.ma_bd = mcp->mc_board_num;
3385 			maddr.ma_bank =  bank;
3386 			maddr.ma_dimm_addr = offset;
3387 			ret = mcaddr_to_pa(mcp, &maddr, paddr);
3388 			if (ret != 0) {
3389 				MC_LOG("mc_get_mem_addr: "
3390 				    "mcaddr_to_pa failed\n");
3391 				ret = ENODEV;
3392 			}
3393 			mutex_exit(&mcp->mc_lock);
3394 			break;
3395 		}
3396 		mutex_exit(&mcp->mc_lock);
3397 	}
3398 	mutex_exit(&mcmutex);
3399 	MC_LOG("mc_get_mem_addr: Ret=%d, Paddr=0x%lx\n", ret, *paddr);
3400 	return (ret);
3401 }
3402 
3403 static void
3404 mc_free_dimm_list(mc_dimm_info_t *d)
3405 {
3406 	mc_dimm_info_t *next;
3407 
3408 	while (d != NULL) {
3409 		next = d->md_next;
3410 		kmem_free(d, sizeof (mc_dimm_info_t));
3411 		d = next;
3412 	}
3413 }
3414 
3415 /*
3416  * mc_get_dimm_list -- get the list of dimms with serial-id info
3417  * from the SP.
3418  */
3419 mc_dimm_info_t *
3420 mc_get_dimm_list(mc_opl_t *mcp)
3421 {
3422 	uint32_t	bufsz;
3423 	uint32_t	maxbufsz;
3424 	int		ret;
3425 	int		sexp;
3426 	board_dimm_info_t *bd_dimmp;
3427 	mc_dimm_info_t	*dimm_list = NULL;
3428 
3429 	maxbufsz = bufsz = sizeof (board_dimm_info_t) +
3430 	    ((MCOPL_MAX_DIMMNAME +  MCOPL_MAX_SERIAL +
3431 	    MCOPL_MAX_PARTNUM) * OPL_MAX_DIMMS);
3432 
3433 	bd_dimmp = (board_dimm_info_t *)kmem_alloc(bufsz, KM_SLEEP);
3434 	ret = scf_get_dimminfo(mcp->mc_board_num, (void *)bd_dimmp, &bufsz);
3435 
3436 	MC_LOG("mc_get_dimm_list:  scf_service_getinfo returned=%d\n", ret);
3437 	if (ret == 0) {
3438 		sexp = sizeof (board_dimm_info_t) +
3439 		    ((bd_dimmp->bd_dnamesz +  bd_dimmp->bd_serialsz +
3440 		    bd_dimmp->bd_partnumsz) * bd_dimmp->bd_numdimms);
3441 
3442 		if ((bd_dimmp->bd_version == OPL_DIMM_INFO_VERSION) &&
3443 		    (bd_dimmp->bd_dnamesz <= MCOPL_MAX_DIMMNAME) &&
3444 		    (bd_dimmp->bd_serialsz <= MCOPL_MAX_SERIAL) &&
3445 		    (bd_dimmp->bd_partnumsz <= MCOPL_MAX_PARTNUM) &&
3446 		    (sexp <= bufsz)) {
3447 
3448 #ifdef DEBUG
3449 			if (oplmc_debug)
3450 				mc_dump_dimm_info(bd_dimmp);
3451 #endif
3452 			dimm_list = mc_prepare_dimmlist(bd_dimmp);
3453 
3454 		} else {
3455 			cmn_err(CE_WARN, "DIMM info version mismatch\n");
3456 		}
3457 	}
3458 	kmem_free(bd_dimmp, maxbufsz);
3459 	MC_LOG("mc_get_dimm_list: dimmlist=0x%p\n", dimm_list);
3460 	return (dimm_list);
3461 }
3462 
3463 /*
3464  * mc_prepare_dimmlist - Prepare the dimm list from the infomation
3465  * recieved from the SP.
3466  */
3467 mc_dimm_info_t *
3468 mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp)
3469 {
3470 	char	*dimm_name;
3471 	char	*serial;
3472 	char	*part;
3473 	int	dimm;
3474 	int	dnamesz = bd_dimmp->bd_dnamesz;
3475 	int	sersz = bd_dimmp->bd_serialsz;
3476 	int	partsz = bd_dimmp->bd_partnumsz;
3477 	mc_dimm_info_t	*dimm_list = NULL;
3478 	mc_dimm_info_t	*d;
3479 
3480 	dimm_name = (char *)(bd_dimmp + 1);
3481 	for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) {
3482 
3483 		d = (mc_dimm_info_t *)kmem_alloc(sizeof (mc_dimm_info_t),
3484 		    KM_SLEEP);
3485 		snprintf(d->md_dimmname, dnamesz + 1, "%s", dimm_name);
3486 		serial = dimm_name + dnamesz;
3487 		snprintf(d->md_serial, sersz + 1, "%s", serial);
3488 		part = serial + sersz;
3489 		snprintf(d->md_partnum, partsz + 1, "%s", part);
3490 
3491 		d->md_next = dimm_list;
3492 		dimm_list = d;
3493 		dimm_name = part + partsz;
3494 	}
3495 	return (dimm_list);
3496 }
3497 
3498 #ifdef DEBUG
3499 void
3500 mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz)
3501 {
3502 	char dname[MCOPL_MAX_DIMMNAME + 1];
3503 	char serial[MCOPL_MAX_SERIAL + 1];
3504 	char part[ MCOPL_MAX_PARTNUM + 1];
3505 	char *b;
3506 
3507 	b = buf;
3508 	snprintf(dname, dnamesz + 1, "%s", b);
3509 	b += dnamesz;
3510 	snprintf(serial, serialsz + 1, "%s", b);
3511 	b += serialsz;
3512 	snprintf(part, partnumsz + 1, "%s", b);
3513 	printf("DIMM=%s  Serial=%s PartNum=%s\n", dname, serial, part);
3514 }
3515 
3516 void
3517 mc_dump_dimm_info(board_dimm_info_t *bd_dimmp)
3518 {
3519 	int	dimm;
3520 	int	dnamesz = bd_dimmp->bd_dnamesz;
3521 	int	sersz = bd_dimmp->bd_serialsz;
3522 	int	partsz = bd_dimmp->bd_partnumsz;
3523 	char	*buf;
3524 
3525 	printf("Version=%d Board=%02d DIMMs=%d NameSize=%d "
3526 	    "SerialSize=%d PartnumSize=%d\n", bd_dimmp->bd_version,
3527 	    bd_dimmp->bd_boardnum, bd_dimmp->bd_numdimms, bd_dimmp->bd_dnamesz,
3528 	    bd_dimmp->bd_serialsz, bd_dimmp->bd_partnumsz);
3529 	printf("======================================================\n");
3530 
3531 	buf = (char *)(bd_dimmp + 1);
3532 	for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) {
3533 		mc_dump_dimm(buf, dnamesz, sersz, partsz);
3534 		buf += dnamesz + sersz + partsz;
3535 	}
3536 	printf("======================================================\n");
3537 }
3538 
3539 
3540 /* ARGSUSED */
3541 static int
3542 mc_ioctl_debug(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
3543 	int *rvalp)
3544 {
3545 	caddr_t	buf;
3546 	uint64_t pa;
3547 	int rv = 0;
3548 	int i;
3549 	uint32_t flags;
3550 	static uint32_t offset = 0;
3551 
3552 
3553 	flags = (cmd >> 4) & 0xfffffff;
3554 
3555 	cmd &= 0xf;
3556 
3557 	MC_LOG("mc_ioctl(cmd = %x, flags = %x)\n", cmd, flags);
3558 
3559 	if (arg != NULL) {
3560 		if (ddi_copyin((const void *)arg, (void *)&pa,
3561 			sizeof (uint64_t), 0) < 0) {
3562 			rv = EFAULT;
3563 			return (rv);
3564 		}
3565 		buf = NULL;
3566 	} else {
3567 		buf = (caddr_t)kmem_alloc(PAGESIZE, KM_SLEEP);
3568 
3569 		pa = va_to_pa(buf);
3570 		pa += offset;
3571 
3572 		offset += 64;
3573 		if (offset >= PAGESIZE)
3574 			offset = 0;
3575 	}
3576 
3577 	switch (cmd) {
3578 	case MCI_CE:
3579 		mc_inject_error(MC_INJECT_INTERMITTENT_CE, pa,
3580 			flags);
3581 		break;
3582 	case MCI_PERM_CE:
3583 		mc_inject_error(MC_INJECT_PERMANENT_CE, pa,
3584 			flags);
3585 		break;
3586 	case MCI_UE:
3587 		mc_inject_error(MC_INJECT_UE, pa,
3588 			flags);
3589 		break;
3590 	case MCI_M_CE:
3591 		mc_inject_error(MC_INJECT_INTERMITTENT_MCE, pa,
3592 			flags);
3593 		break;
3594 	case MCI_M_PCE:
3595 		mc_inject_error(MC_INJECT_PERMANENT_MCE, pa,
3596 			flags);
3597 		break;
3598 	case MCI_M_UE:
3599 		mc_inject_error(MC_INJECT_MUE, pa,
3600 			flags);
3601 		break;
3602 	case MCI_CMP:
3603 		mc_inject_error(MC_INJECT_CMPE, pa,
3604 			flags);
3605 		break;
3606 	case MCI_NOP:
3607 		mc_inject_error(MC_INJECT_NOP, pa, flags);
3608 		break;
3609 	case MCI_SHOW_ALL:
3610 		mc_debug_show_all = 1;
3611 		break;
3612 	case MCI_SHOW_NONE:
3613 		mc_debug_show_all = 0;
3614 		break;
3615 	case MCI_ALLOC:
3616 		/*
3617 		 * just allocate some kernel memory and never free it
3618 		 * 512 MB seems to be the maximum size supported.
3619 		 */
3620 		cmn_err(CE_NOTE, "Allocating kmem %d MB\n", flags * 512);
3621 		for (i = 0; i < flags; i++) {
3622 			buf = kmem_alloc(512 * 1024 * 1024, KM_SLEEP);
3623 			cmn_err(CE_NOTE, "kmem buf %llx PA %llx\n",
3624 				(u_longlong_t)buf, (u_longlong_t)va_to_pa(buf));
3625 		}
3626 		break;
3627 	case MCI_SUSPEND:
3628 		(void) opl_mc_suspend();
3629 		break;
3630 	case MCI_RESUME:
3631 		(void) opl_mc_resume();
3632 		break;
3633 	default:
3634 		rv = ENXIO;
3635 	}
3636 	return (rv);
3637 }
3638 
3639 #endif /* DEBUG */
3640