xref: /illumos-gate/usr/src/uts/sun4u/opl/io/mc-opl.c (revision 392e836b)
125cf1a30Sjl /*
225cf1a30Sjl  * CDDL HEADER START
325cf1a30Sjl  *
425cf1a30Sjl  * The contents of this file are subject to the terms of the
525cf1a30Sjl  * Common Development and Distribution License (the "License").
625cf1a30Sjl  * You may not use this file except in compliance with the License.
725cf1a30Sjl  *
825cf1a30Sjl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl  * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl  * See the License for the specific language governing permissions
1125cf1a30Sjl  * and limitations under the License.
1225cf1a30Sjl  *
1325cf1a30Sjl  * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl  * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl  * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl  * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl  *
1925cf1a30Sjl  * CDDL HEADER END
2025cf1a30Sjl  */
211e2e7a75Shuah /*
22*392e836bSGavin Maltby  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
231e2e7a75Shuah  */
2425cf1a30Sjl /*
2578ed97a7Sjl  * All Rights Reserved, Copyright (c) FUJITSU LIMITED 2008
2625cf1a30Sjl  */
2725cf1a30Sjl 
2825cf1a30Sjl #include <sys/types.h>
2925cf1a30Sjl #include <sys/sysmacros.h>
3025cf1a30Sjl #include <sys/conf.h>
3125cf1a30Sjl #include <sys/modctl.h>
3225cf1a30Sjl #include <sys/stat.h>
3325cf1a30Sjl #include <sys/async.h>
341e2e7a75Shuah #include <sys/machcpuvar.h>
3525cf1a30Sjl #include <sys/machsystm.h>
360cc8ae86Sav #include <sys/promif.h>
3725cf1a30Sjl #include <sys/ksynch.h>
3825cf1a30Sjl #include <sys/ddi.h>
3925cf1a30Sjl #include <sys/sunddi.h>
40d8a0cca9Swh #include <sys/sunndi.h>
4125cf1a30Sjl #include <sys/ddifm.h>
4225cf1a30Sjl #include <sys/fm/protocol.h>
4325cf1a30Sjl #include <sys/fm/util.h>
4425cf1a30Sjl #include <sys/kmem.h>
4525cf1a30Sjl #include <sys/fm/io/opl_mc_fm.h>
4625cf1a30Sjl #include <sys/memlist.h>
4725cf1a30Sjl #include <sys/param.h>
480cc8ae86Sav #include <sys/disp.h>
4925cf1a30Sjl #include <vm/page.h>
5025cf1a30Sjl #include <sys/mc-opl.h>
510cc8ae86Sav #include <sys/opl.h>
520cc8ae86Sav #include <sys/opl_dimm.h>
530cc8ae86Sav #include <sys/scfd/scfostoescf.h>
54cfb9e062Shyw #include <sys/cpu_module.h>
55cfb9e062Shyw #include <vm/seg_kmem.h>
56cfb9e062Shyw #include <sys/vmem.h>
57cfb9e062Shyw #include <vm/hat_sfmmu.h>
58cfb9e062Shyw #include <sys/vmsystm.h>
59738dd194Shyw #include <sys/membar.h>
600b240fcdSwh #include <sys/mem.h>
6125cf1a30Sjl 
6225cf1a30Sjl /*
6325cf1a30Sjl  * Function prototypes
6425cf1a30Sjl  */
6525cf1a30Sjl static int mc_open(dev_t *, int, int, cred_t *);
6625cf1a30Sjl static int mc_close(dev_t, int, int, cred_t *);
6725cf1a30Sjl static int mc_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
6825cf1a30Sjl static int mc_attach(dev_info_t *, ddi_attach_cmd_t);
6925cf1a30Sjl static int mc_detach(dev_info_t *, ddi_detach_cmd_t);
7025cf1a30Sjl 
710cc8ae86Sav static int mc_poll_init(void);
720cc8ae86Sav static void mc_poll_fini(void);
7325cf1a30Sjl static int mc_board_add(mc_opl_t *mcp);
7425cf1a30Sjl static int mc_board_del(mc_opl_t *mcp);
7525cf1a30Sjl static int mc_suspend(mc_opl_t *mcp, uint32_t flag);
7625cf1a30Sjl static int mc_resume(mc_opl_t *mcp, uint32_t flag);
770cc8ae86Sav int opl_mc_suspend(void);
780cc8ae86Sav int opl_mc_resume(void);
7925cf1a30Sjl 
8025cf1a30Sjl static void insert_mcp(mc_opl_t *mcp);
8125cf1a30Sjl static void delete_mcp(mc_opl_t *mcp);
8225cf1a30Sjl 
8325cf1a30Sjl static int pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr);
8425cf1a30Sjl 
85738dd194Shyw static int mc_rangecheck_pa(mc_opl_t *mcp, uint64_t pa);
8625cf1a30Sjl 
8725cf1a30Sjl int mc_get_mem_unum(int, uint64_t, char *, int, int *);
880cc8ae86Sav int mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr);
890cc8ae86Sav int mc_get_mem_offset(uint64_t paddr, uint64_t *offp);
900cc8ae86Sav int mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp);
910cc8ae86Sav int mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf,
920cc8ae86Sav     int buflen, int *lenp);
930cc8ae86Sav mc_dimm_info_t *mc_get_dimm_list(mc_opl_t *mcp);
940cc8ae86Sav mc_dimm_info_t *mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp);
950cc8ae86Sav int mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, int bank,
960cc8ae86Sav     uint32_t mf_type, uint32_t d_slot);
970cc8ae86Sav static void mc_free_dimm_list(mc_dimm_info_t *d);
9825cf1a30Sjl static void mc_get_mlist(mc_opl_t *);
990cc8ae86Sav static void mc_polling(void);
1000cc8ae86Sav static int mc_opl_get_physical_board(int);
1010cc8ae86Sav 
102601c2e1eSdhain static void mc_clear_rewrite(mc_opl_t *mcp, int i);
103601c2e1eSdhain static void mc_set_rewrite(mc_opl_t *mcp, int bank, uint32_t addr, int state);
1040b240fcdSwh static int mc_scf_log_event(mc_flt_page_t *flt_pag);
105601c2e1eSdhain 
1060cc8ae86Sav #ifdef	DEBUG
1070cc8ae86Sav static int mc_ioctl_debug(dev_t, int, intptr_t, int, cred_t *, int *);
1080cc8ae86Sav void mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz);
1090cc8ae86Sav void mc_dump_dimm_info(board_dimm_info_t *bd_dimmp);
1100cc8ae86Sav #endif
11125cf1a30Sjl 
11225cf1a30Sjl #pragma weak opl_get_physical_board
11325cf1a30Sjl extern int opl_get_physical_board(int);
1140cc8ae86Sav extern int plat_max_boards(void);
11525cf1a30Sjl 
11625cf1a30Sjl /*
11725cf1a30Sjl  * Configuration data structures
11825cf1a30Sjl  */
11925cf1a30Sjl static struct cb_ops mc_cb_ops = {
12025cf1a30Sjl 	mc_open,			/* open */
12125cf1a30Sjl 	mc_close,			/* close */
12225cf1a30Sjl 	nulldev,			/* strategy */
12325cf1a30Sjl 	nulldev,			/* print */
12425cf1a30Sjl 	nodev,				/* dump */
12525cf1a30Sjl 	nulldev,			/* read */
12625cf1a30Sjl 	nulldev,			/* write */
12725cf1a30Sjl 	mc_ioctl,			/* ioctl */
12825cf1a30Sjl 	nodev,				/* devmap */
12925cf1a30Sjl 	nodev,				/* mmap */
13025cf1a30Sjl 	nodev,				/* segmap */
13125cf1a30Sjl 	nochpoll,			/* poll */
13225cf1a30Sjl 	ddi_prop_op,			/* cb_prop_op */
13325cf1a30Sjl 	0,				/* streamtab */
13425cf1a30Sjl 	D_MP | D_NEW | D_HOTPLUG,	/* Driver compatibility flag */
13525cf1a30Sjl 	CB_REV,				/* rev */
13625cf1a30Sjl 	nodev,				/* cb_aread */
13725cf1a30Sjl 	nodev				/* cb_awrite */
13825cf1a30Sjl };
13925cf1a30Sjl 
14025cf1a30Sjl static struct dev_ops mc_ops = {
14125cf1a30Sjl 	DEVO_REV,			/* rev */
14225cf1a30Sjl 	0,				/* refcnt  */
14325cf1a30Sjl 	ddi_getinfo_1to1,		/* getinfo */
14425cf1a30Sjl 	nulldev,			/* identify */
14525cf1a30Sjl 	nulldev,			/* probe */
14625cf1a30Sjl 	mc_attach,			/* attach */
14725cf1a30Sjl 	mc_detach,			/* detach */
14825cf1a30Sjl 	nulldev,			/* reset */
14925cf1a30Sjl 	&mc_cb_ops,			/* cb_ops */
15025cf1a30Sjl 	(struct bus_ops *)0,		/* bus_ops */
15119397407SSherry Moore 	nulldev,			/* power */
15219397407SSherry Moore 	ddi_quiesce_not_needed,			/* quiesce */
15325cf1a30Sjl };
15425cf1a30Sjl 
15525cf1a30Sjl /*
15625cf1a30Sjl  * Driver globals
15725cf1a30Sjl  */
15825cf1a30Sjl 
1590cc8ae86Sav static enum {
16078ed97a7Sjl 	MODEL_FF1,
16178ed97a7Sjl 	MODEL_FF2,
16278ed97a7Sjl 	MODEL_DC,
16378ed97a7Sjl 	MODEL_IKKAKU
1640cc8ae86Sav } plat_model = MODEL_DC;	/* The default behaviour is DC */
1650cc8ae86Sav 
1660cc8ae86Sav static struct plat_model_names {
1670cc8ae86Sav 	const char *unit_name;
1680cc8ae86Sav 	const char *mem_name;
1690cc8ae86Sav } model_names[] = {
1700cc8ae86Sav 	{ "MBU_A", "MEMB" },
1710cc8ae86Sav 	{ "MBU_B", "MEMB" },
17278ed97a7Sjl 	{ "CMU", "" },
17378ed97a7Sjl 	{ "MBU_A", "" }
1740cc8ae86Sav };
17525cf1a30Sjl 
1760cc8ae86Sav /*
1770cc8ae86Sav  * The DIMM Names for DC platform.
1780cc8ae86Sav  * The index into this table is made up of (bank, dslot),
1790cc8ae86Sav  * Where dslot occupies bits 0-1 and bank occupies 2-4.
1800cc8ae86Sav  */
1810cc8ae86Sav static char *mc_dc_dimm_unum_table[OPL_MAX_DIMMS] = {
1820cc8ae86Sav 	/* --------CMUnn----------- */
1830cc8ae86Sav 	/* --CS0-----|--CS1------ */
1840cc8ae86Sav 	/* -H-|--L-- | -H- | -L-- */
185c964b0e6Sraghuram 	"03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */
186c964b0e6Sraghuram 	"13A", "12A", "13B", "12B", /* Bank 1 (MAC 0 bank 1) */
187c964b0e6Sraghuram 	"23A", "22A", "23B", "22B", /* Bank 2 (MAC 1 bank 0) */
188c964b0e6Sraghuram 	"33A", "32A", "33B", "32B", /* Bank 3 (MAC 1 bank 1) */
189c964b0e6Sraghuram 	"01A", "00A", "01B", "00B", /* Bank 4 (MAC 2 bank 0) */
190c964b0e6Sraghuram 	"11A", "10A", "11B", "10B", /* Bank 5 (MAC 2 bank 1) */
191c964b0e6Sraghuram 	"21A", "20A", "21B", "20B", /* Bank 6 (MAC 3 bank 0) */
192c964b0e6Sraghuram 	"31A", "30A", "31B", "30B"  /* Bank 7 (MAC 3 bank 1) */
1930cc8ae86Sav };
1940cc8ae86Sav 
1950cc8ae86Sav /*
19678ed97a7Sjl  * The DIMM Names for FF1/FF2/IKKAKU platforms.
1970cc8ae86Sav  * The index into this table is made up of (board, bank, dslot),
1980cc8ae86Sav  * Where dslot occupies bits 0-1, bank occupies 2-4 and
1990cc8ae86Sav  * board occupies the bit 5.
2000cc8ae86Sav  */
2010cc8ae86Sav static char *mc_ff_dimm_unum_table[2 * OPL_MAX_DIMMS] = {
2020cc8ae86Sav 	/* --------CMU0---------- */
2030cc8ae86Sav 	/* --CS0-----|--CS1------ */
2040cc8ae86Sav 	/* -H-|--L-- | -H- | -L-- */
205c964b0e6Sraghuram 	"03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */
206c964b0e6Sraghuram 	"01A", "00A", "01B", "00B", /* Bank 1 (MAC 0 bank 1) */
207c964b0e6Sraghuram 	"13A", "12A", "13B", "12B", /* Bank 2 (MAC 1 bank 0) */
208c964b0e6Sraghuram 	"11A", "10A", "11B", "10B", /* Bank 3 (MAC 1 bank 1) */
209c964b0e6Sraghuram 	"23A", "22A", "23B", "22B", /* Bank 4 (MAC 2 bank 0) */
210c964b0e6Sraghuram 	"21A", "20A", "21B", "20B", /* Bank 5 (MAC 2 bank 1) */
211c964b0e6Sraghuram 	"33A", "32A", "33B", "32B", /* Bank 6 (MAC 3 bank 0) */
212c964b0e6Sraghuram 	"31A", "30A", "31B", "30B", /* Bank 7 (MAC 3 bank 1) */
2130cc8ae86Sav 	/* --------CMU1---------- */
2140cc8ae86Sav 	/* --CS0-----|--CS1------ */
2150cc8ae86Sav 	/* -H-|--L-- | -H- | -L-- */
216c964b0e6Sraghuram 	"43A", "42A", "43B", "42B", /* Bank 0 (MAC 0 bank 0) */
217c964b0e6Sraghuram 	"41A", "40A", "41B", "40B", /* Bank 1 (MAC 0 bank 1) */
218c964b0e6Sraghuram 	"53A", "52A", "53B", "52B", /* Bank 2 (MAC 1 bank 0) */
219c964b0e6Sraghuram 	"51A", "50A", "51B", "50B", /* Bank 3 (MAC 1 bank 1) */
220c964b0e6Sraghuram 	"63A", "62A", "63B", "62B", /* Bank 4 (MAC 2 bank 0) */
221c964b0e6Sraghuram 	"61A", "60A", "61B", "60B", /* Bank 5 (MAC 2 bank 1) */
222c964b0e6Sraghuram 	"73A", "72A", "73B", "72B", /* Bank 6 (MAC 3 bank 0) */
223c964b0e6Sraghuram 	"71A", "70A", "71B", "70B"  /* Bank 7 (MAC 3 bank 1) */
2240cc8ae86Sav };
2250cc8ae86Sav 
2260cc8ae86Sav #define	BD_BK_SLOT_TO_INDEX(bd, bk, s)			\
2270cc8ae86Sav 	(((bd & 0x01) << 5) | ((bk & 0x07) << 2) | (s & 0x03))
2280cc8ae86Sav 
2290cc8ae86Sav #define	INDEX_TO_BANK(i)			(((i) & 0x1C) >> 2)
2300cc8ae86Sav #define	INDEX_TO_SLOT(i)			((i) & 0x03)
2310cc8ae86Sav 
232aeb241b2Sav #define	SLOT_TO_CS(slot)	((slot & 0x3) >> 1)
233aeb241b2Sav 
2340cc8ae86Sav /* Isolation unit size is 64 MB */
2350cc8ae86Sav #define	MC_ISOLATION_BSIZE	(64 * 1024 * 1024)
2360cc8ae86Sav 
2370cc8ae86Sav #define	MC_MAX_SPEEDS 7
2380cc8ae86Sav 
2390cc8ae86Sav typedef struct {
2400cc8ae86Sav 	uint32_t mc_speeds;
2410cc8ae86Sav 	uint32_t mc_period;
2420cc8ae86Sav } mc_scan_speed_t;
2430cc8ae86Sav 
2440cc8ae86Sav #define	MC_CNTL_SPEED_SHIFT 26
2450cc8ae86Sav 
24637afe445Shyw /*
24737afe445Shyw  * In mirror mode, we normalized the bank idx to "even" since
24837afe445Shyw  * the HW treats them as one unit w.r.t programming.
24937afe445Shyw  * This bank index will be the "effective" bank index.
25037afe445Shyw  * All mirrored bank state info on mc_period, mc_speedup_period
25137afe445Shyw  * will be stored in the even bank structure to avoid code duplication.
25237afe445Shyw  */
25337afe445Shyw #define	MIRROR_IDX(bankidx)	(bankidx & ~1)
25437afe445Shyw 
2550cc8ae86Sav static mc_scan_speed_t	mc_scan_speeds[MC_MAX_SPEEDS] = {
2560cc8ae86Sav 	{0x6 << MC_CNTL_SPEED_SHIFT, 0},
2570cc8ae86Sav 	{0x5 << MC_CNTL_SPEED_SHIFT, 32},
2580cc8ae86Sav 	{0x4 << MC_CNTL_SPEED_SHIFT, 64},
2590cc8ae86Sav 	{0x3 << MC_CNTL_SPEED_SHIFT, 128},
2600cc8ae86Sav 	{0x2 << MC_CNTL_SPEED_SHIFT, 256},
2610cc8ae86Sav 	{0x1 << MC_CNTL_SPEED_SHIFT, 512},
2620cc8ae86Sav 	{0x0 << MC_CNTL_SPEED_SHIFT, 1024}
2630cc8ae86Sav };
2640cc8ae86Sav 
2650cc8ae86Sav static uint32_t	mc_max_speed = (0x6 << 26);
2660cc8ae86Sav 
2670cc8ae86Sav int mc_isolation_bsize = MC_ISOLATION_BSIZE;
2680cc8ae86Sav int mc_patrol_interval_sec = MC_PATROL_INTERVAL_SEC;
2690cc8ae86Sav int mc_max_scf_retry = 16;
2700cc8ae86Sav int mc_max_scf_logs = 64;
2710cc8ae86Sav int mc_max_errlog_processed = BANKNUM_PER_SB*2;
2720cc8ae86Sav int mc_scan_period = 12 * 60 * 60;	/* 12 hours period */
2730cc8ae86Sav int mc_max_rewrite_loop = 100;
2740cc8ae86Sav int mc_rewrite_delay = 10;
2750cc8ae86Sav /*
2760cc8ae86Sav  * it takes SCF about 300 m.s. to process a requst.  We can bail out
2770cc8ae86Sav  * if it is busy.  It does not pay to wait for it too long.
2780cc8ae86Sav  */
2790cc8ae86Sav int mc_max_scf_loop = 2;
2800cc8ae86Sav int mc_scf_delay = 100;
2810cc8ae86Sav int mc_pce_dropped = 0;
2820cc8ae86Sav int mc_poll_priority = MINCLSYSPRI;
283601c2e1eSdhain int mc_max_rewrite_retry = 6 * 60;
28425cf1a30Sjl 
2850cc8ae86Sav 
2860cc8ae86Sav /*
2871039f409Sav  * Mutex hierarchy in mc-opl
2880cc8ae86Sav  * If both mcmutex and mc_lock must be held,
2890cc8ae86Sav  * mcmutex must be acquired first, and then mc_lock.
2900cc8ae86Sav  */
2910cc8ae86Sav 
2920cc8ae86Sav static kmutex_t mcmutex;
2930cc8ae86Sav mc_opl_t *mc_instances[OPL_MAX_BOARDS];
2940cc8ae86Sav 
2950cc8ae86Sav static kmutex_t mc_polling_lock;
2960cc8ae86Sav static kcondvar_t mc_polling_cv;
2970cc8ae86Sav static kcondvar_t mc_poll_exit_cv;
2980cc8ae86Sav static int mc_poll_cmd = 0;
2990cc8ae86Sav static int mc_pollthr_running = 0;
3000cc8ae86Sav int mc_timeout_period = 0; /* this is in m.s. */
30125cf1a30Sjl void *mc_statep;
30225cf1a30Sjl 
30325cf1a30Sjl #ifdef	DEBUG
3042742aa22Shyw int oplmc_debug = 0;
30525cf1a30Sjl #endif
30625cf1a30Sjl 
3070cc8ae86Sav static int mc_debug_show_all = 0;
30825cf1a30Sjl 
30925cf1a30Sjl extern struct mod_ops mod_driverops;
31025cf1a30Sjl 
31125cf1a30Sjl static struct modldrv modldrv = {
31225cf1a30Sjl 	&mod_driverops,			/* module type, this one is a driver */
31319397407SSherry Moore 	"OPL Memory-controller",	/* module name */
31425cf1a30Sjl 	&mc_ops,			/* driver ops */
31525cf1a30Sjl };
31625cf1a30Sjl 
31725cf1a30Sjl static struct modlinkage modlinkage = {
31825cf1a30Sjl 	MODREV_1,		/* rev */
31925cf1a30Sjl 	(void *)&modldrv,
32025cf1a30Sjl 	NULL
32125cf1a30Sjl };
32225cf1a30Sjl 
32325cf1a30Sjl #pragma weak opl_get_mem_unum
3240cc8ae86Sav #pragma weak opl_get_mem_sid
3250cc8ae86Sav #pragma weak opl_get_mem_offset
3260cc8ae86Sav #pragma weak opl_get_mem_addr
3270cc8ae86Sav 
32825cf1a30Sjl extern int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *);
3290cc8ae86Sav extern int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp);
3300cc8ae86Sav extern int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp);
3310cc8ae86Sav extern int (*opl_get_mem_addr)(char *unum, char *sid, uint64_t offset,
3320cc8ae86Sav     uint64_t *paddr);
3330cc8ae86Sav 
33425cf1a30Sjl 
33525cf1a30Sjl /*
33625cf1a30Sjl  * pseudo-mc node portid format
33725cf1a30Sjl  *
33825cf1a30Sjl  *		[10]   = 0
33925cf1a30Sjl  *		[9]    = 1
34025cf1a30Sjl  *		[8]    = LSB_ID[4] = 0
34125cf1a30Sjl  *		[7:4]  = LSB_ID[3:0]
34225cf1a30Sjl  *		[3:0]  = 0
34325cf1a30Sjl  *
34425cf1a30Sjl  */
34525cf1a30Sjl 
34625cf1a30Sjl /*
34725cf1a30Sjl  * These are the module initialization routines.
34825cf1a30Sjl  */
34925cf1a30Sjl int
35025cf1a30Sjl _init(void)
35125cf1a30Sjl {
3520cc8ae86Sav 	int	error;
3530cc8ae86Sav 	int	plen;
3540cc8ae86Sav 	char	model[20];
3550cc8ae86Sav 	pnode_t	node;
35625cf1a30Sjl 
35725cf1a30Sjl 
35825cf1a30Sjl 	if ((error = ddi_soft_state_init(&mc_statep,
35925cf1a30Sjl 	    sizeof (mc_opl_t), 1)) != 0)
36025cf1a30Sjl 		return (error);
36125cf1a30Sjl 
3620cc8ae86Sav 	if ((error = mc_poll_init()) != 0) {
3630cc8ae86Sav 		ddi_soft_state_fini(&mc_statep);
3640cc8ae86Sav 		return (error);
3650cc8ae86Sav 	}
3660cc8ae86Sav 
36725cf1a30Sjl 	mutex_init(&mcmutex, NULL, MUTEX_DRIVER, NULL);
36825cf1a30Sjl 	if (&opl_get_mem_unum)
36925cf1a30Sjl 		opl_get_mem_unum = mc_get_mem_unum;
3700cc8ae86Sav 	if (&opl_get_mem_sid)
3710cc8ae86Sav 		opl_get_mem_sid = mc_get_mem_sid;
3720cc8ae86Sav 	if (&opl_get_mem_offset)
3730cc8ae86Sav 		opl_get_mem_offset = mc_get_mem_offset;
3740cc8ae86Sav 	if (&opl_get_mem_addr)
3750cc8ae86Sav 		opl_get_mem_addr = mc_get_mem_addr;
3760cc8ae86Sav 
3770cc8ae86Sav 	node = prom_rootnode();
3780cc8ae86Sav 	plen = prom_getproplen(node, "model");
3790cc8ae86Sav 
3800cc8ae86Sav 	if (plen > 0 && plen < sizeof (model)) {
3810cc8ae86Sav 		(void) prom_getprop(node, "model", model);
3820cc8ae86Sav 		model[plen] = '\0';
3830cc8ae86Sav 		if (strcmp(model, "FF1") == 0)
3840cc8ae86Sav 			plat_model = MODEL_FF1;
3850cc8ae86Sav 		else if (strcmp(model, "FF2") == 0)
3860cc8ae86Sav 			plat_model = MODEL_FF2;
3870cc8ae86Sav 		else if (strncmp(model, "DC", 2) == 0)
3880cc8ae86Sav 			plat_model = MODEL_DC;
38978ed97a7Sjl 		else if (strcmp(model, "IKKAKU") == 0)
39078ed97a7Sjl 			plat_model = MODEL_IKKAKU;
3910cc8ae86Sav 	}
39225cf1a30Sjl 
39325cf1a30Sjl 	error =  mod_install(&modlinkage);
39425cf1a30Sjl 	if (error != 0) {
39525cf1a30Sjl 		if (&opl_get_mem_unum)
39625cf1a30Sjl 			opl_get_mem_unum = NULL;
3970cc8ae86Sav 		if (&opl_get_mem_sid)
3980cc8ae86Sav 			opl_get_mem_sid = NULL;
3990cc8ae86Sav 		if (&opl_get_mem_offset)
4000cc8ae86Sav 			opl_get_mem_offset = NULL;
4010cc8ae86Sav 		if (&opl_get_mem_addr)
4020cc8ae86Sav 			opl_get_mem_addr = NULL;
40325cf1a30Sjl 		mutex_destroy(&mcmutex);
4040cc8ae86Sav 		mc_poll_fini();
40525cf1a30Sjl 		ddi_soft_state_fini(&mc_statep);
40625cf1a30Sjl 	}
40725cf1a30Sjl 	return (error);
40825cf1a30Sjl }
40925cf1a30Sjl 
41025cf1a30Sjl int
41125cf1a30Sjl _fini(void)
41225cf1a30Sjl {
41325cf1a30Sjl 	int error;
41425cf1a30Sjl 
41525cf1a30Sjl 	if ((error = mod_remove(&modlinkage)) != 0)
41625cf1a30Sjl 		return (error);
41725cf1a30Sjl 
41825cf1a30Sjl 	if (&opl_get_mem_unum)
41925cf1a30Sjl 		opl_get_mem_unum = NULL;
4200cc8ae86Sav 	if (&opl_get_mem_sid)
4210cc8ae86Sav 		opl_get_mem_sid = NULL;
4220cc8ae86Sav 	if (&opl_get_mem_offset)
4230cc8ae86Sav 		opl_get_mem_offset = NULL;
4240cc8ae86Sav 	if (&opl_get_mem_addr)
4250cc8ae86Sav 		opl_get_mem_addr = NULL;
42625cf1a30Sjl 
4270cc8ae86Sav 	mutex_destroy(&mcmutex);
4280cc8ae86Sav 	mc_poll_fini();
42925cf1a30Sjl 	ddi_soft_state_fini(&mc_statep);
43025cf1a30Sjl 
43125cf1a30Sjl 	return (0);
43225cf1a30Sjl }
43325cf1a30Sjl 
43425cf1a30Sjl int
43525cf1a30Sjl _info(struct modinfo *modinfop)
43625cf1a30Sjl {
43725cf1a30Sjl 	return (mod_info(&modlinkage, modinfop));
43825cf1a30Sjl }
43925cf1a30Sjl 
4400cc8ae86Sav static void
4410cc8ae86Sav mc_polling_thread()
4420cc8ae86Sav {
4430cc8ae86Sav 	mutex_enter(&mc_polling_lock);
4440cc8ae86Sav 	mc_pollthr_running = 1;
4450cc8ae86Sav 	while (!(mc_poll_cmd & MC_POLL_EXIT)) {
4460cc8ae86Sav 		mc_polling();
44707d06da5SSurya Prakki 		(void) cv_reltimedwait(&mc_polling_cv, &mc_polling_lock,
448d3d50737SRafael Vanoni 		    mc_timeout_period, TR_CLOCK_TICK);
4490cc8ae86Sav 	}
4500cc8ae86Sav 	mc_pollthr_running = 0;
4510cc8ae86Sav 
4520cc8ae86Sav 	/*
4530cc8ae86Sav 	 * signal if any one is waiting for this thread to exit.
4540cc8ae86Sav 	 */
4550cc8ae86Sav 	cv_signal(&mc_poll_exit_cv);
4560cc8ae86Sav 	mutex_exit(&mc_polling_lock);
4570cc8ae86Sav 	thread_exit();
4580cc8ae86Sav 	/* NOTREACHED */
4590cc8ae86Sav }
4600cc8ae86Sav 
4610cc8ae86Sav static int
4620cc8ae86Sav mc_poll_init()
4630cc8ae86Sav {
4640cc8ae86Sav 	mutex_init(&mc_polling_lock, NULL, MUTEX_DRIVER, NULL);
4650cc8ae86Sav 	cv_init(&mc_polling_cv, NULL, CV_DRIVER, NULL);
4660cc8ae86Sav 	cv_init(&mc_poll_exit_cv, NULL, CV_DRIVER, NULL);
4670cc8ae86Sav 	return (0);
4680cc8ae86Sav }
4690cc8ae86Sav 
4700cc8ae86Sav static void
4710cc8ae86Sav mc_poll_fini()
4720cc8ae86Sav {
4730cc8ae86Sav 	mutex_enter(&mc_polling_lock);
4740cc8ae86Sav 	if (mc_pollthr_running) {
4750cc8ae86Sav 		mc_poll_cmd = MC_POLL_EXIT;
4760cc8ae86Sav 		cv_signal(&mc_polling_cv);
4770cc8ae86Sav 		while (mc_pollthr_running) {
4780cc8ae86Sav 			cv_wait(&mc_poll_exit_cv, &mc_polling_lock);
4790cc8ae86Sav 		}
4800cc8ae86Sav 	}
4810cc8ae86Sav 	mutex_exit(&mc_polling_lock);
4820cc8ae86Sav 	mutex_destroy(&mc_polling_lock);
4830cc8ae86Sav 	cv_destroy(&mc_polling_cv);
4840cc8ae86Sav 	cv_destroy(&mc_poll_exit_cv);
4850cc8ae86Sav }
4860cc8ae86Sav 
48725cf1a30Sjl static int
48825cf1a30Sjl mc_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
48925cf1a30Sjl {
49025cf1a30Sjl 	mc_opl_t *mcp;
49125cf1a30Sjl 	int instance;
4920cc8ae86Sav 	int rv;
49325cf1a30Sjl 
49425cf1a30Sjl 	/* get the instance of this devi */
49525cf1a30Sjl 	instance = ddi_get_instance(devi);
49625cf1a30Sjl 
49725cf1a30Sjl 	switch (cmd) {
49825cf1a30Sjl 	case DDI_ATTACH:
49925cf1a30Sjl 		break;
50025cf1a30Sjl 	case DDI_RESUME:
50125cf1a30Sjl 		mcp = ddi_get_soft_state(mc_statep, instance);
5020cc8ae86Sav 		rv = mc_resume(mcp, MC_DRIVER_SUSPENDED);
5030cc8ae86Sav 		return (rv);
50425cf1a30Sjl 	default:
50525cf1a30Sjl 		return (DDI_FAILURE);
50625cf1a30Sjl 	}
50725cf1a30Sjl 
50825cf1a30Sjl 	if (ddi_soft_state_zalloc(mc_statep, instance) != DDI_SUCCESS)
50925cf1a30Sjl 		return (DDI_FAILURE);
51025cf1a30Sjl 
5110b240fcdSwh 	if (ddi_create_minor_node(devi, "mc-opl", S_IFCHR, instance,
5120b240fcdSwh 	    "ddi_mem_ctrl", 0) != DDI_SUCCESS) {
5130b240fcdSwh 		MC_LOG("mc_attach: create_minor_node failed\n");
5140b240fcdSwh 		return (DDI_FAILURE);
5150b240fcdSwh 	}
5160b240fcdSwh 
51725cf1a30Sjl 	if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) {
51825cf1a30Sjl 		goto bad;
51925cf1a30Sjl 	}
52025cf1a30Sjl 
5210cc8ae86Sav 	if (mc_timeout_period == 0) {
5220cc8ae86Sav 		mc_patrol_interval_sec = (int)ddi_getprop(DDI_DEV_T_ANY, devi,
523d8a0cca9Swh 		    DDI_PROP_DONTPASS, "mc-timeout-interval-sec",
524d8a0cca9Swh 		    mc_patrol_interval_sec);
525d8a0cca9Swh 		mc_timeout_period = drv_usectohz(1000000 *
526d8a0cca9Swh 		    mc_patrol_interval_sec / OPL_MAX_BOARDS);
5270cc8ae86Sav 	}
5280cc8ae86Sav 
52925cf1a30Sjl 	/* set informations in mc state */
53025cf1a30Sjl 	mcp->mc_dip = devi;
53125cf1a30Sjl 
53225cf1a30Sjl 	if (mc_board_add(mcp))
53325cf1a30Sjl 		goto bad;
53425cf1a30Sjl 
53525cf1a30Sjl 	insert_mcp(mcp);
5360cc8ae86Sav 
5370cc8ae86Sav 	/*
5380cc8ae86Sav 	 * Start the polling thread if it is not running already.
5390cc8ae86Sav 	 */
5400cc8ae86Sav 	mutex_enter(&mc_polling_lock);
5410cc8ae86Sav 	if (!mc_pollthr_running) {
5420cc8ae86Sav 		(void) thread_create(NULL, 0, (void (*)())mc_polling_thread,
543d8a0cca9Swh 		    NULL, 0, &p0, TS_RUN, mc_poll_priority);
5440cc8ae86Sav 	}
5450cc8ae86Sav 	mutex_exit(&mc_polling_lock);
54625cf1a30Sjl 	ddi_report_dev(devi);
54725cf1a30Sjl 
54825cf1a30Sjl 	return (DDI_SUCCESS);
54925cf1a30Sjl 
55025cf1a30Sjl bad:
5510b240fcdSwh 	ddi_remove_minor_node(devi, NULL);
55225cf1a30Sjl 	ddi_soft_state_free(mc_statep, instance);
55325cf1a30Sjl 	return (DDI_FAILURE);
55425cf1a30Sjl }
55525cf1a30Sjl 
55625cf1a30Sjl /* ARGSUSED */
55725cf1a30Sjl static int
55825cf1a30Sjl mc_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
55925cf1a30Sjl {
5600cc8ae86Sav 	int rv;
56125cf1a30Sjl 	int instance;
56225cf1a30Sjl 	mc_opl_t *mcp;
56325cf1a30Sjl 
56425cf1a30Sjl 	/* get the instance of this devi */
56525cf1a30Sjl 	instance = ddi_get_instance(devi);
56625cf1a30Sjl 	if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) {
56725cf1a30Sjl 		return (DDI_FAILURE);
56825cf1a30Sjl 	}
56925cf1a30Sjl 
57025cf1a30Sjl 	switch (cmd) {
57125cf1a30Sjl 	case DDI_SUSPEND:
5720cc8ae86Sav 		rv = mc_suspend(mcp, MC_DRIVER_SUSPENDED);
5730cc8ae86Sav 		return (rv);
57425cf1a30Sjl 	case DDI_DETACH:
57525cf1a30Sjl 		break;
57625cf1a30Sjl 	default:
57725cf1a30Sjl 		return (DDI_FAILURE);
57825cf1a30Sjl 	}
57925cf1a30Sjl 
5800cc8ae86Sav 	delete_mcp(mcp);
58125cf1a30Sjl 	if (mc_board_del(mcp) != DDI_SUCCESS) {
58225cf1a30Sjl 		return (DDI_FAILURE);
58325cf1a30Sjl 	}
58425cf1a30Sjl 
5850b240fcdSwh 	ddi_remove_minor_node(devi, NULL);
5860b240fcdSwh 
58725cf1a30Sjl 	/* free up the soft state */
58825cf1a30Sjl 	ddi_soft_state_free(mc_statep, instance);
58925cf1a30Sjl 
59025cf1a30Sjl 	return (DDI_SUCCESS);
59125cf1a30Sjl }
59225cf1a30Sjl 
59325cf1a30Sjl /* ARGSUSED */
59425cf1a30Sjl static int
59525cf1a30Sjl mc_open(dev_t *devp, int flag, int otyp, cred_t *credp)
59625cf1a30Sjl {
59725cf1a30Sjl 	return (0);
59825cf1a30Sjl }
59925cf1a30Sjl 
60025cf1a30Sjl /* ARGSUSED */
60125cf1a30Sjl static int
60225cf1a30Sjl mc_close(dev_t devp, int flag, int otyp, cred_t *credp)
60325cf1a30Sjl {
60425cf1a30Sjl 	return (0);
60525cf1a30Sjl }
60625cf1a30Sjl 
60725cf1a30Sjl /* ARGSUSED */
60825cf1a30Sjl static int
60925cf1a30Sjl mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
61025cf1a30Sjl 	int *rvalp)
61125cf1a30Sjl {
6120b240fcdSwh 	mc_flt_page_t flt_page;
6130b240fcdSwh 
6140b240fcdSwh 	if (cmd == MCIOC_FAULT_PAGE) {
6150b240fcdSwh 		if (arg == NULL)
6160b240fcdSwh 			return (EINVAL);
6170b240fcdSwh 
6180b240fcdSwh 		if (ddi_copyin((const void *)arg, (void *)&flt_page,
6190b240fcdSwh 		    sizeof (mc_flt_page_t), 0) < 0)
6200b240fcdSwh 			return (EFAULT);
6210b240fcdSwh 
6220b240fcdSwh 		return (mc_scf_log_event(&flt_page));
6230b240fcdSwh 	}
6240cc8ae86Sav #ifdef DEBUG
6250cc8ae86Sav 	return (mc_ioctl_debug(dev, cmd, arg, mode, credp, rvalp));
6260cc8ae86Sav #else
6270b240fcdSwh 	return (ENOTTY);
6280cc8ae86Sav #endif
62925cf1a30Sjl }
63025cf1a30Sjl 
63125cf1a30Sjl /*
63225cf1a30Sjl  * PA validity check:
633738dd194Shyw  * This function return 1 if the PA is a valid PA
634738dd194Shyw  * in the running Solaris instance i.e. in physinstall
635738dd194Shyw  * Otherwise, return 0.
63625cf1a30Sjl  */
63725cf1a30Sjl 
63825cf1a30Sjl /* ARGSUSED */
63925cf1a30Sjl static int
64025cf1a30Sjl pa_is_valid(mc_opl_t *mcp, uint64_t addr)
64125cf1a30Sjl {
64225cf1a30Sjl 	if (mcp->mlist == NULL)
64325cf1a30Sjl 		mc_get_mlist(mcp);
64425cf1a30Sjl 
64525cf1a30Sjl 	if (mcp->mlist && address_in_memlist(mcp->mlist, addr, 0)) {
64625cf1a30Sjl 		return (1);
64725cf1a30Sjl 	}
64825cf1a30Sjl 	return (0);
64925cf1a30Sjl }
65025cf1a30Sjl 
65125cf1a30Sjl /*
65225cf1a30Sjl  * mac-pa translation routines.
65325cf1a30Sjl  *
65425cf1a30Sjl  *    Input: mc driver state, (LSB#, Bank#, DIMM address)
65525cf1a30Sjl  *    Output: physical address
65625cf1a30Sjl  *
65725cf1a30Sjl  *    Valid   - return value:  0
65825cf1a30Sjl  *    Invalid - return value: -1
65925cf1a30Sjl  */
66025cf1a30Sjl static int
66125cf1a30Sjl mcaddr_to_pa(mc_opl_t *mcp, mc_addr_t *maddr, uint64_t *pa)
66225cf1a30Sjl {
66325cf1a30Sjl 	int i;
66425cf1a30Sjl 	uint64_t pa_offset = 0;
66525cf1a30Sjl 	int cs = (maddr->ma_dimm_addr >> CS_SHIFT) & 1;
66625cf1a30Sjl 	int bank = maddr->ma_bank;
66725cf1a30Sjl 	mc_addr_t maddr1;
66825cf1a30Sjl 	int bank0, bank1;
66925cf1a30Sjl 
67025cf1a30Sjl 	MC_LOG("mcaddr /LSB%d/B%d/%x\n", maddr->ma_bd, bank,
671d8a0cca9Swh 	    maddr->ma_dimm_addr);
67225cf1a30Sjl 
67325cf1a30Sjl 	/* loc validity check */
67425cf1a30Sjl 	ASSERT(maddr->ma_bd >= 0 && OPL_BOARD_MAX > maddr->ma_bd);
67525cf1a30Sjl 	ASSERT(bank >= 0 && OPL_BANK_MAX > bank);
67625cf1a30Sjl 
67725cf1a30Sjl 	/* Do translation */
67825cf1a30Sjl 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
67925cf1a30Sjl 		int pa_bit = 0;
68025cf1a30Sjl 		int mc_bit = mcp->mc_trans_table[cs][i];
68125cf1a30Sjl 		if (mc_bit < MC_ADDRESS_BITS) {
68225cf1a30Sjl 			pa_bit = (maddr->ma_dimm_addr >> mc_bit) & 1;
68325cf1a30Sjl 		} else if (mc_bit == MP_NONE) {
68425cf1a30Sjl 			pa_bit = 0;
68525cf1a30Sjl 		} else if (mc_bit == MP_BANK_0) {
68625cf1a30Sjl 			pa_bit = bank & 1;
68725cf1a30Sjl 		} else if (mc_bit == MP_BANK_1) {
68825cf1a30Sjl 			pa_bit = (bank >> 1) & 1;
68925cf1a30Sjl 		} else if (mc_bit == MP_BANK_2) {
69025cf1a30Sjl 			pa_bit = (bank >> 2) & 1;
69125cf1a30Sjl 		}
69225cf1a30Sjl 		pa_offset |= ((uint64_t)pa_bit) << i;
69325cf1a30Sjl 	}
69425cf1a30Sjl 	*pa = mcp->mc_start_address + pa_offset;
69525cf1a30Sjl 	MC_LOG("pa = %lx\n", *pa);
69625cf1a30Sjl 
69725cf1a30Sjl 	if (pa_to_maddr(mcp, *pa, &maddr1) == -1) {
6980cc8ae86Sav 		cmn_err(CE_WARN, "mcaddr_to_pa: /LSB%d/B%d/%x failed to "
6990cc8ae86Sav 		    "convert PA %lx\n", maddr->ma_bd, bank,
7000cc8ae86Sav 		    maddr->ma_dimm_addr, *pa);
70125cf1a30Sjl 		return (-1);
70225cf1a30Sjl 	}
70325cf1a30Sjl 
7040cc8ae86Sav 	/*
7050cc8ae86Sav 	 * In mirror mode, PA is always translated to the even bank.
7060cc8ae86Sav 	 */
70725cf1a30Sjl 	if (IS_MIRROR(mcp, maddr->ma_bank)) {
70825cf1a30Sjl 		bank0 = maddr->ma_bank & ~(1);
70925cf1a30Sjl 		bank1 = maddr1.ma_bank & ~(1);
71025cf1a30Sjl 	} else {
71125cf1a30Sjl 		bank0 = maddr->ma_bank;
71225cf1a30Sjl 		bank1 = maddr1.ma_bank;
71325cf1a30Sjl 	}
71425cf1a30Sjl 	/*
71525cf1a30Sjl 	 * there is no need to check ma_bd because it is generated from
71625cf1a30Sjl 	 * mcp.  They are the same.
71725cf1a30Sjl 	 */
718d8a0cca9Swh 	if ((bank0 == bank1) && (maddr->ma_dimm_addr ==
719d8a0cca9Swh 	    maddr1.ma_dimm_addr)) {
72025cf1a30Sjl 		return (0);
72125cf1a30Sjl 	} else {
7220b240fcdSwh 		MC_LOG("Translation error source /LSB%d/B%d/%x, "
723d8a0cca9Swh 		    "PA %lx, target /LSB%d/B%d/%x\n", maddr->ma_bd, bank,
724d8a0cca9Swh 		    maddr->ma_dimm_addr, *pa, maddr1.ma_bd, maddr1.ma_bank,
725d8a0cca9Swh 		    maddr1.ma_dimm_addr);
72625cf1a30Sjl 		return (-1);
72725cf1a30Sjl 	}
72825cf1a30Sjl }
72925cf1a30Sjl 
73025cf1a30Sjl /*
73125cf1a30Sjl  * PA to CS (used by pa_to_maddr).
73225cf1a30Sjl  */
73325cf1a30Sjl static int
73425cf1a30Sjl pa_to_cs(mc_opl_t *mcp, uint64_t pa_offset)
73525cf1a30Sjl {
73625cf1a30Sjl 	int i;
737738dd194Shyw 	int cs = 1;
73825cf1a30Sjl 
73925cf1a30Sjl 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
74025cf1a30Sjl 		/* MAC address bit<29> is arranged on the same PA bit */
74125cf1a30Sjl 		/* on both table. So we may use any table. */
74225cf1a30Sjl 		if (mcp->mc_trans_table[0][i] == CS_SHIFT) {
74325cf1a30Sjl 			cs = (pa_offset >> i) & 1;
74425cf1a30Sjl 			break;
74525cf1a30Sjl 		}
74625cf1a30Sjl 	}
74725cf1a30Sjl 	return (cs);
74825cf1a30Sjl }
74925cf1a30Sjl 
75025cf1a30Sjl /*
75125cf1a30Sjl  * PA to DIMM (used by pa_to_maddr).
75225cf1a30Sjl  */
75325cf1a30Sjl /* ARGSUSED */
75425cf1a30Sjl static uint32_t
75525cf1a30Sjl pa_to_dimm(mc_opl_t *mcp, uint64_t pa_offset)
75625cf1a30Sjl {
75725cf1a30Sjl 	int i;
75825cf1a30Sjl 	int cs = pa_to_cs(mcp, pa_offset);
75925cf1a30Sjl 	uint32_t dimm_addr = 0;
76025cf1a30Sjl 
76125cf1a30Sjl 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
76225cf1a30Sjl 		int pa_bit_value = (pa_offset >> i) & 1;
76325cf1a30Sjl 		int mc_bit = mcp->mc_trans_table[cs][i];
76425cf1a30Sjl 		if (mc_bit < MC_ADDRESS_BITS) {
76525cf1a30Sjl 			dimm_addr |= pa_bit_value << mc_bit;
76625cf1a30Sjl 		}
76725cf1a30Sjl 	}
768738dd194Shyw 	dimm_addr |= cs << CS_SHIFT;
76925cf1a30Sjl 	return (dimm_addr);
77025cf1a30Sjl }
77125cf1a30Sjl 
77225cf1a30Sjl /*
77325cf1a30Sjl  * PA to Bank (used by pa_to_maddr).
77425cf1a30Sjl  */
77525cf1a30Sjl static int
77625cf1a30Sjl pa_to_bank(mc_opl_t *mcp, uint64_t pa_offset)
77725cf1a30Sjl {
77825cf1a30Sjl 	int i;
77925cf1a30Sjl 	int cs = pa_to_cs(mcp, pa_offset);
78025cf1a30Sjl 	int bankno = mcp->mc_trans_table[cs][INDEX_OF_BANK_SUPPLEMENT_BIT];
78125cf1a30Sjl 
78225cf1a30Sjl 
78325cf1a30Sjl 	for (i = 0; i < PA_BITS_FOR_MAC; i++) {
78425cf1a30Sjl 		int pa_bit_value = (pa_offset >> i) & 1;
78525cf1a30Sjl 		int mc_bit = mcp->mc_trans_table[cs][i];
78625cf1a30Sjl 		switch (mc_bit) {
78725cf1a30Sjl 		case MP_BANK_0:
78825cf1a30Sjl 			bankno |= pa_bit_value;
78925cf1a30Sjl 			break;
79025cf1a30Sjl 		case MP_BANK_1:
79125cf1a30Sjl 			bankno |= pa_bit_value << 1;
79225cf1a30Sjl 			break;
79325cf1a30Sjl 		case MP_BANK_2:
79425cf1a30Sjl 			bankno |= pa_bit_value << 2;
79525cf1a30Sjl 			break;
79625cf1a30Sjl 		}
79725cf1a30Sjl 	}
79825cf1a30Sjl 
79925cf1a30Sjl 	return (bankno);
80025cf1a30Sjl }
80125cf1a30Sjl 
80225cf1a30Sjl /*
80325cf1a30Sjl  * PA to MAC address translation
80425cf1a30Sjl  *
80525cf1a30Sjl  *   Input: MAC driver state, physicall adress
80625cf1a30Sjl  *   Output: LSB#, Bank id, mac address
80725cf1a30Sjl  *
80825cf1a30Sjl  *    Valid   - return value:  0
80925cf1a30Sjl  *    Invalid - return value: -1
81025cf1a30Sjl  */
81125cf1a30Sjl 
81225cf1a30Sjl int
81325cf1a30Sjl pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr)
81425cf1a30Sjl {
81525cf1a30Sjl 	uint64_t pa_offset;
81625cf1a30Sjl 
817738dd194Shyw 	if (!mc_rangecheck_pa(mcp, pa))
81825cf1a30Sjl 		return (-1);
81925cf1a30Sjl 
82025cf1a30Sjl 	/* Do translation */
82125cf1a30Sjl 	pa_offset = pa - mcp->mc_start_address;
82225cf1a30Sjl 
82325cf1a30Sjl 	maddr->ma_bd = mcp->mc_board_num;
824aeb241b2Sav 	maddr->ma_phys_bd = mcp->mc_phys_board_num;
82525cf1a30Sjl 	maddr->ma_bank = pa_to_bank(mcp, pa_offset);
82625cf1a30Sjl 	maddr->ma_dimm_addr = pa_to_dimm(mcp, pa_offset);
827d8a0cca9Swh 	MC_LOG("pa %lx -> mcaddr /LSB%d/B%d/%x\n", pa_offset, maddr->ma_bd,
828d8a0cca9Swh 	    maddr->ma_bank, maddr->ma_dimm_addr);
82925cf1a30Sjl 	return (0);
83025cf1a30Sjl }
83125cf1a30Sjl 
8320cc8ae86Sav /*
8330cc8ae86Sav  * UNUM format for DC is "/CMUnn/MEMxyZ", where
8340cc8ae86Sav  *	nn = 00..03 for DC1 and 00..07 for DC2 and 00..15 for DC3.
8350cc8ae86Sav  *	x = MAC 0..3
8360cc8ae86Sav  *	y = 0..3 (slot info).
8370cc8ae86Sav  *	Z = 'A' or 'B'
8380cc8ae86Sav  *
8390cc8ae86Sav  * UNUM format for FF1 is "/MBU_A/MEMBx/MEMyZ", where
8400cc8ae86Sav  *	x = 0..3 (MEMB number)
8410cc8ae86Sav  *	y = 0..3 (slot info).
8420cc8ae86Sav  *	Z = 'A' or 'B'
8430cc8ae86Sav  *
84478ed97a7Sjl  * UNUM format for FF2 is "/MBU_B/MEMBx/MEMyZ", where
8450cc8ae86Sav  *	x = 0..7 (MEMB number)
8460cc8ae86Sav  *	y = 0..3 (slot info).
8470cc8ae86Sav  *	Z = 'A' or 'B'
84878ed97a7Sjl  *
84978ed97a7Sjl  * UNUM format for IKKAKU is "/MBU_A/MEMyZ", where
85078ed97a7Sjl  *	y = 0..3 (slot info).
85178ed97a7Sjl  *	Z = 'A' or 'B'
85278ed97a7Sjl  *
8530cc8ae86Sav  */
8540cc8ae86Sav int
855aeb241b2Sav mc_set_mem_unum(char *buf, int buflen, int sb, int bank,
8560cc8ae86Sav     uint32_t mf_type, uint32_t d_slot)
8570cc8ae86Sav {
8580cc8ae86Sav 	char *dimmnm;
8590cc8ae86Sav 	char memb_num;
860aeb241b2Sav 	int cs;
8610cc8ae86Sav 	int i;
862aeb241b2Sav 	int j;
8630cc8ae86Sav 
864aeb241b2Sav 	cs = SLOT_TO_CS(d_slot);
8650cc8ae86Sav 
86678ed97a7Sjl 	switch (plat_model) {
86778ed97a7Sjl 	case MODEL_DC:
868056c948bStsien 		if (mf_type == FLT_TYPE_INTERMITTENT_CE ||
869056c948bStsien 		    mf_type == FLT_TYPE_PERMANENT_CE) {
8700cc8ae86Sav 			i = BD_BK_SLOT_TO_INDEX(0, bank, d_slot);
8710cc8ae86Sav 			dimmnm = mc_dc_dimm_unum_table[i];
87207d06da5SSurya Prakki 			(void) snprintf(buf, buflen, "/%s%02d/MEM%s",
8730cc8ae86Sav 			    model_names[plat_model].unit_name, sb, dimmnm);
8740cc8ae86Sav 		} else {
8750cc8ae86Sav 			i = BD_BK_SLOT_TO_INDEX(0, bank, 0);
876aeb241b2Sav 			j = (cs == 0) ?  i : i + 2;
87707d06da5SSurya Prakki 			(void) snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s",
8780cc8ae86Sav 			    model_names[plat_model].unit_name, sb,
879aeb241b2Sav 			    mc_dc_dimm_unum_table[j],
880aeb241b2Sav 			    mc_dc_dimm_unum_table[j + 1]);
8810cc8ae86Sav 		}
88278ed97a7Sjl 		break;
88378ed97a7Sjl 	case MODEL_FF1:
88478ed97a7Sjl 	case MODEL_FF2:
885056c948bStsien 		if (mf_type == FLT_TYPE_INTERMITTENT_CE ||
886056c948bStsien 		    mf_type == FLT_TYPE_PERMANENT_CE) {
887aeb241b2Sav 			i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot);
8880cc8ae86Sav 			dimmnm = mc_ff_dimm_unum_table[i];
8890cc8ae86Sav 			memb_num = dimmnm[0];
89007d06da5SSurya Prakki 			(void) snprintf(buf, buflen, "/%s/%s%c/MEM%s",
8910cc8ae86Sav 			    model_names[plat_model].unit_name,
8920cc8ae86Sav 			    model_names[plat_model].mem_name,
8930cc8ae86Sav 			    memb_num, &dimmnm[1]);
8940cc8ae86Sav 		} else {
8950cc8ae86Sav 			i = BD_BK_SLOT_TO_INDEX(sb, bank, 0);
896aeb241b2Sav 			j = (cs == 0) ?  i : i + 2;
8970cc8ae86Sav 			memb_num = mc_ff_dimm_unum_table[i][0],
89807d06da5SSurya Prakki 			    (void) snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s",
8990cc8ae86Sav 			    model_names[plat_model].unit_name,
9000cc8ae86Sav 			    model_names[plat_model].mem_name, memb_num,
901aeb241b2Sav 			    &mc_ff_dimm_unum_table[j][1],
902aeb241b2Sav 			    &mc_ff_dimm_unum_table[j + 1][1]);
9030cc8ae86Sav 		}
90478ed97a7Sjl 		break;
90578ed97a7Sjl 	case MODEL_IKKAKU:
90678ed97a7Sjl 		if (mf_type == FLT_TYPE_INTERMITTENT_CE ||
90778ed97a7Sjl 		    mf_type == FLT_TYPE_PERMANENT_CE) {
90878ed97a7Sjl 			i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot);
90978ed97a7Sjl 			dimmnm = mc_ff_dimm_unum_table[i];
91007d06da5SSurya Prakki 			(void) snprintf(buf, buflen, "/%s/MEM%s",
91178ed97a7Sjl 			    model_names[plat_model].unit_name, &dimmnm[1]);
91278ed97a7Sjl 		} else {
91378ed97a7Sjl 			i = BD_BK_SLOT_TO_INDEX(sb, bank, 0);
91478ed97a7Sjl 			j = (cs == 0) ?  i : i + 2;
91578ed97a7Sjl 			memb_num = mc_ff_dimm_unum_table[i][0],
91607d06da5SSurya Prakki 			    (void) snprintf(buf, buflen, "/%s/MEM%s MEM%s",
91778ed97a7Sjl 			    model_names[plat_model].unit_name,
91878ed97a7Sjl 			    &mc_ff_dimm_unum_table[j][1],
91978ed97a7Sjl 			    &mc_ff_dimm_unum_table[j + 1][1]);
92078ed97a7Sjl 		}
92178ed97a7Sjl 		break;
92278ed97a7Sjl 	default:
92378ed97a7Sjl 		return (-1);
9240cc8ae86Sav 	}
9250cc8ae86Sav 	return (0);
9260cc8ae86Sav }
9270cc8ae86Sav 
92825cf1a30Sjl static void
92925cf1a30Sjl mc_ereport_post(mc_aflt_t *mc_aflt)
93025cf1a30Sjl {
93125cf1a30Sjl 	char buf[FM_MAX_CLASS];
93225cf1a30Sjl 	char device_path[MAXPATHLEN];
9330cc8ae86Sav 	char sid[MAXPATHLEN];
93425cf1a30Sjl 	nv_alloc_t *nva = NULL;
93525cf1a30Sjl 	nvlist_t *ereport, *detector, *resource;
93625cf1a30Sjl 	errorq_elem_t *eqep;
93725cf1a30Sjl 	int nflts;
93825cf1a30Sjl 	mc_flt_stat_t *flt_stat;
9390cc8ae86Sav 	int i, n;
9400cc8ae86Sav 	int blen = MAXPATHLEN;
9410cc8ae86Sav 	char *p, *s = NULL;
94225cf1a30Sjl 	uint32_t values[2], synd[2], dslot[2];
9430cc8ae86Sav 	uint64_t offset = (uint64_t)-1;
9440cc8ae86Sav 	int ret = -1;
94525cf1a30Sjl 
94625cf1a30Sjl 	if (panicstr) {
94725cf1a30Sjl 		eqep = errorq_reserve(ereport_errorq);
94825cf1a30Sjl 		if (eqep == NULL)
94925cf1a30Sjl 			return;
95025cf1a30Sjl 		ereport = errorq_elem_nvl(ereport_errorq, eqep);
95125cf1a30Sjl 		nva = errorq_elem_nva(ereport_errorq, eqep);
95225cf1a30Sjl 	} else {
95325cf1a30Sjl 		ereport = fm_nvlist_create(nva);
95425cf1a30Sjl 	}
95525cf1a30Sjl 
95625cf1a30Sjl 	/*
95725cf1a30Sjl 	 * Create the scheme "dev" FMRI.
95825cf1a30Sjl 	 */
95925cf1a30Sjl 	detector = fm_nvlist_create(nva);
96025cf1a30Sjl 	resource = fm_nvlist_create(nva);
96125cf1a30Sjl 
96225cf1a30Sjl 	nflts = mc_aflt->mflt_nflts;
96325cf1a30Sjl 
96425cf1a30Sjl 	ASSERT(nflts >= 1 && nflts <= 2);
96525cf1a30Sjl 
96625cf1a30Sjl 	flt_stat = mc_aflt->mflt_stat[0];
96725cf1a30Sjl 	(void) ddi_pathname(mc_aflt->mflt_mcp->mc_dip, device_path);
96825cf1a30Sjl 	(void) fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL,
969*392e836bSGavin Maltby 	    device_path, NULL, NULL);
97025cf1a30Sjl 
97125cf1a30Sjl 	/*
97225cf1a30Sjl 	 * Encode all the common data into the ereport.
97325cf1a30Sjl 	 */
974d8a0cca9Swh 	(void) snprintf(buf, FM_MAX_CLASS, "%s.%s-%s", MC_OPL_ERROR_CLASS,
975d8a0cca9Swh 	    mc_aflt->mflt_is_ptrl ? MC_OPL_PTRL_SUBCLASS : MC_OPL_MI_SUBCLASS,
976d8a0cca9Swh 	    mc_aflt->mflt_erpt_class);
97725cf1a30Sjl 
97825cf1a30Sjl 	MC_LOG("mc_ereport_post: ereport %s\n", buf);
97925cf1a30Sjl 
98025cf1a30Sjl 
98125cf1a30Sjl 	fm_ereport_set(ereport, FM_EREPORT_VERSION, buf,
982d8a0cca9Swh 	    fm_ena_generate(mc_aflt->mflt_id, FM_ENA_FMT1), detector, NULL);
98325cf1a30Sjl 
98425cf1a30Sjl 	/*
98525cf1a30Sjl 	 * Set payload.
98625cf1a30Sjl 	 */
98725cf1a30Sjl 	fm_payload_set(ereport, MC_OPL_BOARD, DATA_TYPE_UINT32,
988d8a0cca9Swh 	    flt_stat->mf_flt_maddr.ma_bd, NULL);
98925cf1a30Sjl 
99025cf1a30Sjl 	fm_payload_set(ereport, MC_OPL_PA, DATA_TYPE_UINT64,
991d8a0cca9Swh 	    flt_stat->mf_flt_paddr, NULL);
99225cf1a30Sjl 
993056c948bStsien 	if (flt_stat->mf_type == FLT_TYPE_INTERMITTENT_CE ||
994056c948bStsien 	    flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) {
995d8a0cca9Swh 		fm_payload_set(ereport, MC_OPL_FLT_TYPE, DATA_TYPE_UINT8,
996d8a0cca9Swh 		    ECC_STICKY, NULL);
99725cf1a30Sjl 	}
99825cf1a30Sjl 
99925cf1a30Sjl 	for (i = 0; i < nflts; i++)
100025cf1a30Sjl 		values[i] = mc_aflt->mflt_stat[i]->mf_flt_maddr.ma_bank;
100125cf1a30Sjl 
1002d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_BANK, DATA_TYPE_UINT32_ARRAY, nflts,
1003d8a0cca9Swh 	    values, NULL);
100425cf1a30Sjl 
100525cf1a30Sjl 	for (i = 0; i < nflts; i++)
100625cf1a30Sjl 		values[i] = mc_aflt->mflt_stat[i]->mf_cntl;
100725cf1a30Sjl 
1008d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_STATUS, DATA_TYPE_UINT32_ARRAY, nflts,
1009d8a0cca9Swh 	    values, NULL);
101025cf1a30Sjl 
101125cf1a30Sjl 	for (i = 0; i < nflts; i++)
101225cf1a30Sjl 		values[i] = mc_aflt->mflt_stat[i]->mf_err_add;
101325cf1a30Sjl 
1014056c948bStsien 	/* offset is set only for PCE and ICE */
1015056c948bStsien 	if (mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_INTERMITTENT_CE ||
1016056c948bStsien 	    mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_PERMANENT_CE) {
10170cc8ae86Sav 		offset = values[0];
10180cc8ae86Sav 
10190cc8ae86Sav 	}
1020d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_ERR_ADD, DATA_TYPE_UINT32_ARRAY, nflts,
1021d8a0cca9Swh 	    values, NULL);
102225cf1a30Sjl 
102325cf1a30Sjl 	for (i = 0; i < nflts; i++)
102425cf1a30Sjl 		values[i] = mc_aflt->mflt_stat[i]->mf_err_log;
102525cf1a30Sjl 
1026d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_ERR_LOG, DATA_TYPE_UINT32_ARRAY, nflts,
1027d8a0cca9Swh 	    values, NULL);
102825cf1a30Sjl 
102925cf1a30Sjl 	for (i = 0; i < nflts; i++) {
103025cf1a30Sjl 		flt_stat = mc_aflt->mflt_stat[i];
103125cf1a30Sjl 		if (flt_stat->mf_errlog_valid) {
103225cf1a30Sjl 			synd[i] = flt_stat->mf_synd;
103325cf1a30Sjl 			dslot[i] = flt_stat->mf_dimm_slot;
103425cf1a30Sjl 			values[i] = flt_stat->mf_dram_place;
103525cf1a30Sjl 		} else {
103625cf1a30Sjl 			synd[i] = 0;
103725cf1a30Sjl 			dslot[i] = 0;
103825cf1a30Sjl 			values[i] = 0;
103925cf1a30Sjl 		}
104025cf1a30Sjl 	}
104125cf1a30Sjl 
1042d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_ERR_SYND, DATA_TYPE_UINT32_ARRAY, nflts,
1043d8a0cca9Swh 	    synd, NULL);
104425cf1a30Sjl 
1045d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_ERR_DIMMSLOT, DATA_TYPE_UINT32_ARRAY,
1046d8a0cca9Swh 	    nflts, dslot, NULL);
104725cf1a30Sjl 
1048d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_ERR_DRAM, DATA_TYPE_UINT32_ARRAY, nflts,
1049d8a0cca9Swh 	    values, NULL);
105025cf1a30Sjl 
105125cf1a30Sjl 	device_path[0] = 0;
105225cf1a30Sjl 	p = &device_path[0];
10530cc8ae86Sav 	sid[0] = 0;
10540cc8ae86Sav 	s = &sid[0];
10550cc8ae86Sav 	ret = 0;
105625cf1a30Sjl 
105725cf1a30Sjl 	for (i = 0; i < nflts; i++) {
10580cc8ae86Sav 		int bank;
105925cf1a30Sjl 
106025cf1a30Sjl 		flt_stat = mc_aflt->mflt_stat[i];
10610cc8ae86Sav 		bank = flt_stat->mf_flt_maddr.ma_bank;
1062d8a0cca9Swh 		ret = mc_set_mem_unum(p + strlen(p), blen,
1063d8a0cca9Swh 		    flt_stat->mf_flt_maddr.ma_phys_bd, bank, flt_stat->mf_type,
1064d8a0cca9Swh 		    flt_stat->mf_dimm_slot);
10650cc8ae86Sav 
10660cc8ae86Sav 		if (ret != 0) {
10670cc8ae86Sav 			cmn_err(CE_WARN,
10680cc8ae86Sav 			    "mc_ereport_post: Failed to determine the unum "
10690cc8ae86Sav 			    "for board=%d bank=%d type=0x%x slot=0x%x",
10700cc8ae86Sav 			    flt_stat->mf_flt_maddr.ma_bd, bank,
10710cc8ae86Sav 			    flt_stat->mf_type, flt_stat->mf_dimm_slot);
10720cc8ae86Sav 			continue;
107325cf1a30Sjl 		}
10740cc8ae86Sav 		n = strlen(device_path);
107525cf1a30Sjl 		blen = MAXPATHLEN - n;
107625cf1a30Sjl 		p = &device_path[n];
107725cf1a30Sjl 		if (i < (nflts - 1)) {
107807d06da5SSurya Prakki 			(void) snprintf(p, blen, " ");
10790cc8ae86Sav 			blen--;
10800cc8ae86Sav 			p++;
10810cc8ae86Sav 		}
10820cc8ae86Sav 
10830cc8ae86Sav 		if (ret == 0) {
10840cc8ae86Sav 			ret = mc_set_mem_sid(mc_aflt->mflt_mcp, s + strlen(s),
1085aeb241b2Sav 			    blen, flt_stat->mf_flt_maddr.ma_phys_bd, bank,
10860cc8ae86Sav 			    flt_stat->mf_type, flt_stat->mf_dimm_slot);
10870cc8ae86Sav 
108825cf1a30Sjl 		}
108925cf1a30Sjl 	}
109025cf1a30Sjl 
1091d8a0cca9Swh 	(void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, NULL,
1092d8a0cca9Swh 	    device_path, (ret == 0) ? sid : NULL, (ret == 0) ? offset :
1093d8a0cca9Swh 	    (uint64_t)-1);
109425cf1a30Sjl 
1095d8a0cca9Swh 	fm_payload_set(ereport, MC_OPL_RESOURCE, DATA_TYPE_NVLIST, resource,
1096d8a0cca9Swh 	    NULL);
109725cf1a30Sjl 
109825cf1a30Sjl 	if (panicstr) {
109925cf1a30Sjl 		errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC);
110025cf1a30Sjl 	} else {
110125cf1a30Sjl 		(void) fm_ereport_post(ereport, EVCH_TRYHARD);
110225cf1a30Sjl 		fm_nvlist_destroy(ereport, FM_NVA_FREE);
110325cf1a30Sjl 		fm_nvlist_destroy(detector, FM_NVA_FREE);
110425cf1a30Sjl 		fm_nvlist_destroy(resource, FM_NVA_FREE);
110525cf1a30Sjl 	}
110625cf1a30Sjl }
110725cf1a30Sjl 
11080cc8ae86Sav 
110925cf1a30Sjl static void
111025cf1a30Sjl mc_err_drain(mc_aflt_t *mc_aflt)
111125cf1a30Sjl {
111225cf1a30Sjl 	int rv;
111325cf1a30Sjl 	uint64_t pa = (uint64_t)(-1);
11140cc8ae86Sav 	int i;
111525cf1a30Sjl 
1116d8a0cca9Swh 	MC_LOG("mc_err_drain: %s\n", mc_aflt->mflt_erpt_class);
111725cf1a30Sjl 	/*
111825cf1a30Sjl 	 * we come here only when we have:
11191039f409Sav 	 * In mirror mode: MUE, SUE
1120056c948bStsien 	 * In normal mode: UE, Permanent CE, Intermittent CE
112125cf1a30Sjl 	 */
11220cc8ae86Sav 	for (i = 0; i < mc_aflt->mflt_nflts; i++) {
11230cc8ae86Sav 		rv = mcaddr_to_pa(mc_aflt->mflt_mcp,
1124d8a0cca9Swh 		    &(mc_aflt->mflt_stat[i]->mf_flt_maddr), &pa);
1125738dd194Shyw 
1126738dd194Shyw 		/* Ensure the pa is valid (not in isolated memory block) */
1127738dd194Shyw 		if (rv == 0 && pa_is_valid(mc_aflt->mflt_mcp, pa))
11280cc8ae86Sav 			mc_aflt->mflt_stat[i]->mf_flt_paddr = pa;
11290cc8ae86Sav 		else
11300cc8ae86Sav 			mc_aflt->mflt_stat[i]->mf_flt_paddr = (uint64_t)-1;
11310cc8ae86Sav 	}
11320cc8ae86Sav 
1133738dd194Shyw 	MC_LOG("mc_err_drain:pa = %lx\n", pa);
113425cf1a30Sjl 
1135738dd194Shyw 	switch (page_retire_check(pa, NULL)) {
1136738dd194Shyw 	case 0:
1137738dd194Shyw 	case EAGAIN:
1138738dd194Shyw 		MC_LOG("Page retired or pending\n");
1139738dd194Shyw 		return;
1140738dd194Shyw 	case EIO:
1141738dd194Shyw 		/*
1142056c948bStsien 		 * Do page retirement except for the PCE and ICE cases.
1143738dd194Shyw 		 * This is taken care by the OPL DE
1144738dd194Shyw 		 */
1145056c948bStsien 		if (mc_aflt->mflt_stat[0]->mf_type !=
1146056c948bStsien 		    FLT_TYPE_INTERMITTENT_CE &&
1147056c948bStsien 		    mc_aflt->mflt_stat[0]->mf_type != FLT_TYPE_PERMANENT_CE) {
1148738dd194Shyw 			MC_LOG("offline page at pa %lx error %x\n", pa,
1149d8a0cca9Swh 			    mc_aflt->mflt_pr);
1150738dd194Shyw 			(void) page_retire(pa, mc_aflt->mflt_pr);
115125cf1a30Sjl 		}
1152738dd194Shyw 		break;
1153738dd194Shyw 	case EINVAL:
1154738dd194Shyw 	default:
1155738dd194Shyw 		/*
1156738dd194Shyw 		 * Some memory do not have page structure so
1157738dd194Shyw 		 * we keep going in case of EINVAL.
1158738dd194Shyw 		 */
1159738dd194Shyw 		break;
116025cf1a30Sjl 	}
116125cf1a30Sjl 
11620cc8ae86Sav 	for (i = 0; i < mc_aflt->mflt_nflts; i++) {
11630cc8ae86Sav 		mc_aflt_t mc_aflt0;
11640cc8ae86Sav 		if (mc_aflt->mflt_stat[i]->mf_flt_paddr != (uint64_t)-1) {
11650cc8ae86Sav 			mc_aflt0 = *mc_aflt;
11660cc8ae86Sav 			mc_aflt0.mflt_nflts = 1;
11670cc8ae86Sav 			mc_aflt0.mflt_stat[0] = mc_aflt->mflt_stat[i];
11680cc8ae86Sav 			mc_ereport_post(&mc_aflt0);
11690cc8ae86Sav 		}
11700cc8ae86Sav 	}
11710cc8ae86Sav }
117225cf1a30Sjl 
117325cf1a30Sjl /*
117425cf1a30Sjl  * The restart address is actually defined in unit of PA[37:6]
117525cf1a30Sjl  * the mac patrol will convert that to dimm offset.  If the
117625cf1a30Sjl  * address is not in the bank, it will continue to search for
117725cf1a30Sjl  * the next PA that is within the bank.
117825cf1a30Sjl  *
117925cf1a30Sjl  * Also the mac patrol scans the dimms based on PA, not
118025cf1a30Sjl  * dimm offset.
118125cf1a30Sjl  */
118225cf1a30Sjl static int
1183738dd194Shyw restart_patrol(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr_info)
118425cf1a30Sjl {
118525cf1a30Sjl 	uint64_t pa;
118625cf1a30Sjl 	int rv;
118725cf1a30Sjl 
1188601c2e1eSdhain 	if (MC_REWRITE_MODE(mcp, bank)) {
1189601c2e1eSdhain 		return (0);
1190601c2e1eSdhain 	}
1191738dd194Shyw 	if (rsaddr_info == NULL || (rsaddr_info->mi_valid == 0)) {
119225cf1a30Sjl 		MAC_PTRL_START(mcp, bank);
119325cf1a30Sjl 		return (0);
119425cf1a30Sjl 	}
119525cf1a30Sjl 
1196738dd194Shyw 	rv = mcaddr_to_pa(mcp, &rsaddr_info->mi_restartaddr, &pa);
119725cf1a30Sjl 	if (rv != 0) {
119825cf1a30Sjl 		MC_LOG("cannot convert mcaddr to pa. use auto restart\n");
119925cf1a30Sjl 		MAC_PTRL_START(mcp, bank);
120025cf1a30Sjl 		return (0);
120125cf1a30Sjl 	}
120225cf1a30Sjl 
1203738dd194Shyw 	if (!mc_rangecheck_pa(mcp, pa)) {
120425cf1a30Sjl 		/* pa is not on this board, just retry */
120525cf1a30Sjl 		cmn_err(CE_WARN, "restart_patrol: invalid address %lx "
1206d8a0cca9Swh 		    "on board %d\n", pa, mcp->mc_board_num);
120725cf1a30Sjl 		MAC_PTRL_START(mcp, bank);
120825cf1a30Sjl 		return (0);
120925cf1a30Sjl 	}
121025cf1a30Sjl 
121125cf1a30Sjl 	MC_LOG("restart_patrol: pa = %lx\n", pa);
121225cf1a30Sjl 
1213738dd194Shyw 	if (!rsaddr_info->mi_injectrestart) {
1214738dd194Shyw 		/*
12151039f409Sav 		 * For non-error injection restart we need to
1216738dd194Shyw 		 * determine if the current restart pa/page is
1217738dd194Shyw 		 * a "good" page. A "good" page is a page that
1218738dd194Shyw 		 * has not been page retired. If the current
1219738dd194Shyw 		 * page that contains the pa is "good", we will
1220738dd194Shyw 		 * do a HW auto restart and let HW patrol continue
1221738dd194Shyw 		 * where it last stopped. Most desired scenario.
1222738dd194Shyw 		 *
1223738dd194Shyw 		 * If the current page is not "good", we will advance
1224738dd194Shyw 		 * to the next page to find the next "good" page and
1225738dd194Shyw 		 * restart the patrol from there.
1226738dd194Shyw 		 */
1227738dd194Shyw 		int wrapcount = 0;
1228738dd194Shyw 		uint64_t origpa = pa;
1229738dd194Shyw 		while (wrapcount < 2) {
1230d8a0cca9Swh 			if (!pa_is_valid(mcp, pa)) {
1231601c2e1eSdhain 			/*
1232601c2e1eSdhain 			 * Not in physinstall - advance to the
1233601c2e1eSdhain 			 * next memory isolation blocksize
1234601c2e1eSdhain 			 */
1235601c2e1eSdhain 			MC_LOG("Invalid PA\n");
1236601c2e1eSdhain 			pa = roundup(pa + 1, mc_isolation_bsize);
1237d8a0cca9Swh 			} else {
1238601c2e1eSdhain 			int rv;
1239601c2e1eSdhain 			if ((rv = page_retire_check(pa, NULL)) != 0 &&
1240601c2e1eSdhain 			    rv != EAGAIN) {
1241d8a0cca9Swh 					/*
1242d8a0cca9Swh 					 * The page is "good" (not retired),
1243d8a0cca9Swh 					 * we will use automatic HW restart
1244d8a0cca9Swh 					 * algorithm if this is the original
1245d8a0cca9Swh 					 * current starting page.
1246d8a0cca9Swh 					 */
1247601c2e1eSdhain 				if (pa == origpa) {
1248601c2e1eSdhain 					MC_LOG("Page has no error. "
1249601c2e1eSdhain 					    "Auto restart\n");
1250601c2e1eSdhain 					MAC_PTRL_START(mcp, bank);
1251601c2e1eSdhain 					return (0);
1252601c2e1eSdhain 				} else {
1253601c2e1eSdhain 					/*
1254601c2e1eSdhain 					 * found a subsequent good page
1255601c2e1eSdhain 					 */
1256601c2e1eSdhain 					break;
1257738dd194Shyw 				}
1258601c2e1eSdhain 			}
1259738dd194Shyw 
1260601c2e1eSdhain 			/*
1261601c2e1eSdhain 			 * Skip to the next page
1262601c2e1eSdhain 			 */
1263601c2e1eSdhain 			pa = roundup(pa + 1, PAGESIZE);
1264601c2e1eSdhain 			MC_LOG("Skipping bad page to %lx\n", pa);
1265d8a0cca9Swh 			}
1266738dd194Shyw 
1267601c2e1eSdhain 		    /* Check to see if we hit the end of the memory range */
1268d8a0cca9Swh 			if (pa >= (mcp->mc_start_address + mcp->mc_size)) {
1269601c2e1eSdhain 			MC_LOG("Wrap around\n");
1270601c2e1eSdhain 			pa = mcp->mc_start_address;
1271601c2e1eSdhain 			wrapcount++;
1272d8a0cca9Swh 			}
1273738dd194Shyw 		}
1274738dd194Shyw 
1275738dd194Shyw 		if (wrapcount > 1) {
1276d8a0cca9Swh 			MC_LOG("Failed to find a good page. Just restart\n");
1277d8a0cca9Swh 			MAC_PTRL_START(mcp, bank);
1278d8a0cca9Swh 			return (0);
127925cf1a30Sjl 		}
128025cf1a30Sjl 	}
128125cf1a30Sjl 
1282738dd194Shyw 	/*
1283738dd194Shyw 	 * We reached here either:
1284738dd194Shyw 	 * 1. We are doing an error injection restart that specify
1285738dd194Shyw 	 *    the exact pa/page to restart. OR
1286738dd194Shyw 	 * 2. We found a subsequent good page different from the
1287738dd194Shyw 	 *    original restart pa/page.
1288738dd194Shyw 	 * Restart MAC patrol: PA[37:6]
1289738dd194Shyw 	 */
129025cf1a30Sjl 	MC_LOG("restart at pa = %lx\n", pa);
129125cf1a30Sjl 	ST_MAC_REG(MAC_RESTART_ADD(mcp, bank), MAC_RESTART_PA(pa));
129225cf1a30Sjl 	MAC_PTRL_START_ADD(mcp, bank);
129325cf1a30Sjl 
129425cf1a30Sjl 	return (0);
129525cf1a30Sjl }
129625cf1a30Sjl 
1297601c2e1eSdhain static void
1298601c2e1eSdhain mc_retry_info_put(mc_retry_info_t **q, mc_retry_info_t *p)
1299601c2e1eSdhain {
1300601c2e1eSdhain 	ASSERT(p != NULL);
1301601c2e1eSdhain 	p->ri_next = *q;
1302601c2e1eSdhain 	*q = p;
1303601c2e1eSdhain }
1304601c2e1eSdhain 
1305601c2e1eSdhain static mc_retry_info_t *
1306601c2e1eSdhain mc_retry_info_get(mc_retry_info_t **q)
1307601c2e1eSdhain {
1308601c2e1eSdhain 	mc_retry_info_t *p;
1309601c2e1eSdhain 
1310601c2e1eSdhain 	if ((p = *q) != NULL) {
1311601c2e1eSdhain 		*q = p->ri_next;
1312601c2e1eSdhain 		return (p);
1313601c2e1eSdhain 	} else {
1314601c2e1eSdhain 		return (NULL);
1315601c2e1eSdhain 	}
1316601c2e1eSdhain }
1317601c2e1eSdhain 
131825cf1a30Sjl /*
131925cf1a30Sjl  * Rewriting is used for two purposes.
132025cf1a30Sjl  *  - to correct the error in memory.
132125cf1a30Sjl  *  - to determine whether the error is permanent or intermittent.
132225cf1a30Sjl  * It's done by writing the address in MAC_BANKm_REWRITE_ADD
132325cf1a30Sjl  * and issuing REW_REQ command in MAC_BANKm_PTRL_CNRL. After that,
132425cf1a30Sjl  * REW_END (and REW_CE/REW_UE if some error detected) is set when
132525cf1a30Sjl  * rewrite operation is done. See 4.7.3 and 4.7.11 in Columbus2 PRM.
132625cf1a30Sjl  *
132725cf1a30Sjl  * Note that rewrite operation doesn't change RAW_UE to Marked UE.
132825cf1a30Sjl  * Therefore, we use it only CE case.
132925cf1a30Sjl  */
1330601c2e1eSdhain 
133125cf1a30Sjl static uint32_t
1332601c2e1eSdhain do_rewrite(mc_opl_t *mcp, int bank, uint32_t dimm_addr, int retrying)
133325cf1a30Sjl {
133425cf1a30Sjl 	uint32_t cntl;
133525cf1a30Sjl 	int count = 0;
1336601c2e1eSdhain 	int max_count;
1337601c2e1eSdhain 	int retry_state;
1338601c2e1eSdhain 
1339601c2e1eSdhain 	if (retrying)
1340601c2e1eSdhain 		max_count = 1;
1341601c2e1eSdhain 	else
1342601c2e1eSdhain 		max_count = mc_max_rewrite_loop;
1343601c2e1eSdhain 
1344601c2e1eSdhain 	retry_state = RETRY_STATE_PENDING;
1345601c2e1eSdhain 
1346601c2e1eSdhain 	if (!retrying && MC_REWRITE_MODE(mcp, bank)) {
1347601c2e1eSdhain 		goto timeout;
1348601c2e1eSdhain 	}
1349601c2e1eSdhain 
1350601c2e1eSdhain 	retry_state = RETRY_STATE_ACTIVE;
135125cf1a30Sjl 
135225cf1a30Sjl 	/* first wait to make sure PTRL_STATUS is 0 */
1353601c2e1eSdhain 	while (count++ < max_count) {
135425cf1a30Sjl 		cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank));
1355601c2e1eSdhain 		if (!(cntl & MAC_CNTL_PTRL_STATUS)) {
1356601c2e1eSdhain 			count = 0;
135725cf1a30Sjl 			break;
1358601c2e1eSdhain 		}
13590cc8ae86Sav 		drv_usecwait(mc_rewrite_delay);
136025cf1a30Sjl 	}
1361601c2e1eSdhain 	if (count >= max_count)
1362601c2e1eSdhain 		goto timeout;
136325cf1a30Sjl 
136425cf1a30Sjl 	count = 0;
136525cf1a30Sjl 
136625cf1a30Sjl 	ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), dimm_addr);
136725cf1a30Sjl 	MAC_REW_REQ(mcp, bank);
136825cf1a30Sjl 
1369601c2e1eSdhain 	retry_state = RETRY_STATE_REWRITE;
1370601c2e1eSdhain 
137125cf1a30Sjl 	do {
1372601c2e1eSdhain 		if (count++ > max_count) {
1373601c2e1eSdhain 			goto timeout;
13740cc8ae86Sav 		} else {
13750cc8ae86Sav 			drv_usecwait(mc_rewrite_delay);
13760cc8ae86Sav 		}
1377601c2e1eSdhain 		cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank));
137825cf1a30Sjl 	/*
137925cf1a30Sjl 	 * If there are other MEMORY or PCI activities, this
138025cf1a30Sjl 	 * will be BUSY, else it should be set immediately
138125cf1a30Sjl 	 */
138225cf1a30Sjl 	} while (!(cntl & MAC_CNTL_REW_END));
138325cf1a30Sjl 
138425cf1a30Sjl 	MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS);
138525cf1a30Sjl 	return (cntl);
1386601c2e1eSdhain timeout:
1387601c2e1eSdhain 	mc_set_rewrite(mcp, bank, dimm_addr, retry_state);
1388601c2e1eSdhain 
1389601c2e1eSdhain 	return (0);
1390601c2e1eSdhain }
1391601c2e1eSdhain 
1392601c2e1eSdhain void
1393601c2e1eSdhain mc_clear_rewrite(mc_opl_t *mcp, int bank)
1394601c2e1eSdhain {
1395601c2e1eSdhain 	struct mc_bank *bankp;
1396601c2e1eSdhain 	mc_retry_info_t *retry;
1397601c2e1eSdhain 	uint32_t rew_addr;
1398601c2e1eSdhain 
1399601c2e1eSdhain 	bankp = &(mcp->mc_bank[bank]);
1400601c2e1eSdhain 	retry = bankp->mcb_active;
1401601c2e1eSdhain 	bankp->mcb_active = NULL;
1402601c2e1eSdhain 	mc_retry_info_put(&bankp->mcb_retry_freelist, retry);
1403601c2e1eSdhain 
1404601c2e1eSdhain again:
1405601c2e1eSdhain 	bankp->mcb_rewrite_count = 0;
1406601c2e1eSdhain 
1407601c2e1eSdhain 	while (retry = mc_retry_info_get(&bankp->mcb_retry_pending)) {
1408601c2e1eSdhain 		rew_addr = retry->ri_addr;
1409601c2e1eSdhain 		mc_retry_info_put(&bankp->mcb_retry_freelist, retry);
1410601c2e1eSdhain 		if (do_rewrite(mcp, bank, rew_addr, 1) == 0)
1411601c2e1eSdhain 			break;
1412601c2e1eSdhain 	}
1413601c2e1eSdhain 
1414601c2e1eSdhain 	/* we break out if no more pending rewrite or we got timeout again */
1415601c2e1eSdhain 
1416601c2e1eSdhain 	if (!bankp->mcb_active && !bankp->mcb_retry_pending) {
1417601c2e1eSdhain 		if (!IS_MIRROR(mcp, bank)) {
1418601c2e1eSdhain 			MC_CLEAR_REWRITE_MODE(mcp, bank);
1419601c2e1eSdhain 		} else {
1420601c2e1eSdhain 			int mbank = bank ^ 1;
1421601c2e1eSdhain 			bankp = &(mcp->mc_bank[mbank]);
1422601c2e1eSdhain 			if (!bankp->mcb_active && !bankp->mcb_retry_pending) {
1423601c2e1eSdhain 			MC_CLEAR_REWRITE_MODE(mcp, bank);
1424601c2e1eSdhain 			MC_CLEAR_REWRITE_MODE(mcp, mbank);
1425601c2e1eSdhain 			} else {
1426601c2e1eSdhain 			bank = mbank;
1427601c2e1eSdhain 			goto again;
1428601c2e1eSdhain 			}
1429601c2e1eSdhain 		}
1430601c2e1eSdhain 	}
143125cf1a30Sjl }
1432601c2e1eSdhain 
1433601c2e1eSdhain void
1434601c2e1eSdhain mc_set_rewrite(mc_opl_t *mcp, int bank, uint32_t addr, int state)
1435601c2e1eSdhain {
1436601c2e1eSdhain 	mc_retry_info_t *retry;
1437601c2e1eSdhain 	struct mc_bank *bankp;
1438601c2e1eSdhain 
1439601c2e1eSdhain 	bankp = &mcp->mc_bank[bank];
1440601c2e1eSdhain 
1441601c2e1eSdhain 	retry = mc_retry_info_get(&bankp->mcb_retry_freelist);
1442601c2e1eSdhain 
14430b240fcdSwh 	if (retry == NULL) {
14440b240fcdSwh 		mc_addr_t maddr;
14450b240fcdSwh 		uint64_t paddr;
14460b240fcdSwh 		/*
14470b240fcdSwh 		 * previous rewrite request has not completed yet.
14480b240fcdSwh 		 * So we discard this rewrite request.
14490b240fcdSwh 		 */
14500b240fcdSwh 		maddr.ma_bd = mcp->mc_board_num;
14510b240fcdSwh 		maddr.ma_bank =  bank;
14520b240fcdSwh 		maddr.ma_dimm_addr = addr;
14530b240fcdSwh 		if (mcaddr_to_pa(mcp, &maddr, &paddr) == 0) {
14540b240fcdSwh 			cmn_err(CE_WARN, "Discard CE rewrite request"
14550b240fcdSwh 			    " for 0x%lx (/LSB%d/B%d/%x).\n",
14560b240fcdSwh 			    paddr, mcp->mc_board_num, bank, addr);
14570b240fcdSwh 		} else {
14580b240fcdSwh 			cmn_err(CE_WARN, "Discard CE rewrite request"
14590b240fcdSwh 			    " for /LSB%d/B%d/%x.\n",
14600b240fcdSwh 			    mcp->mc_board_num, bank, addr);
14610b240fcdSwh 		}
14620b240fcdSwh 		return;
14630b240fcdSwh 	}
1464601c2e1eSdhain 
1465601c2e1eSdhain 	retry->ri_addr = addr;
1466601c2e1eSdhain 	retry->ri_state = state;
1467601c2e1eSdhain 
1468601c2e1eSdhain 	MC_SET_REWRITE_MODE(mcp, bank);
1469601c2e1eSdhain 
1470601c2e1eSdhain 	if ((state > RETRY_STATE_PENDING)) {
1471601c2e1eSdhain 		ASSERT(bankp->mcb_active == NULL);
1472601c2e1eSdhain 		bankp->mcb_active = retry;
1473601c2e1eSdhain 	} else {
1474601c2e1eSdhain 		mc_retry_info_put(&bankp->mcb_retry_pending, retry);
1475601c2e1eSdhain 	}
1476601c2e1eSdhain 
1477601c2e1eSdhain 	if (IS_MIRROR(mcp, bank)) {
1478601c2e1eSdhain 		int mbank = bank ^1;
1479601c2e1eSdhain 		MC_SET_REWRITE_MODE(mcp, mbank);
1480601c2e1eSdhain 	}
1481601c2e1eSdhain }
1482601c2e1eSdhain 
148325cf1a30Sjl void
148425cf1a30Sjl mc_process_scf_log(mc_opl_t *mcp)
148525cf1a30Sjl {
14860cc8ae86Sav 	int count;
14870cc8ae86Sav 	int n = 0;
148825cf1a30Sjl 	scf_log_t *p;
148925cf1a30Sjl 	int bank;
149025cf1a30Sjl 
14910cc8ae86Sav 	for (bank = 0; bank < BANKNUM_PER_SB; bank++) {
1492d8a0cca9Swh 		while ((p = mcp->mc_scf_log[bank]) != NULL &&
1493d8a0cca9Swh 		    (n < mc_max_errlog_processed)) {
1494601c2e1eSdhain 		ASSERT(bank == p->sl_bank);
1495601c2e1eSdhain 		count = 0;
1496601c2e1eSdhain 		while ((LD_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank))
1497601c2e1eSdhain 		    & MAC_STATIC_ERR_VLD)) {
1498601c2e1eSdhain 			if (count++ >= (mc_max_scf_loop)) {
1499601c2e1eSdhain 				break;
150025cf1a30Sjl 			}
1501601c2e1eSdhain 			drv_usecwait(mc_scf_delay);
1502601c2e1eSdhain 		}
150325cf1a30Sjl 
1504601c2e1eSdhain 		if (count < mc_max_scf_loop) {
1505601c2e1eSdhain 			ST_MAC_REG(MAC_STATIC_ERR_LOG(mcp, p->sl_bank),
1506601c2e1eSdhain 			    p->sl_err_log);
150725cf1a30Sjl 
1508601c2e1eSdhain 			ST_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank),
1509601c2e1eSdhain 			    p->sl_err_add|MAC_STATIC_ERR_VLD);
1510601c2e1eSdhain 			mcp->mc_scf_retry[bank] = 0;
1511601c2e1eSdhain 		} else {
1512601c2e1eSdhain 			/*
1513601c2e1eSdhain 			 * if we try too many times, just drop the req
1514601c2e1eSdhain 			 */
1515601c2e1eSdhain 			if (mcp->mc_scf_retry[bank]++ <=
1516601c2e1eSdhain 			    mc_max_scf_retry) {
1517601c2e1eSdhain 				return;
151825cf1a30Sjl 			} else {
1519601c2e1eSdhain 				if ((++mc_pce_dropped & 0xff) == 0) {
1520601c2e1eSdhain 					cmn_err(CE_WARN, "Cannot "
15210b240fcdSwh 					    "report CE to SCF\n");
1522d8a0cca9Swh 				}
152325cf1a30Sjl 			}
1524601c2e1eSdhain 		}
1525601c2e1eSdhain 		n++;
1526601c2e1eSdhain 		mcp->mc_scf_log[bank] = p->sl_next;
1527601c2e1eSdhain 		mcp->mc_scf_total[bank]--;
1528601c2e1eSdhain 		ASSERT(mcp->mc_scf_total[bank] >= 0);
1529601c2e1eSdhain 		kmem_free(p, sizeof (scf_log_t));
153025cf1a30Sjl 		}
153125cf1a30Sjl 	}
153225cf1a30Sjl }
153325cf1a30Sjl void
153425cf1a30Sjl mc_queue_scf_log(mc_opl_t *mcp, mc_flt_stat_t *flt_stat, int bank)
153525cf1a30Sjl {
153625cf1a30Sjl 	scf_log_t *p;
153725cf1a30Sjl 
15380cc8ae86Sav 	if (mcp->mc_scf_total[bank] >= mc_max_scf_logs) {
15390cc8ae86Sav 		if ((++mc_pce_dropped & 0xff) == 0) {
15400b240fcdSwh 			cmn_err(CE_WARN, "Too many CE requests.\n");
15410cc8ae86Sav 		}
154225cf1a30Sjl 		return;
154325cf1a30Sjl 	}
154425cf1a30Sjl 	p = kmem_zalloc(sizeof (scf_log_t), KM_SLEEP);
154525cf1a30Sjl 	p->sl_next = 0;
154625cf1a30Sjl 	p->sl_err_add = flt_stat->mf_err_add;
154725cf1a30Sjl 	p->sl_err_log = flt_stat->mf_err_log;
154825cf1a30Sjl 	p->sl_bank = bank;
154925cf1a30Sjl 
15500cc8ae86Sav 	if (mcp->mc_scf_log[bank] == NULL) {
155125cf1a30Sjl 		/*
155225cf1a30Sjl 		 * we rely on mc_scf_log to detect NULL queue.
155325cf1a30Sjl 		 * mc_scf_log_tail is irrelevant is such case.
155425cf1a30Sjl 		 */
15550cc8ae86Sav 		mcp->mc_scf_log_tail[bank] = mcp->mc_scf_log[bank] = p;
155625cf1a30Sjl 	} else {
15570cc8ae86Sav 		mcp->mc_scf_log_tail[bank]->sl_next = p;
15580cc8ae86Sav 		mcp->mc_scf_log_tail[bank] = p;
155925cf1a30Sjl 	}
15600cc8ae86Sav 	mcp->mc_scf_total[bank]++;
156125cf1a30Sjl }
156225cf1a30Sjl /*
156325cf1a30Sjl  * This routine determines what kind of CE happens, intermittent
156425cf1a30Sjl  * or permanent as follows. (See 4.7.3 in Columbus2 PRM.)
156525cf1a30Sjl  * - Do rewrite by issuing REW_REQ command to MAC_PTRL_CNTL register.
156625cf1a30Sjl  * - If CE is still detected on the same address even after doing
156725cf1a30Sjl  *   rewrite operation twice, it is determined as permanent error.
156825cf1a30Sjl  * - If error is not detected anymore, it is determined as intermittent
156925cf1a30Sjl  *   error.
157025cf1a30Sjl  * - If UE is detected due to rewrite operation, it should be treated
157125cf1a30Sjl  *   as UE.
157225cf1a30Sjl  */
157325cf1a30Sjl 
157425cf1a30Sjl /* ARGSUSED */
157525cf1a30Sjl static void
157625cf1a30Sjl mc_scrub_ce(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat, int ptrl_error)
157725cf1a30Sjl {
157825cf1a30Sjl 	uint32_t cntl;
157925cf1a30Sjl 	int i;
158025cf1a30Sjl 
158125cf1a30Sjl 	flt_stat->mf_type = FLT_TYPE_PERMANENT_CE;
158225cf1a30Sjl 	/*
158325cf1a30Sjl 	 * rewrite request 1st time reads and correct error data
158425cf1a30Sjl 	 * and write to DIMM.  2nd rewrite request must be issued
158525cf1a30Sjl 	 * after REW_CE/UE/END is 0.  When the 2nd request is completed,
158625cf1a30Sjl 	 * if REW_CE = 1, then it is permanent CE.
158725cf1a30Sjl 	 */
158825cf1a30Sjl 	for (i = 0; i < 2; i++) {
1589601c2e1eSdhain 		cntl = do_rewrite(mcp, bank, flt_stat->mf_err_add, 0);
1590601c2e1eSdhain 
1591601c2e1eSdhain 		if (cntl == 0) {
1592601c2e1eSdhain 			/* timeout case */
1593601c2e1eSdhain 			return;
1594601c2e1eSdhain 		}
159525cf1a30Sjl 		/*
159625cf1a30Sjl 		 * If the error becomes UE or CMPE
159725cf1a30Sjl 		 * we return to the caller immediately.
159825cf1a30Sjl 		 */
159925cf1a30Sjl 		if (cntl & MAC_CNTL_REW_UE) {
160025cf1a30Sjl 			if (ptrl_error)
160125cf1a30Sjl 				flt_stat->mf_cntl |= MAC_CNTL_PTRL_UE;
160225cf1a30Sjl 			else
160325cf1a30Sjl 				flt_stat->mf_cntl |= MAC_CNTL_MI_UE;
160425cf1a30Sjl 			flt_stat->mf_type = FLT_TYPE_UE;
160525cf1a30Sjl 			return;
160625cf1a30Sjl 		}
160725cf1a30Sjl 		if (cntl & MAC_CNTL_REW_CMPE) {
160825cf1a30Sjl 			if (ptrl_error)
160925cf1a30Sjl 				flt_stat->mf_cntl |= MAC_CNTL_PTRL_CMPE;
161025cf1a30Sjl 			else
161125cf1a30Sjl 				flt_stat->mf_cntl |= MAC_CNTL_MI_CMPE;
161225cf1a30Sjl 			flt_stat->mf_type = FLT_TYPE_CMPE;
161325cf1a30Sjl 			return;
161425cf1a30Sjl 		}
161525cf1a30Sjl 	}
161625cf1a30Sjl 	if (!(cntl & MAC_CNTL_REW_CE)) {
161725cf1a30Sjl 		flt_stat->mf_type = FLT_TYPE_INTERMITTENT_CE;
161825cf1a30Sjl 	}
161925cf1a30Sjl 
162025cf1a30Sjl 	if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) {
162125cf1a30Sjl 		/* report PERMANENT_CE to SP via SCF */
162225cf1a30Sjl 		if (!(flt_stat->mf_err_log & MAC_ERR_LOG_INVALID)) {
162325cf1a30Sjl 			mc_queue_scf_log(mcp, flt_stat, bank);
162425cf1a30Sjl 		}
162525cf1a30Sjl 	}
162625cf1a30Sjl }
162725cf1a30Sjl 
162825cf1a30Sjl #define	IS_CMPE(cntl, f)	((cntl) & ((f) ? MAC_CNTL_PTRL_CMPE :\
162925cf1a30Sjl 				MAC_CNTL_MI_CMPE))
163025cf1a30Sjl #define	IS_UE(cntl, f)	((cntl) & ((f) ? MAC_CNTL_PTRL_UE : MAC_CNTL_MI_UE))
163125cf1a30Sjl #define	IS_CE(cntl, f)	((cntl) & ((f) ? MAC_CNTL_PTRL_CE : MAC_CNTL_MI_CE))
163225cf1a30Sjl #define	IS_OK(cntl, f)	(!((cntl) & ((f) ? MAC_CNTL_PTRL_ERRS : \
163325cf1a30Sjl 			MAC_CNTL_MI_ERRS)))
163425cf1a30Sjl 
163525cf1a30Sjl 
163625cf1a30Sjl static int
163725cf1a30Sjl IS_CE_ONLY(uint32_t cntl, int ptrl_error)
163825cf1a30Sjl {
163925cf1a30Sjl 	if (ptrl_error) {
164025cf1a30Sjl 		return ((cntl & MAC_CNTL_PTRL_ERRS) == MAC_CNTL_PTRL_CE);
164125cf1a30Sjl 	} else {
164225cf1a30Sjl 		return ((cntl & MAC_CNTL_MI_ERRS) == MAC_CNTL_MI_CE);
164325cf1a30Sjl 	}
164425cf1a30Sjl }
164525cf1a30Sjl 
164625cf1a30Sjl void
164725cf1a30Sjl mc_write_cntl(mc_opl_t *mcp, int bank, uint32_t value)
164825cf1a30Sjl {
164937afe445Shyw 	int ebank = (IS_MIRROR(mcp, bank)) ? MIRROR_IDX(bank) : bank;
165037afe445Shyw 
165137afe445Shyw 	if (mcp->mc_speedup_period[ebank] > 0)
16520cc8ae86Sav 		value |= mc_max_speed;
16530cc8ae86Sav 	else
16540cc8ae86Sav 		value |= mcp->mc_speed;
165525cf1a30Sjl 	ST_MAC_REG(MAC_PTRL_CNTL(mcp, bank), value);
165625cf1a30Sjl }
165725cf1a30Sjl 
165825cf1a30Sjl static void
165925cf1a30Sjl mc_read_ptrl_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat)
166025cf1a30Sjl {
166125cf1a30Sjl 	flt_stat->mf_cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) &
1662d8a0cca9Swh 	    MAC_CNTL_PTRL_ERRS;
166325cf1a30Sjl 	flt_stat->mf_err_add = LD_MAC_REG(MAC_PTRL_ERR_ADD(mcp, bank));
166425cf1a30Sjl 	flt_stat->mf_err_log = LD_MAC_REG(MAC_PTRL_ERR_LOG(mcp, bank));
166525cf1a30Sjl 	flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num;
1666aeb241b2Sav 	flt_stat->mf_flt_maddr.ma_phys_bd = mcp->mc_phys_board_num;
166725cf1a30Sjl 	flt_stat->mf_flt_maddr.ma_bank = bank;
166825cf1a30Sjl 	flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add;
166925cf1a30Sjl }
167025cf1a30Sjl 
167125cf1a30Sjl static void
167225cf1a30Sjl mc_read_mi_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat)
167325cf1a30Sjl {
167425cf1a30Sjl 	uint32_t status, old_status;
167525cf1a30Sjl 
1676d8a0cca9Swh 	status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & MAC_CNTL_MI_ERRS;
167725cf1a30Sjl 	old_status = 0;
167825cf1a30Sjl 
167925cf1a30Sjl 	/* we keep reading until the status is stable */
168025cf1a30Sjl 	while (old_status != status) {
168125cf1a30Sjl 		old_status = status;
1682d8a0cca9Swh 		flt_stat->mf_err_add = LD_MAC_REG(MAC_MI_ERR_ADD(mcp, bank));
1683d8a0cca9Swh 		flt_stat->mf_err_log = LD_MAC_REG(MAC_MI_ERR_LOG(mcp, bank));
168425cf1a30Sjl 		status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) &
1685d8a0cca9Swh 		    MAC_CNTL_MI_ERRS;
168625cf1a30Sjl 		if (status == old_status) {
168725cf1a30Sjl 			break;
168825cf1a30Sjl 		}
168925cf1a30Sjl 	}
169025cf1a30Sjl 
169125cf1a30Sjl 	flt_stat->mf_cntl = status;
169225cf1a30Sjl 	flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num;
1693aeb241b2Sav 	flt_stat->mf_flt_maddr.ma_phys_bd = mcp->mc_phys_board_num;
169425cf1a30Sjl 	flt_stat->mf_flt_maddr.ma_bank = bank;
169525cf1a30Sjl 	flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add;
169625cf1a30Sjl }
169725cf1a30Sjl 
169825cf1a30Sjl 
169925cf1a30Sjl /*
170025cf1a30Sjl  * Error philosophy for mirror mode:
170125cf1a30Sjl  *
170225cf1a30Sjl  * PTRL (The error address for both banks are same, since ptrl stops if it
170325cf1a30Sjl  * detects error.)
17041039f409Sav  * - Compare error  log CMPE.
170525cf1a30Sjl  *
170625cf1a30Sjl  * - UE-UE           Report MUE.  No rewrite.
170725cf1a30Sjl  *
170825cf1a30Sjl  * - UE-*	     UE-(CE/OK). Rewrite to scrub UE.  Report SUE.
170925cf1a30Sjl  *
171025cf1a30Sjl  * - CE-*            CE-(CE/OK). Scrub to determine if CE is permanent.
171125cf1a30Sjl  *                   If CE is permanent, inform SCF.  Once for each
171225cf1a30Sjl  *		     Dimm.  If CE becomes UE or CMPE, go back to above.
171325cf1a30Sjl  *
171425cf1a30Sjl  *
171525cf1a30Sjl  * MI (The error addresses for each bank are the same or different.)
17161039f409Sav  * - Compare  error  If addresses are the same.  Just CMPE, so log CMPE.
171725cf1a30Sjl  *		     If addresses are different (this could happen
17181039f409Sav  *		     as a result of scrubbing.  Report each separately.
171925cf1a30Sjl  *		     Only report error info on each side.
172025cf1a30Sjl  *
172125cf1a30Sjl  * - UE-UE           Addresses are the same.  Report MUE.
172225cf1a30Sjl  *		     Addresses are different.  Report SUE on each bank.
172325cf1a30Sjl  *		     Rewrite to clear UE.
172425cf1a30Sjl  *
172525cf1a30Sjl  * - UE-*	     UE-(CE/OK)
172625cf1a30Sjl  *		     Rewrite to clear UE.  Report SUE for the bank.
172725cf1a30Sjl  *
172825cf1a30Sjl  * - CE-*            CE-(CE/OK).  Scrub to determine if CE is permanent.
172925cf1a30Sjl  *                   If CE becomes UE or CMPE, go back to above.
173025cf1a30Sjl  *
173125cf1a30Sjl  */
173225cf1a30Sjl 
173325cf1a30Sjl static int
173425cf1a30Sjl mc_process_error_mir(mc_opl_t *mcp, mc_aflt_t *mc_aflt, mc_flt_stat_t *flt_stat)
173525cf1a30Sjl {
173625cf1a30Sjl 	int ptrl_error = mc_aflt->mflt_is_ptrl;
173725cf1a30Sjl 	int i;
173825cf1a30Sjl 	int rv = 0;
1739601c2e1eSdhain 	int bank;
1740601c2e1eSdhain 	int rewrite_timeout = 0;
174125cf1a30Sjl 
174225cf1a30Sjl 	MC_LOG("process mirror errors cntl[0] = %x, cntl[1] = %x\n",
1743d8a0cca9Swh 	    flt_stat[0].mf_cntl, flt_stat[1].mf_cntl);
174425cf1a30Sjl 
174525cf1a30Sjl 	if (ptrl_error) {
1746d8a0cca9Swh 		if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) &
1747d8a0cca9Swh 		    MAC_CNTL_PTRL_ERRS) == 0)
174825cf1a30Sjl 			return (0);
174925cf1a30Sjl 	} else {
1750d8a0cca9Swh 		if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) &
1751d8a0cca9Swh 		    MAC_CNTL_MI_ERRS) == 0)
175225cf1a30Sjl 			return (0);
175325cf1a30Sjl 	}
175425cf1a30Sjl 
175525cf1a30Sjl 	/*
175625cf1a30Sjl 	 * First we take care of the case of CE
175725cf1a30Sjl 	 * because they can become UE or CMPE
175825cf1a30Sjl 	 */
175925cf1a30Sjl 	for (i = 0; i < 2; i++) {
176025cf1a30Sjl 		if (IS_CE_ONLY(flt_stat[i].mf_cntl, ptrl_error)) {
1761601c2e1eSdhain 			bank = flt_stat[i].mf_flt_maddr.ma_bank;
1762601c2e1eSdhain 			MC_LOG("CE detected on bank %d\n", bank);
1763601c2e1eSdhain 			mc_scrub_ce(mcp, bank, &flt_stat[i], ptrl_error);
1764601c2e1eSdhain 			if (MC_REWRITE_ACTIVE(mcp, bank)) {
1765601c2e1eSdhain 				rewrite_timeout = 1;
1766601c2e1eSdhain 			}
176725cf1a30Sjl 			rv = 1;
176825cf1a30Sjl 		}
176925cf1a30Sjl 	}
177025cf1a30Sjl 
1771601c2e1eSdhain 	if (rewrite_timeout)
1772601c2e1eSdhain 		return (0);
1773601c2e1eSdhain 
177425cf1a30Sjl 	/* The above scrubbing can turn CE into UE or CMPE */
177525cf1a30Sjl 
177625cf1a30Sjl 	/*
177725cf1a30Sjl 	 * Now we distinguish two cases: same address or not
177825cf1a30Sjl 	 * the same address.  It might seem more intuitive to
177925cf1a30Sjl 	 * distinguish PTRL v.s. MI error but it is more
178025cf1a30Sjl 	 * complicated that way.
178125cf1a30Sjl 	 */
178225cf1a30Sjl 
178325cf1a30Sjl 	if (flt_stat[0].mf_err_add == flt_stat[1].mf_err_add) {
178425cf1a30Sjl 
178525cf1a30Sjl 		if (IS_CMPE(flt_stat[0].mf_cntl, ptrl_error) ||
178625cf1a30Sjl 		    IS_CMPE(flt_stat[1].mf_cntl, ptrl_error)) {
178725cf1a30Sjl 			flt_stat[0].mf_type = FLT_TYPE_CMPE;
178825cf1a30Sjl 			flt_stat[1].mf_type = FLT_TYPE_CMPE;
178925cf1a30Sjl 			mc_aflt->mflt_erpt_class = MC_OPL_CMPE;
179025cf1a30Sjl 			mc_aflt->mflt_nflts = 2;
179125cf1a30Sjl 			mc_aflt->mflt_stat[0] = &flt_stat[0];
179225cf1a30Sjl 			mc_aflt->mflt_stat[1] = &flt_stat[1];
179325cf1a30Sjl 			mc_aflt->mflt_pr = PR_UE;
17941039f409Sav 			/*
17951039f409Sav 			 * Compare error is result of MAC internal error, so
17961039f409Sav 			 * simply log it instead of publishing an ereport. SCF
17971039f409Sav 			 * diagnoses all the MAC internal and its i/f error.
17981039f409Sav 			 */
17991039f409Sav 			MC_LOG("cmpe error detected\n");
180025cf1a30Sjl 			return (1);
180125cf1a30Sjl 		}
180225cf1a30Sjl 
180325cf1a30Sjl 		if (IS_UE(flt_stat[0].mf_cntl, ptrl_error) &&
1804d8a0cca9Swh 		    IS_UE(flt_stat[1].mf_cntl, ptrl_error)) {
180525cf1a30Sjl 			/* Both side are UE's */
180625cf1a30Sjl 
180725cf1a30Sjl 			MAC_SET_ERRLOG_INFO(&flt_stat[0]);
180825cf1a30Sjl 			MAC_SET_ERRLOG_INFO(&flt_stat[1]);
180925cf1a30Sjl 			MC_LOG("MUE detected\n");
18100cc8ae86Sav 			flt_stat[0].mf_type = FLT_TYPE_MUE;
18110cc8ae86Sav 			flt_stat[1].mf_type = FLT_TYPE_MUE;
181225cf1a30Sjl 			mc_aflt->mflt_erpt_class = MC_OPL_MUE;
181325cf1a30Sjl 			mc_aflt->mflt_nflts = 2;
181425cf1a30Sjl 			mc_aflt->mflt_stat[0] = &flt_stat[0];
181525cf1a30Sjl 			mc_aflt->mflt_stat[1] = &flt_stat[1];
181625cf1a30Sjl 			mc_aflt->mflt_pr = PR_UE;
181725cf1a30Sjl 			mc_err_drain(mc_aflt);
181825cf1a30Sjl 			return (1);
181925cf1a30Sjl 		}
182025cf1a30Sjl 
182125cf1a30Sjl 		/* Now the only case is UE/CE, UE/OK, or don't care */
182225cf1a30Sjl 		for (i = 0; i < 2; i++) {
1823601c2e1eSdhain 			if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) {
18240cc8ae86Sav 
18250cc8ae86Sav 			/* rewrite can clear the one side UE error */
18260cc8ae86Sav 
182725cf1a30Sjl 			if (IS_OK(flt_stat[i^1].mf_cntl, ptrl_error)) {
182825cf1a30Sjl 				(void) do_rewrite(mcp,
182925cf1a30Sjl 				    flt_stat[i].mf_flt_maddr.ma_bank,
1830601c2e1eSdhain 				    flt_stat[i].mf_flt_maddr.ma_dimm_addr, 0);
183125cf1a30Sjl 			}
183225cf1a30Sjl 			flt_stat[i].mf_type = FLT_TYPE_UE;
183325cf1a30Sjl 			MAC_SET_ERRLOG_INFO(&flt_stat[i]);
183425cf1a30Sjl 			mc_aflt->mflt_erpt_class = MC_OPL_SUE;
183525cf1a30Sjl 			mc_aflt->mflt_stat[0] = &flt_stat[i];
183625cf1a30Sjl 			mc_aflt->mflt_nflts = 1;
183725cf1a30Sjl 			mc_aflt->mflt_pr = PR_MCE;
183825cf1a30Sjl 			mc_err_drain(mc_aflt);
183925cf1a30Sjl 			/* Once we hit a UE/CE or UE/OK case, done */
184025cf1a30Sjl 			return (1);
1841601c2e1eSdhain 			}
184225cf1a30Sjl 		}
184325cf1a30Sjl 
184425cf1a30Sjl 	} else {
184525cf1a30Sjl 		/*
184625cf1a30Sjl 		 * addresses are different. That means errors
184725cf1a30Sjl 		 * on the 2 banks are not related at all.
184825cf1a30Sjl 		 */
184925cf1a30Sjl 		for (i = 0; i < 2; i++) {
1850d8a0cca9Swh 			if (IS_CMPE(flt_stat[i].mf_cntl, ptrl_error)) {
1851d8a0cca9Swh 				flt_stat[i].mf_type = FLT_TYPE_CMPE;
1852d8a0cca9Swh 				mc_aflt->mflt_erpt_class = MC_OPL_CMPE;
1853d8a0cca9Swh 				mc_aflt->mflt_nflts = 1;
1854d8a0cca9Swh 				mc_aflt->mflt_stat[0] = &flt_stat[i];
1855d8a0cca9Swh 				mc_aflt->mflt_pr = PR_UE;
1856d8a0cca9Swh 				/*
1857d8a0cca9Swh 				 * Compare error is result of MAC internal
1858d8a0cca9Swh 				 * error, so simply log it instead of
1859d8a0cca9Swh 				 * publishing an ereport. SCF diagnoses all
1860d8a0cca9Swh 				 * the MAC internal and its interface error.
1861d8a0cca9Swh 				 */
1862d8a0cca9Swh 				MC_LOG("cmpe error detected\n");
1863d8a0cca9Swh 				/* no more report on this bank */
1864d8a0cca9Swh 				flt_stat[i].mf_cntl = 0;
1865d8a0cca9Swh 				rv = 1;
1866d8a0cca9Swh 			}
186725cf1a30Sjl 		}
186825cf1a30Sjl 
18690cc8ae86Sav 		/* rewrite can clear the one side UE error */
18700cc8ae86Sav 
187125cf1a30Sjl 		for (i = 0; i < 2; i++) {
1872d8a0cca9Swh 			if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) {
1873d8a0cca9Swh 				(void) do_rewrite(mcp,
1874d8a0cca9Swh 				    flt_stat[i].mf_flt_maddr.ma_bank,
1875601c2e1eSdhain 				    flt_stat[i].mf_flt_maddr.ma_dimm_addr,
1876601c2e1eSdhain 				    0);
1877d8a0cca9Swh 				flt_stat[i].mf_type = FLT_TYPE_UE;
1878d8a0cca9Swh 				MAC_SET_ERRLOG_INFO(&flt_stat[i]);
1879d8a0cca9Swh 				mc_aflt->mflt_erpt_class = MC_OPL_SUE;
1880d8a0cca9Swh 				mc_aflt->mflt_stat[0] = &flt_stat[i];
1881d8a0cca9Swh 				mc_aflt->mflt_nflts = 1;
1882d8a0cca9Swh 				mc_aflt->mflt_pr = PR_MCE;
1883d8a0cca9Swh 				mc_err_drain(mc_aflt);
1884d8a0cca9Swh 				rv = 1;
1885d8a0cca9Swh 			}
188625cf1a30Sjl 		}
188725cf1a30Sjl 	}
188825cf1a30Sjl 	return (rv);
188925cf1a30Sjl }
189025cf1a30Sjl static void
1891738dd194Shyw mc_error_handler_mir(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr)
189225cf1a30Sjl {
189325cf1a30Sjl 	mc_aflt_t mc_aflt;
189425cf1a30Sjl 	mc_flt_stat_t flt_stat[2], mi_flt_stat[2];
18950cc8ae86Sav 	int i;
18960cc8ae86Sav 	int mi_valid;
189725cf1a30Sjl 
1898738dd194Shyw 	ASSERT(rsaddr);
1899738dd194Shyw 
190025cf1a30Sjl 	bzero(&mc_aflt, sizeof (mc_aflt_t));
190125cf1a30Sjl 	bzero(&flt_stat, 2 * sizeof (mc_flt_stat_t));
190225cf1a30Sjl 	bzero(&mi_flt_stat, 2 * sizeof (mc_flt_stat_t));
190325cf1a30Sjl 
1904ad59b69dSbm 
190525cf1a30Sjl 	mc_aflt.mflt_mcp = mcp;
190625cf1a30Sjl 	mc_aflt.mflt_id = gethrtime();
190725cf1a30Sjl 
190825cf1a30Sjl 	/* Now read all the registers into flt_stat */
190925cf1a30Sjl 
19100cc8ae86Sav 	for (i = 0; i < 2; i++) {
19110cc8ae86Sav 		MC_LOG("Reading registers of bank %d\n", bank);
19120cc8ae86Sav 		/* patrol registers */
19130cc8ae86Sav 		mc_read_ptrl_reg(mcp, bank, &flt_stat[i]);
191425cf1a30Sjl 
1915738dd194Shyw 		/*
1916738dd194Shyw 		 * In mirror mode, it is possible that only one bank
1917738dd194Shyw 		 * may report the error. We need to check for it to
1918738dd194Shyw 		 * ensure we pick the right addr value for patrol restart.
1919738dd194Shyw 		 * Note that if both banks reported errors, we pick the
1920738dd194Shyw 		 * 2nd one. Both banks should reported the same error address.
1921738dd194Shyw 		 */
1922738dd194Shyw 		if (flt_stat[i].mf_cntl & MAC_CNTL_PTRL_ERRS)
1923738dd194Shyw 			rsaddr->mi_restartaddr = flt_stat[i].mf_flt_maddr;
192425cf1a30Sjl 
19250cc8ae86Sav 		MC_LOG("ptrl registers cntl %x add %x log %x\n",
1926d8a0cca9Swh 		    flt_stat[i].mf_cntl, flt_stat[i].mf_err_add,
1927d8a0cca9Swh 		    flt_stat[i].mf_err_log);
192825cf1a30Sjl 
19290cc8ae86Sav 		/* MI registers */
19300cc8ae86Sav 		mc_read_mi_reg(mcp, bank, &mi_flt_stat[i]);
193125cf1a30Sjl 
19320cc8ae86Sav 		MC_LOG("MI registers cntl %x add %x log %x\n",
1933d8a0cca9Swh 		    mi_flt_stat[i].mf_cntl, mi_flt_stat[i].mf_err_add,
1934d8a0cca9Swh 		    mi_flt_stat[i].mf_err_log);
193525cf1a30Sjl 
19360cc8ae86Sav 		bank = bank^1;
19370cc8ae86Sav 	}
193825cf1a30Sjl 
193925cf1a30Sjl 	/* clear errors once we read all the registers */
1940d8a0cca9Swh 	MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS));
194125cf1a30Sjl 
19420cc8ae86Sav 	MAC_CLEAR_ERRS(mcp, bank ^ 1, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS));
19430cc8ae86Sav 
19440cc8ae86Sav 	/* Process MI errors first */
194525cf1a30Sjl 
19460cc8ae86Sav 	/* if not error mode, cntl1 is 0 */
19470cc8ae86Sav 	if ((mi_flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) ||
1948d8a0cca9Swh 	    (mi_flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID))
19490cc8ae86Sav 		mi_flt_stat[0].mf_cntl = 0;
19500cc8ae86Sav 
19510cc8ae86Sav 	if ((mi_flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) ||
1952d8a0cca9Swh 	    (mi_flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID))
19530cc8ae86Sav 		mi_flt_stat[1].mf_cntl = 0;
195425cf1a30Sjl 
19550cc8ae86Sav 	mc_aflt.mflt_is_ptrl = 0;
19560cc8ae86Sav 	mi_valid = mc_process_error_mir(mcp, &mc_aflt, &mi_flt_stat[0]);
19570cc8ae86Sav 
19580cc8ae86Sav 	if ((((flt_stat[0].mf_cntl & MAC_CNTL_PTRL_ERRS) >>
1959d8a0cca9Swh 	    MAC_CNTL_PTRL_ERR_SHIFT) == ((mi_flt_stat[0].mf_cntl &
1960d8a0cca9Swh 	    MAC_CNTL_MI_ERRS) >> MAC_CNTL_MI_ERR_SHIFT)) &&
19610b240fcdSwh 	    (flt_stat[0].mf_err_add ==
19620b240fcdSwh 	    ROUNDDOWN(mi_flt_stat[0].mf_err_add, MC_BOUND_BYTE)) &&
1963d8a0cca9Swh 	    (((flt_stat[1].mf_cntl & MAC_CNTL_PTRL_ERRS) >>
1964d8a0cca9Swh 	    MAC_CNTL_PTRL_ERR_SHIFT) == ((mi_flt_stat[1].mf_cntl &
1965d8a0cca9Swh 	    MAC_CNTL_MI_ERRS) >> MAC_CNTL_MI_ERR_SHIFT)) &&
19660b240fcdSwh 	    (flt_stat[1].mf_err_add ==
19670b240fcdSwh 	    ROUNDDOWN(mi_flt_stat[1].mf_err_add, MC_BOUND_BYTE))) {
19680cc8ae86Sav #ifdef DEBUG
19690cc8ae86Sav 		MC_LOG("discarding PTRL error because "
19700cc8ae86Sav 		    "it is the same as MI\n");
19710cc8ae86Sav #endif
1972738dd194Shyw 		rsaddr->mi_valid = mi_valid;
19730cc8ae86Sav 		return;
19740cc8ae86Sav 	}
197525cf1a30Sjl 	/* if not error mode, cntl1 is 0 */
197625cf1a30Sjl 	if ((flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) ||
1977d8a0cca9Swh 	    (flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID))
197825cf1a30Sjl 		flt_stat[0].mf_cntl = 0;
197925cf1a30Sjl 
198025cf1a30Sjl 	if ((flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) ||
1981d8a0cca9Swh 	    (flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID))
198225cf1a30Sjl 		flt_stat[1].mf_cntl = 0;
198325cf1a30Sjl 
198425cf1a30Sjl 	mc_aflt.mflt_is_ptrl = 1;
1985738dd194Shyw 	rsaddr->mi_valid = mc_process_error_mir(mcp, &mc_aflt, &flt_stat[0]);
198625cf1a30Sjl }
198725cf1a30Sjl static int
198825cf1a30Sjl mc_process_error(mc_opl_t *mcp, int bank, mc_aflt_t *mc_aflt,
198925cf1a30Sjl 	mc_flt_stat_t *flt_stat)
199025cf1a30Sjl {
199125cf1a30Sjl 	int ptrl_error = mc_aflt->mflt_is_ptrl;
199225cf1a30Sjl 	int rv = 0;
199325cf1a30Sjl 
199425cf1a30Sjl 	mc_aflt->mflt_erpt_class = NULL;
199525cf1a30Sjl 	if (IS_UE(flt_stat->mf_cntl, ptrl_error)) {
19961039f409Sav 		MC_LOG("UE detected\n");
199725cf1a30Sjl 		flt_stat->mf_type = FLT_TYPE_UE;
199825cf1a30Sjl 		mc_aflt->mflt_erpt_class = MC_OPL_UE;
199925cf1a30Sjl 		mc_aflt->mflt_pr = PR_UE;
200025cf1a30Sjl 		MAC_SET_ERRLOG_INFO(flt_stat);
200125cf1a30Sjl 		rv = 1;
200225cf1a30Sjl 	} else if (IS_CE(flt_stat->mf_cntl, ptrl_error)) {
20031039f409Sav 		MC_LOG("CE detected\n");
200425cf1a30Sjl 		MAC_SET_ERRLOG_INFO(flt_stat);
200525cf1a30Sjl 
20061039f409Sav 		/* Error type can change after scrubbing */
200725cf1a30Sjl 		mc_scrub_ce(mcp, bank, flt_stat, ptrl_error);
2008601c2e1eSdhain 		if (MC_REWRITE_ACTIVE(mcp, bank)) {
2009601c2e1eSdhain 			return (0);
2010601c2e1eSdhain 		}
201125cf1a30Sjl 
2012056c948bStsien 		if (flt_stat->mf_type == FLT_TYPE_INTERMITTENT_CE) {
2013056c948bStsien 			mc_aflt->mflt_erpt_class = MC_OPL_ICE;
2014056c948bStsien 			mc_aflt->mflt_pr = PR_MCE;
2015056c948bStsien 		} else if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) {
201625cf1a30Sjl 			mc_aflt->mflt_erpt_class = MC_OPL_CE;
201725cf1a30Sjl 			mc_aflt->mflt_pr = PR_MCE;
201825cf1a30Sjl 		} else if (flt_stat->mf_type == FLT_TYPE_UE) {
201925cf1a30Sjl 			mc_aflt->mflt_erpt_class = MC_OPL_UE;
202025cf1a30Sjl 			mc_aflt->mflt_pr = PR_UE;
202125cf1a30Sjl 		}
202225cf1a30Sjl 		rv = 1;
202325cf1a30Sjl 	}
2024d8a0cca9Swh 	MC_LOG("mc_process_error: fault type %x erpt %s\n", flt_stat->mf_type,
2025d8a0cca9Swh 	    mc_aflt->mflt_erpt_class);
202625cf1a30Sjl 	if (mc_aflt->mflt_erpt_class) {
202725cf1a30Sjl 		mc_aflt->mflt_stat[0] = flt_stat;
202825cf1a30Sjl 		mc_aflt->mflt_nflts = 1;
202925cf1a30Sjl 		mc_err_drain(mc_aflt);
203025cf1a30Sjl 	}
203125cf1a30Sjl 	return (rv);
203225cf1a30Sjl }
203325cf1a30Sjl 
203425cf1a30Sjl static void
2035738dd194Shyw mc_error_handler(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr)
203625cf1a30Sjl {
203725cf1a30Sjl 	mc_aflt_t mc_aflt;
203825cf1a30Sjl 	mc_flt_stat_t flt_stat, mi_flt_stat;
20390cc8ae86Sav 	int mi_valid;
204025cf1a30Sjl 
204125cf1a30Sjl 	bzero(&mc_aflt, sizeof (mc_aflt_t));
204225cf1a30Sjl 	bzero(&flt_stat, sizeof (mc_flt_stat_t));
204325cf1a30Sjl 	bzero(&mi_flt_stat, sizeof (mc_flt_stat_t));
204425cf1a30Sjl 
204525cf1a30Sjl 	mc_aflt.mflt_mcp = mcp;
204625cf1a30Sjl 	mc_aflt.mflt_id = gethrtime();
204725cf1a30Sjl 
204825cf1a30Sjl 	/* patrol registers */
204925cf1a30Sjl 	mc_read_ptrl_reg(mcp, bank, &flt_stat);
205025cf1a30Sjl 
2051738dd194Shyw 	ASSERT(rsaddr);
2052738dd194Shyw 	rsaddr->mi_restartaddr = flt_stat.mf_flt_maddr;
205325cf1a30Sjl 
2054d8a0cca9Swh 	MC_LOG("ptrl registers cntl %x add %x log %x\n", flt_stat.mf_cntl,
2055d8a0cca9Swh 	    flt_stat.mf_err_add, flt_stat.mf_err_log);
205625cf1a30Sjl 
205725cf1a30Sjl 	/* MI registers */
205825cf1a30Sjl 	mc_read_mi_reg(mcp, bank, &mi_flt_stat);
205925cf1a30Sjl 
20600cc8ae86Sav 
2061d8a0cca9Swh 	MC_LOG("MI registers cntl %x add %x log %x\n", mi_flt_stat.mf_cntl,
2062d8a0cca9Swh 	    mi_flt_stat.mf_err_add, mi_flt_stat.mf_err_log);
206325cf1a30Sjl 
206425cf1a30Sjl 	/* clear errors once we read all the registers */
206525cf1a30Sjl 	MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS));
206625cf1a30Sjl 
20670cc8ae86Sav 	mc_aflt.mflt_is_ptrl = 0;
20680cc8ae86Sav 	if ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) &&
2069d8a0cca9Swh 	    ((mi_flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) &&
2070d8a0cca9Swh 	    ((mi_flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) {
20710cc8ae86Sav 		mi_valid = mc_process_error(mcp, bank, &mc_aflt, &mi_flt_stat);
20720cc8ae86Sav 	}
20730cc8ae86Sav 
20740cc8ae86Sav 	if ((((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) >>
2075d8a0cca9Swh 	    MAC_CNTL_PTRL_ERR_SHIFT) == ((mi_flt_stat.mf_cntl &
2076d8a0cca9Swh 	    MAC_CNTL_MI_ERRS) >> MAC_CNTL_MI_ERR_SHIFT)) &&
20770b240fcdSwh 	    (flt_stat.mf_err_add ==
20780b240fcdSwh 	    ROUNDDOWN(mi_flt_stat.mf_err_add, MC_BOUND_BYTE))) {
20790cc8ae86Sav #ifdef DEBUG
20800cc8ae86Sav 		MC_LOG("discarding PTRL error because "
20810cc8ae86Sav 		    "it is the same as MI\n");
20820cc8ae86Sav #endif
2083738dd194Shyw 		rsaddr->mi_valid = mi_valid;
20840cc8ae86Sav 		return;
20850cc8ae86Sav 	}
20860cc8ae86Sav 
208725cf1a30Sjl 	mc_aflt.mflt_is_ptrl = 1;
208825cf1a30Sjl 	if ((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) &&
2089d8a0cca9Swh 	    ((flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) &&
2090d8a0cca9Swh 	    ((flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) {
2091d8a0cca9Swh 		rsaddr->mi_valid = mc_process_error(mcp, bank, &mc_aflt,
2092d8a0cca9Swh 		    &flt_stat);
209325cf1a30Sjl 	}
209425cf1a30Sjl }
209525cf1a30Sjl /*
209625cf1a30Sjl  *	memory patrol error handling algorithm:
209725cf1a30Sjl  *	timeout() is used to do periodic polling
209825cf1a30Sjl  *	This is the flow chart.
209925cf1a30Sjl  *	timeout ->
210025cf1a30Sjl  *	mc_check_errors()
210125cf1a30Sjl  *	    if memory bank is installed, read the status register
210225cf1a30Sjl  *	    if any error bit is set,
210325cf1a30Sjl  *	    -> mc_error_handler()
21041039f409Sav  *		-> read all error registers
210525cf1a30Sjl  *	        -> mc_process_error()
210625cf1a30Sjl  *	            determine error type
210725cf1a30Sjl  *	            rewrite to clear error or scrub to determine CE type
210825cf1a30Sjl  *	            inform SCF on permanent CE
210925cf1a30Sjl  *	        -> mc_err_drain
211025cf1a30Sjl  *	            page offline processing
211125cf1a30Sjl  *	            -> mc_ereport_post()
211225cf1a30Sjl  */
211325cf1a30Sjl 
2114601c2e1eSdhain static void
2115601c2e1eSdhain mc_process_rewrite(mc_opl_t *mcp, int bank)
2116601c2e1eSdhain {
2117601c2e1eSdhain 	uint32_t rew_addr, cntl;
2118601c2e1eSdhain 	mc_retry_info_t *retry;
2119601c2e1eSdhain 	struct mc_bank *bankp;
2120601c2e1eSdhain 
2121601c2e1eSdhain 	bankp = &(mcp->mc_bank[bank]);
2122601c2e1eSdhain 	retry = bankp->mcb_active;
2123601c2e1eSdhain 	if (retry == NULL)
2124601c2e1eSdhain 		return;
2125601c2e1eSdhain 
2126601c2e1eSdhain 	if (retry->ri_state <= RETRY_STATE_ACTIVE) {
2127601c2e1eSdhain 		cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank));
2128601c2e1eSdhain 		if (cntl & MAC_CNTL_PTRL_STATUS)
2129601c2e1eSdhain 			return;
2130601c2e1eSdhain 		rew_addr = retry->ri_addr;
2131601c2e1eSdhain 		ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), rew_addr);
2132601c2e1eSdhain 		MAC_REW_REQ(mcp, bank);
2133601c2e1eSdhain 
2134601c2e1eSdhain 		retry->ri_state = RETRY_STATE_REWRITE;
2135601c2e1eSdhain 	}
2136601c2e1eSdhain 
2137601c2e1eSdhain 	cntl = ldphysio(MAC_PTRL_CNTL(mcp, bank));
2138601c2e1eSdhain 
2139601c2e1eSdhain 	if (cntl & MAC_CNTL_REW_END) {
2140601c2e1eSdhain 		MAC_CLEAR_ERRS(mcp, bank,
2141601c2e1eSdhain 		    MAC_CNTL_REW_ERRS);
2142601c2e1eSdhain 		mc_clear_rewrite(mcp, bank);
2143601c2e1eSdhain 	} else {
2144601c2e1eSdhain 		/*
2145601c2e1eSdhain 		 * If the rewrite does not complete in
2146601c2e1eSdhain 		 * 1 hour, we have to consider this a HW
2147601c2e1eSdhain 		 * failure.  However, there is no recovery
2148601c2e1eSdhain 		 * mechanism.  The only thing we can do
2149601c2e1eSdhain 		 * to to print a warning message to the
2150601c2e1eSdhain 		 * console.  We continue to increment the
2151601c2e1eSdhain 		 * counter but we only print the message
2152601c2e1eSdhain 		 * once.  It will take the counter a long
2153601c2e1eSdhain 		 * time to wrap around and the user might
2154601c2e1eSdhain 		 * see a second message.  In practice,
2155601c2e1eSdhain 		 * we have never hit this condition but
2156601c2e1eSdhain 		 * we have to keep the code here just in case.
2157601c2e1eSdhain 		 */
2158601c2e1eSdhain 		if (++mcp->mc_bank[bank].mcb_rewrite_count
2159601c2e1eSdhain 		    == mc_max_rewrite_retry) {
2160601c2e1eSdhain 			cmn_err(CE_WARN, "Memory patrol feature is"
2161601c2e1eSdhain 			" partly suspended on /LSB%d/B%d"
2162601c2e1eSdhain 			" due to heavy memory load,"
2163601c2e1eSdhain 			" and it will restart"
2164601c2e1eSdhain 			" automatically.\n", mcp->mc_board_num,
2165601c2e1eSdhain 			    bank);
2166601c2e1eSdhain 		}
2167601c2e1eSdhain 	}
2168601c2e1eSdhain }
2169601c2e1eSdhain 
217025cf1a30Sjl static void
217125cf1a30Sjl mc_check_errors_func(mc_opl_t *mcp)
217225cf1a30Sjl {
2173738dd194Shyw 	mc_rsaddr_info_t rsaddr_info;
217425cf1a30Sjl 	int i, error_count = 0;
217525cf1a30Sjl 	uint32_t stat, cntl;
21760cc8ae86Sav 	int running;
2177cfb9e062Shyw 	int wrapped;
217837afe445Shyw 	int ebk;
217925cf1a30Sjl 
218025cf1a30Sjl 	/*
218125cf1a30Sjl 	 * scan errors.
218225cf1a30Sjl 	 */
21830cc8ae86Sav 	if (mcp->mc_status & MC_MEMORYLESS)
21840cc8ae86Sav 		return;
21850cc8ae86Sav 
218625cf1a30Sjl 	for (i = 0; i < BANKNUM_PER_SB; i++) {
218725cf1a30Sjl 		if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) {
2188601c2e1eSdhain 			if (MC_REWRITE_ACTIVE(mcp, i)) {
2189601c2e1eSdhain 				mc_process_rewrite(mcp, i);
2190601c2e1eSdhain 			}
219125cf1a30Sjl 			stat = ldphysio(MAC_PTRL_STAT(mcp, i));
219225cf1a30Sjl 			cntl = ldphysio(MAC_PTRL_CNTL(mcp, i));
21930cc8ae86Sav 			running = cntl & MAC_CNTL_PTRL_START;
2194cfb9e062Shyw 			wrapped = cntl & MAC_CNTL_PTRL_ADD_MAX;
21950cc8ae86Sav 
219637afe445Shyw 			/* Compute the effective bank idx */
219737afe445Shyw 			ebk = (IS_MIRROR(mcp, i)) ? MIRROR_IDX(i) : i;
219837afe445Shyw 
2199cfb9e062Shyw 			if (mc_debug_show_all || stat) {
2200cfb9e062Shyw 				MC_LOG("/LSB%d/B%d stat %x cntl %x\n",
2201d8a0cca9Swh 				    mcp->mc_board_num, i, stat, cntl);
2202cfb9e062Shyw 			}
2203cfb9e062Shyw 
2204cfb9e062Shyw 			/*
2205cfb9e062Shyw 			 * Update stats and reset flag if the HW patrol
2206cfb9e062Shyw 			 * wrapped around in its scan.
2207cfb9e062Shyw 			 */
2208cfb9e062Shyw 			if (wrapped) {
220925cf1a30Sjl 				MAC_CLEAR_MAX(mcp, i);
221037afe445Shyw 				mcp->mc_period[ebk]++;
221178ed97a7Sjl 				if (IS_MIRROR(mcp, i)) {
2212d8a0cca9Swh 					MC_LOG("mirror mc period %ld on "
2213d8a0cca9Swh 					    "/LSB%d/B%d\n", mcp->mc_period[ebk],
2214d8a0cca9Swh 					    mcp->mc_board_num, i);
221578ed97a7Sjl 				} else {
2216d8a0cca9Swh 					MC_LOG("mc period %ld on "
2217d8a0cca9Swh 					    "/LSB%d/B%d\n", mcp->mc_period[ebk],
2218d8a0cca9Swh 					    mcp->mc_board_num, i);
221937afe445Shyw 				}
222025cf1a30Sjl 			}
2221cfb9e062Shyw 
2222cfb9e062Shyw 			if (running) {
2223cfb9e062Shyw 				/*
2224cfb9e062Shyw 				 * Mac patrol HW is still running.
2225cfb9e062Shyw 				 * Normally when an error is detected,
2226cfb9e062Shyw 				 * the HW patrol will stop so that we
2227cfb9e062Shyw 				 * can collect error data for reporting.
2228cfb9e062Shyw 				 * Certain errors (MI errors) detected may not
2229cfb9e062Shyw 				 * cause the HW patrol to stop which is a
2230cfb9e062Shyw 				 * problem since we cannot read error data while
2231cfb9e062Shyw 				 * the HW patrol is running. SW is not allowed
2232cfb9e062Shyw 				 * to stop the HW patrol while it is running
2233cfb9e062Shyw 				 * as it may cause HW inconsistency. This is
2234cfb9e062Shyw 				 * described in a HW errata.
2235cfb9e062Shyw 				 * In situations where we detected errors
2236cfb9e062Shyw 				 * that may not cause the HW patrol to stop.
2237cfb9e062Shyw 				 * We speed up the HW patrol scanning in
2238cfb9e062Shyw 				 * the hope that it will find the 'real' PTRL
2239cfb9e062Shyw 				 * errors associated with the previous errors
2240cfb9e062Shyw 				 * causing the HW to finally stop so that we
2241cfb9e062Shyw 				 * can do the reporting.
2242cfb9e062Shyw 				 */
2243cfb9e062Shyw 				/*
2244cfb9e062Shyw 				 * Check to see if we did speed up
2245cfb9e062Shyw 				 * the HW patrol due to previous errors
2246cfb9e062Shyw 				 * detected that did not cause the patrol
2247cfb9e062Shyw 				 * to stop. We only do it if HW patrol scan
2248cfb9e062Shyw 				 * wrapped (counted as completing a 'period').
2249cfb9e062Shyw 				 */
225037afe445Shyw 				if (mcp->mc_speedup_period[ebk] > 0) {
2251d8a0cca9Swh 					if (wrapped &&
2252d8a0cca9Swh 					    (--mcp->mc_speedup_period[ebk] ==
2253d8a0cca9Swh 					    0)) {
2254d8a0cca9Swh 						/*
2255d8a0cca9Swh 						 * We did try to speed up.
2256d8a0cca9Swh 						 * The speed up period has
2257d8a0cca9Swh 						 * expired and the HW patrol
2258d8a0cca9Swh 						 * is still running.  The
2259d8a0cca9Swh 						 * errors must be intermittent.
2260d8a0cca9Swh 						 * We have no choice but to
2261d8a0cca9Swh 						 * ignore them, reset the scan
2262d8a0cca9Swh 						 * speed to normal and clear
2263d8a0cca9Swh 						 * the MI error bits. For
2264d8a0cca9Swh 						 * mirror mode, we need to
2265d8a0cca9Swh 						 * clear errors on both banks.
2266d8a0cca9Swh 						 */
2267d8a0cca9Swh 						MC_LOG("Clearing MI errors\n");
2268d8a0cca9Swh 						MAC_CLEAR_ERRS(mcp, i,
2269d8a0cca9Swh 						    MAC_CNTL_MI_ERRS);
2270d8a0cca9Swh 
2271d8a0cca9Swh 						if (IS_MIRROR(mcp, i)) {
2272d8a0cca9Swh 							MC_LOG("Clearing "
2273d8a0cca9Swh 							    "Mirror MI errs\n");
2274d8a0cca9Swh 							MAC_CLEAR_ERRS(mcp,
2275d8a0cca9Swh 							    i^1,
2276d8a0cca9Swh 							    MAC_CNTL_MI_ERRS);
2277d8a0cca9Swh 						}
227837afe445Shyw 					}
2279cfb9e062Shyw 				} else if (stat & MAC_STAT_MI_ERRS) {
2280cfb9e062Shyw 					/*
2281cfb9e062Shyw 					 * MI errors detected but we cannot
2282cfb9e062Shyw 					 * report them since the HW patrol
2283cfb9e062Shyw 					 * is still running.
2284cfb9e062Shyw 					 * We will attempt to speed up the
2285cfb9e062Shyw 					 * scanning and hopefully the HW
2286cfb9e062Shyw 					 * can detect PRTL errors at the same
2287cfb9e062Shyw 					 * location that cause the HW patrol
2288cfb9e062Shyw 					 * to stop.
2289cfb9e062Shyw 					 */
229037afe445Shyw 					mcp->mc_speedup_period[ebk] = 2;
22910cc8ae86Sav 					MAC_CMD(mcp, i, 0);
22920cc8ae86Sav 				}
2293cfb9e062Shyw 			} else if (stat & (MAC_STAT_PTRL_ERRS |
2294cfb9e062Shyw 			    MAC_STAT_MI_ERRS)) {
2295cfb9e062Shyw 				/*
2296cfb9e062Shyw 				 * HW Patrol has stopped and we found errors.
2297cfb9e062Shyw 				 * Proceed to collect and report error info.
2298cfb9e062Shyw 				 */
229937afe445Shyw 				mcp->mc_speedup_period[ebk] = 0;
2300738dd194Shyw 				rsaddr_info.mi_valid = 0;
2301738dd194Shyw 				rsaddr_info.mi_injectrestart = 0;
2302738dd194Shyw 				if (IS_MIRROR(mcp, i)) {
2303d8a0cca9Swh 					mc_error_handler_mir(mcp, i,
2304d8a0cca9Swh 					    &rsaddr_info);
2305738dd194Shyw 				} else {
2306d8a0cca9Swh 					mc_error_handler(mcp, i, &rsaddr_info);
2307738dd194Shyw 				}
2308cfb9e062Shyw 
2309cfb9e062Shyw 				error_count++;
231007d06da5SSurya Prakki 				(void) restart_patrol(mcp, i, &rsaddr_info);
231125cf1a30Sjl 			} else {
2312cfb9e062Shyw 				/*
2313cfb9e062Shyw 				 * HW patrol scan has apparently stopped
2314cfb9e062Shyw 				 * but no errors detected/flagged.
2315cfb9e062Shyw 				 * Restart the HW patrol just to be sure.
231637afe445Shyw 				 * In mirror mode, the odd bank might have
231737afe445Shyw 				 * reported errors that caused the patrol to
231837afe445Shyw 				 * stop. We'll defer the restart to the odd
231937afe445Shyw 				 * bank in this case.
2320cfb9e062Shyw 				 */
232137afe445Shyw 				if (!IS_MIRROR(mcp, i) || (i & 0x1))
232207d06da5SSurya Prakki 					(void) restart_patrol(mcp, i, NULL);
232325cf1a30Sjl 			}
232425cf1a30Sjl 		}
232525cf1a30Sjl 	}
232625cf1a30Sjl 	if (error_count > 0)
232725cf1a30Sjl 		mcp->mc_last_error += error_count;
232825cf1a30Sjl 	else
232925cf1a30Sjl 		mcp->mc_last_error = 0;
233025cf1a30Sjl }
233125cf1a30Sjl 
23320cc8ae86Sav /*
23330cc8ae86Sav  * mc_polling -- Check errors for only one instance,
23340cc8ae86Sav  * but process errors for all instances to make sure we drain the errors
23350cc8ae86Sav  * faster than they can be accumulated.
23360cc8ae86Sav  *
23370cc8ae86Sav  * Polling on each board should be done only once per each
23380cc8ae86Sav  * mc_patrol_interval_sec.  This is equivalent to setting mc_tick_left
23390cc8ae86Sav  * to OPL_MAX_BOARDS and decrement by 1 on each timeout.
23400cc8ae86Sav  * Once mc_tick_left becomes negative, the board becomes a candidate
23410cc8ae86Sav  * for polling because it has waited for at least
23420cc8ae86Sav  * mc_patrol_interval_sec's long.    If mc_timeout_period is calculated
23431039f409Sav  * differently, this has to be updated accordingly.
23440cc8ae86Sav  */
234525cf1a30Sjl 
234625cf1a30Sjl static void
23470cc8ae86Sav mc_polling(void)
234825cf1a30Sjl {
23490cc8ae86Sav 	int i, scan_error;
23500cc8ae86Sav 	mc_opl_t *mcp;
235125cf1a30Sjl 
235225cf1a30Sjl 
23530cc8ae86Sav 	scan_error = 1;
23540cc8ae86Sav 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
23550cc8ae86Sav 		mutex_enter(&mcmutex);
23560cc8ae86Sav 		if ((mcp = mc_instances[i]) == NULL) {
23570cc8ae86Sav 			mutex_exit(&mcmutex);
23580cc8ae86Sav 			continue;
23590cc8ae86Sav 		}
23600cc8ae86Sav 		mutex_enter(&mcp->mc_lock);
23610cc8ae86Sav 		mutex_exit(&mcmutex);
2362738dd194Shyw 		if (!(mcp->mc_status & MC_POLL_RUNNING)) {
2363738dd194Shyw 			mutex_exit(&mcp->mc_lock);
2364738dd194Shyw 			continue;
2365738dd194Shyw 		}
23660cc8ae86Sav 		if (scan_error && mcp->mc_tick_left <= 0) {
23670cc8ae86Sav 			mc_check_errors_func((void *)mcp);
23680cc8ae86Sav 			mcp->mc_tick_left = OPL_MAX_BOARDS;
23690cc8ae86Sav 			scan_error = 0;
23700cc8ae86Sav 		} else {
23710cc8ae86Sav 			mcp->mc_tick_left--;
23720cc8ae86Sav 		}
23730cc8ae86Sav 		mc_process_scf_log(mcp);
23740cc8ae86Sav 		mutex_exit(&mcp->mc_lock);
237525cf1a30Sjl 	}
237625cf1a30Sjl }
237725cf1a30Sjl 
237825cf1a30Sjl static void
237925cf1a30Sjl get_ptrl_start_address(mc_opl_t *mcp, int bank, mc_addr_t *maddr)
238025cf1a30Sjl {
238125cf1a30Sjl 	maddr->ma_bd = mcp->mc_board_num;
238225cf1a30Sjl 	maddr->ma_bank = bank;
238325cf1a30Sjl 	maddr->ma_dimm_addr = 0;
238425cf1a30Sjl }
238525cf1a30Sjl 
238625cf1a30Sjl typedef struct mc_mem_range {
238725cf1a30Sjl 	uint64_t	addr;
238825cf1a30Sjl 	uint64_t	size;
238925cf1a30Sjl } mc_mem_range_t;
239025cf1a30Sjl 
239125cf1a30Sjl static int
239225cf1a30Sjl get_base_address(mc_opl_t *mcp)
239325cf1a30Sjl {
239425cf1a30Sjl 	mc_mem_range_t *mem_range;
239525cf1a30Sjl 	int len;
239625cf1a30Sjl 
239725cf1a30Sjl 	if (ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS,
2398d8a0cca9Swh 	    "sb-mem-ranges", (caddr_t)&mem_range, &len) != DDI_SUCCESS) {
239925cf1a30Sjl 		return (DDI_FAILURE);
240025cf1a30Sjl 	}
240125cf1a30Sjl 
240225cf1a30Sjl 	mcp->mc_start_address = mem_range->addr;
240325cf1a30Sjl 	mcp->mc_size = mem_range->size;
240425cf1a30Sjl 
240525cf1a30Sjl 	kmem_free(mem_range, len);
240625cf1a30Sjl 	return (DDI_SUCCESS);
240725cf1a30Sjl }
240825cf1a30Sjl 
240925cf1a30Sjl struct mc_addr_spec {
241025cf1a30Sjl 	uint32_t bank;
241125cf1a30Sjl 	uint32_t phys_hi;
241225cf1a30Sjl 	uint32_t phys_lo;
241325cf1a30Sjl };
241425cf1a30Sjl 
241525cf1a30Sjl #define	REGS_PA(m, i) ((((uint64_t)m[i].phys_hi)<<32) | m[i].phys_lo)
241625cf1a30Sjl 
241725cf1a30Sjl static char *mc_tbl_name[] = {
241825cf1a30Sjl 	"cs0-mc-pa-trans-table",
241925cf1a30Sjl 	"cs1-mc-pa-trans-table"
242025cf1a30Sjl };
242125cf1a30Sjl 
2422738dd194Shyw /*
2423738dd194Shyw  * This routine performs a rangecheck for a given PA
2424738dd194Shyw  * to see if it belongs to the memory range for this board.
2425738dd194Shyw  * Return 1 if it is valid (within the range) and 0 otherwise
2426738dd194Shyw  */
242725cf1a30Sjl static int
2428738dd194Shyw mc_rangecheck_pa(mc_opl_t *mcp, uint64_t pa)
242925cf1a30Sjl {
2430d8a0cca9Swh 	if ((pa < mcp->mc_start_address) || (mcp->mc_start_address +
2431d8a0cca9Swh 	    mcp->mc_size <= pa))
2432738dd194Shyw 		return (0);
2433738dd194Shyw 	else
2434738dd194Shyw 		return (1);
243525cf1a30Sjl }
243625cf1a30Sjl 
243725cf1a30Sjl static void
243825cf1a30Sjl mc_memlist_delete(struct memlist *mlist)
243925cf1a30Sjl {
244025cf1a30Sjl 	struct memlist *ml;
244125cf1a30Sjl 
244225cf1a30Sjl 	for (ml = mlist; ml; ml = mlist) {
244356f33205SJonathan Adams 		mlist = ml->ml_next;
244425cf1a30Sjl 		kmem_free(ml, sizeof (struct memlist));
244525cf1a30Sjl 	}
244625cf1a30Sjl }
244725cf1a30Sjl 
244825cf1a30Sjl static struct memlist *
244925cf1a30Sjl mc_memlist_dup(struct memlist *mlist)
245025cf1a30Sjl {
245125cf1a30Sjl 	struct memlist *hl = NULL, *tl, **mlp;
245225cf1a30Sjl 
245325cf1a30Sjl 	if (mlist == NULL)
245425cf1a30Sjl 		return (NULL);
245525cf1a30Sjl 
245625cf1a30Sjl 	mlp = &hl;
245725cf1a30Sjl 	tl = *mlp;
245856f33205SJonathan Adams 	for (; mlist; mlist = mlist->ml_next) {
245925cf1a30Sjl 		*mlp = kmem_alloc(sizeof (struct memlist), KM_SLEEP);
246056f33205SJonathan Adams 		(*mlp)->ml_address = mlist->ml_address;
246156f33205SJonathan Adams 		(*mlp)->ml_size = mlist->ml_size;
246256f33205SJonathan Adams 		(*mlp)->ml_prev = tl;
246325cf1a30Sjl 		tl = *mlp;
246456f33205SJonathan Adams 		mlp = &((*mlp)->ml_next);
246525cf1a30Sjl 	}
246625cf1a30Sjl 	*mlp = NULL;
246725cf1a30Sjl 
246825cf1a30Sjl 	return (hl);
246925cf1a30Sjl }
247025cf1a30Sjl 
247125cf1a30Sjl 
247225cf1a30Sjl static struct memlist *
247325cf1a30Sjl mc_memlist_del_span(struct memlist *mlist, uint64_t base, uint64_t len)
247425cf1a30Sjl {
247525cf1a30Sjl 	uint64_t	end;
247625cf1a30Sjl 	struct memlist	*ml, *tl, *nlp;
247725cf1a30Sjl 
247825cf1a30Sjl 	if (mlist == NULL)
247925cf1a30Sjl 		return (NULL);
248025cf1a30Sjl 
248125cf1a30Sjl 	end = base + len;
248256f33205SJonathan Adams 	if ((end <= mlist->ml_address) || (base == end))
248325cf1a30Sjl 		return (mlist);
248425cf1a30Sjl 
248525cf1a30Sjl 	for (tl = ml = mlist; ml; tl = ml, ml = nlp) {
248625cf1a30Sjl 		uint64_t	mend;
248725cf1a30Sjl 
248856f33205SJonathan Adams 		nlp = ml->ml_next;
248925cf1a30Sjl 
249056f33205SJonathan Adams 		if (end <= ml->ml_address)
249125cf1a30Sjl 			break;
249225cf1a30Sjl 
249356f33205SJonathan Adams 		mend = ml->ml_address + ml->ml_size;
249425cf1a30Sjl 		if (base < mend) {
249556f33205SJonathan Adams 			if (base <= ml->ml_address) {
249656f33205SJonathan Adams 				ml->ml_address = end;
249725cf1a30Sjl 				if (end >= mend)
249856f33205SJonathan Adams 					ml->ml_size = 0ull;
249925cf1a30Sjl 				else
250056f33205SJonathan Adams 					ml->ml_size = mend - ml->ml_address;
250125cf1a30Sjl 			} else {
250256f33205SJonathan Adams 				ml->ml_size = base - ml->ml_address;
250325cf1a30Sjl 				if (end < mend) {
250425cf1a30Sjl 					struct memlist	*nl;
250525cf1a30Sjl 					/*
250625cf1a30Sjl 					 * splitting an memlist entry.
250725cf1a30Sjl 					 */
250825cf1a30Sjl 					nl = kmem_alloc(sizeof (struct memlist),
2509d8a0cca9Swh 					    KM_SLEEP);
251056f33205SJonathan Adams 					nl->ml_address = end;
251156f33205SJonathan Adams 					nl->ml_size = mend - nl->ml_address;
251256f33205SJonathan Adams 					if ((nl->ml_next = nlp) != NULL)
251356f33205SJonathan Adams 						nlp->ml_prev = nl;
251456f33205SJonathan Adams 					nl->ml_prev = ml;
251556f33205SJonathan Adams 					ml->ml_next = nl;
251625cf1a30Sjl 					nlp = nl;
251725cf1a30Sjl 				}
251825cf1a30Sjl 			}
251956f33205SJonathan Adams 			if (ml->ml_size == 0ull) {
252025cf1a30Sjl 				if (ml == mlist) {
252125cf1a30Sjl 					if ((mlist = nlp) != NULL)
252256f33205SJonathan Adams 						nlp->ml_prev = NULL;
252325cf1a30Sjl 					kmem_free(ml, sizeof (struct memlist));
252425cf1a30Sjl 					if (mlist == NULL)
252525cf1a30Sjl 						break;
252625cf1a30Sjl 					ml = nlp;
252725cf1a30Sjl 				} else {
252856f33205SJonathan Adams 					if ((tl->ml_next = nlp) != NULL)
252956f33205SJonathan Adams 						nlp->ml_prev = tl;
253025cf1a30Sjl 					kmem_free(ml, sizeof (struct memlist));
253125cf1a30Sjl 					ml = tl;
253225cf1a30Sjl 				}
253325cf1a30Sjl 			}
253425cf1a30Sjl 		}
253525cf1a30Sjl 	}
253625cf1a30Sjl 
253725cf1a30Sjl 	return (mlist);
253825cf1a30Sjl }
253925cf1a30Sjl 
254025cf1a30Sjl static void
254125cf1a30Sjl mc_get_mlist(mc_opl_t *mcp)
254225cf1a30Sjl {
254325cf1a30Sjl 	struct memlist *mlist;
254425cf1a30Sjl 
254525cf1a30Sjl 	memlist_read_lock();
254625cf1a30Sjl 	mlist = mc_memlist_dup(phys_install);
254725cf1a30Sjl 	memlist_read_unlock();
254825cf1a30Sjl 
254925cf1a30Sjl 	if (mlist) {
255025cf1a30Sjl 		mlist = mc_memlist_del_span(mlist, 0ull, mcp->mc_start_address);
255125cf1a30Sjl 	}
255225cf1a30Sjl 
255325cf1a30Sjl 	if (mlist) {
255425cf1a30Sjl 		uint64_t startpa, endpa;
255525cf1a30Sjl 
255625cf1a30Sjl 		startpa = mcp->mc_start_address + mcp->mc_size;
255725cf1a30Sjl 		endpa = ptob(physmax + 1);
255825cf1a30Sjl 		if (endpa > startpa) {
2559d8a0cca9Swh 			mlist = mc_memlist_del_span(mlist, startpa,
2560d8a0cca9Swh 			    endpa - startpa);
256125cf1a30Sjl 		}
256225cf1a30Sjl 	}
256325cf1a30Sjl 
256425cf1a30Sjl 	if (mlist) {
256525cf1a30Sjl 		mcp->mlist = mlist;
256625cf1a30Sjl 	}
256725cf1a30Sjl }
256825cf1a30Sjl 
256925cf1a30Sjl int
257025cf1a30Sjl mc_board_add(mc_opl_t *mcp)
257125cf1a30Sjl {
257225cf1a30Sjl 	struct mc_addr_spec *macaddr;
25730cc8ae86Sav 	cs_status_t *cs_status;
25740cc8ae86Sav 	int len, len1, i, bk, cc;
2575738dd194Shyw 	mc_rsaddr_info_t rsaddr;
257625cf1a30Sjl 	uint32_t mirr;
25770cc8ae86Sav 	int nbanks = 0;
25780cc8ae86Sav 	uint64_t nbytes = 0;
2579d8a0cca9Swh 	int mirror_mode = 0;
2580d8a0cca9Swh 	int ret;
258125cf1a30Sjl 
258225cf1a30Sjl 	/*
258325cf1a30Sjl 	 * Get configurations from "pseudo-mc" node which includes:
258425cf1a30Sjl 	 * board# : LSB number
258525cf1a30Sjl 	 * mac-addr : physical base address of MAC registers
258625cf1a30Sjl 	 * csX-mac-pa-trans-table: translation table from DIMM address
258725cf1a30Sjl 	 *			to physical address or vice versa.
258825cf1a30Sjl 	 */
258925cf1a30Sjl 	mcp->mc_board_num = (int)ddi_getprop(DDI_DEV_T_ANY, mcp->mc_dip,
2590d8a0cca9Swh 	    DDI_PROP_DONTPASS, "board#", -1);
259125cf1a30Sjl 
25920cc8ae86Sav 	if (mcp->mc_board_num == -1) {
25930cc8ae86Sav 		return (DDI_FAILURE);
25940cc8ae86Sav 	}
25950cc8ae86Sav 
259625cf1a30Sjl 	/*
259725cf1a30Sjl 	 * Get start address in this CAB. It can be gotten from
259825cf1a30Sjl 	 * "sb-mem-ranges" property.
259925cf1a30Sjl 	 */
260025cf1a30Sjl 
260125cf1a30Sjl 	if (get_base_address(mcp) == DDI_FAILURE) {
260225cf1a30Sjl 		return (DDI_FAILURE);
260325cf1a30Sjl 	}
260425cf1a30Sjl 	/* get mac-pa trans tables */
260525cf1a30Sjl 	for (i = 0; i < MC_TT_CS; i++) {
260625cf1a30Sjl 		len = MC_TT_ENTRIES;
260725cf1a30Sjl 		cc = ddi_getlongprop_buf(DDI_DEV_T_ANY, mcp->mc_dip,
2608d8a0cca9Swh 		    DDI_PROP_DONTPASS, mc_tbl_name[i],
2609d8a0cca9Swh 		    (caddr_t)mcp->mc_trans_table[i], &len);
261025cf1a30Sjl 
261125cf1a30Sjl 		if (cc != DDI_SUCCESS) {
261225cf1a30Sjl 			bzero(mcp->mc_trans_table[i], MC_TT_ENTRIES);
261325cf1a30Sjl 		}
261425cf1a30Sjl 	}
261525cf1a30Sjl 	mcp->mlist = NULL;
261625cf1a30Sjl 
261725cf1a30Sjl 	mc_get_mlist(mcp);
261825cf1a30Sjl 
261925cf1a30Sjl 	/* initialize bank informations */
262025cf1a30Sjl 	cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS,
2621d8a0cca9Swh 	    "mc-addr", (caddr_t)&macaddr, &len);
262225cf1a30Sjl 	if (cc != DDI_SUCCESS) {
262325cf1a30Sjl 		cmn_err(CE_WARN, "Cannot get mc-addr. err=%d\n", cc);
262425cf1a30Sjl 		return (DDI_FAILURE);
262525cf1a30Sjl 	}
262625cf1a30Sjl 
26270cc8ae86Sav 	cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS,
2628d8a0cca9Swh 	    "cs-status", (caddr_t)&cs_status, &len1);
262925cf1a30Sjl 
26300cc8ae86Sav 	if (cc != DDI_SUCCESS) {
26310cc8ae86Sav 		if (len > 0)
26320cc8ae86Sav 			kmem_free(macaddr, len);
26330cc8ae86Sav 		cmn_err(CE_WARN, "Cannot get cs-status. err=%d\n", cc);
26340cc8ae86Sav 		return (DDI_FAILURE);
26350cc8ae86Sav 	}
2636aeb241b2Sav 	/* get the physical board number for a given logical board number */
2637aeb241b2Sav 	mcp->mc_phys_board_num = mc_opl_get_physical_board(mcp->mc_board_num);
2638aeb241b2Sav 
2639aeb241b2Sav 	if (mcp->mc_phys_board_num < 0) {
2640aeb241b2Sav 		if (len > 0)
2641aeb241b2Sav 			kmem_free(macaddr, len);
2642aeb241b2Sav 		cmn_err(CE_WARN, "Unable to obtain the physical board number");
2643aeb241b2Sav 		return (DDI_FAILURE);
2644aeb241b2Sav 	}
264525cf1a30Sjl 
26460cc8ae86Sav 	mutex_init(&mcp->mc_lock, NULL, MUTEX_DRIVER, NULL);
26470cc8ae86Sav 
26480cc8ae86Sav 	for (i = 0; i < len1 / sizeof (cs_status_t); i++) {
26490cc8ae86Sav 		nbytes += ((uint64_t)cs_status[i].cs_avail_hi << 32) |
2650d8a0cca9Swh 		    ((uint64_t)cs_status[i].cs_avail_low);
26510cc8ae86Sav 	}
26520cc8ae86Sav 	if (len1 > 0)
26530cc8ae86Sav 		kmem_free(cs_status, len1);
26540cc8ae86Sav 	nbanks = len / sizeof (struct mc_addr_spec);
26550cc8ae86Sav 
26560cc8ae86Sav 	if (nbanks > 0)
26570cc8ae86Sav 		nbytes /= nbanks;
26580cc8ae86Sav 	else {
26590cc8ae86Sav 		/* No need to free macaddr because len must be 0 */
26600cc8ae86Sav 		mcp->mc_status |= MC_MEMORYLESS;
26610cc8ae86Sav 		return (DDI_SUCCESS);
26620cc8ae86Sav 	}
26630cc8ae86Sav 
26640cc8ae86Sav 	for (i = 0; i < BANKNUM_PER_SB; i++) {
26650cc8ae86Sav 		mcp->mc_scf_retry[i] = 0;
26660cc8ae86Sav 		mcp->mc_period[i] = 0;
26670cc8ae86Sav 		mcp->mc_speedup_period[i] = 0;
26680cc8ae86Sav 	}
26690cc8ae86Sav 
26700cc8ae86Sav 	/*
26710cc8ae86Sav 	 * Get the memory size here. Let it be B (bytes).
26720cc8ae86Sav 	 * Let T be the time in u.s. to scan 64 bytes.
26730cc8ae86Sav 	 * If we want to complete 1 round of scanning in P seconds.
26740cc8ae86Sav 	 *
26750cc8ae86Sav 	 *	B * T * 10^(-6)	= P
26760cc8ae86Sav 	 *	---------------
26770cc8ae86Sav 	 *		64
26780cc8ae86Sav 	 *
26790cc8ae86Sav 	 *	T = P * 64 * 10^6
26800cc8ae86Sav 	 *	    -------------
26810cc8ae86Sav 	 *		B
26820cc8ae86Sav 	 *
26830cc8ae86Sav 	 *	  = P * 64 * 10^6
26840cc8ae86Sav 	 *	    -------------
26850cc8ae86Sav 	 *		B
26860cc8ae86Sav 	 *
26870cc8ae86Sav 	 *	The timing bits are set in PTRL_CNTL[28:26] where
26880cc8ae86Sav 	 *
26890cc8ae86Sav 	 *	0	- 1 m.s
26900cc8ae86Sav 	 *	1	- 512 u.s.
26910cc8ae86Sav 	 *	10	- 256 u.s.
26920cc8ae86Sav 	 *	11	- 128 u.s.
26930cc8ae86Sav 	 *	100	- 64 u.s.
26940cc8ae86Sav 	 *	101	- 32 u.s.
26950cc8ae86Sav 	 *	110	- 0 u.s.
26960cc8ae86Sav 	 *	111	- reserved.
26970cc8ae86Sav 	 *
26980cc8ae86Sav 	 *
26990cc8ae86Sav 	 *	a[0] = 110, a[1] = 101, ... a[6] = 0
27000cc8ae86Sav 	 *
27010cc8ae86Sav 	 *	cs-status property is int x 7
27020cc8ae86Sav 	 *	0 - cs#
27030cc8ae86Sav 	 *	1 - cs-status
27040cc8ae86Sav 	 *	2 - cs-avail.hi
27050cc8ae86Sav 	 *	3 - cs-avail.lo
27060cc8ae86Sav 	 *	4 - dimm-capa.hi
27070cc8ae86Sav 	 *	5 - dimm-capa.lo
27080cc8ae86Sav 	 *	6 - #of dimms
27090cc8ae86Sav 	 */
27100cc8ae86Sav 
27110cc8ae86Sav 	if (nbytes > 0) {
27120cc8ae86Sav 		int i;
27130cc8ae86Sav 		uint64_t ms;
27140cc8ae86Sav 		ms = ((uint64_t)mc_scan_period * 64 * 1000000)/nbytes;
27150cc8ae86Sav 		mcp->mc_speed = mc_scan_speeds[MC_MAX_SPEEDS - 1].mc_speeds;
27160cc8ae86Sav 		for (i = 0; i < MC_MAX_SPEEDS - 1; i++) {
27170cc8ae86Sav 			if (ms < mc_scan_speeds[i + 1].mc_period) {
27180cc8ae86Sav 				mcp->mc_speed = mc_scan_speeds[i].mc_speeds;
27190cc8ae86Sav 				break;
27200cc8ae86Sav 			}
27210cc8ae86Sav 		}
27220cc8ae86Sav 	} else
27230cc8ae86Sav 		mcp->mc_speed = 0;
27240cc8ae86Sav 
27250cc8ae86Sav 
27260cc8ae86Sav 	for (i = 0; i < len / sizeof (struct mc_addr_spec); i++) {
27270cc8ae86Sav 		struct mc_bank *bankp;
2728601c2e1eSdhain 		mc_retry_info_t *retry;
27290cc8ae86Sav 		uint32_t reg;
2730601c2e1eSdhain 		int k;
27310cc8ae86Sav 
27320cc8ae86Sav 		/*
27330cc8ae86Sav 		 * setup bank
27340cc8ae86Sav 		 */
27350cc8ae86Sav 		bk = macaddr[i].bank;
27360cc8ae86Sav 		bankp = &(mcp->mc_bank[bk]);
27370cc8ae86Sav 		bankp->mcb_status = BANK_INSTALLED;
27380cc8ae86Sav 		bankp->mcb_reg_base = REGS_PA(macaddr, i);
27390cc8ae86Sav 
2740601c2e1eSdhain 		bankp->mcb_retry_freelist = NULL;
2741601c2e1eSdhain 		bankp->mcb_retry_pending = NULL;
2742601c2e1eSdhain 		bankp->mcb_active = NULL;
2743601c2e1eSdhain 		retry = &bankp->mcb_retry_infos[0];
2744601c2e1eSdhain 		for (k = 0; k < MC_RETRY_COUNT; k++, retry++) {
2745601c2e1eSdhain 			mc_retry_info_put(&bankp->mcb_retry_freelist, retry);
2746601c2e1eSdhain 		}
2747601c2e1eSdhain 
27480cc8ae86Sav 		reg = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bk));
27490cc8ae86Sav 		bankp->mcb_ptrl_cntl = (reg & MAC_CNTL_PTRL_PRESERVE_BITS);
275025cf1a30Sjl 
275125cf1a30Sjl 		/*
275225cf1a30Sjl 		 * check if mirror mode
275325cf1a30Sjl 		 */
275425cf1a30Sjl 		mirr = LD_MAC_REG(MAC_MIRR(mcp, bk));
275525cf1a30Sjl 
275625cf1a30Sjl 		if (mirr & MAC_MIRR_MIRROR_MODE) {
2757d8a0cca9Swh 			MC_LOG("Mirror -> /LSB%d/B%d\n", mcp->mc_board_num,
2758d8a0cca9Swh 			    bk);
275925cf1a30Sjl 			bankp->mcb_status |= BANK_MIRROR_MODE;
2760d8a0cca9Swh 			mirror_mode = 1;
276125cf1a30Sjl 			/*
276225cf1a30Sjl 			 * The following bit is only used for
276325cf1a30Sjl 			 * error injection.  We should clear it
276425cf1a30Sjl 			 */
276525cf1a30Sjl 			if (mirr & MAC_MIRR_BANK_EXCLUSIVE)
2766d8a0cca9Swh 				ST_MAC_REG(MAC_MIRR(mcp, bk), 0);
276725cf1a30Sjl 		}
276825cf1a30Sjl 
276925cf1a30Sjl 		/*
277025cf1a30Sjl 		 * restart if not mirror mode or the other bank
277125cf1a30Sjl 		 * of the mirror is not running
277225cf1a30Sjl 		 */
277325cf1a30Sjl 		if (!(mirr & MAC_MIRR_MIRROR_MODE) ||
2774d8a0cca9Swh 		    !(mcp->mc_bank[bk^1].mcb_status & BANK_PTRL_RUNNING)) {
2775d8a0cca9Swh 			MC_LOG("Starting up /LSB%d/B%d\n", mcp->mc_board_num,
2776d8a0cca9Swh 			    bk);
2777738dd194Shyw 			get_ptrl_start_address(mcp, bk, &rsaddr.mi_restartaddr);
2778738dd194Shyw 			rsaddr.mi_valid = 0;
2779738dd194Shyw 			rsaddr.mi_injectrestart = 0;
278007d06da5SSurya Prakki 			(void) restart_patrol(mcp, bk, &rsaddr);
278125cf1a30Sjl 		} else {
278225cf1a30Sjl 			MC_LOG("Not starting up /LSB%d/B%d\n",
2783d8a0cca9Swh 			    mcp->mc_board_num, bk);
278425cf1a30Sjl 		}
278525cf1a30Sjl 		bankp->mcb_status |= BANK_PTRL_RUNNING;
278625cf1a30Sjl 	}
27870cc8ae86Sav 	if (len > 0)
27880cc8ae86Sav 		kmem_free(macaddr, len);
27890cc8ae86Sav 
2790d8a0cca9Swh 	ret = ndi_prop_update_int(DDI_DEV_T_NONE, mcp->mc_dip, "mirror-mode",
2791d8a0cca9Swh 	    mirror_mode);
2792d8a0cca9Swh 	if (ret != DDI_PROP_SUCCESS) {
2793d8a0cca9Swh 		cmn_err(CE_WARN, "Unable to update mirror-mode property");
2794d8a0cca9Swh 	}
2795d8a0cca9Swh 
27960cc8ae86Sav 	mcp->mc_dimm_list = mc_get_dimm_list(mcp);
279725cf1a30Sjl 
279825cf1a30Sjl 	/*
279925cf1a30Sjl 	 * set interval in HZ.
280025cf1a30Sjl 	 */
280125cf1a30Sjl 	mcp->mc_last_error = 0;
280225cf1a30Sjl 
280325cf1a30Sjl 	/* restart memory patrol checking */
280425cf1a30Sjl 	mcp->mc_status |= MC_POLL_RUNNING;
280525cf1a30Sjl 
280625cf1a30Sjl 	return (DDI_SUCCESS);
280725cf1a30Sjl }
280825cf1a30Sjl 
280925cf1a30Sjl int
281025cf1a30Sjl mc_board_del(mc_opl_t *mcp)
281125cf1a30Sjl {
281225cf1a30Sjl 	int i;
281325cf1a30Sjl 	scf_log_t *p;
281425cf1a30Sjl 
281525cf1a30Sjl 	/*
281625cf1a30Sjl 	 * cleanup mac state
281725cf1a30Sjl 	 */
281825cf1a30Sjl 	mutex_enter(&mcp->mc_lock);
28190cc8ae86Sav 	if (mcp->mc_status & MC_MEMORYLESS) {
28200cc8ae86Sav 		mutex_exit(&mcp->mc_lock);
28210cc8ae86Sav 		mutex_destroy(&mcp->mc_lock);
28220cc8ae86Sav 		return (DDI_SUCCESS);
28230cc8ae86Sav 	}
282425cf1a30Sjl 	for (i = 0; i < BANKNUM_PER_SB; i++) {
282525cf1a30Sjl 		if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) {
282625cf1a30Sjl 			mcp->mc_bank[i].mcb_status &= ~BANK_INSTALLED;
282725cf1a30Sjl 		}
282825cf1a30Sjl 	}
282925cf1a30Sjl 
283025cf1a30Sjl 	/* stop memory patrol checking */
2831738dd194Shyw 	mcp->mc_status &= ~MC_POLL_RUNNING;
283225cf1a30Sjl 
283325cf1a30Sjl 	/* just throw away all the scf logs */
28340cc8ae86Sav 	for (i = 0; i < BANKNUM_PER_SB; i++) {
2835d8a0cca9Swh 		while ((p = mcp->mc_scf_log[i]) != NULL) {
2836d8a0cca9Swh 			mcp->mc_scf_log[i] = p->sl_next;
2837d8a0cca9Swh 			mcp->mc_scf_total[i]--;
2838d8a0cca9Swh 			kmem_free(p, sizeof (scf_log_t));
2839d8a0cca9Swh 		}
284025cf1a30Sjl 	}
284125cf1a30Sjl 
284225cf1a30Sjl 	if (mcp->mlist)
284325cf1a30Sjl 		mc_memlist_delete(mcp->mlist);
284425cf1a30Sjl 
28450cc8ae86Sav 	if (mcp->mc_dimm_list)
28460cc8ae86Sav 		mc_free_dimm_list(mcp->mc_dimm_list);
28470cc8ae86Sav 
284825cf1a30Sjl 	mutex_exit(&mcp->mc_lock);
284925cf1a30Sjl 
285025cf1a30Sjl 	mutex_destroy(&mcp->mc_lock);
285125cf1a30Sjl 	return (DDI_SUCCESS);
285225cf1a30Sjl }
285325cf1a30Sjl 
285425cf1a30Sjl int
285525cf1a30Sjl mc_suspend(mc_opl_t *mcp, uint32_t flag)
285625cf1a30Sjl {
285725cf1a30Sjl 	/* stop memory patrol checking */
285825cf1a30Sjl 	mutex_enter(&mcp->mc_lock);
28590cc8ae86Sav 	if (mcp->mc_status & MC_MEMORYLESS) {
28600cc8ae86Sav 		mutex_exit(&mcp->mc_lock);
28610cc8ae86Sav 		return (DDI_SUCCESS);
28620cc8ae86Sav 	}
28630cc8ae86Sav 
2864738dd194Shyw 	mcp->mc_status &= ~MC_POLL_RUNNING;
2865738dd194Shyw 
286625cf1a30Sjl 	mcp->mc_status |= flag;
286725cf1a30Sjl 	mutex_exit(&mcp->mc_lock);
286825cf1a30Sjl 
286925cf1a30Sjl 	return (DDI_SUCCESS);
287025cf1a30Sjl }
287125cf1a30Sjl 
287268ac2337Sjl void
287368ac2337Sjl opl_mc_update_mlist(void)
287468ac2337Sjl {
287568ac2337Sjl 	int i;
287668ac2337Sjl 	mc_opl_t *mcp;
287768ac2337Sjl 
287868ac2337Sjl 	/*
287968ac2337Sjl 	 * memory information is not updated until
288068ac2337Sjl 	 * the post attach/detach stage during DR.
288168ac2337Sjl 	 * This interface is used by dr_mem to inform
288268ac2337Sjl 	 * mc-opl to update the mlist.
288368ac2337Sjl 	 */
288468ac2337Sjl 
288568ac2337Sjl 	mutex_enter(&mcmutex);
288668ac2337Sjl 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
288768ac2337Sjl 		if ((mcp = mc_instances[i]) == NULL)
288868ac2337Sjl 			continue;
288968ac2337Sjl 		mutex_enter(&mcp->mc_lock);
289068ac2337Sjl 		if (mcp->mlist)
289168ac2337Sjl 			mc_memlist_delete(mcp->mlist);
289268ac2337Sjl 		mcp->mlist = NULL;
289368ac2337Sjl 		mc_get_mlist(mcp);
289468ac2337Sjl 		mutex_exit(&mcp->mc_lock);
289568ac2337Sjl 	}
289668ac2337Sjl 	mutex_exit(&mcmutex);
289768ac2337Sjl }
289868ac2337Sjl 
289925cf1a30Sjl /* caller must clear the SUSPEND bits or this will do nothing */
290025cf1a30Sjl 
290125cf1a30Sjl int
290225cf1a30Sjl mc_resume(mc_opl_t *mcp, uint32_t flag)
290325cf1a30Sjl {
290425cf1a30Sjl 	int i;
290525cf1a30Sjl 	uint64_t basepa;
290625cf1a30Sjl 
290725cf1a30Sjl 	mutex_enter(&mcp->mc_lock);
29080cc8ae86Sav 	if (mcp->mc_status & MC_MEMORYLESS) {
29090cc8ae86Sav 		mutex_exit(&mcp->mc_lock);
29100cc8ae86Sav 		return (DDI_SUCCESS);
29110cc8ae86Sav 	}
291225cf1a30Sjl 	basepa = mcp->mc_start_address;
291325cf1a30Sjl 	if (get_base_address(mcp) == DDI_FAILURE) {
291425cf1a30Sjl 		mutex_exit(&mcp->mc_lock);
291525cf1a30Sjl 		return (DDI_FAILURE);
291625cf1a30Sjl 	}
291725cf1a30Sjl 
291825cf1a30Sjl 	if (basepa != mcp->mc_start_address) {
291925cf1a30Sjl 		if (mcp->mlist)
292025cf1a30Sjl 			mc_memlist_delete(mcp->mlist);
292125cf1a30Sjl 		mcp->mlist = NULL;
292225cf1a30Sjl 		mc_get_mlist(mcp);
292325cf1a30Sjl 	}
292425cf1a30Sjl 
292525cf1a30Sjl 	mcp->mc_status &= ~flag;
292625cf1a30Sjl 
292725cf1a30Sjl 	if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) {
292825cf1a30Sjl 		mutex_exit(&mcp->mc_lock);
292925cf1a30Sjl 		return (DDI_SUCCESS);
293025cf1a30Sjl 	}
293125cf1a30Sjl 
293225cf1a30Sjl 	if (!(mcp->mc_status & MC_POLL_RUNNING)) {
293325cf1a30Sjl 		/* restart memory patrol checking */
293425cf1a30Sjl 		mcp->mc_status |= MC_POLL_RUNNING;
293525cf1a30Sjl 		for (i = 0; i < BANKNUM_PER_SB; i++) {
293625cf1a30Sjl 			if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) {
2937601c2e1eSdhain 				mc_check_errors_func(mcp);
293825cf1a30Sjl 			}
293925cf1a30Sjl 		}
294025cf1a30Sjl 	}
294125cf1a30Sjl 	mutex_exit(&mcp->mc_lock);
294225cf1a30Sjl 
294325cf1a30Sjl 	return (DDI_SUCCESS);
294425cf1a30Sjl }
294525cf1a30Sjl 
294625cf1a30Sjl static mc_opl_t *
294725cf1a30Sjl mc_pa_to_mcp(uint64_t pa)
294825cf1a30Sjl {
29490cc8ae86Sav 	mc_opl_t *mcp;
29500cc8ae86Sav 	int i;
29510cc8ae86Sav 
295225cf1a30Sjl 	ASSERT(MUTEX_HELD(&mcmutex));
29530cc8ae86Sav 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
29540cc8ae86Sav 		if ((mcp = mc_instances[i]) == NULL)
29550cc8ae86Sav 			continue;
295625cf1a30Sjl 		/* if mac patrol is suspended, we cannot rely on it */
29570cc8ae86Sav 		if (!(mcp->mc_status & MC_POLL_RUNNING) ||
2958d8a0cca9Swh 		    (mcp->mc_status & MC_SOFT_SUSPENDED))
295925cf1a30Sjl 			continue;
2960738dd194Shyw 		if (mc_rangecheck_pa(mcp, pa)) {
29610cc8ae86Sav 			return (mcp);
296225cf1a30Sjl 		}
296325cf1a30Sjl 	}
296425cf1a30Sjl 	return (NULL);
296525cf1a30Sjl }
296625cf1a30Sjl 
296725cf1a30Sjl /*
296825cf1a30Sjl  * Get Physical Board number from Logical one.
296925cf1a30Sjl  */
297025cf1a30Sjl static int
297125cf1a30Sjl mc_opl_get_physical_board(int sb)
297225cf1a30Sjl {
297325cf1a30Sjl 	if (&opl_get_physical_board) {
297425cf1a30Sjl 		return (opl_get_physical_board(sb));
297525cf1a30Sjl 	}
297625cf1a30Sjl 
297725cf1a30Sjl 	cmn_err(CE_NOTE, "!opl_get_physical_board() not loaded\n");
297825cf1a30Sjl 	return (-1);
297925cf1a30Sjl }
298025cf1a30Sjl 
298125cf1a30Sjl /* ARGSUSED */
298225cf1a30Sjl int
298325cf1a30Sjl mc_get_mem_unum(int synd_code, uint64_t flt_addr, char *buf, int buflen,
298425cf1a30Sjl 	int *lenp)
298525cf1a30Sjl {
29860cc8ae86Sav 	int i;
2987aeb241b2Sav 	int j;
298825cf1a30Sjl 	int sb;
29890cc8ae86Sav 	int bank;
2990aeb241b2Sav 	int cs;
299178ed97a7Sjl 	int rv = 0;
29920cc8ae86Sav 	mc_opl_t *mcp;
29930cc8ae86Sav 	char memb_num;
299425cf1a30Sjl 
299525cf1a30Sjl 	mutex_enter(&mcmutex);
299625cf1a30Sjl 
299725cf1a30Sjl 	if (((mcp = mc_pa_to_mcp(flt_addr)) == NULL) ||
2998d8a0cca9Swh 	    (!pa_is_valid(mcp, flt_addr))) {
299925cf1a30Sjl 		mutex_exit(&mcmutex);
300025cf1a30Sjl 		if (snprintf(buf, buflen, "UNKNOWN") >= buflen) {
300125cf1a30Sjl 			return (ENOSPC);
300225cf1a30Sjl 		} else {
300325cf1a30Sjl 			if (lenp)
300425cf1a30Sjl 				*lenp = strlen(buf);
300525cf1a30Sjl 		}
300625cf1a30Sjl 		return (0);
300725cf1a30Sjl 	}
300825cf1a30Sjl 
300925cf1a30Sjl 	bank = pa_to_bank(mcp, flt_addr - mcp->mc_start_address);
3010aeb241b2Sav 	sb = mcp->mc_phys_board_num;
3011aeb241b2Sav 	cs = pa_to_cs(mcp, flt_addr - mcp->mc_start_address);
301225cf1a30Sjl 
301325cf1a30Sjl 	if (sb == -1) {
301425cf1a30Sjl 		mutex_exit(&mcmutex);
301525cf1a30Sjl 		return (ENXIO);
301625cf1a30Sjl 	}
301725cf1a30Sjl 
301878ed97a7Sjl 	switch (plat_model) {
301978ed97a7Sjl 	case MODEL_DC:
30200cc8ae86Sav 		i = BD_BK_SLOT_TO_INDEX(0, bank, 0);
3021aeb241b2Sav 		j = (cs == 0) ? i : i + 2;
302207d06da5SSurya Prakki 		(void) snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s",
30230cc8ae86Sav 		    model_names[plat_model].unit_name, sb,
3024aeb241b2Sav 		    mc_dc_dimm_unum_table[j],
3025aeb241b2Sav 		    mc_dc_dimm_unum_table[j + 1]);
302678ed97a7Sjl 		break;
302778ed97a7Sjl 	case MODEL_FF2:
302878ed97a7Sjl 	case MODEL_FF1:
30290cc8ae86Sav 		i = BD_BK_SLOT_TO_INDEX(sb, bank, 0);
3030aeb241b2Sav 		j = (cs == 0) ? i : i + 2;
30310cc8ae86Sav 		memb_num = mc_ff_dimm_unum_table[i][0];
303207d06da5SSurya Prakki 		(void) snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s",
30330cc8ae86Sav 		    model_names[plat_model].unit_name,
30340cc8ae86Sav 		    model_names[plat_model].mem_name, memb_num,
3035aeb241b2Sav 		    &mc_ff_dimm_unum_table[j][1],
3036aeb241b2Sav 		    &mc_ff_dimm_unum_table[j + 1][1]);
303778ed97a7Sjl 		break;
303878ed97a7Sjl 	case MODEL_IKKAKU:
303978ed97a7Sjl 		i = BD_BK_SLOT_TO_INDEX(sb, bank, 0);
304078ed97a7Sjl 		j = (cs == 0) ? i : i + 2;
304107d06da5SSurya Prakki 		(void) snprintf(buf, buflen, "/%s/MEM%s MEM%s",
304278ed97a7Sjl 		    model_names[plat_model].unit_name,
304378ed97a7Sjl 		    &mc_ff_dimm_unum_table[j][1],
304478ed97a7Sjl 		    &mc_ff_dimm_unum_table[j + 1][1]);
304578ed97a7Sjl 		break;
304678ed97a7Sjl 	default:
304778ed97a7Sjl 		rv = ENXIO;
30480cc8ae86Sav 	}
30490cc8ae86Sav 	if (lenp) {
30500cc8ae86Sav 		*lenp = strlen(buf);
305125cf1a30Sjl 	}
305225cf1a30Sjl 	mutex_exit(&mcmutex);
305378ed97a7Sjl 	return (rv);
305425cf1a30Sjl }
305525cf1a30Sjl 
305625cf1a30Sjl int
30570cc8ae86Sav opl_mc_suspend(void)
305825cf1a30Sjl {
305925cf1a30Sjl 	mc_opl_t *mcp;
30600cc8ae86Sav 	int i;
306125cf1a30Sjl 
306225cf1a30Sjl 	mutex_enter(&mcmutex);
30630cc8ae86Sav 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
30640cc8ae86Sav 		if ((mcp = mc_instances[i]) == NULL)
30650cc8ae86Sav 			continue;
306607d06da5SSurya Prakki 		(void) mc_suspend(mcp, MC_SOFT_SUSPENDED);
306725cf1a30Sjl 	}
306825cf1a30Sjl 	mutex_exit(&mcmutex);
30690cc8ae86Sav 
307025cf1a30Sjl 	return (0);
307125cf1a30Sjl }
307225cf1a30Sjl 
307325cf1a30Sjl int
30740cc8ae86Sav opl_mc_resume(void)
307525cf1a30Sjl {
307625cf1a30Sjl 	mc_opl_t *mcp;
30770cc8ae86Sav 	int i;
307825cf1a30Sjl 
307925cf1a30Sjl 	mutex_enter(&mcmutex);
30800cc8ae86Sav 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
30810cc8ae86Sav 		if ((mcp = mc_instances[i]) == NULL)
30820cc8ae86Sav 			continue;
308307d06da5SSurya Prakki 		(void) mc_resume(mcp, MC_SOFT_SUSPENDED);
308425cf1a30Sjl 	}
308525cf1a30Sjl 	mutex_exit(&mcmutex);
30860cc8ae86Sav 
308725cf1a30Sjl 	return (0);
308825cf1a30Sjl }
308925cf1a30Sjl static void
309025cf1a30Sjl insert_mcp(mc_opl_t *mcp)
309125cf1a30Sjl {
309225cf1a30Sjl 	mutex_enter(&mcmutex);
30930cc8ae86Sav 	if (mc_instances[mcp->mc_board_num] != NULL) {
30940cc8ae86Sav 		MC_LOG("mc-opl instance for board# %d already exists\n",
3095d8a0cca9Swh 		    mcp->mc_board_num);
30960cc8ae86Sav 	}
30970cc8ae86Sav 	mc_instances[mcp->mc_board_num] = mcp;
309825cf1a30Sjl 	mutex_exit(&mcmutex);
309925cf1a30Sjl }
310025cf1a30Sjl 
310125cf1a30Sjl static void
310225cf1a30Sjl delete_mcp(mc_opl_t *mcp)
310325cf1a30Sjl {
31040cc8ae86Sav 	mutex_enter(&mcmutex);
31050cc8ae86Sav 	mc_instances[mcp->mc_board_num] = 0;
31060cc8ae86Sav 	mutex_exit(&mcmutex);
310725cf1a30Sjl }
310825cf1a30Sjl 
310925cf1a30Sjl /* Error injection interface */
311025cf1a30Sjl 
3111cfb9e062Shyw static void
3112cfb9e062Shyw mc_lock_va(uint64_t pa, caddr_t new_va)
3113cfb9e062Shyw {
3114cfb9e062Shyw 	tte_t tte;
3115cfb9e062Shyw 
3116738dd194Shyw 	vtag_flushpage(new_va, (uint64_t)ksfmmup);
3117d8a0cca9Swh 	sfmmu_memtte(&tte, pa >> PAGESHIFT, PROC_DATA|HAT_NOSYNC, TTE8K);
3118cfb9e062Shyw 	tte.tte_intlo |= TTE_LCK_INT;
3119cfb9e062Shyw 	sfmmu_dtlb_ld_kva(new_va, &tte);
3120cfb9e062Shyw }
3121cfb9e062Shyw 
3122cfb9e062Shyw static void
3123cfb9e062Shyw mc_unlock_va(caddr_t va)
3124cfb9e062Shyw {
3125cfb9e062Shyw 	vtag_flushpage(va, (uint64_t)ksfmmup);
3126cfb9e062Shyw }
3127cfb9e062Shyw 
312825cf1a30Sjl /* ARGSUSED */
312925cf1a30Sjl int
313025cf1a30Sjl mc_inject_error(int error_type, uint64_t pa, uint32_t flags)
313125cf1a30Sjl {
313225cf1a30Sjl 	mc_opl_t *mcp;
313325cf1a30Sjl 	int bank;
313425cf1a30Sjl 	uint32_t dimm_addr;
313525cf1a30Sjl 	uint32_t cntl;
3136738dd194Shyw 	mc_rsaddr_info_t rsaddr;
313725cf1a30Sjl 	uint32_t data, stat;
313825cf1a30Sjl 	int both_sides = 0;
313925cf1a30Sjl 	uint64_t pa0;
3140cfb9e062Shyw 	int extra_injection_needed = 0;
314125cf1a30Sjl 	extern void cpu_flush_ecache(void);
314225cf1a30Sjl 
314325cf1a30Sjl 	MC_LOG("HW mc_inject_error(%x, %lx, %x)\n", error_type, pa, flags);
314425cf1a30Sjl 
314525cf1a30Sjl 	mutex_enter(&mcmutex);
314625cf1a30Sjl 	if ((mcp = mc_pa_to_mcp(pa)) == NULL) {
314725cf1a30Sjl 		mutex_exit(&mcmutex);
314825cf1a30Sjl 		MC_LOG("mc_inject_error: invalid pa\n");
314925cf1a30Sjl 		return (ENOTSUP);
315025cf1a30Sjl 	}
315125cf1a30Sjl 
315225cf1a30Sjl 	mutex_enter(&mcp->mc_lock);
315325cf1a30Sjl 	mutex_exit(&mcmutex);
315425cf1a30Sjl 
315525cf1a30Sjl 	if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) {
315625cf1a30Sjl 		mutex_exit(&mcp->mc_lock);
315725cf1a30Sjl 		MC_LOG("mc-opl has been suspended.  No error injection.\n");
315825cf1a30Sjl 		return (EBUSY);
315925cf1a30Sjl 	}
316025cf1a30Sjl 
316125cf1a30Sjl 	/* convert pa to offset within the board */
316225cf1a30Sjl 	MC_LOG("pa %lx, offset %lx\n", pa, pa - mcp->mc_start_address);
316325cf1a30Sjl 
316425cf1a30Sjl 	if (!pa_is_valid(mcp, pa)) {
316525cf1a30Sjl 		mutex_exit(&mcp->mc_lock);
316625cf1a30Sjl 		return (EINVAL);
316725cf1a30Sjl 	}
316825cf1a30Sjl 
316925cf1a30Sjl 	pa0 = pa - mcp->mc_start_address;
317025cf1a30Sjl 
317125cf1a30Sjl 	bank = pa_to_bank(mcp, pa0);
317225cf1a30Sjl 
317325cf1a30Sjl 	if (flags & MC_INJECT_FLAG_OTHER)
317425cf1a30Sjl 		bank = bank ^ 1;
317525cf1a30Sjl 
317625cf1a30Sjl 	if (MC_INJECT_MIRROR(error_type) && !IS_MIRROR(mcp, bank)) {
317725cf1a30Sjl 		mutex_exit(&mcp->mc_lock);
317825cf1a30Sjl 		MC_LOG("Not mirror mode\n");
317925cf1a30Sjl 		return (EINVAL);
318025cf1a30Sjl 	}
318125cf1a30Sjl 
318225cf1a30Sjl 	dimm_addr = pa_to_dimm(mcp, pa0);
318325cf1a30Sjl 
3184d8a0cca9Swh 	MC_LOG("injecting error to /LSB%d/B%d/%x\n", mcp->mc_board_num, bank,
3185d8a0cca9Swh 	    dimm_addr);
318625cf1a30Sjl 
318725cf1a30Sjl 
318825cf1a30Sjl 	switch (error_type) {
318925cf1a30Sjl 	case MC_INJECT_INTERMITTENT_MCE:
319025cf1a30Sjl 	case MC_INJECT_PERMANENT_MCE:
319125cf1a30Sjl 	case MC_INJECT_MUE:
319225cf1a30Sjl 		both_sides = 1;
319325cf1a30Sjl 	}
319425cf1a30Sjl 
319525cf1a30Sjl 	if (flags & MC_INJECT_FLAG_RESET)
319625cf1a30Sjl 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 0);
319725cf1a30Sjl 
319825cf1a30Sjl 	ST_MAC_REG(MAC_EG_ADD(mcp, bank), dimm_addr & MAC_EG_ADD_MASK);
319925cf1a30Sjl 
320025cf1a30Sjl 	if (both_sides) {
320125cf1a30Sjl 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), 0);
3202d8a0cca9Swh 		ST_MAC_REG(MAC_EG_ADD(mcp, bank^1), dimm_addr &
3203d8a0cca9Swh 		    MAC_EG_ADD_MASK);
320425cf1a30Sjl 	}
320525cf1a30Sjl 
320625cf1a30Sjl 	switch (error_type) {
320725cf1a30Sjl 	case MC_INJECT_SUE:
3208cfb9e062Shyw 		extra_injection_needed = 1;
3209cfb9e062Shyw 		/*FALLTHROUGH*/
3210cfb9e062Shyw 	case MC_INJECT_UE:
321125cf1a30Sjl 	case MC_INJECT_MUE:
321225cf1a30Sjl 		if (flags & MC_INJECT_FLAG_PATH) {
3213d8a0cca9Swh 			cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_READ00 |
3214d8a0cca9Swh 			    MAC_EG_FORCE_READ16 | MAC_EG_RDERR_ONCE;
321525cf1a30Sjl 		} else {
3216d8a0cca9Swh 			cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_DERR00 |
3217d8a0cca9Swh 			    MAC_EG_FORCE_DERR16 | MAC_EG_DERR_ONCE;
321825cf1a30Sjl 		}
321925cf1a30Sjl 		flags |= MC_INJECT_FLAG_ST;
322025cf1a30Sjl 		break;
322125cf1a30Sjl 	case MC_INJECT_INTERMITTENT_CE:
322225cf1a30Sjl 	case MC_INJECT_INTERMITTENT_MCE:
322325cf1a30Sjl 		if (flags & MC_INJECT_FLAG_PATH) {
3224d8a0cca9Swh 			cntl = MAC_EG_ADD_FIX |MAC_EG_FORCE_READ00 |
3225d8a0cca9Swh 			    MAC_EG_RDERR_ONCE;
322625cf1a30Sjl 		} else {
3227d8a0cca9Swh 			cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_DERR16 |
3228d8a0cca9Swh 			    MAC_EG_DERR_ONCE;
322925cf1a30Sjl 		}
3230cfb9e062Shyw 		extra_injection_needed = 1;
323125cf1a30Sjl 		flags |= MC_INJECT_FLAG_ST;
323225cf1a30Sjl 		break;
323325cf1a30Sjl 	case MC_INJECT_PERMANENT_CE:
323425cf1a30Sjl 	case MC_INJECT_PERMANENT_MCE:
323525cf1a30Sjl 		if (flags & MC_INJECT_FLAG_PATH) {
3236d8a0cca9Swh 			cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_READ00 |
3237d8a0cca9Swh 			    MAC_EG_RDERR_ALWAYS;
323825cf1a30Sjl 		} else {
3239d8a0cca9Swh 			cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_DERR16 |
3240d8a0cca9Swh 			    MAC_EG_DERR_ALWAYS;
324125cf1a30Sjl 		}
324225cf1a30Sjl 		flags |= MC_INJECT_FLAG_ST;
324325cf1a30Sjl 		break;
324425cf1a30Sjl 	case MC_INJECT_CMPE:
324525cf1a30Sjl 		data = 0xabcdefab;
324625cf1a30Sjl 		stphys(pa, data);
324725cf1a30Sjl 		cpu_flush_ecache();
324825cf1a30Sjl 		MC_LOG("CMPE: writing data %x to %lx\n", data, pa);
324925cf1a30Sjl 		ST_MAC_REG(MAC_MIRR(mcp, bank), MAC_MIRR_BANK_EXCLUSIVE);
325025cf1a30Sjl 		stphys(pa, data ^ 0xffffffff);
3251738dd194Shyw 		membar_sync();
325225cf1a30Sjl 		cpu_flush_ecache();
325325cf1a30Sjl 		ST_MAC_REG(MAC_MIRR(mcp, bank), 0);
325425cf1a30Sjl 		MC_LOG("CMPE: write new data %xto %lx\n", data, pa);
325525cf1a30Sjl 		cntl = 0;
325625cf1a30Sjl 		break;
325725cf1a30Sjl 	case MC_INJECT_NOP:
325825cf1a30Sjl 		cntl = 0;
325925cf1a30Sjl 		break;
326025cf1a30Sjl 	default:
326125cf1a30Sjl 		MC_LOG("mc_inject_error: invalid option\n");
326225cf1a30Sjl 		cntl = 0;
326325cf1a30Sjl 	}
326425cf1a30Sjl 
326525cf1a30Sjl 	if (cntl) {
326625cf1a30Sjl 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl & MAC_EG_SETUP_MASK);
326725cf1a30Sjl 		ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl);
326825cf1a30Sjl 
326925cf1a30Sjl 		if (both_sides) {
327025cf1a30Sjl 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl &
3271d8a0cca9Swh 			    MAC_EG_SETUP_MASK);
327225cf1a30Sjl 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl);
327325cf1a30Sjl 		}
327425cf1a30Sjl 	}
327525cf1a30Sjl 
327625cf1a30Sjl 	/*
327725cf1a30Sjl 	 * For all injection cases except compare error, we
327825cf1a30Sjl 	 * must write to the PA to trigger the error.
327925cf1a30Sjl 	 */
328025cf1a30Sjl 
328125cf1a30Sjl 	if (flags & MC_INJECT_FLAG_ST) {
328225cf1a30Sjl 		data = 0xf0e0d0c0;
328325cf1a30Sjl 		MC_LOG("Writing %x to %lx\n", data, pa);
328425cf1a30Sjl 		stphys(pa, data);
328525cf1a30Sjl 		cpu_flush_ecache();
328625cf1a30Sjl 	}
328725cf1a30Sjl 
328825cf1a30Sjl 
328925cf1a30Sjl 	if (flags & MC_INJECT_FLAG_LD) {
3290cfb9e062Shyw 		if (flags & MC_INJECT_FLAG_PREFETCH) {
3291cfb9e062Shyw 			/*
3292cfb9e062Shyw 			 * Use strong prefetch operation to
3293cfb9e062Shyw 			 * inject MI errors.
3294cfb9e062Shyw 			 */
3295cfb9e062Shyw 			page_t *pp;
3296cfb9e062Shyw 			extern void mc_prefetch(caddr_t);
3297cfb9e062Shyw 
3298cfb9e062Shyw 			MC_LOG("prefetch\n");
3299cfb9e062Shyw 
3300cfb9e062Shyw 			pp = page_numtopp_nolock(pa >> PAGESHIFT);
3301cfb9e062Shyw 			if (pp != NULL) {
3302cfb9e062Shyw 				caddr_t	va, va1;
3303cfb9e062Shyw 
3304cfb9e062Shyw 				va = ppmapin(pp, PROT_READ|PROT_WRITE,
3305d8a0cca9Swh 				    (caddr_t)-1);
3306cfb9e062Shyw 				kpreempt_disable();
3307cfb9e062Shyw 				mc_lock_va((uint64_t)pa, va);
3308cfb9e062Shyw 				va1 = va + (pa & (PAGESIZE - 1));
3309cfb9e062Shyw 				mc_prefetch(va1);
3310cfb9e062Shyw 				mc_unlock_va(va);
3311cfb9e062Shyw 				kpreempt_enable();
3312cfb9e062Shyw 				ppmapout(va);
3313cfb9e062Shyw 
3314cfb9e062Shyw 				/*
3315cfb9e062Shyw 				 * For MI errors, we need one extra
3316cfb9e062Shyw 				 * injection for HW patrol to stop.
3317cfb9e062Shyw 				 */
3318cfb9e062Shyw 				extra_injection_needed = 1;
331925cf1a30Sjl 			} else {
3320cfb9e062Shyw 				cmn_err(CE_WARN, "Cannot find page structure"
3321d8a0cca9Swh 				    " for PA %lx\n", pa);
332225cf1a30Sjl 			}
332325cf1a30Sjl 		} else {
332425cf1a30Sjl 			MC_LOG("Reading from %lx\n", pa);
332525cf1a30Sjl 			data = ldphys(pa);
332625cf1a30Sjl 			MC_LOG("data = %x\n", data);
332725cf1a30Sjl 		}
3328cfb9e062Shyw 
3329cfb9e062Shyw 		if (extra_injection_needed) {
3330cfb9e062Shyw 			/*
3331cfb9e062Shyw 			 * These are the injection cases where the
3332cfb9e062Shyw 			 * requested injected errors will not cause the HW
3333cfb9e062Shyw 			 * patrol to stop. For these cases, we need to inject
3334cfb9e062Shyw 			 * an extra 'real' PTRL error to force the
3335cfb9e062Shyw 			 * HW patrol to stop so that we can report the
3336cfb9e062Shyw 			 * errors injected. Note that we cannot read
3337cfb9e062Shyw 			 * and report error status while the HW patrol
3338cfb9e062Shyw 			 * is running.
3339cfb9e062Shyw 			 */
3340cfb9e062Shyw 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank),
3341d8a0cca9Swh 			    cntl & MAC_EG_SETUP_MASK);
3342cfb9e062Shyw 			ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl);
3343cfb9e062Shyw 
3344cfb9e062Shyw 			if (both_sides) {
3345d8a0cca9Swh 				ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl &
3346d8a0cca9Swh 				    MAC_EG_SETUP_MASK);
3347d8a0cca9Swh 				ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl);
3348cfb9e062Shyw 			}
3349cfb9e062Shyw 			data = 0xf0e0d0c0;
3350cfb9e062Shyw 			MC_LOG("Writing %x to %lx\n", data, pa);
3351cfb9e062Shyw 			stphys(pa, data);
3352cfb9e062Shyw 			cpu_flush_ecache();
3353cfb9e062Shyw 		}
335425cf1a30Sjl 	}
335525cf1a30Sjl 
335625cf1a30Sjl 	if (flags & MC_INJECT_FLAG_RESTART) {
335725cf1a30Sjl 		MC_LOG("Restart patrol\n");
3358738dd194Shyw 		rsaddr.mi_restartaddr.ma_bd = mcp->mc_board_num;
3359738dd194Shyw 		rsaddr.mi_restartaddr.ma_bank = bank;
3360738dd194Shyw 		rsaddr.mi_restartaddr.ma_dimm_addr = dimm_addr;
3361738dd194Shyw 		rsaddr.mi_valid = 1;
3362738dd194Shyw 		rsaddr.mi_injectrestart = 1;
336307d06da5SSurya Prakki 		(void) restart_patrol(mcp, bank, &rsaddr);
336425cf1a30Sjl 	}
336525cf1a30Sjl 
336625cf1a30Sjl 	if (flags & MC_INJECT_FLAG_POLL) {
33670cc8ae86Sav 		int running;
336837afe445Shyw 		int ebank = (IS_MIRROR(mcp, bank)) ? MIRROR_IDX(bank) : bank;
336925cf1a30Sjl 
337025cf1a30Sjl 		MC_LOG("Poll patrol error\n");
337125cf1a30Sjl 		stat = LD_MAC_REG(MAC_PTRL_STAT(mcp, bank));
337225cf1a30Sjl 		cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank));
33730cc8ae86Sav 		running = cntl & MAC_CNTL_PTRL_START;
337425cf1a30Sjl 
3375cfb9e062Shyw 		if (!running &&
3376cfb9e062Shyw 		    (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS))) {
3377cfb9e062Shyw 			/*
3378cfb9e062Shyw 			 * HW patrol stopped and we have errors to
3379cfb9e062Shyw 			 * report. Do it.
3380cfb9e062Shyw 			 */
338137afe445Shyw 			mcp->mc_speedup_period[ebank] = 0;
3382738dd194Shyw 			rsaddr.mi_valid = 0;
3383738dd194Shyw 			rsaddr.mi_injectrestart = 0;
3384738dd194Shyw 			if (IS_MIRROR(mcp, bank)) {
3385738dd194Shyw 				mc_error_handler_mir(mcp, bank, &rsaddr);
3386738dd194Shyw 			} else {
3387738dd194Shyw 				mc_error_handler(mcp, bank, &rsaddr);
3388738dd194Shyw 			}
3389cfb9e062Shyw 
339007d06da5SSurya Prakki 			(void) restart_patrol(mcp, bank, &rsaddr);
3391cfb9e062Shyw 		} else {
3392cfb9e062Shyw 			/*
3393cfb9e062Shyw 			 * We are expecting to report injected
3394cfb9e062Shyw 			 * errors but the HW patrol is still running.
3395cfb9e062Shyw 			 * Speed up the scanning
3396cfb9e062Shyw 			 */
339737afe445Shyw 			mcp->mc_speedup_period[ebank] = 2;
3398cfb9e062Shyw 			MAC_CMD(mcp, bank, 0);
339907d06da5SSurya Prakki 			(void) restart_patrol(mcp, bank, NULL);
3400cfb9e062Shyw 		}
340125cf1a30Sjl 	}
340225cf1a30Sjl 
340325cf1a30Sjl 	mutex_exit(&mcp->mc_lock);
340425cf1a30Sjl 	return (0);
340525cf1a30Sjl }
3406cfb9e062Shyw 
340725cf1a30Sjl void
340825cf1a30Sjl mc_stphysio(uint64_t pa, uint32_t data)
340925cf1a30Sjl {
341025cf1a30Sjl 	MC_LOG("0x%x -> pa(%lx)\n", data, pa);
341125cf1a30Sjl 	stphysio(pa, data);
34120cc8ae86Sav 
34130cc8ae86Sav 	/* force the above write to be processed by mac patrol */
3414cfb9e062Shyw 	data = ldphysio(pa);
3415cfb9e062Shyw 	MC_LOG("pa(%lx) = 0x%x\n", pa, data);
341625cf1a30Sjl }
341725cf1a30Sjl 
341825cf1a30Sjl uint32_t
341925cf1a30Sjl mc_ldphysio(uint64_t pa)
342025cf1a30Sjl {
342125cf1a30Sjl 	uint32_t rv;
342225cf1a30Sjl 
342325cf1a30Sjl 	rv = ldphysio(pa);
342425cf1a30Sjl 	MC_LOG("pa(%lx) = 0x%x\n", pa, rv);
342525cf1a30Sjl 	return (rv);
342625cf1a30Sjl }
34270cc8ae86Sav 
34280cc8ae86Sav #define	isdigit(ch)	((ch) >= '0' && (ch) <= '9')
34290cc8ae86Sav 
34300cc8ae86Sav /*
34310cc8ae86Sav  * parse_unum_memory -- extract the board number and the DIMM name from
34320cc8ae86Sav  * the unum.
34330cc8ae86Sav  *
34340cc8ae86Sav  * Return 0 for success and non-zero for a failure.
34350cc8ae86Sav  */
34360cc8ae86Sav int
34370cc8ae86Sav parse_unum_memory(char *unum, int *board, char *dname)
34380cc8ae86Sav {
34390cc8ae86Sav 	char *c;
34400cc8ae86Sav 	char x, y, z;
34410cc8ae86Sav 
34420cc8ae86Sav 	if ((c = strstr(unum, "CMU")) != NULL) {
34430cc8ae86Sav 		/* DC Model */
34440cc8ae86Sav 		c += 3;
34450cc8ae86Sav 		*board = (uint8_t)stoi(&c);
34460cc8ae86Sav 		if ((c = strstr(c, "MEM")) == NULL) {
34470cc8ae86Sav 			return (1);
34480cc8ae86Sav 		}
34490cc8ae86Sav 		c += 3;
34500cc8ae86Sav 		if (strlen(c) < 3) {
34510cc8ae86Sav 			return (2);
34520cc8ae86Sav 		}
34530cc8ae86Sav 		if ((!isdigit(c[0])) || (!(isdigit(c[1]))) ||
34540cc8ae86Sav 		    ((c[2] != 'A') && (c[2] != 'B'))) {
34550cc8ae86Sav 			return (3);
34560cc8ae86Sav 		}
34570cc8ae86Sav 		x = c[0];
34580cc8ae86Sav 		y = c[1];
34590cc8ae86Sav 		z = c[2];
34600cc8ae86Sav 	} else if ((c = strstr(unum, "MBU_")) != NULL) {
346178ed97a7Sjl 		/*  FF1/FF2/Ikkaku Model */
34620cc8ae86Sav 		c += 4;
34630cc8ae86Sav 		if ((c[0] != 'A') && (c[0] != 'B')) {
34640cc8ae86Sav 			return (4);
34650cc8ae86Sav 		}
346678ed97a7Sjl 		if (plat_model == MODEL_IKKAKU) {
346778ed97a7Sjl 			/* Ikkaku Model */
346878ed97a7Sjl 			x = '0';
346978ed97a7Sjl 			*board = 0;
347078ed97a7Sjl 		} else {
347178ed97a7Sjl 			/* FF1/FF2 Model */
347278ed97a7Sjl 			if ((c = strstr(c, "MEMB")) == NULL) {
347378ed97a7Sjl 				return (5);
347478ed97a7Sjl 			}
347578ed97a7Sjl 			c += 4;
347678ed97a7Sjl 
347778ed97a7Sjl 			x = c[0];
347878ed97a7Sjl 			*board =  ((uint8_t)stoi(&c)) / 4;
34790cc8ae86Sav 		}
34800cc8ae86Sav 
34810cc8ae86Sav 		if ((c = strstr(c, "MEM")) == NULL) {
34820cc8ae86Sav 			return (6);
34830cc8ae86Sav 		}
34840cc8ae86Sav 		c += 3;
34850cc8ae86Sav 		if (strlen(c) < 2) {
34860cc8ae86Sav 			return (7);
34870cc8ae86Sav 		}
34880cc8ae86Sav 		if ((!isdigit(c[0])) || ((c[1] != 'A') && (c[1] != 'B'))) {
34890cc8ae86Sav 			return (8);
34900cc8ae86Sav 		}
34910cc8ae86Sav 		y = c[0];
34920cc8ae86Sav 		z = c[1];
34930cc8ae86Sav 	} else {
34940cc8ae86Sav 		return (9);
34950cc8ae86Sav 	}
34960cc8ae86Sav 	if (*board < 0) {
34970cc8ae86Sav 		return (10);
34980cc8ae86Sav 	}
34990cc8ae86Sav 	dname[0] = x;
35000cc8ae86Sav 	dname[1] = y;
35010cc8ae86Sav 	dname[2] = z;
35020cc8ae86Sav 	dname[3] = '\0';
35030cc8ae86Sav 	return (0);
35040cc8ae86Sav }
35050cc8ae86Sav 
35060cc8ae86Sav /*
35070cc8ae86Sav  * mc_get_mem_sid_dimm -- Get the serial-ID for a given board and
35080cc8ae86Sav  * the DIMM name.
35090cc8ae86Sav  */
35100cc8ae86Sav int
35110cc8ae86Sav mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf,
35120cc8ae86Sav     int buflen, int *lenp)
35130cc8ae86Sav {
35140cc8ae86Sav 	int		ret = ENODEV;
35150cc8ae86Sav 	mc_dimm_info_t	*d = NULL;
35160cc8ae86Sav 
3517feb5832bSMary Beale 	if ((d = mcp->mc_dimm_list) == NULL) {
3518feb5832bSMary Beale 		MC_LOG("mc_get_mem_sid_dimm: mc_dimm_list is NULL\n");
3519feb5832bSMary Beale 		return (EINVAL);
3520feb5832bSMary Beale 		}
35210cc8ae86Sav 
35220cc8ae86Sav 	for (; d != NULL; d = d->md_next) {
35230cc8ae86Sav 		if (strcmp(d->md_dimmname, dname) == 0) {
35240cc8ae86Sav 			break;
35250cc8ae86Sav 		}
35260cc8ae86Sav 	}
35270cc8ae86Sav 	if (d != NULL) {
35280cc8ae86Sav 		*lenp = strlen(d->md_serial) + strlen(d->md_partnum);
35290cc8ae86Sav 		if (buflen <=  *lenp) {
35300cc8ae86Sav 			cmn_err(CE_WARN, "mc_get_mem_sid_dimm: "
35310cc8ae86Sav 			    "buflen is smaller than %d\n", *lenp);
35320cc8ae86Sav 			ret = ENOSPC;
35330cc8ae86Sav 		} else {
353407d06da5SSurya Prakki 			(void) snprintf(buf, buflen, "%s:%s",
35350cc8ae86Sav 			    d->md_serial, d->md_partnum);
35360cc8ae86Sav 			ret = 0;
35370cc8ae86Sav 		}
35380cc8ae86Sav 	}
35390cc8ae86Sav 	MC_LOG("mc_get_mem_sid_dimm: Ret=%d Name=%s Serial-ID=%s\n",
35400cc8ae86Sav 	    ret, dname, (ret == 0) ? buf : "");
35410cc8ae86Sav 	return (ret);
35420cc8ae86Sav }
35430cc8ae86Sav 
35440cc8ae86Sav int
3545aeb241b2Sav mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int sb,
35460cc8ae86Sav     int bank, uint32_t mf_type, uint32_t d_slot)
35470cc8ae86Sav {
35480cc8ae86Sav 	int	lenp = buflen;
35490cc8ae86Sav 	int	id;
35500cc8ae86Sav 	int	ret;
35510cc8ae86Sav 	char	*dimmnm;
35520cc8ae86Sav 
3553056c948bStsien 	if (mf_type == FLT_TYPE_INTERMITTENT_CE ||
3554056c948bStsien 	    mf_type == FLT_TYPE_PERMANENT_CE) {
35550cc8ae86Sav 		if (plat_model == MODEL_DC) {
355678ed97a7Sjl 			/*
355778ed97a7Sjl 			 * All DC models
355878ed97a7Sjl 			 */
35590cc8ae86Sav 			id = BD_BK_SLOT_TO_INDEX(0, bank, d_slot);
3560aeb241b2Sav 			dimmnm = mc_dc_dimm_unum_table[id];
35610cc8ae86Sav 		} else {
356278ed97a7Sjl 			/*
356378ed97a7Sjl 			 * All FF and Ikkaku models
356478ed97a7Sjl 			 */
35650cc8ae86Sav 			id = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot);
3566aeb241b2Sav 			dimmnm = mc_ff_dimm_unum_table[id];
35670cc8ae86Sav 		}
35680cc8ae86Sav 		if ((ret = mc_get_mem_sid_dimm(mcp, dimmnm, buf, buflen,
35690cc8ae86Sav 		    &lenp)) != 0) {
35700cc8ae86Sav 			return (ret);
35710cc8ae86Sav 		}
35720cc8ae86Sav 	} else {
35730cc8ae86Sav 		return (1);
35740cc8ae86Sav 	}
35750cc8ae86Sav 
35760cc8ae86Sav 	return (0);
35770cc8ae86Sav }
35780cc8ae86Sav 
35790cc8ae86Sav /*
35800cc8ae86Sav  * mc_get_mem_sid -- get the DIMM serial-ID corresponding to the unum.
35810cc8ae86Sav  */
35820cc8ae86Sav int
35830cc8ae86Sav mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp)
35840cc8ae86Sav {
35850cc8ae86Sav 	int	i;
35860cc8ae86Sav 	int	ret = ENODEV;
35870cc8ae86Sav 	int	board;
35880cc8ae86Sav 	char	dname[MCOPL_MAX_DIMMNAME + 1];
35890cc8ae86Sav 	mc_opl_t *mcp;
35900cc8ae86Sav 
35910cc8ae86Sav 	MC_LOG("mc_get_mem_sid: unum=%s buflen=%d\n", unum, buflen);
35920cc8ae86Sav 	if ((ret = parse_unum_memory(unum, &board, dname)) != 0) {
35930cc8ae86Sav 		MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n",
35940cc8ae86Sav 		    unum, ret);
35950cc8ae86Sav 		return (EINVAL);
35960cc8ae86Sav 	}
35970cc8ae86Sav 
35980cc8ae86Sav 	if (board < 0) {
35990cc8ae86Sav 		MC_LOG("mc_get_mem_sid: Invalid board=%d dimm=%s\n",
36000cc8ae86Sav 		    board, dname);
36010cc8ae86Sav 		return (EINVAL);
36020cc8ae86Sav 	}
36030cc8ae86Sav 
36040cc8ae86Sav 	mutex_enter(&mcmutex);
36051039f409Sav 	/*
36061039f409Sav 	 * return ENOENT if we can not find the matching board.
36071039f409Sav 	 */
36081039f409Sav 	ret = ENOENT;
36090cc8ae86Sav 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
36100cc8ae86Sav 		if ((mcp = mc_instances[i]) == NULL)
36110cc8ae86Sav 			continue;
36120cc8ae86Sav 		mutex_enter(&mcp->mc_lock);
3613aeb241b2Sav 		if (mcp->mc_phys_board_num != board) {
3614aeb241b2Sav 			mutex_exit(&mcp->mc_lock);
3615aeb241b2Sav 			continue;
3616aeb241b2Sav 		}
3617aeb241b2Sav 		ret = mc_get_mem_sid_dimm(mcp, dname, buf, buflen, lenp);
3618aeb241b2Sav 		if (ret == 0) {
36190cc8ae86Sav 			mutex_exit(&mcp->mc_lock);
36200cc8ae86Sav 			break;
36210cc8ae86Sav 		}
36220cc8ae86Sav 		mutex_exit(&mcp->mc_lock);
36230cc8ae86Sav 	}
36240cc8ae86Sav 	mutex_exit(&mcmutex);
36250cc8ae86Sav 	return (ret);
36260cc8ae86Sav }
36270cc8ae86Sav 
36280cc8ae86Sav /*
36290cc8ae86Sav  * mc_get_mem_offset -- get the offset in a DIMM for a given physical address.
36300cc8ae86Sav  */
36310cc8ae86Sav int
36320cc8ae86Sav mc_get_mem_offset(uint64_t paddr, uint64_t *offp)
36330cc8ae86Sav {
36340cc8ae86Sav 	int		i;
36350cc8ae86Sav 	int		ret = ENODEV;
36360cc8ae86Sav 	mc_addr_t	maddr;
36370cc8ae86Sav 	mc_opl_t	*mcp;
36380cc8ae86Sav 
36390cc8ae86Sav 	mutex_enter(&mcmutex);
3640c964b0e6Sraghuram 	for (i = 0; ((i < OPL_MAX_BOARDS) && (ret != 0)); i++) {
36410cc8ae86Sav 		if ((mcp = mc_instances[i]) == NULL)
36420cc8ae86Sav 			continue;
36430cc8ae86Sav 		mutex_enter(&mcp->mc_lock);
36440cc8ae86Sav 		if (!pa_is_valid(mcp, paddr)) {
36450cc8ae86Sav 			mutex_exit(&mcp->mc_lock);
36460cc8ae86Sav 			continue;
36470cc8ae86Sav 		}
36480cc8ae86Sav 		if (pa_to_maddr(mcp, paddr, &maddr) == 0) {
36490cc8ae86Sav 			*offp = maddr.ma_dimm_addr;
36500cc8ae86Sav 			ret = 0;
36510cc8ae86Sav 		}
36520cc8ae86Sav 		mutex_exit(&mcp->mc_lock);
36530cc8ae86Sav 	}
36540cc8ae86Sav 	mutex_exit(&mcmutex);
36550cc8ae86Sav 	MC_LOG("mc_get_mem_offset: Ret=%d paddr=0x%lx offset=0x%lx\n",
36560cc8ae86Sav 	    ret, paddr, *offp);
36570cc8ae86Sav 	return (ret);
36580cc8ae86Sav }
36590cc8ae86Sav 
36600cc8ae86Sav /*
36610cc8ae86Sav  * dname_to_bankslot - Get the bank and slot number from the DIMM name.
36620cc8ae86Sav  */
36630cc8ae86Sav int
36640cc8ae86Sav dname_to_bankslot(char *dname, int *bank, int *slot)
36650cc8ae86Sav {
36660cc8ae86Sav 	int i;
36670cc8ae86Sav 	int tsz;
36680cc8ae86Sav 	char **tbl;
36690cc8ae86Sav 
367078ed97a7Sjl 	if (plat_model == MODEL_DC) {
367178ed97a7Sjl 		/*
367278ed97a7Sjl 		 * All DC models
367378ed97a7Sjl 		 */
36740cc8ae86Sav 		tbl = mc_dc_dimm_unum_table;
36750cc8ae86Sav 		tsz = OPL_MAX_DIMMS;
36760cc8ae86Sav 	} else {
367778ed97a7Sjl 		/*
367878ed97a7Sjl 		 * All FF and Ikkaku models
367978ed97a7Sjl 		 */
36800cc8ae86Sav 		tbl = mc_ff_dimm_unum_table;
36810cc8ae86Sav 		tsz = 2 * OPL_MAX_DIMMS;
36820cc8ae86Sav 	}
36830cc8ae86Sav 
36840cc8ae86Sav 	for (i = 0; i < tsz; i++) {
36850cc8ae86Sav 		if (strcmp(dname,  tbl[i]) == 0) {
36860cc8ae86Sav 			break;
36870cc8ae86Sav 		}
36880cc8ae86Sav 	}
36890cc8ae86Sav 	if (i == tsz) {
36900cc8ae86Sav 		return (1);
36910cc8ae86Sav 	}
36920cc8ae86Sav 	*bank = INDEX_TO_BANK(i);
36930cc8ae86Sav 	*slot = INDEX_TO_SLOT(i);
36940cc8ae86Sav 	return (0);
36950cc8ae86Sav }
36960cc8ae86Sav 
36970cc8ae86Sav /*
36980cc8ae86Sav  * mc_get_mem_addr -- get the physical address of a DIMM corresponding
36990cc8ae86Sav  * to the unum and sid.
37000cc8ae86Sav  */
37010cc8ae86Sav int
37020cc8ae86Sav mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr)
37030cc8ae86Sav {
37040cc8ae86Sav 	int	board;
37050cc8ae86Sav 	int	bank;
37060cc8ae86Sav 	int	slot;
37070cc8ae86Sav 	int	i;
37080cc8ae86Sav 	int	ret = ENODEV;
37090cc8ae86Sav 	char	dname[MCOPL_MAX_DIMMNAME + 1];
37100cc8ae86Sav 	mc_addr_t maddr;
37110cc8ae86Sav 	mc_opl_t *mcp;
37120cc8ae86Sav 
37130cc8ae86Sav 	MC_LOG("mc_get_mem_addr: unum=%s sid=%s offset=0x%lx\n",
37140cc8ae86Sav 	    unum, sid, offset);
37150cc8ae86Sav 	if (parse_unum_memory(unum, &board, dname) != 0) {
37160cc8ae86Sav 		MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n",
37170cc8ae86Sav 		    unum, ret);
37180cc8ae86Sav 		return (EINVAL);
37190cc8ae86Sav 	}
37200cc8ae86Sav 
37210cc8ae86Sav 	if (board < 0) {
37220cc8ae86Sav 		MC_LOG("mc_get_mem_addr: Invalid board=%d dimm=%s\n",
37230cc8ae86Sav 		    board, dname);
37240cc8ae86Sav 		return (EINVAL);
37250cc8ae86Sav 	}
37260cc8ae86Sav 
37270cc8ae86Sav 	mutex_enter(&mcmutex);
37280cc8ae86Sav 	for (i = 0; i < OPL_MAX_BOARDS; i++) {
37290cc8ae86Sav 		if ((mcp = mc_instances[i]) == NULL)
37300cc8ae86Sav 			continue;
37310cc8ae86Sav 		mutex_enter(&mcp->mc_lock);
3732aeb241b2Sav 		if (mcp->mc_phys_board_num != board) {
37330cc8ae86Sav 			mutex_exit(&mcp->mc_lock);
37340cc8ae86Sav 			continue;
37350cc8ae86Sav 		}
37360cc8ae86Sav 
37370cc8ae86Sav 		ret = dname_to_bankslot(dname, &bank, &slot);
37380cc8ae86Sav 		MC_LOG("mc_get_mem_addr: bank=%d slot=%d\n", bank, slot);
37390cc8ae86Sav 		if (ret != 0) {
37400cc8ae86Sav 			MC_LOG("mc_get_mem_addr: dname_to_bankslot failed\n");
37410cc8ae86Sav 			ret = ENODEV;
37420cc8ae86Sav 		} else {
3743aeb241b2Sav 			maddr.ma_bd = mcp->mc_board_num;
37440cc8ae86Sav 			maddr.ma_bank =  bank;
37450cc8ae86Sav 			maddr.ma_dimm_addr = offset;
37460cc8ae86Sav 			ret = mcaddr_to_pa(mcp, &maddr, paddr);
37470cc8ae86Sav 			if (ret != 0) {
37480cc8ae86Sav 				MC_LOG("mc_get_mem_addr: "
37490cc8ae86Sav 				    "mcaddr_to_pa failed\n");
37500cc8ae86Sav 				ret = ENODEV;
37510b240fcdSwh 				mutex_exit(&mcp->mc_lock);
37520b240fcdSwh 				continue;
37530cc8ae86Sav 			}
3754aeb241b2Sav 			mutex_exit(&mcp->mc_lock);
3755aeb241b2Sav 			break;
37560cc8ae86Sav 		}
37570cc8ae86Sav 		mutex_exit(&mcp->mc_lock);
37580cc8ae86Sav 	}
37590cc8ae86Sav 	mutex_exit(&mcmutex);
37600cc8ae86Sav 	MC_LOG("mc_get_mem_addr: Ret=%d, Paddr=0x%lx\n", ret, *paddr);
37610cc8ae86Sav 	return (ret);
37620cc8ae86Sav }
37630cc8ae86Sav 
37640cc8ae86Sav static void
37650cc8ae86Sav mc_free_dimm_list(mc_dimm_info_t *d)
37660cc8ae86Sav {
37670cc8ae86Sav 	mc_dimm_info_t *next;
37680cc8ae86Sav 
37690cc8ae86Sav 	while (d != NULL) {
37700cc8ae86Sav 		next = d->md_next;
37710cc8ae86Sav 		kmem_free(d, sizeof (mc_dimm_info_t));
37720cc8ae86Sav 		d = next;
37730cc8ae86Sav 	}
37740cc8ae86Sav }
37750cc8ae86Sav 
37760cc8ae86Sav /*
37770cc8ae86Sav  * mc_get_dimm_list -- get the list of dimms with serial-id info
37780cc8ae86Sav  * from the SP.
37790cc8ae86Sav  */
37800cc8ae86Sav mc_dimm_info_t *
37810cc8ae86Sav mc_get_dimm_list(mc_opl_t *mcp)
37820cc8ae86Sav {
37830cc8ae86Sav 	uint32_t	bufsz;
37840cc8ae86Sav 	uint32_t	maxbufsz;
37850cc8ae86Sav 	int		ret;
37860cc8ae86Sav 	int		sexp;
37870cc8ae86Sav 	board_dimm_info_t *bd_dimmp;
37880cc8ae86Sav 	mc_dimm_info_t	*dimm_list = NULL;
37890cc8ae86Sav 
37900cc8ae86Sav 	maxbufsz = bufsz = sizeof (board_dimm_info_t) +
37910cc8ae86Sav 	    ((MCOPL_MAX_DIMMNAME +  MCOPL_MAX_SERIAL +
37920cc8ae86Sav 	    MCOPL_MAX_PARTNUM) * OPL_MAX_DIMMS);
37930cc8ae86Sav 
37940cc8ae86Sav 	bd_dimmp = (board_dimm_info_t *)kmem_alloc(bufsz, KM_SLEEP);
37950cc8ae86Sav 	ret = scf_get_dimminfo(mcp->mc_board_num, (void *)bd_dimmp, &bufsz);
37960cc8ae86Sav 
37970cc8ae86Sav 	MC_LOG("mc_get_dimm_list:  scf_service_getinfo returned=%d\n", ret);
37980cc8ae86Sav 	if (ret == 0) {
37990cc8ae86Sav 		sexp = sizeof (board_dimm_info_t) +
38000cc8ae86Sav 		    ((bd_dimmp->bd_dnamesz +  bd_dimmp->bd_serialsz +
38010cc8ae86Sav 		    bd_dimmp->bd_partnumsz) * bd_dimmp->bd_numdimms);
38020cc8ae86Sav 
38030cc8ae86Sav 		if ((bd_dimmp->bd_version == OPL_DIMM_INFO_VERSION) &&
38040cc8ae86Sav 		    (bd_dimmp->bd_dnamesz <= MCOPL_MAX_DIMMNAME) &&
38050cc8ae86Sav 		    (bd_dimmp->bd_serialsz <= MCOPL_MAX_SERIAL) &&
38060cc8ae86Sav 		    (bd_dimmp->bd_partnumsz <= MCOPL_MAX_PARTNUM) &&
38070cc8ae86Sav 		    (sexp <= bufsz)) {
38080cc8ae86Sav 
38090cc8ae86Sav #ifdef DEBUG
38100cc8ae86Sav 			if (oplmc_debug)
38110cc8ae86Sav 				mc_dump_dimm_info(bd_dimmp);
38120cc8ae86Sav #endif
38130cc8ae86Sav 			dimm_list = mc_prepare_dimmlist(bd_dimmp);
38140cc8ae86Sav 
38150cc8ae86Sav 		} else {
38160cc8ae86Sav 			cmn_err(CE_WARN, "DIMM info version mismatch\n");
38170cc8ae86Sav 		}
38180cc8ae86Sav 	}
38190cc8ae86Sav 	kmem_free(bd_dimmp, maxbufsz);
382007d06da5SSurya Prakki 	MC_LOG("mc_get_dimm_list: dimmlist=0x%p\n", (void *)dimm_list);
38210cc8ae86Sav 	return (dimm_list);
38220cc8ae86Sav }
38230cc8ae86Sav 
38240cc8ae86Sav /*
38251039f409Sav  * mc_prepare_dimmlist - Prepare the dimm list from the information
38261039f409Sav  * received from the SP.
38270cc8ae86Sav  */
38280cc8ae86Sav mc_dimm_info_t *
38290cc8ae86Sav mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp)
38300cc8ae86Sav {
38310cc8ae86Sav 	char	*dimm_name;
38320cc8ae86Sav 	char	*serial;
38330cc8ae86Sav 	char	*part;
38340cc8ae86Sav 	int	dimm;
38350cc8ae86Sav 	int	dnamesz = bd_dimmp->bd_dnamesz;
38360cc8ae86Sav 	int	sersz = bd_dimmp->bd_serialsz;
38370cc8ae86Sav 	int	partsz = bd_dimmp->bd_partnumsz;
38380cc8ae86Sav 	mc_dimm_info_t	*dimm_list = NULL;
38390cc8ae86Sav 	mc_dimm_info_t	*d;
38400cc8ae86Sav 
38410cc8ae86Sav 	dimm_name = (char *)(bd_dimmp + 1);
38420cc8ae86Sav 	for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) {
38430cc8ae86Sav 
38440cc8ae86Sav 		d = (mc_dimm_info_t *)kmem_alloc(sizeof (mc_dimm_info_t),
38450cc8ae86Sav 		    KM_SLEEP);
3846ad59b69dSbm 
3847ad59b69dSbm 		bcopy(dimm_name, d->md_dimmname, dnamesz);
3848ad59b69dSbm 		d->md_dimmname[dnamesz] = 0;
3849ad59b69dSbm 
38500cc8ae86Sav 		serial = dimm_name + dnamesz;
3851ad59b69dSbm 		bcopy(serial, d->md_serial, sersz);
3852ad59b69dSbm 		d->md_serial[sersz] = 0;
3853ad59b69dSbm 
38540cc8ae86Sav 		part = serial + sersz;
3855ad59b69dSbm 		bcopy(part, d->md_partnum, partsz);
3856ad59b69dSbm 		d->md_partnum[partsz] = 0;
38570cc8ae86Sav 
38580cc8ae86Sav 		d->md_next = dimm_list;
38590cc8ae86Sav 		dimm_list = d;
38600cc8ae86Sav 		dimm_name = part + partsz;
38610cc8ae86Sav 	}
38620cc8ae86Sav 	return (dimm_list);
38630cc8ae86Sav }
38640cc8ae86Sav 
38650b240fcdSwh static int
38660b240fcdSwh mc_get_mem_fmri(mc_flt_page_t *fpag, char **unum)
38670b240fcdSwh {
38680b240fcdSwh 	if (fpag->fmri_addr == 0 || fpag->fmri_sz > MEM_FMRI_MAX_BUFSIZE)
38690b240fcdSwh 		return (EINVAL);
38700b240fcdSwh 
38710b240fcdSwh 	*unum = kmem_alloc(fpag->fmri_sz, KM_SLEEP);
38720b240fcdSwh 	if (copyin((void *)fpag->fmri_addr, *unum, fpag->fmri_sz) != 0) {
38730b240fcdSwh 		kmem_free(*unum, fpag->fmri_sz);
38740b240fcdSwh 		return (EFAULT);
38750b240fcdSwh 	}
38760b240fcdSwh 	return (0);
38770b240fcdSwh }
38780b240fcdSwh 
38790b240fcdSwh static int
38800b240fcdSwh mc_scf_log_event(mc_flt_page_t *flt_pag)
38810b240fcdSwh {
38820b240fcdSwh 	mc_opl_t *mcp;
38830b240fcdSwh 	int board, bank, slot;
38840b240fcdSwh 	int len, rv = 0;
38850b240fcdSwh 	char *unum, *sid;
38860b240fcdSwh 	char dname[MCOPL_MAX_DIMMNAME + 1];
38870b240fcdSwh 	size_t sid_sz;
38880b240fcdSwh 	uint64_t pa;
38890b240fcdSwh 	mc_flt_stat_t flt_stat;
38900b240fcdSwh 
38910b240fcdSwh 	if ((sid_sz = cpu_get_name_bufsize()) == 0)
38920b240fcdSwh 		return (ENOTSUP);
38930b240fcdSwh 
38940b240fcdSwh 	if ((rv = mc_get_mem_fmri(flt_pag, &unum)) != 0) {
38950b240fcdSwh 		MC_LOG("mc_scf_log_event: mc_get_mem_fmri failed\n");
38960b240fcdSwh 		return (rv);
38970b240fcdSwh 	}
38980b240fcdSwh 
38990b240fcdSwh 	sid = kmem_zalloc(sid_sz, KM_SLEEP);
39000b240fcdSwh 
39010b240fcdSwh 	if ((rv = mc_get_mem_sid(unum, sid, sid_sz, &len)) != 0) {
39020b240fcdSwh 		MC_LOG("mc_scf_log_event: mc_get_mem_sid failed\n");
39030b240fcdSwh 		goto out;
39040b240fcdSwh 	}
39050b240fcdSwh 
39060b240fcdSwh 	if ((rv = mc_get_mem_addr(unum, sid, (uint64_t)flt_pag->err_add,
39070b240fcdSwh 	    &pa)) != 0) {
39080b240fcdSwh 		MC_LOG("mc_scf_log_event: mc_get_mem_addr failed\n");
39090b240fcdSwh 		goto out;
39100b240fcdSwh 	}
39110b240fcdSwh 
39120b240fcdSwh 	if (parse_unum_memory(unum, &board, dname) != 0) {
39130b240fcdSwh 		MC_LOG("mc_scf_log_event: parse_unum_memory failed\n");
39140b240fcdSwh 		rv = EINVAL;
39150b240fcdSwh 		goto out;
39160b240fcdSwh 	}
39170b240fcdSwh 
39180b240fcdSwh 	if (board < 0) {
39190b240fcdSwh 		MC_LOG("mc_scf_log_event: Invalid board=%d dimm=%s\n",
39200b240fcdSwh 		    board, dname);
39210b240fcdSwh 		rv = EINVAL;
39220b240fcdSwh 		goto out;
39230b240fcdSwh 	}
39240b240fcdSwh 
39250b240fcdSwh 	if (dname_to_bankslot(dname, &bank, &slot) != 0) {
39260b240fcdSwh 		MC_LOG("mc_scf_log_event: dname_to_bankslot failed\n");
39270b240fcdSwh 		rv = EINVAL;
39280b240fcdSwh 		goto out;
39290b240fcdSwh 	}
39300b240fcdSwh 
39310b240fcdSwh 	mutex_enter(&mcmutex);
39320b240fcdSwh 
39330b240fcdSwh 	flt_stat.mf_err_add = flt_pag->err_add;
39340b240fcdSwh 	flt_stat.mf_err_log = flt_pag->err_log;
39350b240fcdSwh 	flt_stat.mf_flt_paddr = pa;
39360b240fcdSwh 
39370b240fcdSwh 	if ((mcp = mc_pa_to_mcp(pa)) == NULL) {
39380b240fcdSwh 		mutex_exit(&mcmutex);
39390b240fcdSwh 		MC_LOG("mc_scf_log_event: invalid pa\n");
39400b240fcdSwh 		rv = EINVAL;
39410b240fcdSwh 		goto out;
39420b240fcdSwh 	}
39430b240fcdSwh 
39440b240fcdSwh 	MC_LOG("mc_scf_log_event: DIMM%s, /LSB%d/B%d/%x, pa %lx elog %x\n",
39450b240fcdSwh 	    unum, mcp->mc_board_num, bank, flt_pag->err_add, pa,
39460b240fcdSwh 	    flt_pag->err_log);
39470b240fcdSwh 
39480b240fcdSwh 	mutex_enter(&mcp->mc_lock);
39490b240fcdSwh 
39500b240fcdSwh 	if (!pa_is_valid(mcp, pa)) {
39510b240fcdSwh 		mutex_exit(&mcp->mc_lock);
39520b240fcdSwh 		mutex_exit(&mcmutex);
39530b240fcdSwh 		rv = EINVAL;
39540b240fcdSwh 		goto out;
39550b240fcdSwh 	}
39560b240fcdSwh 
39570b240fcdSwh 	rv = 0;
39580b240fcdSwh 
39590b240fcdSwh 	mc_queue_scf_log(mcp, &flt_stat, bank);
39600b240fcdSwh 
39610b240fcdSwh 	mutex_exit(&mcp->mc_lock);
39620b240fcdSwh 	mutex_exit(&mcmutex);
39630b240fcdSwh 
39640b240fcdSwh out:
39650b240fcdSwh 	kmem_free(unum, flt_pag->fmri_sz);
39660b240fcdSwh 	kmem_free(sid, sid_sz);
39670b240fcdSwh 
39680b240fcdSwh 	return (rv);
39690b240fcdSwh }
39700b240fcdSwh 
39710cc8ae86Sav #ifdef DEBUG
39720cc8ae86Sav void
39730cc8ae86Sav mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz)
39740cc8ae86Sav {
39750cc8ae86Sav 	char dname[MCOPL_MAX_DIMMNAME + 1];
39760cc8ae86Sav 	char serial[MCOPL_MAX_SERIAL + 1];
39770cc8ae86Sav 	char part[ MCOPL_MAX_PARTNUM + 1];
39780cc8ae86Sav 	char *b;
39790cc8ae86Sav 
39800cc8ae86Sav 	b = buf;
3981ad59b69dSbm 	bcopy(b, dname, dnamesz);
3982ad59b69dSbm 	dname[dnamesz] = 0;
3983ad59b69dSbm 
39840cc8ae86Sav 	b += dnamesz;
3985ad59b69dSbm 	bcopy(b, serial, serialsz);
3986ad59b69dSbm 	serial[serialsz] = 0;
3987ad59b69dSbm 
39880cc8ae86Sav 	b += serialsz;
3989ad59b69dSbm 	bcopy(b, part, partnumsz);
3990ad59b69dSbm 	part[partnumsz] = 0;
3991ad59b69dSbm 
39920cc8ae86Sav 	printf("DIMM=%s  Serial=%s PartNum=%s\n", dname, serial, part);
39930cc8ae86Sav }
39940cc8ae86Sav 
39950cc8ae86Sav void
39960cc8ae86Sav mc_dump_dimm_info(board_dimm_info_t *bd_dimmp)
39970cc8ae86Sav {
39980cc8ae86Sav 	int	dimm;
39990cc8ae86Sav 	int	dnamesz = bd_dimmp->bd_dnamesz;
40000cc8ae86Sav 	int	sersz = bd_dimmp->bd_serialsz;
40010cc8ae86Sav 	int	partsz = bd_dimmp->bd_partnumsz;
40020cc8ae86Sav 	char	*buf;
40030cc8ae86Sav 
40040cc8ae86Sav 	printf("Version=%d Board=%02d DIMMs=%d NameSize=%d "
40050cc8ae86Sav 	    "SerialSize=%d PartnumSize=%d\n", bd_dimmp->bd_version,
40060cc8ae86Sav 	    bd_dimmp->bd_boardnum, bd_dimmp->bd_numdimms, bd_dimmp->bd_dnamesz,
40070cc8ae86Sav 	    bd_dimmp->bd_serialsz, bd_dimmp->bd_partnumsz);
40080cc8ae86Sav 	printf("======================================================\n");
40090cc8ae86Sav 
40100cc8ae86Sav 	buf = (char *)(bd_dimmp + 1);
40110cc8ae86Sav 	for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) {
40120cc8ae86Sav 		mc_dump_dimm(buf, dnamesz, sersz, partsz);
40130cc8ae86Sav 		buf += dnamesz + sersz + partsz;
40140cc8ae86Sav 	}
40150cc8ae86Sav 	printf("======================================================\n");
40160cc8ae86Sav }
40170cc8ae86Sav 
40180cc8ae86Sav 
40190cc8ae86Sav /* ARGSUSED */
40200cc8ae86Sav static int
40210cc8ae86Sav mc_ioctl_debug(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
40220cc8ae86Sav 	int *rvalp)
40230cc8ae86Sav {
40240b240fcdSwh 	caddr_t	buf, kbuf;
40250cc8ae86Sav 	uint64_t pa;
40260cc8ae86Sav 	int rv = 0;
40270cc8ae86Sav 	int i;
40280cc8ae86Sav 	uint32_t flags;
40290cc8ae86Sav 	static uint32_t offset = 0;
40300cc8ae86Sav 
40310cc8ae86Sav 
40320cc8ae86Sav 	flags = (cmd >> 4) & 0xfffffff;
40330cc8ae86Sav 
40340cc8ae86Sav 	cmd &= 0xf;
40350cc8ae86Sav 
40360cc8ae86Sav 	MC_LOG("mc_ioctl(cmd = %x, flags = %x)\n", cmd, flags);
40370cc8ae86Sav 
40380cc8ae86Sav 	if (arg != NULL) {
40390cc8ae86Sav 		if (ddi_copyin((const void *)arg, (void *)&pa,
4040d8a0cca9Swh 		    sizeof (uint64_t), 0) < 0) {
40410cc8ae86Sav 			rv = EFAULT;
40420cc8ae86Sav 			return (rv);
40430cc8ae86Sav 		}
40440cc8ae86Sav 		buf = NULL;
40450cc8ae86Sav 	} else {
40460cc8ae86Sav 		buf = (caddr_t)kmem_alloc(PAGESIZE, KM_SLEEP);
40470cc8ae86Sav 
40480cc8ae86Sav 		pa = va_to_pa(buf);
40490cc8ae86Sav 		pa += offset;
40500cc8ae86Sav 
40510cc8ae86Sav 		offset += 64;
40520cc8ae86Sav 		if (offset >= PAGESIZE)
40530cc8ae86Sav 			offset = 0;
40540cc8ae86Sav 	}
40550cc8ae86Sav 
40560cc8ae86Sav 	switch (cmd) {
40570cc8ae86Sav 	case MCI_CE:
405807d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_INTERMITTENT_CE, pa, flags);
40590cc8ae86Sav 		break;
40600cc8ae86Sav 	case MCI_PERM_CE:
406107d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_PERMANENT_CE, pa, flags);
40620cc8ae86Sav 		break;
40630cc8ae86Sav 	case MCI_UE:
406407d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_UE, pa, flags);
40650cc8ae86Sav 		break;
40660cc8ae86Sav 	case MCI_M_CE:
406707d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_INTERMITTENT_MCE, pa, flags);
40680cc8ae86Sav 		break;
40690cc8ae86Sav 	case MCI_M_PCE:
407007d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_PERMANENT_MCE, pa, flags);
40710cc8ae86Sav 		break;
40720cc8ae86Sav 	case MCI_M_UE:
407307d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_MUE, pa, flags);
40740cc8ae86Sav 		break;
40750cc8ae86Sav 	case MCI_CMP:
407607d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_CMPE, pa, flags);
40770cc8ae86Sav 		break;
40780cc8ae86Sav 	case MCI_NOP:
407907d06da5SSurya Prakki 		(void) mc_inject_error(MC_INJECT_NOP, pa, flags); break;
40800cc8ae86Sav 	case MCI_SHOW_ALL:
40810cc8ae86Sav 		mc_debug_show_all = 1;
40820cc8ae86Sav 		break;
40830cc8ae86Sav 	case MCI_SHOW_NONE:
40840cc8ae86Sav 		mc_debug_show_all = 0;
40850cc8ae86Sav 		break;
40860cc8ae86Sav 	case MCI_ALLOC:
40870cc8ae86Sav 		/*
40880cc8ae86Sav 		 * just allocate some kernel memory and never free it
40890cc8ae86Sav 		 * 512 MB seems to be the maximum size supported.
40900cc8ae86Sav 		 */
40910cc8ae86Sav 		cmn_err(CE_NOTE, "Allocating kmem %d MB\n", flags * 512);
40920cc8ae86Sav 		for (i = 0; i < flags; i++) {
40930b240fcdSwh 			kbuf = kmem_alloc(512 * 1024 * 1024, KM_SLEEP);
40940cc8ae86Sav 			cmn_err(CE_NOTE, "kmem buf %llx PA %llx\n",
40950b240fcdSwh 			    (u_longlong_t)kbuf, (u_longlong_t)va_to_pa(kbuf));
40960cc8ae86Sav 		}
40970cc8ae86Sav 		break;
40980cc8ae86Sav 	case MCI_SUSPEND:
40990cc8ae86Sav 		(void) opl_mc_suspend();
41000cc8ae86Sav 		break;
41010cc8ae86Sav 	case MCI_RESUME:
41020cc8ae86Sav 		(void) opl_mc_resume();
41030cc8ae86Sav 		break;
41040cc8ae86Sav 	default:
41050cc8ae86Sav 		rv = ENXIO;
41060cc8ae86Sav 	}
41070b240fcdSwh 	if (buf)
41080b240fcdSwh 		kmem_free(buf, PAGESIZE);
41090b240fcdSwh 
41100cc8ae86Sav 	return (rv);
41110cc8ae86Sav }
41120cc8ae86Sav 
41130cc8ae86Sav #endif /* DEBUG */
4114