125cf1a30Sjl /* 225cf1a30Sjl * CDDL HEADER START 325cf1a30Sjl * 425cf1a30Sjl * The contents of this file are subject to the terms of the 525cf1a30Sjl * Common Development and Distribution License (the "License"). 625cf1a30Sjl * You may not use this file except in compliance with the License. 725cf1a30Sjl * 825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 925cf1a30Sjl * or http://www.opensolaris.org/os/licensing. 1025cf1a30Sjl * See the License for the specific language governing permissions 1125cf1a30Sjl * and limitations under the License. 1225cf1a30Sjl * 1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each 1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the 1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying 1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner] 1825cf1a30Sjl * 1925cf1a30Sjl * CDDL HEADER END 2025cf1a30Sjl */ 211e2e7a75Shuah /* 22ee1dce25Sjimand * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 231e2e7a75Shuah * Use is subject to license terms. 241e2e7a75Shuah */ 2525cf1a30Sjl /* 2678ed97a7Sjl * All Rights Reserved, Copyright (c) FUJITSU LIMITED 2008 2725cf1a30Sjl */ 2825cf1a30Sjl 2925cf1a30Sjl 3025cf1a30Sjl #include <sys/types.h> 3125cf1a30Sjl #include <sys/sysmacros.h> 3225cf1a30Sjl #include <sys/conf.h> 3325cf1a30Sjl #include <sys/modctl.h> 3425cf1a30Sjl #include <sys/stat.h> 3525cf1a30Sjl #include <sys/async.h> 361e2e7a75Shuah #include <sys/machcpuvar.h> 3725cf1a30Sjl #include <sys/machsystm.h> 380cc8ae86Sav #include <sys/promif.h> 3925cf1a30Sjl #include <sys/ksynch.h> 4025cf1a30Sjl #include <sys/ddi.h> 4125cf1a30Sjl #include <sys/sunddi.h> 42d8a0cca9Swh #include <sys/sunndi.h> 4325cf1a30Sjl #include <sys/ddifm.h> 4425cf1a30Sjl #include <sys/fm/protocol.h> 4525cf1a30Sjl #include <sys/fm/util.h> 4625cf1a30Sjl #include <sys/kmem.h> 4725cf1a30Sjl #include <sys/fm/io/opl_mc_fm.h> 4825cf1a30Sjl #include <sys/memlist.h> 4925cf1a30Sjl #include <sys/param.h> 500cc8ae86Sav #include <sys/disp.h> 5125cf1a30Sjl #include <vm/page.h> 5225cf1a30Sjl #include <sys/mc-opl.h> 530cc8ae86Sav #include <sys/opl.h> 540cc8ae86Sav #include <sys/opl_dimm.h> 550cc8ae86Sav #include <sys/scfd/scfostoescf.h> 56cfb9e062Shyw #include <sys/cpu_module.h> 57cfb9e062Shyw #include <vm/seg_kmem.h> 58cfb9e062Shyw #include <sys/vmem.h> 59cfb9e062Shyw #include <vm/hat_sfmmu.h> 60cfb9e062Shyw #include <sys/vmsystm.h> 61738dd194Shyw #include <sys/membar.h> 620b240fcdSwh #include <sys/mem.h> 6325cf1a30Sjl 6425cf1a30Sjl /* 6525cf1a30Sjl * Function prototypes 6625cf1a30Sjl */ 6725cf1a30Sjl static int mc_open(dev_t *, int, int, cred_t *); 6825cf1a30Sjl static int mc_close(dev_t, int, int, cred_t *); 6925cf1a30Sjl static int mc_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 7025cf1a30Sjl static int mc_attach(dev_info_t *, ddi_attach_cmd_t); 7125cf1a30Sjl static int mc_detach(dev_info_t *, ddi_detach_cmd_t); 7225cf1a30Sjl 730cc8ae86Sav static int mc_poll_init(void); 740cc8ae86Sav static void mc_poll_fini(void); 7525cf1a30Sjl static int mc_board_add(mc_opl_t *mcp); 7625cf1a30Sjl static int mc_board_del(mc_opl_t *mcp); 7725cf1a30Sjl static int mc_suspend(mc_opl_t *mcp, uint32_t flag); 7825cf1a30Sjl static int mc_resume(mc_opl_t *mcp, uint32_t flag); 790cc8ae86Sav int opl_mc_suspend(void); 800cc8ae86Sav int opl_mc_resume(void); 8125cf1a30Sjl 8225cf1a30Sjl static void insert_mcp(mc_opl_t *mcp); 8325cf1a30Sjl static void delete_mcp(mc_opl_t *mcp); 8425cf1a30Sjl 8525cf1a30Sjl static int pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr); 8625cf1a30Sjl 87738dd194Shyw static int mc_rangecheck_pa(mc_opl_t *mcp, uint64_t pa); 8825cf1a30Sjl 8925cf1a30Sjl int mc_get_mem_unum(int, uint64_t, char *, int, int *); 900cc8ae86Sav int mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr); 910cc8ae86Sav int mc_get_mem_offset(uint64_t paddr, uint64_t *offp); 920cc8ae86Sav int mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp); 930cc8ae86Sav int mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 940cc8ae86Sav int buflen, int *lenp); 950cc8ae86Sav mc_dimm_info_t *mc_get_dimm_list(mc_opl_t *mcp); 960cc8ae86Sav mc_dimm_info_t *mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp); 970cc8ae86Sav int mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, int bank, 980cc8ae86Sav uint32_t mf_type, uint32_t d_slot); 990cc8ae86Sav static void mc_free_dimm_list(mc_dimm_info_t *d); 10025cf1a30Sjl static void mc_get_mlist(mc_opl_t *); 1010cc8ae86Sav static void mc_polling(void); 1020cc8ae86Sav static int mc_opl_get_physical_board(int); 1030cc8ae86Sav 104601c2e1eSdhain static void mc_clear_rewrite(mc_opl_t *mcp, int i); 105601c2e1eSdhain static void mc_set_rewrite(mc_opl_t *mcp, int bank, uint32_t addr, int state); 1060b240fcdSwh static int mc_scf_log_event(mc_flt_page_t *flt_pag); 107601c2e1eSdhain 1080cc8ae86Sav #ifdef DEBUG 1090cc8ae86Sav static int mc_ioctl_debug(dev_t, int, intptr_t, int, cred_t *, int *); 1100cc8ae86Sav void mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz); 1110cc8ae86Sav void mc_dump_dimm_info(board_dimm_info_t *bd_dimmp); 1120cc8ae86Sav #endif 11325cf1a30Sjl 11425cf1a30Sjl #pragma weak opl_get_physical_board 11525cf1a30Sjl extern int opl_get_physical_board(int); 1160cc8ae86Sav extern int plat_max_boards(void); 11725cf1a30Sjl 11825cf1a30Sjl /* 11925cf1a30Sjl * Configuration data structures 12025cf1a30Sjl */ 12125cf1a30Sjl static struct cb_ops mc_cb_ops = { 12225cf1a30Sjl mc_open, /* open */ 12325cf1a30Sjl mc_close, /* close */ 12425cf1a30Sjl nulldev, /* strategy */ 12525cf1a30Sjl nulldev, /* print */ 12625cf1a30Sjl nodev, /* dump */ 12725cf1a30Sjl nulldev, /* read */ 12825cf1a30Sjl nulldev, /* write */ 12925cf1a30Sjl mc_ioctl, /* ioctl */ 13025cf1a30Sjl nodev, /* devmap */ 13125cf1a30Sjl nodev, /* mmap */ 13225cf1a30Sjl nodev, /* segmap */ 13325cf1a30Sjl nochpoll, /* poll */ 13425cf1a30Sjl ddi_prop_op, /* cb_prop_op */ 13525cf1a30Sjl 0, /* streamtab */ 13625cf1a30Sjl D_MP | D_NEW | D_HOTPLUG, /* Driver compatibility flag */ 13725cf1a30Sjl CB_REV, /* rev */ 13825cf1a30Sjl nodev, /* cb_aread */ 13925cf1a30Sjl nodev /* cb_awrite */ 14025cf1a30Sjl }; 14125cf1a30Sjl 14225cf1a30Sjl static struct dev_ops mc_ops = { 14325cf1a30Sjl DEVO_REV, /* rev */ 14425cf1a30Sjl 0, /* refcnt */ 14525cf1a30Sjl ddi_getinfo_1to1, /* getinfo */ 14625cf1a30Sjl nulldev, /* identify */ 14725cf1a30Sjl nulldev, /* probe */ 14825cf1a30Sjl mc_attach, /* attach */ 14925cf1a30Sjl mc_detach, /* detach */ 15025cf1a30Sjl nulldev, /* reset */ 15125cf1a30Sjl &mc_cb_ops, /* cb_ops */ 15225cf1a30Sjl (struct bus_ops *)0, /* bus_ops */ 153*19397407SSherry Moore nulldev, /* power */ 154*19397407SSherry Moore ddi_quiesce_not_needed, /* quiesce */ 15525cf1a30Sjl }; 15625cf1a30Sjl 15725cf1a30Sjl /* 15825cf1a30Sjl * Driver globals 15925cf1a30Sjl */ 16025cf1a30Sjl 1610cc8ae86Sav static enum { 16278ed97a7Sjl MODEL_FF1, 16378ed97a7Sjl MODEL_FF2, 16478ed97a7Sjl MODEL_DC, 16578ed97a7Sjl MODEL_IKKAKU 1660cc8ae86Sav } plat_model = MODEL_DC; /* The default behaviour is DC */ 1670cc8ae86Sav 1680cc8ae86Sav static struct plat_model_names { 1690cc8ae86Sav const char *unit_name; 1700cc8ae86Sav const char *mem_name; 1710cc8ae86Sav } model_names[] = { 1720cc8ae86Sav { "MBU_A", "MEMB" }, 1730cc8ae86Sav { "MBU_B", "MEMB" }, 17478ed97a7Sjl { "CMU", "" }, 17578ed97a7Sjl { "MBU_A", "" } 1760cc8ae86Sav }; 17725cf1a30Sjl 1780cc8ae86Sav /* 1790cc8ae86Sav * The DIMM Names for DC platform. 1800cc8ae86Sav * The index into this table is made up of (bank, dslot), 1810cc8ae86Sav * Where dslot occupies bits 0-1 and bank occupies 2-4. 1820cc8ae86Sav */ 1830cc8ae86Sav static char *mc_dc_dimm_unum_table[OPL_MAX_DIMMS] = { 1840cc8ae86Sav /* --------CMUnn----------- */ 1850cc8ae86Sav /* --CS0-----|--CS1------ */ 1860cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 187c964b0e6Sraghuram "03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */ 188c964b0e6Sraghuram "13A", "12A", "13B", "12B", /* Bank 1 (MAC 0 bank 1) */ 189c964b0e6Sraghuram "23A", "22A", "23B", "22B", /* Bank 2 (MAC 1 bank 0) */ 190c964b0e6Sraghuram "33A", "32A", "33B", "32B", /* Bank 3 (MAC 1 bank 1) */ 191c964b0e6Sraghuram "01A", "00A", "01B", "00B", /* Bank 4 (MAC 2 bank 0) */ 192c964b0e6Sraghuram "11A", "10A", "11B", "10B", /* Bank 5 (MAC 2 bank 1) */ 193c964b0e6Sraghuram "21A", "20A", "21B", "20B", /* Bank 6 (MAC 3 bank 0) */ 194c964b0e6Sraghuram "31A", "30A", "31B", "30B" /* Bank 7 (MAC 3 bank 1) */ 1950cc8ae86Sav }; 1960cc8ae86Sav 1970cc8ae86Sav /* 19878ed97a7Sjl * The DIMM Names for FF1/FF2/IKKAKU platforms. 1990cc8ae86Sav * The index into this table is made up of (board, bank, dslot), 2000cc8ae86Sav * Where dslot occupies bits 0-1, bank occupies 2-4 and 2010cc8ae86Sav * board occupies the bit 5. 2020cc8ae86Sav */ 2030cc8ae86Sav static char *mc_ff_dimm_unum_table[2 * OPL_MAX_DIMMS] = { 2040cc8ae86Sav /* --------CMU0---------- */ 2050cc8ae86Sav /* --CS0-----|--CS1------ */ 2060cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 207c964b0e6Sraghuram "03A", "02A", "03B", "02B", /* Bank 0 (MAC 0 bank 0) */ 208c964b0e6Sraghuram "01A", "00A", "01B", "00B", /* Bank 1 (MAC 0 bank 1) */ 209c964b0e6Sraghuram "13A", "12A", "13B", "12B", /* Bank 2 (MAC 1 bank 0) */ 210c964b0e6Sraghuram "11A", "10A", "11B", "10B", /* Bank 3 (MAC 1 bank 1) */ 211c964b0e6Sraghuram "23A", "22A", "23B", "22B", /* Bank 4 (MAC 2 bank 0) */ 212c964b0e6Sraghuram "21A", "20A", "21B", "20B", /* Bank 5 (MAC 2 bank 1) */ 213c964b0e6Sraghuram "33A", "32A", "33B", "32B", /* Bank 6 (MAC 3 bank 0) */ 214c964b0e6Sraghuram "31A", "30A", "31B", "30B", /* Bank 7 (MAC 3 bank 1) */ 2150cc8ae86Sav /* --------CMU1---------- */ 2160cc8ae86Sav /* --CS0-----|--CS1------ */ 2170cc8ae86Sav /* -H-|--L-- | -H- | -L-- */ 218c964b0e6Sraghuram "43A", "42A", "43B", "42B", /* Bank 0 (MAC 0 bank 0) */ 219c964b0e6Sraghuram "41A", "40A", "41B", "40B", /* Bank 1 (MAC 0 bank 1) */ 220c964b0e6Sraghuram "53A", "52A", "53B", "52B", /* Bank 2 (MAC 1 bank 0) */ 221c964b0e6Sraghuram "51A", "50A", "51B", "50B", /* Bank 3 (MAC 1 bank 1) */ 222c964b0e6Sraghuram "63A", "62A", "63B", "62B", /* Bank 4 (MAC 2 bank 0) */ 223c964b0e6Sraghuram "61A", "60A", "61B", "60B", /* Bank 5 (MAC 2 bank 1) */ 224c964b0e6Sraghuram "73A", "72A", "73B", "72B", /* Bank 6 (MAC 3 bank 0) */ 225c964b0e6Sraghuram "71A", "70A", "71B", "70B" /* Bank 7 (MAC 3 bank 1) */ 2260cc8ae86Sav }; 2270cc8ae86Sav 2280cc8ae86Sav #define BD_BK_SLOT_TO_INDEX(bd, bk, s) \ 2290cc8ae86Sav (((bd & 0x01) << 5) | ((bk & 0x07) << 2) | (s & 0x03)) 2300cc8ae86Sav 2310cc8ae86Sav #define INDEX_TO_BANK(i) (((i) & 0x1C) >> 2) 2320cc8ae86Sav #define INDEX_TO_SLOT(i) ((i) & 0x03) 2330cc8ae86Sav 234aeb241b2Sav #define SLOT_TO_CS(slot) ((slot & 0x3) >> 1) 235aeb241b2Sav 2360cc8ae86Sav /* Isolation unit size is 64 MB */ 2370cc8ae86Sav #define MC_ISOLATION_BSIZE (64 * 1024 * 1024) 2380cc8ae86Sav 2390cc8ae86Sav #define MC_MAX_SPEEDS 7 2400cc8ae86Sav 2410cc8ae86Sav typedef struct { 2420cc8ae86Sav uint32_t mc_speeds; 2430cc8ae86Sav uint32_t mc_period; 2440cc8ae86Sav } mc_scan_speed_t; 2450cc8ae86Sav 2460cc8ae86Sav #define MC_CNTL_SPEED_SHIFT 26 2470cc8ae86Sav 24837afe445Shyw /* 24937afe445Shyw * In mirror mode, we normalized the bank idx to "even" since 25037afe445Shyw * the HW treats them as one unit w.r.t programming. 25137afe445Shyw * This bank index will be the "effective" bank index. 25237afe445Shyw * All mirrored bank state info on mc_period, mc_speedup_period 25337afe445Shyw * will be stored in the even bank structure to avoid code duplication. 25437afe445Shyw */ 25537afe445Shyw #define MIRROR_IDX(bankidx) (bankidx & ~1) 25637afe445Shyw 2570cc8ae86Sav static mc_scan_speed_t mc_scan_speeds[MC_MAX_SPEEDS] = { 2580cc8ae86Sav {0x6 << MC_CNTL_SPEED_SHIFT, 0}, 2590cc8ae86Sav {0x5 << MC_CNTL_SPEED_SHIFT, 32}, 2600cc8ae86Sav {0x4 << MC_CNTL_SPEED_SHIFT, 64}, 2610cc8ae86Sav {0x3 << MC_CNTL_SPEED_SHIFT, 128}, 2620cc8ae86Sav {0x2 << MC_CNTL_SPEED_SHIFT, 256}, 2630cc8ae86Sav {0x1 << MC_CNTL_SPEED_SHIFT, 512}, 2640cc8ae86Sav {0x0 << MC_CNTL_SPEED_SHIFT, 1024} 2650cc8ae86Sav }; 2660cc8ae86Sav 2670cc8ae86Sav static uint32_t mc_max_speed = (0x6 << 26); 2680cc8ae86Sav 2690cc8ae86Sav int mc_isolation_bsize = MC_ISOLATION_BSIZE; 2700cc8ae86Sav int mc_patrol_interval_sec = MC_PATROL_INTERVAL_SEC; 2710cc8ae86Sav int mc_max_scf_retry = 16; 2720cc8ae86Sav int mc_max_scf_logs = 64; 2730cc8ae86Sav int mc_max_errlog_processed = BANKNUM_PER_SB*2; 2740cc8ae86Sav int mc_scan_period = 12 * 60 * 60; /* 12 hours period */ 2750cc8ae86Sav int mc_max_rewrite_loop = 100; 2760cc8ae86Sav int mc_rewrite_delay = 10; 2770cc8ae86Sav /* 2780cc8ae86Sav * it takes SCF about 300 m.s. to process a requst. We can bail out 2790cc8ae86Sav * if it is busy. It does not pay to wait for it too long. 2800cc8ae86Sav */ 2810cc8ae86Sav int mc_max_scf_loop = 2; 2820cc8ae86Sav int mc_scf_delay = 100; 2830cc8ae86Sav int mc_pce_dropped = 0; 2840cc8ae86Sav int mc_poll_priority = MINCLSYSPRI; 285601c2e1eSdhain int mc_max_rewrite_retry = 6 * 60; 28625cf1a30Sjl 2870cc8ae86Sav 2880cc8ae86Sav /* 2891039f409Sav * Mutex hierarchy in mc-opl 2900cc8ae86Sav * If both mcmutex and mc_lock must be held, 2910cc8ae86Sav * mcmutex must be acquired first, and then mc_lock. 2920cc8ae86Sav */ 2930cc8ae86Sav 2940cc8ae86Sav static kmutex_t mcmutex; 2950cc8ae86Sav mc_opl_t *mc_instances[OPL_MAX_BOARDS]; 2960cc8ae86Sav 2970cc8ae86Sav static kmutex_t mc_polling_lock; 2980cc8ae86Sav static kcondvar_t mc_polling_cv; 2990cc8ae86Sav static kcondvar_t mc_poll_exit_cv; 3000cc8ae86Sav static int mc_poll_cmd = 0; 3010cc8ae86Sav static int mc_pollthr_running = 0; 3020cc8ae86Sav int mc_timeout_period = 0; /* this is in m.s. */ 30325cf1a30Sjl void *mc_statep; 30425cf1a30Sjl 30525cf1a30Sjl #ifdef DEBUG 3062742aa22Shyw int oplmc_debug = 0; 30725cf1a30Sjl #endif 30825cf1a30Sjl 3090cc8ae86Sav static int mc_debug_show_all = 0; 31025cf1a30Sjl 31125cf1a30Sjl extern struct mod_ops mod_driverops; 31225cf1a30Sjl 31325cf1a30Sjl static struct modldrv modldrv = { 31425cf1a30Sjl &mod_driverops, /* module type, this one is a driver */ 315*19397407SSherry Moore "OPL Memory-controller", /* module name */ 31625cf1a30Sjl &mc_ops, /* driver ops */ 31725cf1a30Sjl }; 31825cf1a30Sjl 31925cf1a30Sjl static struct modlinkage modlinkage = { 32025cf1a30Sjl MODREV_1, /* rev */ 32125cf1a30Sjl (void *)&modldrv, 32225cf1a30Sjl NULL 32325cf1a30Sjl }; 32425cf1a30Sjl 32525cf1a30Sjl #pragma weak opl_get_mem_unum 3260cc8ae86Sav #pragma weak opl_get_mem_sid 3270cc8ae86Sav #pragma weak opl_get_mem_offset 3280cc8ae86Sav #pragma weak opl_get_mem_addr 3290cc8ae86Sav 33025cf1a30Sjl extern int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *); 3310cc8ae86Sav extern int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp); 3320cc8ae86Sav extern int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp); 3330cc8ae86Sav extern int (*opl_get_mem_addr)(char *unum, char *sid, uint64_t offset, 3340cc8ae86Sav uint64_t *paddr); 3350cc8ae86Sav 33625cf1a30Sjl 33725cf1a30Sjl /* 33825cf1a30Sjl * pseudo-mc node portid format 33925cf1a30Sjl * 34025cf1a30Sjl * [10] = 0 34125cf1a30Sjl * [9] = 1 34225cf1a30Sjl * [8] = LSB_ID[4] = 0 34325cf1a30Sjl * [7:4] = LSB_ID[3:0] 34425cf1a30Sjl * [3:0] = 0 34525cf1a30Sjl * 34625cf1a30Sjl */ 34725cf1a30Sjl 34825cf1a30Sjl /* 34925cf1a30Sjl * These are the module initialization routines. 35025cf1a30Sjl */ 35125cf1a30Sjl int 35225cf1a30Sjl _init(void) 35325cf1a30Sjl { 3540cc8ae86Sav int error; 3550cc8ae86Sav int plen; 3560cc8ae86Sav char model[20]; 3570cc8ae86Sav pnode_t node; 35825cf1a30Sjl 35925cf1a30Sjl 36025cf1a30Sjl if ((error = ddi_soft_state_init(&mc_statep, 36125cf1a30Sjl sizeof (mc_opl_t), 1)) != 0) 36225cf1a30Sjl return (error); 36325cf1a30Sjl 3640cc8ae86Sav if ((error = mc_poll_init()) != 0) { 3650cc8ae86Sav ddi_soft_state_fini(&mc_statep); 3660cc8ae86Sav return (error); 3670cc8ae86Sav } 3680cc8ae86Sav 36925cf1a30Sjl mutex_init(&mcmutex, NULL, MUTEX_DRIVER, NULL); 37025cf1a30Sjl if (&opl_get_mem_unum) 37125cf1a30Sjl opl_get_mem_unum = mc_get_mem_unum; 3720cc8ae86Sav if (&opl_get_mem_sid) 3730cc8ae86Sav opl_get_mem_sid = mc_get_mem_sid; 3740cc8ae86Sav if (&opl_get_mem_offset) 3750cc8ae86Sav opl_get_mem_offset = mc_get_mem_offset; 3760cc8ae86Sav if (&opl_get_mem_addr) 3770cc8ae86Sav opl_get_mem_addr = mc_get_mem_addr; 3780cc8ae86Sav 3790cc8ae86Sav node = prom_rootnode(); 3800cc8ae86Sav plen = prom_getproplen(node, "model"); 3810cc8ae86Sav 3820cc8ae86Sav if (plen > 0 && plen < sizeof (model)) { 3830cc8ae86Sav (void) prom_getprop(node, "model", model); 3840cc8ae86Sav model[plen] = '\0'; 3850cc8ae86Sav if (strcmp(model, "FF1") == 0) 3860cc8ae86Sav plat_model = MODEL_FF1; 3870cc8ae86Sav else if (strcmp(model, "FF2") == 0) 3880cc8ae86Sav plat_model = MODEL_FF2; 3890cc8ae86Sav else if (strncmp(model, "DC", 2) == 0) 3900cc8ae86Sav plat_model = MODEL_DC; 39178ed97a7Sjl else if (strcmp(model, "IKKAKU") == 0) 39278ed97a7Sjl plat_model = MODEL_IKKAKU; 3930cc8ae86Sav } 39425cf1a30Sjl 39525cf1a30Sjl error = mod_install(&modlinkage); 39625cf1a30Sjl if (error != 0) { 39725cf1a30Sjl if (&opl_get_mem_unum) 39825cf1a30Sjl opl_get_mem_unum = NULL; 3990cc8ae86Sav if (&opl_get_mem_sid) 4000cc8ae86Sav opl_get_mem_sid = NULL; 4010cc8ae86Sav if (&opl_get_mem_offset) 4020cc8ae86Sav opl_get_mem_offset = NULL; 4030cc8ae86Sav if (&opl_get_mem_addr) 4040cc8ae86Sav opl_get_mem_addr = NULL; 40525cf1a30Sjl mutex_destroy(&mcmutex); 4060cc8ae86Sav mc_poll_fini(); 40725cf1a30Sjl ddi_soft_state_fini(&mc_statep); 40825cf1a30Sjl } 40925cf1a30Sjl return (error); 41025cf1a30Sjl } 41125cf1a30Sjl 41225cf1a30Sjl int 41325cf1a30Sjl _fini(void) 41425cf1a30Sjl { 41525cf1a30Sjl int error; 41625cf1a30Sjl 41725cf1a30Sjl if ((error = mod_remove(&modlinkage)) != 0) 41825cf1a30Sjl return (error); 41925cf1a30Sjl 42025cf1a30Sjl if (&opl_get_mem_unum) 42125cf1a30Sjl opl_get_mem_unum = NULL; 4220cc8ae86Sav if (&opl_get_mem_sid) 4230cc8ae86Sav opl_get_mem_sid = NULL; 4240cc8ae86Sav if (&opl_get_mem_offset) 4250cc8ae86Sav opl_get_mem_offset = NULL; 4260cc8ae86Sav if (&opl_get_mem_addr) 4270cc8ae86Sav opl_get_mem_addr = NULL; 42825cf1a30Sjl 4290cc8ae86Sav mutex_destroy(&mcmutex); 4300cc8ae86Sav mc_poll_fini(); 43125cf1a30Sjl ddi_soft_state_fini(&mc_statep); 43225cf1a30Sjl 43325cf1a30Sjl return (0); 43425cf1a30Sjl } 43525cf1a30Sjl 43625cf1a30Sjl int 43725cf1a30Sjl _info(struct modinfo *modinfop) 43825cf1a30Sjl { 43925cf1a30Sjl return (mod_info(&modlinkage, modinfop)); 44025cf1a30Sjl } 44125cf1a30Sjl 4420cc8ae86Sav static void 4430cc8ae86Sav mc_polling_thread() 4440cc8ae86Sav { 4450cc8ae86Sav mutex_enter(&mc_polling_lock); 4460cc8ae86Sav mc_pollthr_running = 1; 4470cc8ae86Sav while (!(mc_poll_cmd & MC_POLL_EXIT)) { 4480cc8ae86Sav mc_polling(); 4490cc8ae86Sav cv_timedwait(&mc_polling_cv, &mc_polling_lock, 4500cc8ae86Sav ddi_get_lbolt() + mc_timeout_period); 4510cc8ae86Sav } 4520cc8ae86Sav mc_pollthr_running = 0; 4530cc8ae86Sav 4540cc8ae86Sav /* 4550cc8ae86Sav * signal if any one is waiting for this thread to exit. 4560cc8ae86Sav */ 4570cc8ae86Sav cv_signal(&mc_poll_exit_cv); 4580cc8ae86Sav mutex_exit(&mc_polling_lock); 4590cc8ae86Sav thread_exit(); 4600cc8ae86Sav /* NOTREACHED */ 4610cc8ae86Sav } 4620cc8ae86Sav 4630cc8ae86Sav static int 4640cc8ae86Sav mc_poll_init() 4650cc8ae86Sav { 4660cc8ae86Sav mutex_init(&mc_polling_lock, NULL, MUTEX_DRIVER, NULL); 4670cc8ae86Sav cv_init(&mc_polling_cv, NULL, CV_DRIVER, NULL); 4680cc8ae86Sav cv_init(&mc_poll_exit_cv, NULL, CV_DRIVER, NULL); 4690cc8ae86Sav return (0); 4700cc8ae86Sav } 4710cc8ae86Sav 4720cc8ae86Sav static void 4730cc8ae86Sav mc_poll_fini() 4740cc8ae86Sav { 4750cc8ae86Sav mutex_enter(&mc_polling_lock); 4760cc8ae86Sav if (mc_pollthr_running) { 4770cc8ae86Sav mc_poll_cmd = MC_POLL_EXIT; 4780cc8ae86Sav cv_signal(&mc_polling_cv); 4790cc8ae86Sav while (mc_pollthr_running) { 4800cc8ae86Sav cv_wait(&mc_poll_exit_cv, &mc_polling_lock); 4810cc8ae86Sav } 4820cc8ae86Sav } 4830cc8ae86Sav mutex_exit(&mc_polling_lock); 4840cc8ae86Sav mutex_destroy(&mc_polling_lock); 4850cc8ae86Sav cv_destroy(&mc_polling_cv); 4860cc8ae86Sav cv_destroy(&mc_poll_exit_cv); 4870cc8ae86Sav } 4880cc8ae86Sav 48925cf1a30Sjl static int 49025cf1a30Sjl mc_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 49125cf1a30Sjl { 49225cf1a30Sjl mc_opl_t *mcp; 49325cf1a30Sjl int instance; 4940cc8ae86Sav int rv; 49525cf1a30Sjl 49625cf1a30Sjl /* get the instance of this devi */ 49725cf1a30Sjl instance = ddi_get_instance(devi); 49825cf1a30Sjl 49925cf1a30Sjl switch (cmd) { 50025cf1a30Sjl case DDI_ATTACH: 50125cf1a30Sjl break; 50225cf1a30Sjl case DDI_RESUME: 50325cf1a30Sjl mcp = ddi_get_soft_state(mc_statep, instance); 5040cc8ae86Sav rv = mc_resume(mcp, MC_DRIVER_SUSPENDED); 5050cc8ae86Sav return (rv); 50625cf1a30Sjl default: 50725cf1a30Sjl return (DDI_FAILURE); 50825cf1a30Sjl } 50925cf1a30Sjl 51025cf1a30Sjl if (ddi_soft_state_zalloc(mc_statep, instance) != DDI_SUCCESS) 51125cf1a30Sjl return (DDI_FAILURE); 51225cf1a30Sjl 5130b240fcdSwh if (ddi_create_minor_node(devi, "mc-opl", S_IFCHR, instance, 5140b240fcdSwh "ddi_mem_ctrl", 0) != DDI_SUCCESS) { 5150b240fcdSwh MC_LOG("mc_attach: create_minor_node failed\n"); 5160b240fcdSwh return (DDI_FAILURE); 5170b240fcdSwh } 5180b240fcdSwh 51925cf1a30Sjl if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 52025cf1a30Sjl goto bad; 52125cf1a30Sjl } 52225cf1a30Sjl 5230cc8ae86Sav if (mc_timeout_period == 0) { 5240cc8ae86Sav mc_patrol_interval_sec = (int)ddi_getprop(DDI_DEV_T_ANY, devi, 525d8a0cca9Swh DDI_PROP_DONTPASS, "mc-timeout-interval-sec", 526d8a0cca9Swh mc_patrol_interval_sec); 527d8a0cca9Swh mc_timeout_period = drv_usectohz(1000000 * 528d8a0cca9Swh mc_patrol_interval_sec / OPL_MAX_BOARDS); 5290cc8ae86Sav } 5300cc8ae86Sav 53125cf1a30Sjl /* set informations in mc state */ 53225cf1a30Sjl mcp->mc_dip = devi; 53325cf1a30Sjl 53425cf1a30Sjl if (mc_board_add(mcp)) 53525cf1a30Sjl goto bad; 53625cf1a30Sjl 53725cf1a30Sjl insert_mcp(mcp); 5380cc8ae86Sav 5390cc8ae86Sav /* 5400cc8ae86Sav * Start the polling thread if it is not running already. 5410cc8ae86Sav */ 5420cc8ae86Sav mutex_enter(&mc_polling_lock); 5430cc8ae86Sav if (!mc_pollthr_running) { 5440cc8ae86Sav (void) thread_create(NULL, 0, (void (*)())mc_polling_thread, 545d8a0cca9Swh NULL, 0, &p0, TS_RUN, mc_poll_priority); 5460cc8ae86Sav } 5470cc8ae86Sav mutex_exit(&mc_polling_lock); 54825cf1a30Sjl ddi_report_dev(devi); 54925cf1a30Sjl 55025cf1a30Sjl return (DDI_SUCCESS); 55125cf1a30Sjl 55225cf1a30Sjl bad: 5530b240fcdSwh ddi_remove_minor_node(devi, NULL); 55425cf1a30Sjl ddi_soft_state_free(mc_statep, instance); 55525cf1a30Sjl return (DDI_FAILURE); 55625cf1a30Sjl } 55725cf1a30Sjl 55825cf1a30Sjl /* ARGSUSED */ 55925cf1a30Sjl static int 56025cf1a30Sjl mc_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 56125cf1a30Sjl { 5620cc8ae86Sav int rv; 56325cf1a30Sjl int instance; 56425cf1a30Sjl mc_opl_t *mcp; 56525cf1a30Sjl 56625cf1a30Sjl /* get the instance of this devi */ 56725cf1a30Sjl instance = ddi_get_instance(devi); 56825cf1a30Sjl if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 56925cf1a30Sjl return (DDI_FAILURE); 57025cf1a30Sjl } 57125cf1a30Sjl 57225cf1a30Sjl switch (cmd) { 57325cf1a30Sjl case DDI_SUSPEND: 5740cc8ae86Sav rv = mc_suspend(mcp, MC_DRIVER_SUSPENDED); 5750cc8ae86Sav return (rv); 57625cf1a30Sjl case DDI_DETACH: 57725cf1a30Sjl break; 57825cf1a30Sjl default: 57925cf1a30Sjl return (DDI_FAILURE); 58025cf1a30Sjl } 58125cf1a30Sjl 5820cc8ae86Sav delete_mcp(mcp); 58325cf1a30Sjl if (mc_board_del(mcp) != DDI_SUCCESS) { 58425cf1a30Sjl return (DDI_FAILURE); 58525cf1a30Sjl } 58625cf1a30Sjl 5870b240fcdSwh ddi_remove_minor_node(devi, NULL); 5880b240fcdSwh 58925cf1a30Sjl /* free up the soft state */ 59025cf1a30Sjl ddi_soft_state_free(mc_statep, instance); 59125cf1a30Sjl 59225cf1a30Sjl return (DDI_SUCCESS); 59325cf1a30Sjl } 59425cf1a30Sjl 59525cf1a30Sjl /* ARGSUSED */ 59625cf1a30Sjl static int 59725cf1a30Sjl mc_open(dev_t *devp, int flag, int otyp, cred_t *credp) 59825cf1a30Sjl { 59925cf1a30Sjl return (0); 60025cf1a30Sjl } 60125cf1a30Sjl 60225cf1a30Sjl /* ARGSUSED */ 60325cf1a30Sjl static int 60425cf1a30Sjl mc_close(dev_t devp, int flag, int otyp, cred_t *credp) 60525cf1a30Sjl { 60625cf1a30Sjl return (0); 60725cf1a30Sjl } 60825cf1a30Sjl 60925cf1a30Sjl /* ARGSUSED */ 61025cf1a30Sjl static int 61125cf1a30Sjl mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 61225cf1a30Sjl int *rvalp) 61325cf1a30Sjl { 6140b240fcdSwh mc_flt_page_t flt_page; 6150b240fcdSwh 6160b240fcdSwh if (cmd == MCIOC_FAULT_PAGE) { 6170b240fcdSwh if (arg == NULL) 6180b240fcdSwh return (EINVAL); 6190b240fcdSwh 6200b240fcdSwh if (ddi_copyin((const void *)arg, (void *)&flt_page, 6210b240fcdSwh sizeof (mc_flt_page_t), 0) < 0) 6220b240fcdSwh return (EFAULT); 6230b240fcdSwh 6240b240fcdSwh return (mc_scf_log_event(&flt_page)); 6250b240fcdSwh } 6260cc8ae86Sav #ifdef DEBUG 6270cc8ae86Sav return (mc_ioctl_debug(dev, cmd, arg, mode, credp, rvalp)); 6280cc8ae86Sav #else 6290b240fcdSwh return (ENOTTY); 6300cc8ae86Sav #endif 63125cf1a30Sjl } 63225cf1a30Sjl 63325cf1a30Sjl /* 63425cf1a30Sjl * PA validity check: 635738dd194Shyw * This function return 1 if the PA is a valid PA 636738dd194Shyw * in the running Solaris instance i.e. in physinstall 637738dd194Shyw * Otherwise, return 0. 63825cf1a30Sjl */ 63925cf1a30Sjl 64025cf1a30Sjl /* ARGSUSED */ 64125cf1a30Sjl static int 64225cf1a30Sjl pa_is_valid(mc_opl_t *mcp, uint64_t addr) 64325cf1a30Sjl { 64425cf1a30Sjl if (mcp->mlist == NULL) 64525cf1a30Sjl mc_get_mlist(mcp); 64625cf1a30Sjl 64725cf1a30Sjl if (mcp->mlist && address_in_memlist(mcp->mlist, addr, 0)) { 64825cf1a30Sjl return (1); 64925cf1a30Sjl } 65025cf1a30Sjl return (0); 65125cf1a30Sjl } 65225cf1a30Sjl 65325cf1a30Sjl /* 65425cf1a30Sjl * mac-pa translation routines. 65525cf1a30Sjl * 65625cf1a30Sjl * Input: mc driver state, (LSB#, Bank#, DIMM address) 65725cf1a30Sjl * Output: physical address 65825cf1a30Sjl * 65925cf1a30Sjl * Valid - return value: 0 66025cf1a30Sjl * Invalid - return value: -1 66125cf1a30Sjl */ 66225cf1a30Sjl static int 66325cf1a30Sjl mcaddr_to_pa(mc_opl_t *mcp, mc_addr_t *maddr, uint64_t *pa) 66425cf1a30Sjl { 66525cf1a30Sjl int i; 66625cf1a30Sjl uint64_t pa_offset = 0; 66725cf1a30Sjl int cs = (maddr->ma_dimm_addr >> CS_SHIFT) & 1; 66825cf1a30Sjl int bank = maddr->ma_bank; 66925cf1a30Sjl mc_addr_t maddr1; 67025cf1a30Sjl int bank0, bank1; 67125cf1a30Sjl 67225cf1a30Sjl MC_LOG("mcaddr /LSB%d/B%d/%x\n", maddr->ma_bd, bank, 673d8a0cca9Swh maddr->ma_dimm_addr); 67425cf1a30Sjl 67525cf1a30Sjl /* loc validity check */ 67625cf1a30Sjl ASSERT(maddr->ma_bd >= 0 && OPL_BOARD_MAX > maddr->ma_bd); 67725cf1a30Sjl ASSERT(bank >= 0 && OPL_BANK_MAX > bank); 67825cf1a30Sjl 67925cf1a30Sjl /* Do translation */ 68025cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 68125cf1a30Sjl int pa_bit = 0; 68225cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 68325cf1a30Sjl if (mc_bit < MC_ADDRESS_BITS) { 68425cf1a30Sjl pa_bit = (maddr->ma_dimm_addr >> mc_bit) & 1; 68525cf1a30Sjl } else if (mc_bit == MP_NONE) { 68625cf1a30Sjl pa_bit = 0; 68725cf1a30Sjl } else if (mc_bit == MP_BANK_0) { 68825cf1a30Sjl pa_bit = bank & 1; 68925cf1a30Sjl } else if (mc_bit == MP_BANK_1) { 69025cf1a30Sjl pa_bit = (bank >> 1) & 1; 69125cf1a30Sjl } else if (mc_bit == MP_BANK_2) { 69225cf1a30Sjl pa_bit = (bank >> 2) & 1; 69325cf1a30Sjl } 69425cf1a30Sjl pa_offset |= ((uint64_t)pa_bit) << i; 69525cf1a30Sjl } 69625cf1a30Sjl *pa = mcp->mc_start_address + pa_offset; 69725cf1a30Sjl MC_LOG("pa = %lx\n", *pa); 69825cf1a30Sjl 69925cf1a30Sjl if (pa_to_maddr(mcp, *pa, &maddr1) == -1) { 7000cc8ae86Sav cmn_err(CE_WARN, "mcaddr_to_pa: /LSB%d/B%d/%x failed to " 7010cc8ae86Sav "convert PA %lx\n", maddr->ma_bd, bank, 7020cc8ae86Sav maddr->ma_dimm_addr, *pa); 70325cf1a30Sjl return (-1); 70425cf1a30Sjl } 70525cf1a30Sjl 7060cc8ae86Sav /* 7070cc8ae86Sav * In mirror mode, PA is always translated to the even bank. 7080cc8ae86Sav */ 70925cf1a30Sjl if (IS_MIRROR(mcp, maddr->ma_bank)) { 71025cf1a30Sjl bank0 = maddr->ma_bank & ~(1); 71125cf1a30Sjl bank1 = maddr1.ma_bank & ~(1); 71225cf1a30Sjl } else { 71325cf1a30Sjl bank0 = maddr->ma_bank; 71425cf1a30Sjl bank1 = maddr1.ma_bank; 71525cf1a30Sjl } 71625cf1a30Sjl /* 71725cf1a30Sjl * there is no need to check ma_bd because it is generated from 71825cf1a30Sjl * mcp. They are the same. 71925cf1a30Sjl */ 720d8a0cca9Swh if ((bank0 == bank1) && (maddr->ma_dimm_addr == 721d8a0cca9Swh maddr1.ma_dimm_addr)) { 72225cf1a30Sjl return (0); 72325cf1a30Sjl } else { 7240b240fcdSwh MC_LOG("Translation error source /LSB%d/B%d/%x, " 725d8a0cca9Swh "PA %lx, target /LSB%d/B%d/%x\n", maddr->ma_bd, bank, 726d8a0cca9Swh maddr->ma_dimm_addr, *pa, maddr1.ma_bd, maddr1.ma_bank, 727d8a0cca9Swh maddr1.ma_dimm_addr); 72825cf1a30Sjl return (-1); 72925cf1a30Sjl } 73025cf1a30Sjl } 73125cf1a30Sjl 73225cf1a30Sjl /* 73325cf1a30Sjl * PA to CS (used by pa_to_maddr). 73425cf1a30Sjl */ 73525cf1a30Sjl static int 73625cf1a30Sjl pa_to_cs(mc_opl_t *mcp, uint64_t pa_offset) 73725cf1a30Sjl { 73825cf1a30Sjl int i; 739738dd194Shyw int cs = 1; 74025cf1a30Sjl 74125cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 74225cf1a30Sjl /* MAC address bit<29> is arranged on the same PA bit */ 74325cf1a30Sjl /* on both table. So we may use any table. */ 74425cf1a30Sjl if (mcp->mc_trans_table[0][i] == CS_SHIFT) { 74525cf1a30Sjl cs = (pa_offset >> i) & 1; 74625cf1a30Sjl break; 74725cf1a30Sjl } 74825cf1a30Sjl } 74925cf1a30Sjl return (cs); 75025cf1a30Sjl } 75125cf1a30Sjl 75225cf1a30Sjl /* 75325cf1a30Sjl * PA to DIMM (used by pa_to_maddr). 75425cf1a30Sjl */ 75525cf1a30Sjl /* ARGSUSED */ 75625cf1a30Sjl static uint32_t 75725cf1a30Sjl pa_to_dimm(mc_opl_t *mcp, uint64_t pa_offset) 75825cf1a30Sjl { 75925cf1a30Sjl int i; 76025cf1a30Sjl int cs = pa_to_cs(mcp, pa_offset); 76125cf1a30Sjl uint32_t dimm_addr = 0; 76225cf1a30Sjl 76325cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 76425cf1a30Sjl int pa_bit_value = (pa_offset >> i) & 1; 76525cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 76625cf1a30Sjl if (mc_bit < MC_ADDRESS_BITS) { 76725cf1a30Sjl dimm_addr |= pa_bit_value << mc_bit; 76825cf1a30Sjl } 76925cf1a30Sjl } 770738dd194Shyw dimm_addr |= cs << CS_SHIFT; 77125cf1a30Sjl return (dimm_addr); 77225cf1a30Sjl } 77325cf1a30Sjl 77425cf1a30Sjl /* 77525cf1a30Sjl * PA to Bank (used by pa_to_maddr). 77625cf1a30Sjl */ 77725cf1a30Sjl static int 77825cf1a30Sjl pa_to_bank(mc_opl_t *mcp, uint64_t pa_offset) 77925cf1a30Sjl { 78025cf1a30Sjl int i; 78125cf1a30Sjl int cs = pa_to_cs(mcp, pa_offset); 78225cf1a30Sjl int bankno = mcp->mc_trans_table[cs][INDEX_OF_BANK_SUPPLEMENT_BIT]; 78325cf1a30Sjl 78425cf1a30Sjl 78525cf1a30Sjl for (i = 0; i < PA_BITS_FOR_MAC; i++) { 78625cf1a30Sjl int pa_bit_value = (pa_offset >> i) & 1; 78725cf1a30Sjl int mc_bit = mcp->mc_trans_table[cs][i]; 78825cf1a30Sjl switch (mc_bit) { 78925cf1a30Sjl case MP_BANK_0: 79025cf1a30Sjl bankno |= pa_bit_value; 79125cf1a30Sjl break; 79225cf1a30Sjl case MP_BANK_1: 79325cf1a30Sjl bankno |= pa_bit_value << 1; 79425cf1a30Sjl break; 79525cf1a30Sjl case MP_BANK_2: 79625cf1a30Sjl bankno |= pa_bit_value << 2; 79725cf1a30Sjl break; 79825cf1a30Sjl } 79925cf1a30Sjl } 80025cf1a30Sjl 80125cf1a30Sjl return (bankno); 80225cf1a30Sjl } 80325cf1a30Sjl 80425cf1a30Sjl /* 80525cf1a30Sjl * PA to MAC address translation 80625cf1a30Sjl * 80725cf1a30Sjl * Input: MAC driver state, physicall adress 80825cf1a30Sjl * Output: LSB#, Bank id, mac address 80925cf1a30Sjl * 81025cf1a30Sjl * Valid - return value: 0 81125cf1a30Sjl * Invalid - return value: -1 81225cf1a30Sjl */ 81325cf1a30Sjl 81425cf1a30Sjl int 81525cf1a30Sjl pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr) 81625cf1a30Sjl { 81725cf1a30Sjl uint64_t pa_offset; 81825cf1a30Sjl 819738dd194Shyw if (!mc_rangecheck_pa(mcp, pa)) 82025cf1a30Sjl return (-1); 82125cf1a30Sjl 82225cf1a30Sjl /* Do translation */ 82325cf1a30Sjl pa_offset = pa - mcp->mc_start_address; 82425cf1a30Sjl 82525cf1a30Sjl maddr->ma_bd = mcp->mc_board_num; 826aeb241b2Sav maddr->ma_phys_bd = mcp->mc_phys_board_num; 82725cf1a30Sjl maddr->ma_bank = pa_to_bank(mcp, pa_offset); 82825cf1a30Sjl maddr->ma_dimm_addr = pa_to_dimm(mcp, pa_offset); 829d8a0cca9Swh MC_LOG("pa %lx -> mcaddr /LSB%d/B%d/%x\n", pa_offset, maddr->ma_bd, 830d8a0cca9Swh maddr->ma_bank, maddr->ma_dimm_addr); 83125cf1a30Sjl return (0); 83225cf1a30Sjl } 83325cf1a30Sjl 8340cc8ae86Sav /* 8350cc8ae86Sav * UNUM format for DC is "/CMUnn/MEMxyZ", where 8360cc8ae86Sav * nn = 00..03 for DC1 and 00..07 for DC2 and 00..15 for DC3. 8370cc8ae86Sav * x = MAC 0..3 8380cc8ae86Sav * y = 0..3 (slot info). 8390cc8ae86Sav * Z = 'A' or 'B' 8400cc8ae86Sav * 8410cc8ae86Sav * UNUM format for FF1 is "/MBU_A/MEMBx/MEMyZ", where 8420cc8ae86Sav * x = 0..3 (MEMB number) 8430cc8ae86Sav * y = 0..3 (slot info). 8440cc8ae86Sav * Z = 'A' or 'B' 8450cc8ae86Sav * 84678ed97a7Sjl * UNUM format for FF2 is "/MBU_B/MEMBx/MEMyZ", where 8470cc8ae86Sav * x = 0..7 (MEMB number) 8480cc8ae86Sav * y = 0..3 (slot info). 8490cc8ae86Sav * Z = 'A' or 'B' 85078ed97a7Sjl * 85178ed97a7Sjl * UNUM format for IKKAKU is "/MBU_A/MEMyZ", where 85278ed97a7Sjl * y = 0..3 (slot info). 85378ed97a7Sjl * Z = 'A' or 'B' 85478ed97a7Sjl * 8550cc8ae86Sav */ 8560cc8ae86Sav int 857aeb241b2Sav mc_set_mem_unum(char *buf, int buflen, int sb, int bank, 8580cc8ae86Sav uint32_t mf_type, uint32_t d_slot) 8590cc8ae86Sav { 8600cc8ae86Sav char *dimmnm; 8610cc8ae86Sav char memb_num; 862aeb241b2Sav int cs; 8630cc8ae86Sav int i; 864aeb241b2Sav int j; 8650cc8ae86Sav 866aeb241b2Sav cs = SLOT_TO_CS(d_slot); 8670cc8ae86Sav 86878ed97a7Sjl switch (plat_model) { 86978ed97a7Sjl case MODEL_DC: 870056c948bStsien if (mf_type == FLT_TYPE_INTERMITTENT_CE || 871056c948bStsien mf_type == FLT_TYPE_PERMANENT_CE) { 8720cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 8730cc8ae86Sav dimmnm = mc_dc_dimm_unum_table[i]; 8740cc8ae86Sav snprintf(buf, buflen, "/%s%02d/MEM%s", 8750cc8ae86Sav model_names[plat_model].unit_name, sb, dimmnm); 8760cc8ae86Sav } else { 8770cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 878aeb241b2Sav j = (cs == 0) ? i : i + 2; 879aeb241b2Sav snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s", 8800cc8ae86Sav model_names[plat_model].unit_name, sb, 881aeb241b2Sav mc_dc_dimm_unum_table[j], 882aeb241b2Sav mc_dc_dimm_unum_table[j + 1]); 8830cc8ae86Sav } 88478ed97a7Sjl break; 88578ed97a7Sjl case MODEL_FF1: 88678ed97a7Sjl case MODEL_FF2: 887056c948bStsien if (mf_type == FLT_TYPE_INTERMITTENT_CE || 888056c948bStsien mf_type == FLT_TYPE_PERMANENT_CE) { 889aeb241b2Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 8900cc8ae86Sav dimmnm = mc_ff_dimm_unum_table[i]; 8910cc8ae86Sav memb_num = dimmnm[0]; 8920cc8ae86Sav snprintf(buf, buflen, "/%s/%s%c/MEM%s", 8930cc8ae86Sav model_names[plat_model].unit_name, 8940cc8ae86Sav model_names[plat_model].mem_name, 8950cc8ae86Sav memb_num, &dimmnm[1]); 8960cc8ae86Sav } else { 8970cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 898aeb241b2Sav j = (cs == 0) ? i : i + 2; 8990cc8ae86Sav memb_num = mc_ff_dimm_unum_table[i][0], 900d8a0cca9Swh snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s", 9010cc8ae86Sav model_names[plat_model].unit_name, 9020cc8ae86Sav model_names[plat_model].mem_name, memb_num, 903aeb241b2Sav &mc_ff_dimm_unum_table[j][1], 904aeb241b2Sav &mc_ff_dimm_unum_table[j + 1][1]); 9050cc8ae86Sav } 90678ed97a7Sjl break; 90778ed97a7Sjl case MODEL_IKKAKU: 90878ed97a7Sjl if (mf_type == FLT_TYPE_INTERMITTENT_CE || 90978ed97a7Sjl mf_type == FLT_TYPE_PERMANENT_CE) { 91078ed97a7Sjl i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 91178ed97a7Sjl dimmnm = mc_ff_dimm_unum_table[i]; 91278ed97a7Sjl snprintf(buf, buflen, "/%s/MEM%s", 91378ed97a7Sjl model_names[plat_model].unit_name, &dimmnm[1]); 91478ed97a7Sjl } else { 91578ed97a7Sjl i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 91678ed97a7Sjl j = (cs == 0) ? i : i + 2; 91778ed97a7Sjl memb_num = mc_ff_dimm_unum_table[i][0], 91878ed97a7Sjl snprintf(buf, buflen, "/%s/MEM%s MEM%s", 91978ed97a7Sjl model_names[plat_model].unit_name, 92078ed97a7Sjl &mc_ff_dimm_unum_table[j][1], 92178ed97a7Sjl &mc_ff_dimm_unum_table[j + 1][1]); 92278ed97a7Sjl } 92378ed97a7Sjl break; 92478ed97a7Sjl default: 92578ed97a7Sjl return (-1); 9260cc8ae86Sav } 9270cc8ae86Sav return (0); 9280cc8ae86Sav } 9290cc8ae86Sav 93025cf1a30Sjl static void 93125cf1a30Sjl mc_ereport_post(mc_aflt_t *mc_aflt) 93225cf1a30Sjl { 93325cf1a30Sjl char buf[FM_MAX_CLASS]; 93425cf1a30Sjl char device_path[MAXPATHLEN]; 9350cc8ae86Sav char sid[MAXPATHLEN]; 93625cf1a30Sjl nv_alloc_t *nva = NULL; 93725cf1a30Sjl nvlist_t *ereport, *detector, *resource; 93825cf1a30Sjl errorq_elem_t *eqep; 93925cf1a30Sjl int nflts; 94025cf1a30Sjl mc_flt_stat_t *flt_stat; 9410cc8ae86Sav int i, n; 9420cc8ae86Sav int blen = MAXPATHLEN; 9430cc8ae86Sav char *p, *s = NULL; 94425cf1a30Sjl uint32_t values[2], synd[2], dslot[2]; 9450cc8ae86Sav uint64_t offset = (uint64_t)-1; 9460cc8ae86Sav int ret = -1; 94725cf1a30Sjl 94825cf1a30Sjl if (panicstr) { 94925cf1a30Sjl eqep = errorq_reserve(ereport_errorq); 95025cf1a30Sjl if (eqep == NULL) 95125cf1a30Sjl return; 95225cf1a30Sjl ereport = errorq_elem_nvl(ereport_errorq, eqep); 95325cf1a30Sjl nva = errorq_elem_nva(ereport_errorq, eqep); 95425cf1a30Sjl } else { 95525cf1a30Sjl ereport = fm_nvlist_create(nva); 95625cf1a30Sjl } 95725cf1a30Sjl 95825cf1a30Sjl /* 95925cf1a30Sjl * Create the scheme "dev" FMRI. 96025cf1a30Sjl */ 96125cf1a30Sjl detector = fm_nvlist_create(nva); 96225cf1a30Sjl resource = fm_nvlist_create(nva); 96325cf1a30Sjl 96425cf1a30Sjl nflts = mc_aflt->mflt_nflts; 96525cf1a30Sjl 96625cf1a30Sjl ASSERT(nflts >= 1 && nflts <= 2); 96725cf1a30Sjl 96825cf1a30Sjl flt_stat = mc_aflt->mflt_stat[0]; 96925cf1a30Sjl (void) ddi_pathname(mc_aflt->mflt_mcp->mc_dip, device_path); 97025cf1a30Sjl (void) fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, 97125cf1a30Sjl device_path, NULL); 97225cf1a30Sjl 97325cf1a30Sjl /* 97425cf1a30Sjl * Encode all the common data into the ereport. 97525cf1a30Sjl */ 976d8a0cca9Swh (void) snprintf(buf, FM_MAX_CLASS, "%s.%s-%s", MC_OPL_ERROR_CLASS, 977d8a0cca9Swh mc_aflt->mflt_is_ptrl ? MC_OPL_PTRL_SUBCLASS : MC_OPL_MI_SUBCLASS, 978d8a0cca9Swh mc_aflt->mflt_erpt_class); 97925cf1a30Sjl 98025cf1a30Sjl MC_LOG("mc_ereport_post: ereport %s\n", buf); 98125cf1a30Sjl 98225cf1a30Sjl 98325cf1a30Sjl fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 984d8a0cca9Swh fm_ena_generate(mc_aflt->mflt_id, FM_ENA_FMT1), detector, NULL); 98525cf1a30Sjl 98625cf1a30Sjl /* 98725cf1a30Sjl * Set payload. 98825cf1a30Sjl */ 98925cf1a30Sjl fm_payload_set(ereport, MC_OPL_BOARD, DATA_TYPE_UINT32, 990d8a0cca9Swh flt_stat->mf_flt_maddr.ma_bd, NULL); 99125cf1a30Sjl 99225cf1a30Sjl fm_payload_set(ereport, MC_OPL_PA, DATA_TYPE_UINT64, 993d8a0cca9Swh flt_stat->mf_flt_paddr, NULL); 99425cf1a30Sjl 995056c948bStsien if (flt_stat->mf_type == FLT_TYPE_INTERMITTENT_CE || 996056c948bStsien flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 997d8a0cca9Swh fm_payload_set(ereport, MC_OPL_FLT_TYPE, DATA_TYPE_UINT8, 998d8a0cca9Swh ECC_STICKY, NULL); 99925cf1a30Sjl } 100025cf1a30Sjl 100125cf1a30Sjl for (i = 0; i < nflts; i++) 100225cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_flt_maddr.ma_bank; 100325cf1a30Sjl 1004d8a0cca9Swh fm_payload_set(ereport, MC_OPL_BANK, DATA_TYPE_UINT32_ARRAY, nflts, 1005d8a0cca9Swh values, NULL); 100625cf1a30Sjl 100725cf1a30Sjl for (i = 0; i < nflts; i++) 100825cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_cntl; 100925cf1a30Sjl 1010d8a0cca9Swh fm_payload_set(ereport, MC_OPL_STATUS, DATA_TYPE_UINT32_ARRAY, nflts, 1011d8a0cca9Swh values, NULL); 101225cf1a30Sjl 101325cf1a30Sjl for (i = 0; i < nflts; i++) 101425cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_err_add; 101525cf1a30Sjl 1016056c948bStsien /* offset is set only for PCE and ICE */ 1017056c948bStsien if (mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_INTERMITTENT_CE || 1018056c948bStsien mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_PERMANENT_CE) { 10190cc8ae86Sav offset = values[0]; 10200cc8ae86Sav 10210cc8ae86Sav } 1022d8a0cca9Swh fm_payload_set(ereport, MC_OPL_ERR_ADD, DATA_TYPE_UINT32_ARRAY, nflts, 1023d8a0cca9Swh values, NULL); 102425cf1a30Sjl 102525cf1a30Sjl for (i = 0; i < nflts; i++) 102625cf1a30Sjl values[i] = mc_aflt->mflt_stat[i]->mf_err_log; 102725cf1a30Sjl 1028d8a0cca9Swh fm_payload_set(ereport, MC_OPL_ERR_LOG, DATA_TYPE_UINT32_ARRAY, nflts, 1029d8a0cca9Swh values, NULL); 103025cf1a30Sjl 103125cf1a30Sjl for (i = 0; i < nflts; i++) { 103225cf1a30Sjl flt_stat = mc_aflt->mflt_stat[i]; 103325cf1a30Sjl if (flt_stat->mf_errlog_valid) { 103425cf1a30Sjl synd[i] = flt_stat->mf_synd; 103525cf1a30Sjl dslot[i] = flt_stat->mf_dimm_slot; 103625cf1a30Sjl values[i] = flt_stat->mf_dram_place; 103725cf1a30Sjl } else { 103825cf1a30Sjl synd[i] = 0; 103925cf1a30Sjl dslot[i] = 0; 104025cf1a30Sjl values[i] = 0; 104125cf1a30Sjl } 104225cf1a30Sjl } 104325cf1a30Sjl 1044d8a0cca9Swh fm_payload_set(ereport, MC_OPL_ERR_SYND, DATA_TYPE_UINT32_ARRAY, nflts, 1045d8a0cca9Swh synd, NULL); 104625cf1a30Sjl 1047d8a0cca9Swh fm_payload_set(ereport, MC_OPL_ERR_DIMMSLOT, DATA_TYPE_UINT32_ARRAY, 1048d8a0cca9Swh nflts, dslot, NULL); 104925cf1a30Sjl 1050d8a0cca9Swh fm_payload_set(ereport, MC_OPL_ERR_DRAM, DATA_TYPE_UINT32_ARRAY, nflts, 1051d8a0cca9Swh values, NULL); 105225cf1a30Sjl 105325cf1a30Sjl device_path[0] = 0; 105425cf1a30Sjl p = &device_path[0]; 10550cc8ae86Sav sid[0] = 0; 10560cc8ae86Sav s = &sid[0]; 10570cc8ae86Sav ret = 0; 105825cf1a30Sjl 105925cf1a30Sjl for (i = 0; i < nflts; i++) { 10600cc8ae86Sav int bank; 106125cf1a30Sjl 106225cf1a30Sjl flt_stat = mc_aflt->mflt_stat[i]; 10630cc8ae86Sav bank = flt_stat->mf_flt_maddr.ma_bank; 1064d8a0cca9Swh ret = mc_set_mem_unum(p + strlen(p), blen, 1065d8a0cca9Swh flt_stat->mf_flt_maddr.ma_phys_bd, bank, flt_stat->mf_type, 1066d8a0cca9Swh flt_stat->mf_dimm_slot); 10670cc8ae86Sav 10680cc8ae86Sav if (ret != 0) { 10690cc8ae86Sav cmn_err(CE_WARN, 10700cc8ae86Sav "mc_ereport_post: Failed to determine the unum " 10710cc8ae86Sav "for board=%d bank=%d type=0x%x slot=0x%x", 10720cc8ae86Sav flt_stat->mf_flt_maddr.ma_bd, bank, 10730cc8ae86Sav flt_stat->mf_type, flt_stat->mf_dimm_slot); 10740cc8ae86Sav continue; 107525cf1a30Sjl } 10760cc8ae86Sav n = strlen(device_path); 107725cf1a30Sjl blen = MAXPATHLEN - n; 107825cf1a30Sjl p = &device_path[n]; 107925cf1a30Sjl if (i < (nflts - 1)) { 108025cf1a30Sjl snprintf(p, blen, " "); 10810cc8ae86Sav blen--; 10820cc8ae86Sav p++; 10830cc8ae86Sav } 10840cc8ae86Sav 10850cc8ae86Sav if (ret == 0) { 10860cc8ae86Sav ret = mc_set_mem_sid(mc_aflt->mflt_mcp, s + strlen(s), 1087aeb241b2Sav blen, flt_stat->mf_flt_maddr.ma_phys_bd, bank, 10880cc8ae86Sav flt_stat->mf_type, flt_stat->mf_dimm_slot); 10890cc8ae86Sav 109025cf1a30Sjl } 109125cf1a30Sjl } 109225cf1a30Sjl 1093d8a0cca9Swh (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, NULL, 1094d8a0cca9Swh device_path, (ret == 0) ? sid : NULL, (ret == 0) ? offset : 1095d8a0cca9Swh (uint64_t)-1); 109625cf1a30Sjl 1097d8a0cca9Swh fm_payload_set(ereport, MC_OPL_RESOURCE, DATA_TYPE_NVLIST, resource, 1098d8a0cca9Swh NULL); 109925cf1a30Sjl 110025cf1a30Sjl if (panicstr) { 110125cf1a30Sjl errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 110225cf1a30Sjl } else { 110325cf1a30Sjl (void) fm_ereport_post(ereport, EVCH_TRYHARD); 110425cf1a30Sjl fm_nvlist_destroy(ereport, FM_NVA_FREE); 110525cf1a30Sjl fm_nvlist_destroy(detector, FM_NVA_FREE); 110625cf1a30Sjl fm_nvlist_destroy(resource, FM_NVA_FREE); 110725cf1a30Sjl } 110825cf1a30Sjl } 110925cf1a30Sjl 11100cc8ae86Sav 111125cf1a30Sjl static void 111225cf1a30Sjl mc_err_drain(mc_aflt_t *mc_aflt) 111325cf1a30Sjl { 111425cf1a30Sjl int rv; 111525cf1a30Sjl uint64_t pa = (uint64_t)(-1); 11160cc8ae86Sav int i; 111725cf1a30Sjl 1118d8a0cca9Swh MC_LOG("mc_err_drain: %s\n", mc_aflt->mflt_erpt_class); 111925cf1a30Sjl /* 112025cf1a30Sjl * we come here only when we have: 11211039f409Sav * In mirror mode: MUE, SUE 1122056c948bStsien * In normal mode: UE, Permanent CE, Intermittent CE 112325cf1a30Sjl */ 11240cc8ae86Sav for (i = 0; i < mc_aflt->mflt_nflts; i++) { 11250cc8ae86Sav rv = mcaddr_to_pa(mc_aflt->mflt_mcp, 1126d8a0cca9Swh &(mc_aflt->mflt_stat[i]->mf_flt_maddr), &pa); 1127738dd194Shyw 1128738dd194Shyw /* Ensure the pa is valid (not in isolated memory block) */ 1129738dd194Shyw if (rv == 0 && pa_is_valid(mc_aflt->mflt_mcp, pa)) 11300cc8ae86Sav mc_aflt->mflt_stat[i]->mf_flt_paddr = pa; 11310cc8ae86Sav else 11320cc8ae86Sav mc_aflt->mflt_stat[i]->mf_flt_paddr = (uint64_t)-1; 11330cc8ae86Sav } 11340cc8ae86Sav 1135738dd194Shyw MC_LOG("mc_err_drain:pa = %lx\n", pa); 113625cf1a30Sjl 1137738dd194Shyw switch (page_retire_check(pa, NULL)) { 1138738dd194Shyw case 0: 1139738dd194Shyw case EAGAIN: 1140738dd194Shyw MC_LOG("Page retired or pending\n"); 1141738dd194Shyw return; 1142738dd194Shyw case EIO: 1143738dd194Shyw /* 1144056c948bStsien * Do page retirement except for the PCE and ICE cases. 1145738dd194Shyw * This is taken care by the OPL DE 1146738dd194Shyw */ 1147056c948bStsien if (mc_aflt->mflt_stat[0]->mf_type != 1148056c948bStsien FLT_TYPE_INTERMITTENT_CE && 1149056c948bStsien mc_aflt->mflt_stat[0]->mf_type != FLT_TYPE_PERMANENT_CE) { 1150738dd194Shyw MC_LOG("offline page at pa %lx error %x\n", pa, 1151d8a0cca9Swh mc_aflt->mflt_pr); 1152738dd194Shyw (void) page_retire(pa, mc_aflt->mflt_pr); 115325cf1a30Sjl } 1154738dd194Shyw break; 1155738dd194Shyw case EINVAL: 1156738dd194Shyw default: 1157738dd194Shyw /* 1158738dd194Shyw * Some memory do not have page structure so 1159738dd194Shyw * we keep going in case of EINVAL. 1160738dd194Shyw */ 1161738dd194Shyw break; 116225cf1a30Sjl } 116325cf1a30Sjl 11640cc8ae86Sav for (i = 0; i < mc_aflt->mflt_nflts; i++) { 11650cc8ae86Sav mc_aflt_t mc_aflt0; 11660cc8ae86Sav if (mc_aflt->mflt_stat[i]->mf_flt_paddr != (uint64_t)-1) { 11670cc8ae86Sav mc_aflt0 = *mc_aflt; 11680cc8ae86Sav mc_aflt0.mflt_nflts = 1; 11690cc8ae86Sav mc_aflt0.mflt_stat[0] = mc_aflt->mflt_stat[i]; 11700cc8ae86Sav mc_ereport_post(&mc_aflt0); 11710cc8ae86Sav } 11720cc8ae86Sav } 11730cc8ae86Sav } 117425cf1a30Sjl 117525cf1a30Sjl /* 117625cf1a30Sjl * The restart address is actually defined in unit of PA[37:6] 117725cf1a30Sjl * the mac patrol will convert that to dimm offset. If the 117825cf1a30Sjl * address is not in the bank, it will continue to search for 117925cf1a30Sjl * the next PA that is within the bank. 118025cf1a30Sjl * 118125cf1a30Sjl * Also the mac patrol scans the dimms based on PA, not 118225cf1a30Sjl * dimm offset. 118325cf1a30Sjl */ 118425cf1a30Sjl static int 1185738dd194Shyw restart_patrol(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr_info) 118625cf1a30Sjl { 118725cf1a30Sjl uint64_t pa; 118825cf1a30Sjl int rv; 118925cf1a30Sjl 1190601c2e1eSdhain if (MC_REWRITE_MODE(mcp, bank)) { 1191601c2e1eSdhain return (0); 1192601c2e1eSdhain } 1193738dd194Shyw if (rsaddr_info == NULL || (rsaddr_info->mi_valid == 0)) { 119425cf1a30Sjl MAC_PTRL_START(mcp, bank); 119525cf1a30Sjl return (0); 119625cf1a30Sjl } 119725cf1a30Sjl 1198738dd194Shyw rv = mcaddr_to_pa(mcp, &rsaddr_info->mi_restartaddr, &pa); 119925cf1a30Sjl if (rv != 0) { 120025cf1a30Sjl MC_LOG("cannot convert mcaddr to pa. use auto restart\n"); 120125cf1a30Sjl MAC_PTRL_START(mcp, bank); 120225cf1a30Sjl return (0); 120325cf1a30Sjl } 120425cf1a30Sjl 1205738dd194Shyw if (!mc_rangecheck_pa(mcp, pa)) { 120625cf1a30Sjl /* pa is not on this board, just retry */ 120725cf1a30Sjl cmn_err(CE_WARN, "restart_patrol: invalid address %lx " 1208d8a0cca9Swh "on board %d\n", pa, mcp->mc_board_num); 120925cf1a30Sjl MAC_PTRL_START(mcp, bank); 121025cf1a30Sjl return (0); 121125cf1a30Sjl } 121225cf1a30Sjl 121325cf1a30Sjl MC_LOG("restart_patrol: pa = %lx\n", pa); 121425cf1a30Sjl 1215738dd194Shyw if (!rsaddr_info->mi_injectrestart) { 1216738dd194Shyw /* 12171039f409Sav * For non-error injection restart we need to 1218738dd194Shyw * determine if the current restart pa/page is 1219738dd194Shyw * a "good" page. A "good" page is a page that 1220738dd194Shyw * has not been page retired. If the current 1221738dd194Shyw * page that contains the pa is "good", we will 1222738dd194Shyw * do a HW auto restart and let HW patrol continue 1223738dd194Shyw * where it last stopped. Most desired scenario. 1224738dd194Shyw * 1225738dd194Shyw * If the current page is not "good", we will advance 1226738dd194Shyw * to the next page to find the next "good" page and 1227738dd194Shyw * restart the patrol from there. 1228738dd194Shyw */ 1229738dd194Shyw int wrapcount = 0; 1230738dd194Shyw uint64_t origpa = pa; 1231738dd194Shyw while (wrapcount < 2) { 1232d8a0cca9Swh if (!pa_is_valid(mcp, pa)) { 1233601c2e1eSdhain /* 1234601c2e1eSdhain * Not in physinstall - advance to the 1235601c2e1eSdhain * next memory isolation blocksize 1236601c2e1eSdhain */ 1237601c2e1eSdhain MC_LOG("Invalid PA\n"); 1238601c2e1eSdhain pa = roundup(pa + 1, mc_isolation_bsize); 1239d8a0cca9Swh } else { 1240601c2e1eSdhain int rv; 1241601c2e1eSdhain if ((rv = page_retire_check(pa, NULL)) != 0 && 1242601c2e1eSdhain rv != EAGAIN) { 1243d8a0cca9Swh /* 1244d8a0cca9Swh * The page is "good" (not retired), 1245d8a0cca9Swh * we will use automatic HW restart 1246d8a0cca9Swh * algorithm if this is the original 1247d8a0cca9Swh * current starting page. 1248d8a0cca9Swh */ 1249601c2e1eSdhain if (pa == origpa) { 1250601c2e1eSdhain MC_LOG("Page has no error. " 1251601c2e1eSdhain "Auto restart\n"); 1252601c2e1eSdhain MAC_PTRL_START(mcp, bank); 1253601c2e1eSdhain return (0); 1254601c2e1eSdhain } else { 1255601c2e1eSdhain /* 1256601c2e1eSdhain * found a subsequent good page 1257601c2e1eSdhain */ 1258601c2e1eSdhain break; 1259738dd194Shyw } 1260601c2e1eSdhain } 1261738dd194Shyw 1262601c2e1eSdhain /* 1263601c2e1eSdhain * Skip to the next page 1264601c2e1eSdhain */ 1265601c2e1eSdhain pa = roundup(pa + 1, PAGESIZE); 1266601c2e1eSdhain MC_LOG("Skipping bad page to %lx\n", pa); 1267d8a0cca9Swh } 1268738dd194Shyw 1269601c2e1eSdhain /* Check to see if we hit the end of the memory range */ 1270d8a0cca9Swh if (pa >= (mcp->mc_start_address + mcp->mc_size)) { 1271601c2e1eSdhain MC_LOG("Wrap around\n"); 1272601c2e1eSdhain pa = mcp->mc_start_address; 1273601c2e1eSdhain wrapcount++; 1274d8a0cca9Swh } 1275738dd194Shyw } 1276738dd194Shyw 1277738dd194Shyw if (wrapcount > 1) { 1278d8a0cca9Swh MC_LOG("Failed to find a good page. Just restart\n"); 1279d8a0cca9Swh MAC_PTRL_START(mcp, bank); 1280d8a0cca9Swh return (0); 128125cf1a30Sjl } 128225cf1a30Sjl } 128325cf1a30Sjl 1284738dd194Shyw /* 1285738dd194Shyw * We reached here either: 1286738dd194Shyw * 1. We are doing an error injection restart that specify 1287738dd194Shyw * the exact pa/page to restart. OR 1288738dd194Shyw * 2. We found a subsequent good page different from the 1289738dd194Shyw * original restart pa/page. 1290738dd194Shyw * Restart MAC patrol: PA[37:6] 1291738dd194Shyw */ 129225cf1a30Sjl MC_LOG("restart at pa = %lx\n", pa); 129325cf1a30Sjl ST_MAC_REG(MAC_RESTART_ADD(mcp, bank), MAC_RESTART_PA(pa)); 129425cf1a30Sjl MAC_PTRL_START_ADD(mcp, bank); 129525cf1a30Sjl 129625cf1a30Sjl return (0); 129725cf1a30Sjl } 129825cf1a30Sjl 1299601c2e1eSdhain static void 1300601c2e1eSdhain mc_retry_info_put(mc_retry_info_t **q, mc_retry_info_t *p) 1301601c2e1eSdhain { 1302601c2e1eSdhain ASSERT(p != NULL); 1303601c2e1eSdhain p->ri_next = *q; 1304601c2e1eSdhain *q = p; 1305601c2e1eSdhain } 1306601c2e1eSdhain 1307601c2e1eSdhain static mc_retry_info_t * 1308601c2e1eSdhain mc_retry_info_get(mc_retry_info_t **q) 1309601c2e1eSdhain { 1310601c2e1eSdhain mc_retry_info_t *p; 1311601c2e1eSdhain 1312601c2e1eSdhain if ((p = *q) != NULL) { 1313601c2e1eSdhain *q = p->ri_next; 1314601c2e1eSdhain return (p); 1315601c2e1eSdhain } else { 1316601c2e1eSdhain return (NULL); 1317601c2e1eSdhain } 1318601c2e1eSdhain } 1319601c2e1eSdhain 132025cf1a30Sjl /* 132125cf1a30Sjl * Rewriting is used for two purposes. 132225cf1a30Sjl * - to correct the error in memory. 132325cf1a30Sjl * - to determine whether the error is permanent or intermittent. 132425cf1a30Sjl * It's done by writing the address in MAC_BANKm_REWRITE_ADD 132525cf1a30Sjl * and issuing REW_REQ command in MAC_BANKm_PTRL_CNRL. After that, 132625cf1a30Sjl * REW_END (and REW_CE/REW_UE if some error detected) is set when 132725cf1a30Sjl * rewrite operation is done. See 4.7.3 and 4.7.11 in Columbus2 PRM. 132825cf1a30Sjl * 132925cf1a30Sjl * Note that rewrite operation doesn't change RAW_UE to Marked UE. 133025cf1a30Sjl * Therefore, we use it only CE case. 133125cf1a30Sjl */ 1332601c2e1eSdhain 133325cf1a30Sjl static uint32_t 1334601c2e1eSdhain do_rewrite(mc_opl_t *mcp, int bank, uint32_t dimm_addr, int retrying) 133525cf1a30Sjl { 133625cf1a30Sjl uint32_t cntl; 133725cf1a30Sjl int count = 0; 1338601c2e1eSdhain int max_count; 1339601c2e1eSdhain int retry_state; 1340601c2e1eSdhain 1341601c2e1eSdhain if (retrying) 1342601c2e1eSdhain max_count = 1; 1343601c2e1eSdhain else 1344601c2e1eSdhain max_count = mc_max_rewrite_loop; 1345601c2e1eSdhain 1346601c2e1eSdhain retry_state = RETRY_STATE_PENDING; 1347601c2e1eSdhain 1348601c2e1eSdhain if (!retrying && MC_REWRITE_MODE(mcp, bank)) { 1349601c2e1eSdhain goto timeout; 1350601c2e1eSdhain } 1351601c2e1eSdhain 1352601c2e1eSdhain retry_state = RETRY_STATE_ACTIVE; 135325cf1a30Sjl 135425cf1a30Sjl /* first wait to make sure PTRL_STATUS is 0 */ 1355601c2e1eSdhain while (count++ < max_count) { 135625cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 1357601c2e1eSdhain if (!(cntl & MAC_CNTL_PTRL_STATUS)) { 1358601c2e1eSdhain count = 0; 135925cf1a30Sjl break; 1360601c2e1eSdhain } 13610cc8ae86Sav drv_usecwait(mc_rewrite_delay); 136225cf1a30Sjl } 1363601c2e1eSdhain if (count >= max_count) 1364601c2e1eSdhain goto timeout; 136525cf1a30Sjl 136625cf1a30Sjl count = 0; 136725cf1a30Sjl 136825cf1a30Sjl ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), dimm_addr); 136925cf1a30Sjl MAC_REW_REQ(mcp, bank); 137025cf1a30Sjl 1371601c2e1eSdhain retry_state = RETRY_STATE_REWRITE; 1372601c2e1eSdhain 137325cf1a30Sjl do { 1374601c2e1eSdhain if (count++ > max_count) { 1375601c2e1eSdhain goto timeout; 13760cc8ae86Sav } else { 13770cc8ae86Sav drv_usecwait(mc_rewrite_delay); 13780cc8ae86Sav } 1379601c2e1eSdhain cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 138025cf1a30Sjl /* 138125cf1a30Sjl * If there are other MEMORY or PCI activities, this 138225cf1a30Sjl * will be BUSY, else it should be set immediately 138325cf1a30Sjl */ 138425cf1a30Sjl } while (!(cntl & MAC_CNTL_REW_END)); 138525cf1a30Sjl 138625cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS); 138725cf1a30Sjl return (cntl); 1388601c2e1eSdhain timeout: 1389601c2e1eSdhain mc_set_rewrite(mcp, bank, dimm_addr, retry_state); 1390601c2e1eSdhain 1391601c2e1eSdhain return (0); 1392601c2e1eSdhain } 1393601c2e1eSdhain 1394601c2e1eSdhain void 1395601c2e1eSdhain mc_clear_rewrite(mc_opl_t *mcp, int bank) 1396601c2e1eSdhain { 1397601c2e1eSdhain struct mc_bank *bankp; 1398601c2e1eSdhain mc_retry_info_t *retry; 1399601c2e1eSdhain uint32_t rew_addr; 1400601c2e1eSdhain 1401601c2e1eSdhain bankp = &(mcp->mc_bank[bank]); 1402601c2e1eSdhain retry = bankp->mcb_active; 1403601c2e1eSdhain bankp->mcb_active = NULL; 1404601c2e1eSdhain mc_retry_info_put(&bankp->mcb_retry_freelist, retry); 1405601c2e1eSdhain 1406601c2e1eSdhain again: 1407601c2e1eSdhain bankp->mcb_rewrite_count = 0; 1408601c2e1eSdhain 1409601c2e1eSdhain while (retry = mc_retry_info_get(&bankp->mcb_retry_pending)) { 1410601c2e1eSdhain rew_addr = retry->ri_addr; 1411601c2e1eSdhain mc_retry_info_put(&bankp->mcb_retry_freelist, retry); 1412601c2e1eSdhain if (do_rewrite(mcp, bank, rew_addr, 1) == 0) 1413601c2e1eSdhain break; 1414601c2e1eSdhain } 1415601c2e1eSdhain 1416601c2e1eSdhain /* we break out if no more pending rewrite or we got timeout again */ 1417601c2e1eSdhain 1418601c2e1eSdhain if (!bankp->mcb_active && !bankp->mcb_retry_pending) { 1419601c2e1eSdhain if (!IS_MIRROR(mcp, bank)) { 1420601c2e1eSdhain MC_CLEAR_REWRITE_MODE(mcp, bank); 1421601c2e1eSdhain } else { 1422601c2e1eSdhain int mbank = bank ^ 1; 1423601c2e1eSdhain bankp = &(mcp->mc_bank[mbank]); 1424601c2e1eSdhain if (!bankp->mcb_active && !bankp->mcb_retry_pending) { 1425601c2e1eSdhain MC_CLEAR_REWRITE_MODE(mcp, bank); 1426601c2e1eSdhain MC_CLEAR_REWRITE_MODE(mcp, mbank); 1427601c2e1eSdhain } else { 1428601c2e1eSdhain bank = mbank; 1429601c2e1eSdhain goto again; 1430601c2e1eSdhain } 1431601c2e1eSdhain } 1432601c2e1eSdhain } 143325cf1a30Sjl } 1434601c2e1eSdhain 1435601c2e1eSdhain void 1436601c2e1eSdhain mc_set_rewrite(mc_opl_t *mcp, int bank, uint32_t addr, int state) 1437601c2e1eSdhain { 1438601c2e1eSdhain mc_retry_info_t *retry; 1439601c2e1eSdhain struct mc_bank *bankp; 1440601c2e1eSdhain 1441601c2e1eSdhain bankp = &mcp->mc_bank[bank]; 1442601c2e1eSdhain 1443601c2e1eSdhain retry = mc_retry_info_get(&bankp->mcb_retry_freelist); 1444601c2e1eSdhain 14450b240fcdSwh if (retry == NULL) { 14460b240fcdSwh mc_addr_t maddr; 14470b240fcdSwh uint64_t paddr; 14480b240fcdSwh /* 14490b240fcdSwh * previous rewrite request has not completed yet. 14500b240fcdSwh * So we discard this rewrite request. 14510b240fcdSwh */ 14520b240fcdSwh maddr.ma_bd = mcp->mc_board_num; 14530b240fcdSwh maddr.ma_bank = bank; 14540b240fcdSwh maddr.ma_dimm_addr = addr; 14550b240fcdSwh if (mcaddr_to_pa(mcp, &maddr, &paddr) == 0) { 14560b240fcdSwh cmn_err(CE_WARN, "Discard CE rewrite request" 14570b240fcdSwh " for 0x%lx (/LSB%d/B%d/%x).\n", 14580b240fcdSwh paddr, mcp->mc_board_num, bank, addr); 14590b240fcdSwh } else { 14600b240fcdSwh cmn_err(CE_WARN, "Discard CE rewrite request" 14610b240fcdSwh " for /LSB%d/B%d/%x.\n", 14620b240fcdSwh mcp->mc_board_num, bank, addr); 14630b240fcdSwh } 14640b240fcdSwh return; 14650b240fcdSwh } 1466601c2e1eSdhain 1467601c2e1eSdhain retry->ri_addr = addr; 1468601c2e1eSdhain retry->ri_state = state; 1469601c2e1eSdhain 1470601c2e1eSdhain MC_SET_REWRITE_MODE(mcp, bank); 1471601c2e1eSdhain 1472601c2e1eSdhain if ((state > RETRY_STATE_PENDING)) { 1473601c2e1eSdhain ASSERT(bankp->mcb_active == NULL); 1474601c2e1eSdhain bankp->mcb_active = retry; 1475601c2e1eSdhain } else { 1476601c2e1eSdhain mc_retry_info_put(&bankp->mcb_retry_pending, retry); 1477601c2e1eSdhain } 1478601c2e1eSdhain 1479601c2e1eSdhain if (IS_MIRROR(mcp, bank)) { 1480601c2e1eSdhain int mbank = bank ^1; 1481601c2e1eSdhain MC_SET_REWRITE_MODE(mcp, mbank); 1482601c2e1eSdhain } 1483601c2e1eSdhain } 1484601c2e1eSdhain 148525cf1a30Sjl void 148625cf1a30Sjl mc_process_scf_log(mc_opl_t *mcp) 148725cf1a30Sjl { 14880cc8ae86Sav int count; 14890cc8ae86Sav int n = 0; 149025cf1a30Sjl scf_log_t *p; 149125cf1a30Sjl int bank; 149225cf1a30Sjl 14930cc8ae86Sav for (bank = 0; bank < BANKNUM_PER_SB; bank++) { 1494d8a0cca9Swh while ((p = mcp->mc_scf_log[bank]) != NULL && 1495d8a0cca9Swh (n < mc_max_errlog_processed)) { 1496601c2e1eSdhain ASSERT(bank == p->sl_bank); 1497601c2e1eSdhain count = 0; 1498601c2e1eSdhain while ((LD_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank)) 1499601c2e1eSdhain & MAC_STATIC_ERR_VLD)) { 1500601c2e1eSdhain if (count++ >= (mc_max_scf_loop)) { 1501601c2e1eSdhain break; 150225cf1a30Sjl } 1503601c2e1eSdhain drv_usecwait(mc_scf_delay); 1504601c2e1eSdhain } 150525cf1a30Sjl 1506601c2e1eSdhain if (count < mc_max_scf_loop) { 1507601c2e1eSdhain ST_MAC_REG(MAC_STATIC_ERR_LOG(mcp, p->sl_bank), 1508601c2e1eSdhain p->sl_err_log); 150925cf1a30Sjl 1510601c2e1eSdhain ST_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank), 1511601c2e1eSdhain p->sl_err_add|MAC_STATIC_ERR_VLD); 1512601c2e1eSdhain mcp->mc_scf_retry[bank] = 0; 1513601c2e1eSdhain } else { 1514601c2e1eSdhain /* 1515601c2e1eSdhain * if we try too many times, just drop the req 1516601c2e1eSdhain */ 1517601c2e1eSdhain if (mcp->mc_scf_retry[bank]++ <= 1518601c2e1eSdhain mc_max_scf_retry) { 1519601c2e1eSdhain return; 152025cf1a30Sjl } else { 1521601c2e1eSdhain if ((++mc_pce_dropped & 0xff) == 0) { 1522601c2e1eSdhain cmn_err(CE_WARN, "Cannot " 15230b240fcdSwh "report CE to SCF\n"); 1524d8a0cca9Swh } 152525cf1a30Sjl } 1526601c2e1eSdhain } 1527601c2e1eSdhain n++; 1528601c2e1eSdhain mcp->mc_scf_log[bank] = p->sl_next; 1529601c2e1eSdhain mcp->mc_scf_total[bank]--; 1530601c2e1eSdhain ASSERT(mcp->mc_scf_total[bank] >= 0); 1531601c2e1eSdhain kmem_free(p, sizeof (scf_log_t)); 153225cf1a30Sjl } 153325cf1a30Sjl } 153425cf1a30Sjl } 153525cf1a30Sjl void 153625cf1a30Sjl mc_queue_scf_log(mc_opl_t *mcp, mc_flt_stat_t *flt_stat, int bank) 153725cf1a30Sjl { 153825cf1a30Sjl scf_log_t *p; 153925cf1a30Sjl 15400cc8ae86Sav if (mcp->mc_scf_total[bank] >= mc_max_scf_logs) { 15410cc8ae86Sav if ((++mc_pce_dropped & 0xff) == 0) { 15420b240fcdSwh cmn_err(CE_WARN, "Too many CE requests.\n"); 15430cc8ae86Sav } 154425cf1a30Sjl return; 154525cf1a30Sjl } 154625cf1a30Sjl p = kmem_zalloc(sizeof (scf_log_t), KM_SLEEP); 154725cf1a30Sjl p->sl_next = 0; 154825cf1a30Sjl p->sl_err_add = flt_stat->mf_err_add; 154925cf1a30Sjl p->sl_err_log = flt_stat->mf_err_log; 155025cf1a30Sjl p->sl_bank = bank; 155125cf1a30Sjl 15520cc8ae86Sav if (mcp->mc_scf_log[bank] == NULL) { 155325cf1a30Sjl /* 155425cf1a30Sjl * we rely on mc_scf_log to detect NULL queue. 155525cf1a30Sjl * mc_scf_log_tail is irrelevant is such case. 155625cf1a30Sjl */ 15570cc8ae86Sav mcp->mc_scf_log_tail[bank] = mcp->mc_scf_log[bank] = p; 155825cf1a30Sjl } else { 15590cc8ae86Sav mcp->mc_scf_log_tail[bank]->sl_next = p; 15600cc8ae86Sav mcp->mc_scf_log_tail[bank] = p; 156125cf1a30Sjl } 15620cc8ae86Sav mcp->mc_scf_total[bank]++; 156325cf1a30Sjl } 156425cf1a30Sjl /* 156525cf1a30Sjl * This routine determines what kind of CE happens, intermittent 156625cf1a30Sjl * or permanent as follows. (See 4.7.3 in Columbus2 PRM.) 156725cf1a30Sjl * - Do rewrite by issuing REW_REQ command to MAC_PTRL_CNTL register. 156825cf1a30Sjl * - If CE is still detected on the same address even after doing 156925cf1a30Sjl * rewrite operation twice, it is determined as permanent error. 157025cf1a30Sjl * - If error is not detected anymore, it is determined as intermittent 157125cf1a30Sjl * error. 157225cf1a30Sjl * - If UE is detected due to rewrite operation, it should be treated 157325cf1a30Sjl * as UE. 157425cf1a30Sjl */ 157525cf1a30Sjl 157625cf1a30Sjl /* ARGSUSED */ 157725cf1a30Sjl static void 157825cf1a30Sjl mc_scrub_ce(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat, int ptrl_error) 157925cf1a30Sjl { 158025cf1a30Sjl uint32_t cntl; 158125cf1a30Sjl int i; 158225cf1a30Sjl 158325cf1a30Sjl flt_stat->mf_type = FLT_TYPE_PERMANENT_CE; 158425cf1a30Sjl /* 158525cf1a30Sjl * rewrite request 1st time reads and correct error data 158625cf1a30Sjl * and write to DIMM. 2nd rewrite request must be issued 158725cf1a30Sjl * after REW_CE/UE/END is 0. When the 2nd request is completed, 158825cf1a30Sjl * if REW_CE = 1, then it is permanent CE. 158925cf1a30Sjl */ 159025cf1a30Sjl for (i = 0; i < 2; i++) { 1591601c2e1eSdhain cntl = do_rewrite(mcp, bank, flt_stat->mf_err_add, 0); 1592601c2e1eSdhain 1593601c2e1eSdhain if (cntl == 0) { 1594601c2e1eSdhain /* timeout case */ 1595601c2e1eSdhain return; 1596601c2e1eSdhain } 159725cf1a30Sjl /* 159825cf1a30Sjl * If the error becomes UE or CMPE 159925cf1a30Sjl * we return to the caller immediately. 160025cf1a30Sjl */ 160125cf1a30Sjl if (cntl & MAC_CNTL_REW_UE) { 160225cf1a30Sjl if (ptrl_error) 160325cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_PTRL_UE; 160425cf1a30Sjl else 160525cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_MI_UE; 160625cf1a30Sjl flt_stat->mf_type = FLT_TYPE_UE; 160725cf1a30Sjl return; 160825cf1a30Sjl } 160925cf1a30Sjl if (cntl & MAC_CNTL_REW_CMPE) { 161025cf1a30Sjl if (ptrl_error) 161125cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_PTRL_CMPE; 161225cf1a30Sjl else 161325cf1a30Sjl flt_stat->mf_cntl |= MAC_CNTL_MI_CMPE; 161425cf1a30Sjl flt_stat->mf_type = FLT_TYPE_CMPE; 161525cf1a30Sjl return; 161625cf1a30Sjl } 161725cf1a30Sjl } 161825cf1a30Sjl if (!(cntl & MAC_CNTL_REW_CE)) { 161925cf1a30Sjl flt_stat->mf_type = FLT_TYPE_INTERMITTENT_CE; 162025cf1a30Sjl } 162125cf1a30Sjl 162225cf1a30Sjl if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 162325cf1a30Sjl /* report PERMANENT_CE to SP via SCF */ 162425cf1a30Sjl if (!(flt_stat->mf_err_log & MAC_ERR_LOG_INVALID)) { 162525cf1a30Sjl mc_queue_scf_log(mcp, flt_stat, bank); 162625cf1a30Sjl } 162725cf1a30Sjl } 162825cf1a30Sjl } 162925cf1a30Sjl 163025cf1a30Sjl #define IS_CMPE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CMPE :\ 163125cf1a30Sjl MAC_CNTL_MI_CMPE)) 163225cf1a30Sjl #define IS_UE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_UE : MAC_CNTL_MI_UE)) 163325cf1a30Sjl #define IS_CE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CE : MAC_CNTL_MI_CE)) 163425cf1a30Sjl #define IS_OK(cntl, f) (!((cntl) & ((f) ? MAC_CNTL_PTRL_ERRS : \ 163525cf1a30Sjl MAC_CNTL_MI_ERRS))) 163625cf1a30Sjl 163725cf1a30Sjl 163825cf1a30Sjl static int 163925cf1a30Sjl IS_CE_ONLY(uint32_t cntl, int ptrl_error) 164025cf1a30Sjl { 164125cf1a30Sjl if (ptrl_error) { 164225cf1a30Sjl return ((cntl & MAC_CNTL_PTRL_ERRS) == MAC_CNTL_PTRL_CE); 164325cf1a30Sjl } else { 164425cf1a30Sjl return ((cntl & MAC_CNTL_MI_ERRS) == MAC_CNTL_MI_CE); 164525cf1a30Sjl } 164625cf1a30Sjl } 164725cf1a30Sjl 164825cf1a30Sjl void 164925cf1a30Sjl mc_write_cntl(mc_opl_t *mcp, int bank, uint32_t value) 165025cf1a30Sjl { 165137afe445Shyw int ebank = (IS_MIRROR(mcp, bank)) ? MIRROR_IDX(bank) : bank; 165237afe445Shyw 165337afe445Shyw if (mcp->mc_speedup_period[ebank] > 0) 16540cc8ae86Sav value |= mc_max_speed; 16550cc8ae86Sav else 16560cc8ae86Sav value |= mcp->mc_speed; 165725cf1a30Sjl ST_MAC_REG(MAC_PTRL_CNTL(mcp, bank), value); 165825cf1a30Sjl } 165925cf1a30Sjl 166025cf1a30Sjl static void 166125cf1a30Sjl mc_read_ptrl_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 166225cf1a30Sjl { 166325cf1a30Sjl flt_stat->mf_cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 1664d8a0cca9Swh MAC_CNTL_PTRL_ERRS; 166525cf1a30Sjl flt_stat->mf_err_add = LD_MAC_REG(MAC_PTRL_ERR_ADD(mcp, bank)); 166625cf1a30Sjl flt_stat->mf_err_log = LD_MAC_REG(MAC_PTRL_ERR_LOG(mcp, bank)); 166725cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 1668aeb241b2Sav flt_stat->mf_flt_maddr.ma_phys_bd = mcp->mc_phys_board_num; 166925cf1a30Sjl flt_stat->mf_flt_maddr.ma_bank = bank; 167025cf1a30Sjl flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 167125cf1a30Sjl } 167225cf1a30Sjl 167325cf1a30Sjl static void 167425cf1a30Sjl mc_read_mi_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 167525cf1a30Sjl { 167625cf1a30Sjl uint32_t status, old_status; 167725cf1a30Sjl 1678d8a0cca9Swh status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & MAC_CNTL_MI_ERRS; 167925cf1a30Sjl old_status = 0; 168025cf1a30Sjl 168125cf1a30Sjl /* we keep reading until the status is stable */ 168225cf1a30Sjl while (old_status != status) { 168325cf1a30Sjl old_status = status; 1684d8a0cca9Swh flt_stat->mf_err_add = LD_MAC_REG(MAC_MI_ERR_ADD(mcp, bank)); 1685d8a0cca9Swh flt_stat->mf_err_log = LD_MAC_REG(MAC_MI_ERR_LOG(mcp, bank)); 168625cf1a30Sjl status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 1687d8a0cca9Swh MAC_CNTL_MI_ERRS; 168825cf1a30Sjl if (status == old_status) { 168925cf1a30Sjl break; 169025cf1a30Sjl } 169125cf1a30Sjl } 169225cf1a30Sjl 169325cf1a30Sjl flt_stat->mf_cntl = status; 169425cf1a30Sjl flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 1695aeb241b2Sav flt_stat->mf_flt_maddr.ma_phys_bd = mcp->mc_phys_board_num; 169625cf1a30Sjl flt_stat->mf_flt_maddr.ma_bank = bank; 169725cf1a30Sjl flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 169825cf1a30Sjl } 169925cf1a30Sjl 170025cf1a30Sjl 170125cf1a30Sjl /* 170225cf1a30Sjl * Error philosophy for mirror mode: 170325cf1a30Sjl * 170425cf1a30Sjl * PTRL (The error address for both banks are same, since ptrl stops if it 170525cf1a30Sjl * detects error.) 17061039f409Sav * - Compare error log CMPE. 170725cf1a30Sjl * 170825cf1a30Sjl * - UE-UE Report MUE. No rewrite. 170925cf1a30Sjl * 171025cf1a30Sjl * - UE-* UE-(CE/OK). Rewrite to scrub UE. Report SUE. 171125cf1a30Sjl * 171225cf1a30Sjl * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 171325cf1a30Sjl * If CE is permanent, inform SCF. Once for each 171425cf1a30Sjl * Dimm. If CE becomes UE or CMPE, go back to above. 171525cf1a30Sjl * 171625cf1a30Sjl * 171725cf1a30Sjl * MI (The error addresses for each bank are the same or different.) 17181039f409Sav * - Compare error If addresses are the same. Just CMPE, so log CMPE. 171925cf1a30Sjl * If addresses are different (this could happen 17201039f409Sav * as a result of scrubbing. Report each separately. 172125cf1a30Sjl * Only report error info on each side. 172225cf1a30Sjl * 172325cf1a30Sjl * - UE-UE Addresses are the same. Report MUE. 172425cf1a30Sjl * Addresses are different. Report SUE on each bank. 172525cf1a30Sjl * Rewrite to clear UE. 172625cf1a30Sjl * 172725cf1a30Sjl * - UE-* UE-(CE/OK) 172825cf1a30Sjl * Rewrite to clear UE. Report SUE for the bank. 172925cf1a30Sjl * 173025cf1a30Sjl * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 173125cf1a30Sjl * If CE becomes UE or CMPE, go back to above. 173225cf1a30Sjl * 173325cf1a30Sjl */ 173425cf1a30Sjl 173525cf1a30Sjl static int 173625cf1a30Sjl mc_process_error_mir(mc_opl_t *mcp, mc_aflt_t *mc_aflt, mc_flt_stat_t *flt_stat) 173725cf1a30Sjl { 173825cf1a30Sjl int ptrl_error = mc_aflt->mflt_is_ptrl; 173925cf1a30Sjl int i; 174025cf1a30Sjl int rv = 0; 1741601c2e1eSdhain int bank; 1742601c2e1eSdhain int rewrite_timeout = 0; 174325cf1a30Sjl 174425cf1a30Sjl MC_LOG("process mirror errors cntl[0] = %x, cntl[1] = %x\n", 1745d8a0cca9Swh flt_stat[0].mf_cntl, flt_stat[1].mf_cntl); 174625cf1a30Sjl 174725cf1a30Sjl if (ptrl_error) { 1748d8a0cca9Swh if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) & 1749d8a0cca9Swh MAC_CNTL_PTRL_ERRS) == 0) 175025cf1a30Sjl return (0); 175125cf1a30Sjl } else { 1752d8a0cca9Swh if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) & 1753d8a0cca9Swh MAC_CNTL_MI_ERRS) == 0) 175425cf1a30Sjl return (0); 175525cf1a30Sjl } 175625cf1a30Sjl 175725cf1a30Sjl /* 175825cf1a30Sjl * First we take care of the case of CE 175925cf1a30Sjl * because they can become UE or CMPE 176025cf1a30Sjl */ 176125cf1a30Sjl for (i = 0; i < 2; i++) { 176225cf1a30Sjl if (IS_CE_ONLY(flt_stat[i].mf_cntl, ptrl_error)) { 1763601c2e1eSdhain bank = flt_stat[i].mf_flt_maddr.ma_bank; 1764601c2e1eSdhain MC_LOG("CE detected on bank %d\n", bank); 1765601c2e1eSdhain mc_scrub_ce(mcp, bank, &flt_stat[i], ptrl_error); 1766601c2e1eSdhain if (MC_REWRITE_ACTIVE(mcp, bank)) { 1767601c2e1eSdhain rewrite_timeout = 1; 1768601c2e1eSdhain } 176925cf1a30Sjl rv = 1; 177025cf1a30Sjl } 177125cf1a30Sjl } 177225cf1a30Sjl 1773601c2e1eSdhain if (rewrite_timeout) 1774601c2e1eSdhain return (0); 1775601c2e1eSdhain 177625cf1a30Sjl /* The above scrubbing can turn CE into UE or CMPE */ 177725cf1a30Sjl 177825cf1a30Sjl /* 177925cf1a30Sjl * Now we distinguish two cases: same address or not 178025cf1a30Sjl * the same address. It might seem more intuitive to 178125cf1a30Sjl * distinguish PTRL v.s. MI error but it is more 178225cf1a30Sjl * complicated that way. 178325cf1a30Sjl */ 178425cf1a30Sjl 178525cf1a30Sjl if (flt_stat[0].mf_err_add == flt_stat[1].mf_err_add) { 178625cf1a30Sjl 178725cf1a30Sjl if (IS_CMPE(flt_stat[0].mf_cntl, ptrl_error) || 178825cf1a30Sjl IS_CMPE(flt_stat[1].mf_cntl, ptrl_error)) { 178925cf1a30Sjl flt_stat[0].mf_type = FLT_TYPE_CMPE; 179025cf1a30Sjl flt_stat[1].mf_type = FLT_TYPE_CMPE; 179125cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 179225cf1a30Sjl mc_aflt->mflt_nflts = 2; 179325cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[0]; 179425cf1a30Sjl mc_aflt->mflt_stat[1] = &flt_stat[1]; 179525cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 17961039f409Sav /* 17971039f409Sav * Compare error is result of MAC internal error, so 17981039f409Sav * simply log it instead of publishing an ereport. SCF 17991039f409Sav * diagnoses all the MAC internal and its i/f error. 18001039f409Sav */ 18011039f409Sav MC_LOG("cmpe error detected\n"); 180225cf1a30Sjl return (1); 180325cf1a30Sjl } 180425cf1a30Sjl 180525cf1a30Sjl if (IS_UE(flt_stat[0].mf_cntl, ptrl_error) && 1806d8a0cca9Swh IS_UE(flt_stat[1].mf_cntl, ptrl_error)) { 180725cf1a30Sjl /* Both side are UE's */ 180825cf1a30Sjl 180925cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[0]); 181025cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[1]); 181125cf1a30Sjl MC_LOG("MUE detected\n"); 18120cc8ae86Sav flt_stat[0].mf_type = FLT_TYPE_MUE; 18130cc8ae86Sav flt_stat[1].mf_type = FLT_TYPE_MUE; 181425cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_MUE; 181525cf1a30Sjl mc_aflt->mflt_nflts = 2; 181625cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[0]; 181725cf1a30Sjl mc_aflt->mflt_stat[1] = &flt_stat[1]; 181825cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 181925cf1a30Sjl mc_err_drain(mc_aflt); 182025cf1a30Sjl return (1); 182125cf1a30Sjl } 182225cf1a30Sjl 182325cf1a30Sjl /* Now the only case is UE/CE, UE/OK, or don't care */ 182425cf1a30Sjl for (i = 0; i < 2; i++) { 1825601c2e1eSdhain if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 18260cc8ae86Sav 18270cc8ae86Sav /* rewrite can clear the one side UE error */ 18280cc8ae86Sav 182925cf1a30Sjl if (IS_OK(flt_stat[i^1].mf_cntl, ptrl_error)) { 183025cf1a30Sjl (void) do_rewrite(mcp, 183125cf1a30Sjl flt_stat[i].mf_flt_maddr.ma_bank, 1832601c2e1eSdhain flt_stat[i].mf_flt_maddr.ma_dimm_addr, 0); 183325cf1a30Sjl } 183425cf1a30Sjl flt_stat[i].mf_type = FLT_TYPE_UE; 183525cf1a30Sjl MAC_SET_ERRLOG_INFO(&flt_stat[i]); 183625cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_SUE; 183725cf1a30Sjl mc_aflt->mflt_stat[0] = &flt_stat[i]; 183825cf1a30Sjl mc_aflt->mflt_nflts = 1; 183925cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 184025cf1a30Sjl mc_err_drain(mc_aflt); 184125cf1a30Sjl /* Once we hit a UE/CE or UE/OK case, done */ 184225cf1a30Sjl return (1); 1843601c2e1eSdhain } 184425cf1a30Sjl } 184525cf1a30Sjl 184625cf1a30Sjl } else { 184725cf1a30Sjl /* 184825cf1a30Sjl * addresses are different. That means errors 184925cf1a30Sjl * on the 2 banks are not related at all. 185025cf1a30Sjl */ 185125cf1a30Sjl for (i = 0; i < 2; i++) { 1852d8a0cca9Swh if (IS_CMPE(flt_stat[i].mf_cntl, ptrl_error)) { 1853d8a0cca9Swh flt_stat[i].mf_type = FLT_TYPE_CMPE; 1854d8a0cca9Swh mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 1855d8a0cca9Swh mc_aflt->mflt_nflts = 1; 1856d8a0cca9Swh mc_aflt->mflt_stat[0] = &flt_stat[i]; 1857d8a0cca9Swh mc_aflt->mflt_pr = PR_UE; 1858d8a0cca9Swh /* 1859d8a0cca9Swh * Compare error is result of MAC internal 1860d8a0cca9Swh * error, so simply log it instead of 1861d8a0cca9Swh * publishing an ereport. SCF diagnoses all 1862d8a0cca9Swh * the MAC internal and its interface error. 1863d8a0cca9Swh */ 1864d8a0cca9Swh MC_LOG("cmpe error detected\n"); 1865d8a0cca9Swh /* no more report on this bank */ 1866d8a0cca9Swh flt_stat[i].mf_cntl = 0; 1867d8a0cca9Swh rv = 1; 1868d8a0cca9Swh } 186925cf1a30Sjl } 187025cf1a30Sjl 18710cc8ae86Sav /* rewrite can clear the one side UE error */ 18720cc8ae86Sav 187325cf1a30Sjl for (i = 0; i < 2; i++) { 1874d8a0cca9Swh if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 1875d8a0cca9Swh (void) do_rewrite(mcp, 1876d8a0cca9Swh flt_stat[i].mf_flt_maddr.ma_bank, 1877601c2e1eSdhain flt_stat[i].mf_flt_maddr.ma_dimm_addr, 1878601c2e1eSdhain 0); 1879d8a0cca9Swh flt_stat[i].mf_type = FLT_TYPE_UE; 1880d8a0cca9Swh MAC_SET_ERRLOG_INFO(&flt_stat[i]); 1881d8a0cca9Swh mc_aflt->mflt_erpt_class = MC_OPL_SUE; 1882d8a0cca9Swh mc_aflt->mflt_stat[0] = &flt_stat[i]; 1883d8a0cca9Swh mc_aflt->mflt_nflts = 1; 1884d8a0cca9Swh mc_aflt->mflt_pr = PR_MCE; 1885d8a0cca9Swh mc_err_drain(mc_aflt); 1886d8a0cca9Swh rv = 1; 1887d8a0cca9Swh } 188825cf1a30Sjl } 188925cf1a30Sjl } 189025cf1a30Sjl return (rv); 189125cf1a30Sjl } 189225cf1a30Sjl static void 1893738dd194Shyw mc_error_handler_mir(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr) 189425cf1a30Sjl { 189525cf1a30Sjl mc_aflt_t mc_aflt; 189625cf1a30Sjl mc_flt_stat_t flt_stat[2], mi_flt_stat[2]; 18970cc8ae86Sav int i; 18980cc8ae86Sav int mi_valid; 189925cf1a30Sjl 1900738dd194Shyw ASSERT(rsaddr); 1901738dd194Shyw 190225cf1a30Sjl bzero(&mc_aflt, sizeof (mc_aflt_t)); 190325cf1a30Sjl bzero(&flt_stat, 2 * sizeof (mc_flt_stat_t)); 190425cf1a30Sjl bzero(&mi_flt_stat, 2 * sizeof (mc_flt_stat_t)); 190525cf1a30Sjl 1906ad59b69dSbm 190725cf1a30Sjl mc_aflt.mflt_mcp = mcp; 190825cf1a30Sjl mc_aflt.mflt_id = gethrtime(); 190925cf1a30Sjl 191025cf1a30Sjl /* Now read all the registers into flt_stat */ 191125cf1a30Sjl 19120cc8ae86Sav for (i = 0; i < 2; i++) { 19130cc8ae86Sav MC_LOG("Reading registers of bank %d\n", bank); 19140cc8ae86Sav /* patrol registers */ 19150cc8ae86Sav mc_read_ptrl_reg(mcp, bank, &flt_stat[i]); 191625cf1a30Sjl 1917738dd194Shyw /* 1918738dd194Shyw * In mirror mode, it is possible that only one bank 1919738dd194Shyw * may report the error. We need to check for it to 1920738dd194Shyw * ensure we pick the right addr value for patrol restart. 1921738dd194Shyw * Note that if both banks reported errors, we pick the 1922738dd194Shyw * 2nd one. Both banks should reported the same error address. 1923738dd194Shyw */ 1924738dd194Shyw if (flt_stat[i].mf_cntl & MAC_CNTL_PTRL_ERRS) 1925738dd194Shyw rsaddr->mi_restartaddr = flt_stat[i].mf_flt_maddr; 192625cf1a30Sjl 19270cc8ae86Sav MC_LOG("ptrl registers cntl %x add %x log %x\n", 1928d8a0cca9Swh flt_stat[i].mf_cntl, flt_stat[i].mf_err_add, 1929d8a0cca9Swh flt_stat[i].mf_err_log); 193025cf1a30Sjl 19310cc8ae86Sav /* MI registers */ 19320cc8ae86Sav mc_read_mi_reg(mcp, bank, &mi_flt_stat[i]); 193325cf1a30Sjl 19340cc8ae86Sav MC_LOG("MI registers cntl %x add %x log %x\n", 1935d8a0cca9Swh mi_flt_stat[i].mf_cntl, mi_flt_stat[i].mf_err_add, 1936d8a0cca9Swh mi_flt_stat[i].mf_err_log); 193725cf1a30Sjl 19380cc8ae86Sav bank = bank^1; 19390cc8ae86Sav } 194025cf1a30Sjl 194125cf1a30Sjl /* clear errors once we read all the registers */ 1942d8a0cca9Swh MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 194325cf1a30Sjl 19440cc8ae86Sav MAC_CLEAR_ERRS(mcp, bank ^ 1, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 19450cc8ae86Sav 19460cc8ae86Sav /* Process MI errors first */ 194725cf1a30Sjl 19480cc8ae86Sav /* if not error mode, cntl1 is 0 */ 19490cc8ae86Sav if ((mi_flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 1950d8a0cca9Swh (mi_flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 19510cc8ae86Sav mi_flt_stat[0].mf_cntl = 0; 19520cc8ae86Sav 19530cc8ae86Sav if ((mi_flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 1954d8a0cca9Swh (mi_flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 19550cc8ae86Sav mi_flt_stat[1].mf_cntl = 0; 195625cf1a30Sjl 19570cc8ae86Sav mc_aflt.mflt_is_ptrl = 0; 19580cc8ae86Sav mi_valid = mc_process_error_mir(mcp, &mc_aflt, &mi_flt_stat[0]); 19590cc8ae86Sav 19600cc8ae86Sav if ((((flt_stat[0].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 1961d8a0cca9Swh MAC_CNTL_PTRL_ERR_SHIFT) == ((mi_flt_stat[0].mf_cntl & 1962d8a0cca9Swh MAC_CNTL_MI_ERRS) >> MAC_CNTL_MI_ERR_SHIFT)) && 19630b240fcdSwh (flt_stat[0].mf_err_add == 19640b240fcdSwh ROUNDDOWN(mi_flt_stat[0].mf_err_add, MC_BOUND_BYTE)) && 1965d8a0cca9Swh (((flt_stat[1].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 1966d8a0cca9Swh MAC_CNTL_PTRL_ERR_SHIFT) == ((mi_flt_stat[1].mf_cntl & 1967d8a0cca9Swh MAC_CNTL_MI_ERRS) >> MAC_CNTL_MI_ERR_SHIFT)) && 19680b240fcdSwh (flt_stat[1].mf_err_add == 19690b240fcdSwh ROUNDDOWN(mi_flt_stat[1].mf_err_add, MC_BOUND_BYTE))) { 19700cc8ae86Sav #ifdef DEBUG 19710cc8ae86Sav MC_LOG("discarding PTRL error because " 19720cc8ae86Sav "it is the same as MI\n"); 19730cc8ae86Sav #endif 1974738dd194Shyw rsaddr->mi_valid = mi_valid; 19750cc8ae86Sav return; 19760cc8ae86Sav } 197725cf1a30Sjl /* if not error mode, cntl1 is 0 */ 197825cf1a30Sjl if ((flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 1979d8a0cca9Swh (flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 198025cf1a30Sjl flt_stat[0].mf_cntl = 0; 198125cf1a30Sjl 198225cf1a30Sjl if ((flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 1983d8a0cca9Swh (flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 198425cf1a30Sjl flt_stat[1].mf_cntl = 0; 198525cf1a30Sjl 198625cf1a30Sjl mc_aflt.mflt_is_ptrl = 1; 1987738dd194Shyw rsaddr->mi_valid = mc_process_error_mir(mcp, &mc_aflt, &flt_stat[0]); 198825cf1a30Sjl } 198925cf1a30Sjl static int 199025cf1a30Sjl mc_process_error(mc_opl_t *mcp, int bank, mc_aflt_t *mc_aflt, 199125cf1a30Sjl mc_flt_stat_t *flt_stat) 199225cf1a30Sjl { 199325cf1a30Sjl int ptrl_error = mc_aflt->mflt_is_ptrl; 199425cf1a30Sjl int rv = 0; 199525cf1a30Sjl 199625cf1a30Sjl mc_aflt->mflt_erpt_class = NULL; 199725cf1a30Sjl if (IS_UE(flt_stat->mf_cntl, ptrl_error)) { 19981039f409Sav MC_LOG("UE detected\n"); 199925cf1a30Sjl flt_stat->mf_type = FLT_TYPE_UE; 200025cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_UE; 200125cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 200225cf1a30Sjl MAC_SET_ERRLOG_INFO(flt_stat); 200325cf1a30Sjl rv = 1; 200425cf1a30Sjl } else if (IS_CE(flt_stat->mf_cntl, ptrl_error)) { 20051039f409Sav MC_LOG("CE detected\n"); 200625cf1a30Sjl MAC_SET_ERRLOG_INFO(flt_stat); 200725cf1a30Sjl 20081039f409Sav /* Error type can change after scrubbing */ 200925cf1a30Sjl mc_scrub_ce(mcp, bank, flt_stat, ptrl_error); 2010601c2e1eSdhain if (MC_REWRITE_ACTIVE(mcp, bank)) { 2011601c2e1eSdhain return (0); 2012601c2e1eSdhain } 201325cf1a30Sjl 2014056c948bStsien if (flt_stat->mf_type == FLT_TYPE_INTERMITTENT_CE) { 2015056c948bStsien mc_aflt->mflt_erpt_class = MC_OPL_ICE; 2016056c948bStsien mc_aflt->mflt_pr = PR_MCE; 2017056c948bStsien } else if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 201825cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_CE; 201925cf1a30Sjl mc_aflt->mflt_pr = PR_MCE; 202025cf1a30Sjl } else if (flt_stat->mf_type == FLT_TYPE_UE) { 202125cf1a30Sjl mc_aflt->mflt_erpt_class = MC_OPL_UE; 202225cf1a30Sjl mc_aflt->mflt_pr = PR_UE; 202325cf1a30Sjl } 202425cf1a30Sjl rv = 1; 202525cf1a30Sjl } 2026d8a0cca9Swh MC_LOG("mc_process_error: fault type %x erpt %s\n", flt_stat->mf_type, 2027d8a0cca9Swh mc_aflt->mflt_erpt_class); 202825cf1a30Sjl if (mc_aflt->mflt_erpt_class) { 202925cf1a30Sjl mc_aflt->mflt_stat[0] = flt_stat; 203025cf1a30Sjl mc_aflt->mflt_nflts = 1; 203125cf1a30Sjl mc_err_drain(mc_aflt); 203225cf1a30Sjl } 203325cf1a30Sjl return (rv); 203425cf1a30Sjl } 203525cf1a30Sjl 203625cf1a30Sjl static void 2037738dd194Shyw mc_error_handler(mc_opl_t *mcp, int bank, mc_rsaddr_info_t *rsaddr) 203825cf1a30Sjl { 203925cf1a30Sjl mc_aflt_t mc_aflt; 204025cf1a30Sjl mc_flt_stat_t flt_stat, mi_flt_stat; 20410cc8ae86Sav int mi_valid; 204225cf1a30Sjl 204325cf1a30Sjl bzero(&mc_aflt, sizeof (mc_aflt_t)); 204425cf1a30Sjl bzero(&flt_stat, sizeof (mc_flt_stat_t)); 204525cf1a30Sjl bzero(&mi_flt_stat, sizeof (mc_flt_stat_t)); 204625cf1a30Sjl 204725cf1a30Sjl mc_aflt.mflt_mcp = mcp; 204825cf1a30Sjl mc_aflt.mflt_id = gethrtime(); 204925cf1a30Sjl 205025cf1a30Sjl /* patrol registers */ 205125cf1a30Sjl mc_read_ptrl_reg(mcp, bank, &flt_stat); 205225cf1a30Sjl 2053738dd194Shyw ASSERT(rsaddr); 2054738dd194Shyw rsaddr->mi_restartaddr = flt_stat.mf_flt_maddr; 205525cf1a30Sjl 2056d8a0cca9Swh MC_LOG("ptrl registers cntl %x add %x log %x\n", flt_stat.mf_cntl, 2057d8a0cca9Swh flt_stat.mf_err_add, flt_stat.mf_err_log); 205825cf1a30Sjl 205925cf1a30Sjl /* MI registers */ 206025cf1a30Sjl mc_read_mi_reg(mcp, bank, &mi_flt_stat); 206125cf1a30Sjl 20620cc8ae86Sav 2063d8a0cca9Swh MC_LOG("MI registers cntl %x add %x log %x\n", mi_flt_stat.mf_cntl, 2064d8a0cca9Swh mi_flt_stat.mf_err_add, mi_flt_stat.mf_err_log); 206525cf1a30Sjl 206625cf1a30Sjl /* clear errors once we read all the registers */ 206725cf1a30Sjl MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 206825cf1a30Sjl 20690cc8ae86Sav mc_aflt.mflt_is_ptrl = 0; 20700cc8ae86Sav if ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) && 2071d8a0cca9Swh ((mi_flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 2072d8a0cca9Swh ((mi_flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 20730cc8ae86Sav mi_valid = mc_process_error(mcp, bank, &mc_aflt, &mi_flt_stat); 20740cc8ae86Sav } 20750cc8ae86Sav 20760cc8ae86Sav if ((((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) >> 2077d8a0cca9Swh MAC_CNTL_PTRL_ERR_SHIFT) == ((mi_flt_stat.mf_cntl & 2078d8a0cca9Swh MAC_CNTL_MI_ERRS) >> MAC_CNTL_MI_ERR_SHIFT)) && 20790b240fcdSwh (flt_stat.mf_err_add == 20800b240fcdSwh ROUNDDOWN(mi_flt_stat.mf_err_add, MC_BOUND_BYTE))) { 20810cc8ae86Sav #ifdef DEBUG 20820cc8ae86Sav MC_LOG("discarding PTRL error because " 20830cc8ae86Sav "it is the same as MI\n"); 20840cc8ae86Sav #endif 2085738dd194Shyw rsaddr->mi_valid = mi_valid; 20860cc8ae86Sav return; 20870cc8ae86Sav } 20880cc8ae86Sav 208925cf1a30Sjl mc_aflt.mflt_is_ptrl = 1; 209025cf1a30Sjl if ((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) && 2091d8a0cca9Swh ((flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 2092d8a0cca9Swh ((flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 2093d8a0cca9Swh rsaddr->mi_valid = mc_process_error(mcp, bank, &mc_aflt, 2094d8a0cca9Swh &flt_stat); 209525cf1a30Sjl } 209625cf1a30Sjl } 209725cf1a30Sjl /* 209825cf1a30Sjl * memory patrol error handling algorithm: 209925cf1a30Sjl * timeout() is used to do periodic polling 210025cf1a30Sjl * This is the flow chart. 210125cf1a30Sjl * timeout -> 210225cf1a30Sjl * mc_check_errors() 210325cf1a30Sjl * if memory bank is installed, read the status register 210425cf1a30Sjl * if any error bit is set, 210525cf1a30Sjl * -> mc_error_handler() 21061039f409Sav * -> read all error registers 210725cf1a30Sjl * -> mc_process_error() 210825cf1a30Sjl * determine error type 210925cf1a30Sjl * rewrite to clear error or scrub to determine CE type 211025cf1a30Sjl * inform SCF on permanent CE 211125cf1a30Sjl * -> mc_err_drain 211225cf1a30Sjl * page offline processing 211325cf1a30Sjl * -> mc_ereport_post() 211425cf1a30Sjl */ 211525cf1a30Sjl 2116601c2e1eSdhain static void 2117601c2e1eSdhain mc_process_rewrite(mc_opl_t *mcp, int bank) 2118601c2e1eSdhain { 2119601c2e1eSdhain uint32_t rew_addr, cntl; 2120601c2e1eSdhain mc_retry_info_t *retry; 2121601c2e1eSdhain struct mc_bank *bankp; 2122601c2e1eSdhain 2123601c2e1eSdhain bankp = &(mcp->mc_bank[bank]); 2124601c2e1eSdhain retry = bankp->mcb_active; 2125601c2e1eSdhain if (retry == NULL) 2126601c2e1eSdhain return; 2127601c2e1eSdhain 2128601c2e1eSdhain if (retry->ri_state <= RETRY_STATE_ACTIVE) { 2129601c2e1eSdhain cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 2130601c2e1eSdhain if (cntl & MAC_CNTL_PTRL_STATUS) 2131601c2e1eSdhain return; 2132601c2e1eSdhain rew_addr = retry->ri_addr; 2133601c2e1eSdhain ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), rew_addr); 2134601c2e1eSdhain MAC_REW_REQ(mcp, bank); 2135601c2e1eSdhain 2136601c2e1eSdhain retry->ri_state = RETRY_STATE_REWRITE; 2137601c2e1eSdhain } 2138601c2e1eSdhain 2139601c2e1eSdhain cntl = ldphysio(MAC_PTRL_CNTL(mcp, bank)); 2140601c2e1eSdhain 2141601c2e1eSdhain if (cntl & MAC_CNTL_REW_END) { 2142601c2e1eSdhain MAC_CLEAR_ERRS(mcp, bank, 2143601c2e1eSdhain MAC_CNTL_REW_ERRS); 2144601c2e1eSdhain mc_clear_rewrite(mcp, bank); 2145601c2e1eSdhain } else { 2146601c2e1eSdhain /* 2147601c2e1eSdhain * If the rewrite does not complete in 2148601c2e1eSdhain * 1 hour, we have to consider this a HW 2149601c2e1eSdhain * failure. However, there is no recovery 2150601c2e1eSdhain * mechanism. The only thing we can do 2151601c2e1eSdhain * to to print a warning message to the 2152601c2e1eSdhain * console. We continue to increment the 2153601c2e1eSdhain * counter but we only print the message 2154601c2e1eSdhain * once. It will take the counter a long 2155601c2e1eSdhain * time to wrap around and the user might 2156601c2e1eSdhain * see a second message. In practice, 2157601c2e1eSdhain * we have never hit this condition but 2158601c2e1eSdhain * we have to keep the code here just in case. 2159601c2e1eSdhain */ 2160601c2e1eSdhain if (++mcp->mc_bank[bank].mcb_rewrite_count 2161601c2e1eSdhain == mc_max_rewrite_retry) { 2162601c2e1eSdhain cmn_err(CE_WARN, "Memory patrol feature is" 2163601c2e1eSdhain " partly suspended on /LSB%d/B%d" 2164601c2e1eSdhain " due to heavy memory load," 2165601c2e1eSdhain " and it will restart" 2166601c2e1eSdhain " automatically.\n", mcp->mc_board_num, 2167601c2e1eSdhain bank); 2168601c2e1eSdhain } 2169601c2e1eSdhain } 2170601c2e1eSdhain } 2171601c2e1eSdhain 217225cf1a30Sjl static void 217325cf1a30Sjl mc_check_errors_func(mc_opl_t *mcp) 217425cf1a30Sjl { 2175738dd194Shyw mc_rsaddr_info_t rsaddr_info; 217625cf1a30Sjl int i, error_count = 0; 217725cf1a30Sjl uint32_t stat, cntl; 21780cc8ae86Sav int running; 2179cfb9e062Shyw int wrapped; 218037afe445Shyw int ebk; 218125cf1a30Sjl 218225cf1a30Sjl /* 218325cf1a30Sjl * scan errors. 218425cf1a30Sjl */ 21850cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) 21860cc8ae86Sav return; 21870cc8ae86Sav 218825cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 218925cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 2190601c2e1eSdhain if (MC_REWRITE_ACTIVE(mcp, i)) { 2191601c2e1eSdhain mc_process_rewrite(mcp, i); 2192601c2e1eSdhain } 219325cf1a30Sjl stat = ldphysio(MAC_PTRL_STAT(mcp, i)); 219425cf1a30Sjl cntl = ldphysio(MAC_PTRL_CNTL(mcp, i)); 21950cc8ae86Sav running = cntl & MAC_CNTL_PTRL_START; 2196cfb9e062Shyw wrapped = cntl & MAC_CNTL_PTRL_ADD_MAX; 21970cc8ae86Sav 219837afe445Shyw /* Compute the effective bank idx */ 219937afe445Shyw ebk = (IS_MIRROR(mcp, i)) ? MIRROR_IDX(i) : i; 220037afe445Shyw 2201cfb9e062Shyw if (mc_debug_show_all || stat) { 2202cfb9e062Shyw MC_LOG("/LSB%d/B%d stat %x cntl %x\n", 2203d8a0cca9Swh mcp->mc_board_num, i, stat, cntl); 2204cfb9e062Shyw } 2205cfb9e062Shyw 2206cfb9e062Shyw /* 2207cfb9e062Shyw * Update stats and reset flag if the HW patrol 2208cfb9e062Shyw * wrapped around in its scan. 2209cfb9e062Shyw */ 2210cfb9e062Shyw if (wrapped) { 221125cf1a30Sjl MAC_CLEAR_MAX(mcp, i); 221237afe445Shyw mcp->mc_period[ebk]++; 221378ed97a7Sjl if (IS_MIRROR(mcp, i)) { 2214d8a0cca9Swh MC_LOG("mirror mc period %ld on " 2215d8a0cca9Swh "/LSB%d/B%d\n", mcp->mc_period[ebk], 2216d8a0cca9Swh mcp->mc_board_num, i); 221778ed97a7Sjl } else { 2218d8a0cca9Swh MC_LOG("mc period %ld on " 2219d8a0cca9Swh "/LSB%d/B%d\n", mcp->mc_period[ebk], 2220d8a0cca9Swh mcp->mc_board_num, i); 222137afe445Shyw } 222225cf1a30Sjl } 2223cfb9e062Shyw 2224cfb9e062Shyw if (running) { 2225cfb9e062Shyw /* 2226cfb9e062Shyw * Mac patrol HW is still running. 2227cfb9e062Shyw * Normally when an error is detected, 2228cfb9e062Shyw * the HW patrol will stop so that we 2229cfb9e062Shyw * can collect error data for reporting. 2230cfb9e062Shyw * Certain errors (MI errors) detected may not 2231cfb9e062Shyw * cause the HW patrol to stop which is a 2232cfb9e062Shyw * problem since we cannot read error data while 2233cfb9e062Shyw * the HW patrol is running. SW is not allowed 2234cfb9e062Shyw * to stop the HW patrol while it is running 2235cfb9e062Shyw * as it may cause HW inconsistency. This is 2236cfb9e062Shyw * described in a HW errata. 2237cfb9e062Shyw * In situations where we detected errors 2238cfb9e062Shyw * that may not cause the HW patrol to stop. 2239cfb9e062Shyw * We speed up the HW patrol scanning in 2240cfb9e062Shyw * the hope that it will find the 'real' PTRL 2241cfb9e062Shyw * errors associated with the previous errors 2242cfb9e062Shyw * causing the HW to finally stop so that we 2243cfb9e062Shyw * can do the reporting. 2244cfb9e062Shyw */ 2245cfb9e062Shyw /* 2246cfb9e062Shyw * Check to see if we did speed up 2247cfb9e062Shyw * the HW patrol due to previous errors 2248cfb9e062Shyw * detected that did not cause the patrol 2249cfb9e062Shyw * to stop. We only do it if HW patrol scan 2250cfb9e062Shyw * wrapped (counted as completing a 'period'). 2251cfb9e062Shyw */ 225237afe445Shyw if (mcp->mc_speedup_period[ebk] > 0) { 2253d8a0cca9Swh if (wrapped && 2254d8a0cca9Swh (--mcp->mc_speedup_period[ebk] == 2255d8a0cca9Swh 0)) { 2256d8a0cca9Swh /* 2257d8a0cca9Swh * We did try to speed up. 2258d8a0cca9Swh * The speed up period has 2259d8a0cca9Swh * expired and the HW patrol 2260d8a0cca9Swh * is still running. The 2261d8a0cca9Swh * errors must be intermittent. 2262d8a0cca9Swh * We have no choice but to 2263d8a0cca9Swh * ignore them, reset the scan 2264d8a0cca9Swh * speed to normal and clear 2265d8a0cca9Swh * the MI error bits. For 2266d8a0cca9Swh * mirror mode, we need to 2267d8a0cca9Swh * clear errors on both banks. 2268d8a0cca9Swh */ 2269d8a0cca9Swh MC_LOG("Clearing MI errors\n"); 2270d8a0cca9Swh MAC_CLEAR_ERRS(mcp, i, 2271d8a0cca9Swh MAC_CNTL_MI_ERRS); 2272d8a0cca9Swh 2273d8a0cca9Swh if (IS_MIRROR(mcp, i)) { 2274d8a0cca9Swh MC_LOG("Clearing " 2275d8a0cca9Swh "Mirror MI errs\n"); 2276d8a0cca9Swh MAC_CLEAR_ERRS(mcp, 2277d8a0cca9Swh i^1, 2278d8a0cca9Swh MAC_CNTL_MI_ERRS); 2279d8a0cca9Swh } 228037afe445Shyw } 2281cfb9e062Shyw } else if (stat & MAC_STAT_MI_ERRS) { 2282cfb9e062Shyw /* 2283cfb9e062Shyw * MI errors detected but we cannot 2284cfb9e062Shyw * report them since the HW patrol 2285cfb9e062Shyw * is still running. 2286cfb9e062Shyw * We will attempt to speed up the 2287cfb9e062Shyw * scanning and hopefully the HW 2288cfb9e062Shyw * can detect PRTL errors at the same 2289cfb9e062Shyw * location that cause the HW patrol 2290cfb9e062Shyw * to stop. 2291cfb9e062Shyw */ 229237afe445Shyw mcp->mc_speedup_period[ebk] = 2; 22930cc8ae86Sav MAC_CMD(mcp, i, 0); 22940cc8ae86Sav } 2295cfb9e062Shyw } else if (stat & (MAC_STAT_PTRL_ERRS | 2296cfb9e062Shyw MAC_STAT_MI_ERRS)) { 2297cfb9e062Shyw /* 2298cfb9e062Shyw * HW Patrol has stopped and we found errors. 2299cfb9e062Shyw * Proceed to collect and report error info. 2300cfb9e062Shyw */ 230137afe445Shyw mcp->mc_speedup_period[ebk] = 0; 2302738dd194Shyw rsaddr_info.mi_valid = 0; 2303738dd194Shyw rsaddr_info.mi_injectrestart = 0; 2304738dd194Shyw if (IS_MIRROR(mcp, i)) { 2305d8a0cca9Swh mc_error_handler_mir(mcp, i, 2306d8a0cca9Swh &rsaddr_info); 2307738dd194Shyw } else { 2308d8a0cca9Swh mc_error_handler(mcp, i, &rsaddr_info); 2309738dd194Shyw } 2310cfb9e062Shyw 2311cfb9e062Shyw error_count++; 2312738dd194Shyw restart_patrol(mcp, i, &rsaddr_info); 231325cf1a30Sjl } else { 2314cfb9e062Shyw /* 2315cfb9e062Shyw * HW patrol scan has apparently stopped 2316cfb9e062Shyw * but no errors detected/flagged. 2317cfb9e062Shyw * Restart the HW patrol just to be sure. 231837afe445Shyw * In mirror mode, the odd bank might have 231937afe445Shyw * reported errors that caused the patrol to 232037afe445Shyw * stop. We'll defer the restart to the odd 232137afe445Shyw * bank in this case. 2322cfb9e062Shyw */ 232337afe445Shyw if (!IS_MIRROR(mcp, i) || (i & 0x1)) 232437afe445Shyw restart_patrol(mcp, i, NULL); 232525cf1a30Sjl } 232625cf1a30Sjl } 232725cf1a30Sjl } 232825cf1a30Sjl if (error_count > 0) 232925cf1a30Sjl mcp->mc_last_error += error_count; 233025cf1a30Sjl else 233125cf1a30Sjl mcp->mc_last_error = 0; 233225cf1a30Sjl } 233325cf1a30Sjl 23340cc8ae86Sav /* 23350cc8ae86Sav * mc_polling -- Check errors for only one instance, 23360cc8ae86Sav * but process errors for all instances to make sure we drain the errors 23370cc8ae86Sav * faster than they can be accumulated. 23380cc8ae86Sav * 23390cc8ae86Sav * Polling on each board should be done only once per each 23400cc8ae86Sav * mc_patrol_interval_sec. This is equivalent to setting mc_tick_left 23410cc8ae86Sav * to OPL_MAX_BOARDS and decrement by 1 on each timeout. 23420cc8ae86Sav * Once mc_tick_left becomes negative, the board becomes a candidate 23430cc8ae86Sav * for polling because it has waited for at least 23440cc8ae86Sav * mc_patrol_interval_sec's long. If mc_timeout_period is calculated 23451039f409Sav * differently, this has to be updated accordingly. 23460cc8ae86Sav */ 234725cf1a30Sjl 234825cf1a30Sjl static void 23490cc8ae86Sav mc_polling(void) 235025cf1a30Sjl { 23510cc8ae86Sav int i, scan_error; 23520cc8ae86Sav mc_opl_t *mcp; 235325cf1a30Sjl 235425cf1a30Sjl 23550cc8ae86Sav scan_error = 1; 23560cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 23570cc8ae86Sav mutex_enter(&mcmutex); 23580cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) { 23590cc8ae86Sav mutex_exit(&mcmutex); 23600cc8ae86Sav continue; 23610cc8ae86Sav } 23620cc8ae86Sav mutex_enter(&mcp->mc_lock); 23630cc8ae86Sav mutex_exit(&mcmutex); 2364738dd194Shyw if (!(mcp->mc_status & MC_POLL_RUNNING)) { 2365738dd194Shyw mutex_exit(&mcp->mc_lock); 2366738dd194Shyw continue; 2367738dd194Shyw } 23680cc8ae86Sav if (scan_error && mcp->mc_tick_left <= 0) { 23690cc8ae86Sav mc_check_errors_func((void *)mcp); 23700cc8ae86Sav mcp->mc_tick_left = OPL_MAX_BOARDS; 23710cc8ae86Sav scan_error = 0; 23720cc8ae86Sav } else { 23730cc8ae86Sav mcp->mc_tick_left--; 23740cc8ae86Sav } 23750cc8ae86Sav mc_process_scf_log(mcp); 23760cc8ae86Sav mutex_exit(&mcp->mc_lock); 237725cf1a30Sjl } 237825cf1a30Sjl } 237925cf1a30Sjl 238025cf1a30Sjl static void 238125cf1a30Sjl get_ptrl_start_address(mc_opl_t *mcp, int bank, mc_addr_t *maddr) 238225cf1a30Sjl { 238325cf1a30Sjl maddr->ma_bd = mcp->mc_board_num; 238425cf1a30Sjl maddr->ma_bank = bank; 238525cf1a30Sjl maddr->ma_dimm_addr = 0; 238625cf1a30Sjl } 238725cf1a30Sjl 238825cf1a30Sjl typedef struct mc_mem_range { 238925cf1a30Sjl uint64_t addr; 239025cf1a30Sjl uint64_t size; 239125cf1a30Sjl } mc_mem_range_t; 239225cf1a30Sjl 239325cf1a30Sjl static int 239425cf1a30Sjl get_base_address(mc_opl_t *mcp) 239525cf1a30Sjl { 239625cf1a30Sjl mc_mem_range_t *mem_range; 239725cf1a30Sjl int len; 239825cf1a30Sjl 239925cf1a30Sjl if (ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 2400d8a0cca9Swh "sb-mem-ranges", (caddr_t)&mem_range, &len) != DDI_SUCCESS) { 240125cf1a30Sjl return (DDI_FAILURE); 240225cf1a30Sjl } 240325cf1a30Sjl 240425cf1a30Sjl mcp->mc_start_address = mem_range->addr; 240525cf1a30Sjl mcp->mc_size = mem_range->size; 240625cf1a30Sjl 240725cf1a30Sjl kmem_free(mem_range, len); 240825cf1a30Sjl return (DDI_SUCCESS); 240925cf1a30Sjl } 241025cf1a30Sjl 241125cf1a30Sjl struct mc_addr_spec { 241225cf1a30Sjl uint32_t bank; 241325cf1a30Sjl uint32_t phys_hi; 241425cf1a30Sjl uint32_t phys_lo; 241525cf1a30Sjl }; 241625cf1a30Sjl 241725cf1a30Sjl #define REGS_PA(m, i) ((((uint64_t)m[i].phys_hi)<<32) | m[i].phys_lo) 241825cf1a30Sjl 241925cf1a30Sjl static char *mc_tbl_name[] = { 242025cf1a30Sjl "cs0-mc-pa-trans-table", 242125cf1a30Sjl "cs1-mc-pa-trans-table" 242225cf1a30Sjl }; 242325cf1a30Sjl 2424738dd194Shyw /* 2425738dd194Shyw * This routine performs a rangecheck for a given PA 2426738dd194Shyw * to see if it belongs to the memory range for this board. 2427738dd194Shyw * Return 1 if it is valid (within the range) and 0 otherwise 2428738dd194Shyw */ 242925cf1a30Sjl static int 2430738dd194Shyw mc_rangecheck_pa(mc_opl_t *mcp, uint64_t pa) 243125cf1a30Sjl { 2432d8a0cca9Swh if ((pa < mcp->mc_start_address) || (mcp->mc_start_address + 2433d8a0cca9Swh mcp->mc_size <= pa)) 2434738dd194Shyw return (0); 2435738dd194Shyw else 2436738dd194Shyw return (1); 243725cf1a30Sjl } 243825cf1a30Sjl 243925cf1a30Sjl static void 244025cf1a30Sjl mc_memlist_delete(struct memlist *mlist) 244125cf1a30Sjl { 244225cf1a30Sjl struct memlist *ml; 244325cf1a30Sjl 244425cf1a30Sjl for (ml = mlist; ml; ml = mlist) { 244525cf1a30Sjl mlist = ml->next; 244625cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 244725cf1a30Sjl } 244825cf1a30Sjl } 244925cf1a30Sjl 245025cf1a30Sjl static struct memlist * 245125cf1a30Sjl mc_memlist_dup(struct memlist *mlist) 245225cf1a30Sjl { 245325cf1a30Sjl struct memlist *hl = NULL, *tl, **mlp; 245425cf1a30Sjl 245525cf1a30Sjl if (mlist == NULL) 245625cf1a30Sjl return (NULL); 245725cf1a30Sjl 245825cf1a30Sjl mlp = &hl; 245925cf1a30Sjl tl = *mlp; 246025cf1a30Sjl for (; mlist; mlist = mlist->next) { 246125cf1a30Sjl *mlp = kmem_alloc(sizeof (struct memlist), KM_SLEEP); 246225cf1a30Sjl (*mlp)->address = mlist->address; 246325cf1a30Sjl (*mlp)->size = mlist->size; 246425cf1a30Sjl (*mlp)->prev = tl; 246525cf1a30Sjl tl = *mlp; 246625cf1a30Sjl mlp = &((*mlp)->next); 246725cf1a30Sjl } 246825cf1a30Sjl *mlp = NULL; 246925cf1a30Sjl 247025cf1a30Sjl return (hl); 247125cf1a30Sjl } 247225cf1a30Sjl 247325cf1a30Sjl 247425cf1a30Sjl static struct memlist * 247525cf1a30Sjl mc_memlist_del_span(struct memlist *mlist, uint64_t base, uint64_t len) 247625cf1a30Sjl { 247725cf1a30Sjl uint64_t end; 247825cf1a30Sjl struct memlist *ml, *tl, *nlp; 247925cf1a30Sjl 248025cf1a30Sjl if (mlist == NULL) 248125cf1a30Sjl return (NULL); 248225cf1a30Sjl 248325cf1a30Sjl end = base + len; 248425cf1a30Sjl if ((end <= mlist->address) || (base == end)) 248525cf1a30Sjl return (mlist); 248625cf1a30Sjl 248725cf1a30Sjl for (tl = ml = mlist; ml; tl = ml, ml = nlp) { 248825cf1a30Sjl uint64_t mend; 248925cf1a30Sjl 249025cf1a30Sjl nlp = ml->next; 249125cf1a30Sjl 249225cf1a30Sjl if (end <= ml->address) 249325cf1a30Sjl break; 249425cf1a30Sjl 249525cf1a30Sjl mend = ml->address + ml->size; 249625cf1a30Sjl if (base < mend) { 249725cf1a30Sjl if (base <= ml->address) { 249825cf1a30Sjl ml->address = end; 249925cf1a30Sjl if (end >= mend) 250025cf1a30Sjl ml->size = 0ull; 250125cf1a30Sjl else 250225cf1a30Sjl ml->size = mend - ml->address; 250325cf1a30Sjl } else { 250425cf1a30Sjl ml->size = base - ml->address; 250525cf1a30Sjl if (end < mend) { 250625cf1a30Sjl struct memlist *nl; 250725cf1a30Sjl /* 250825cf1a30Sjl * splitting an memlist entry. 250925cf1a30Sjl */ 251025cf1a30Sjl nl = kmem_alloc(sizeof (struct memlist), 2511d8a0cca9Swh KM_SLEEP); 251225cf1a30Sjl nl->address = end; 251325cf1a30Sjl nl->size = mend - nl->address; 251425cf1a30Sjl if ((nl->next = nlp) != NULL) 251525cf1a30Sjl nlp->prev = nl; 251625cf1a30Sjl nl->prev = ml; 251725cf1a30Sjl ml->next = nl; 251825cf1a30Sjl nlp = nl; 251925cf1a30Sjl } 252025cf1a30Sjl } 252125cf1a30Sjl if (ml->size == 0ull) { 252225cf1a30Sjl if (ml == mlist) { 252325cf1a30Sjl if ((mlist = nlp) != NULL) 252425cf1a30Sjl nlp->prev = NULL; 252525cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 252625cf1a30Sjl if (mlist == NULL) 252725cf1a30Sjl break; 252825cf1a30Sjl ml = nlp; 252925cf1a30Sjl } else { 253025cf1a30Sjl if ((tl->next = nlp) != NULL) 253125cf1a30Sjl nlp->prev = tl; 253225cf1a30Sjl kmem_free(ml, sizeof (struct memlist)); 253325cf1a30Sjl ml = tl; 253425cf1a30Sjl } 253525cf1a30Sjl } 253625cf1a30Sjl } 253725cf1a30Sjl } 253825cf1a30Sjl 253925cf1a30Sjl return (mlist); 254025cf1a30Sjl } 254125cf1a30Sjl 254225cf1a30Sjl static void 254325cf1a30Sjl mc_get_mlist(mc_opl_t *mcp) 254425cf1a30Sjl { 254525cf1a30Sjl struct memlist *mlist; 254625cf1a30Sjl 254725cf1a30Sjl memlist_read_lock(); 254825cf1a30Sjl mlist = mc_memlist_dup(phys_install); 254925cf1a30Sjl memlist_read_unlock(); 255025cf1a30Sjl 255125cf1a30Sjl if (mlist) { 255225cf1a30Sjl mlist = mc_memlist_del_span(mlist, 0ull, mcp->mc_start_address); 255325cf1a30Sjl } 255425cf1a30Sjl 255525cf1a30Sjl if (mlist) { 255625cf1a30Sjl uint64_t startpa, endpa; 255725cf1a30Sjl 255825cf1a30Sjl startpa = mcp->mc_start_address + mcp->mc_size; 255925cf1a30Sjl endpa = ptob(physmax + 1); 256025cf1a30Sjl if (endpa > startpa) { 2561d8a0cca9Swh mlist = mc_memlist_del_span(mlist, startpa, 2562d8a0cca9Swh endpa - startpa); 256325cf1a30Sjl } 256425cf1a30Sjl } 256525cf1a30Sjl 256625cf1a30Sjl if (mlist) { 256725cf1a30Sjl mcp->mlist = mlist; 256825cf1a30Sjl } 256925cf1a30Sjl } 257025cf1a30Sjl 257125cf1a30Sjl int 257225cf1a30Sjl mc_board_add(mc_opl_t *mcp) 257325cf1a30Sjl { 257425cf1a30Sjl struct mc_addr_spec *macaddr; 25750cc8ae86Sav cs_status_t *cs_status; 25760cc8ae86Sav int len, len1, i, bk, cc; 2577738dd194Shyw mc_rsaddr_info_t rsaddr; 257825cf1a30Sjl uint32_t mirr; 25790cc8ae86Sav int nbanks = 0; 25800cc8ae86Sav uint64_t nbytes = 0; 2581d8a0cca9Swh int mirror_mode = 0; 2582d8a0cca9Swh int ret; 258325cf1a30Sjl 258425cf1a30Sjl /* 258525cf1a30Sjl * Get configurations from "pseudo-mc" node which includes: 258625cf1a30Sjl * board# : LSB number 258725cf1a30Sjl * mac-addr : physical base address of MAC registers 258825cf1a30Sjl * csX-mac-pa-trans-table: translation table from DIMM address 258925cf1a30Sjl * to physical address or vice versa. 259025cf1a30Sjl */ 259125cf1a30Sjl mcp->mc_board_num = (int)ddi_getprop(DDI_DEV_T_ANY, mcp->mc_dip, 2592d8a0cca9Swh DDI_PROP_DONTPASS, "board#", -1); 259325cf1a30Sjl 25940cc8ae86Sav if (mcp->mc_board_num == -1) { 25950cc8ae86Sav return (DDI_FAILURE); 25960cc8ae86Sav } 25970cc8ae86Sav 259825cf1a30Sjl /* 259925cf1a30Sjl * Get start address in this CAB. It can be gotten from 260025cf1a30Sjl * "sb-mem-ranges" property. 260125cf1a30Sjl */ 260225cf1a30Sjl 260325cf1a30Sjl if (get_base_address(mcp) == DDI_FAILURE) { 260425cf1a30Sjl return (DDI_FAILURE); 260525cf1a30Sjl } 260625cf1a30Sjl /* get mac-pa trans tables */ 260725cf1a30Sjl for (i = 0; i < MC_TT_CS; i++) { 260825cf1a30Sjl len = MC_TT_ENTRIES; 260925cf1a30Sjl cc = ddi_getlongprop_buf(DDI_DEV_T_ANY, mcp->mc_dip, 2610d8a0cca9Swh DDI_PROP_DONTPASS, mc_tbl_name[i], 2611d8a0cca9Swh (caddr_t)mcp->mc_trans_table[i], &len); 261225cf1a30Sjl 261325cf1a30Sjl if (cc != DDI_SUCCESS) { 261425cf1a30Sjl bzero(mcp->mc_trans_table[i], MC_TT_ENTRIES); 261525cf1a30Sjl } 261625cf1a30Sjl } 261725cf1a30Sjl mcp->mlist = NULL; 261825cf1a30Sjl 261925cf1a30Sjl mc_get_mlist(mcp); 262025cf1a30Sjl 262125cf1a30Sjl /* initialize bank informations */ 262225cf1a30Sjl cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 2623d8a0cca9Swh "mc-addr", (caddr_t)&macaddr, &len); 262425cf1a30Sjl if (cc != DDI_SUCCESS) { 262525cf1a30Sjl cmn_err(CE_WARN, "Cannot get mc-addr. err=%d\n", cc); 262625cf1a30Sjl return (DDI_FAILURE); 262725cf1a30Sjl } 262825cf1a30Sjl 26290cc8ae86Sav cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 2630d8a0cca9Swh "cs-status", (caddr_t)&cs_status, &len1); 263125cf1a30Sjl 26320cc8ae86Sav if (cc != DDI_SUCCESS) { 26330cc8ae86Sav if (len > 0) 26340cc8ae86Sav kmem_free(macaddr, len); 26350cc8ae86Sav cmn_err(CE_WARN, "Cannot get cs-status. err=%d\n", cc); 26360cc8ae86Sav return (DDI_FAILURE); 26370cc8ae86Sav } 2638aeb241b2Sav /* get the physical board number for a given logical board number */ 2639aeb241b2Sav mcp->mc_phys_board_num = mc_opl_get_physical_board(mcp->mc_board_num); 2640aeb241b2Sav 2641aeb241b2Sav if (mcp->mc_phys_board_num < 0) { 2642aeb241b2Sav if (len > 0) 2643aeb241b2Sav kmem_free(macaddr, len); 2644aeb241b2Sav cmn_err(CE_WARN, "Unable to obtain the physical board number"); 2645aeb241b2Sav return (DDI_FAILURE); 2646aeb241b2Sav } 264725cf1a30Sjl 26480cc8ae86Sav mutex_init(&mcp->mc_lock, NULL, MUTEX_DRIVER, NULL); 26490cc8ae86Sav 26500cc8ae86Sav for (i = 0; i < len1 / sizeof (cs_status_t); i++) { 26510cc8ae86Sav nbytes += ((uint64_t)cs_status[i].cs_avail_hi << 32) | 2652d8a0cca9Swh ((uint64_t)cs_status[i].cs_avail_low); 26530cc8ae86Sav } 26540cc8ae86Sav if (len1 > 0) 26550cc8ae86Sav kmem_free(cs_status, len1); 26560cc8ae86Sav nbanks = len / sizeof (struct mc_addr_spec); 26570cc8ae86Sav 26580cc8ae86Sav if (nbanks > 0) 26590cc8ae86Sav nbytes /= nbanks; 26600cc8ae86Sav else { 26610cc8ae86Sav /* No need to free macaddr because len must be 0 */ 26620cc8ae86Sav mcp->mc_status |= MC_MEMORYLESS; 26630cc8ae86Sav return (DDI_SUCCESS); 26640cc8ae86Sav } 26650cc8ae86Sav 26660cc8ae86Sav for (i = 0; i < BANKNUM_PER_SB; i++) { 26670cc8ae86Sav mcp->mc_scf_retry[i] = 0; 26680cc8ae86Sav mcp->mc_period[i] = 0; 26690cc8ae86Sav mcp->mc_speedup_period[i] = 0; 26700cc8ae86Sav } 26710cc8ae86Sav 26720cc8ae86Sav /* 26730cc8ae86Sav * Get the memory size here. Let it be B (bytes). 26740cc8ae86Sav * Let T be the time in u.s. to scan 64 bytes. 26750cc8ae86Sav * If we want to complete 1 round of scanning in P seconds. 26760cc8ae86Sav * 26770cc8ae86Sav * B * T * 10^(-6) = P 26780cc8ae86Sav * --------------- 26790cc8ae86Sav * 64 26800cc8ae86Sav * 26810cc8ae86Sav * T = P * 64 * 10^6 26820cc8ae86Sav * ------------- 26830cc8ae86Sav * B 26840cc8ae86Sav * 26850cc8ae86Sav * = P * 64 * 10^6 26860cc8ae86Sav * ------------- 26870cc8ae86Sav * B 26880cc8ae86Sav * 26890cc8ae86Sav * The timing bits are set in PTRL_CNTL[28:26] where 26900cc8ae86Sav * 26910cc8ae86Sav * 0 - 1 m.s 26920cc8ae86Sav * 1 - 512 u.s. 26930cc8ae86Sav * 10 - 256 u.s. 26940cc8ae86Sav * 11 - 128 u.s. 26950cc8ae86Sav * 100 - 64 u.s. 26960cc8ae86Sav * 101 - 32 u.s. 26970cc8ae86Sav * 110 - 0 u.s. 26980cc8ae86Sav * 111 - reserved. 26990cc8ae86Sav * 27000cc8ae86Sav * 27010cc8ae86Sav * a[0] = 110, a[1] = 101, ... a[6] = 0 27020cc8ae86Sav * 27030cc8ae86Sav * cs-status property is int x 7 27040cc8ae86Sav * 0 - cs# 27050cc8ae86Sav * 1 - cs-status 27060cc8ae86Sav * 2 - cs-avail.hi 27070cc8ae86Sav * 3 - cs-avail.lo 27080cc8ae86Sav * 4 - dimm-capa.hi 27090cc8ae86Sav * 5 - dimm-capa.lo 27100cc8ae86Sav * 6 - #of dimms 27110cc8ae86Sav */ 27120cc8ae86Sav 27130cc8ae86Sav if (nbytes > 0) { 27140cc8ae86Sav int i; 27150cc8ae86Sav uint64_t ms; 27160cc8ae86Sav ms = ((uint64_t)mc_scan_period * 64 * 1000000)/nbytes; 27170cc8ae86Sav mcp->mc_speed = mc_scan_speeds[MC_MAX_SPEEDS - 1].mc_speeds; 27180cc8ae86Sav for (i = 0; i < MC_MAX_SPEEDS - 1; i++) { 27190cc8ae86Sav if (ms < mc_scan_speeds[i + 1].mc_period) { 27200cc8ae86Sav mcp->mc_speed = mc_scan_speeds[i].mc_speeds; 27210cc8ae86Sav break; 27220cc8ae86Sav } 27230cc8ae86Sav } 27240cc8ae86Sav } else 27250cc8ae86Sav mcp->mc_speed = 0; 27260cc8ae86Sav 27270cc8ae86Sav 27280cc8ae86Sav for (i = 0; i < len / sizeof (struct mc_addr_spec); i++) { 27290cc8ae86Sav struct mc_bank *bankp; 2730601c2e1eSdhain mc_retry_info_t *retry; 27310cc8ae86Sav uint32_t reg; 2732601c2e1eSdhain int k; 27330cc8ae86Sav 27340cc8ae86Sav /* 27350cc8ae86Sav * setup bank 27360cc8ae86Sav */ 27370cc8ae86Sav bk = macaddr[i].bank; 27380cc8ae86Sav bankp = &(mcp->mc_bank[bk]); 27390cc8ae86Sav bankp->mcb_status = BANK_INSTALLED; 27400cc8ae86Sav bankp->mcb_reg_base = REGS_PA(macaddr, i); 27410cc8ae86Sav 2742601c2e1eSdhain bankp->mcb_retry_freelist = NULL; 2743601c2e1eSdhain bankp->mcb_retry_pending = NULL; 2744601c2e1eSdhain bankp->mcb_active = NULL; 2745601c2e1eSdhain retry = &bankp->mcb_retry_infos[0]; 2746601c2e1eSdhain for (k = 0; k < MC_RETRY_COUNT; k++, retry++) { 2747601c2e1eSdhain mc_retry_info_put(&bankp->mcb_retry_freelist, retry); 2748601c2e1eSdhain } 2749601c2e1eSdhain 27500cc8ae86Sav reg = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bk)); 27510cc8ae86Sav bankp->mcb_ptrl_cntl = (reg & MAC_CNTL_PTRL_PRESERVE_BITS); 275225cf1a30Sjl 275325cf1a30Sjl /* 275425cf1a30Sjl * check if mirror mode 275525cf1a30Sjl */ 275625cf1a30Sjl mirr = LD_MAC_REG(MAC_MIRR(mcp, bk)); 275725cf1a30Sjl 275825cf1a30Sjl if (mirr & MAC_MIRR_MIRROR_MODE) { 2759d8a0cca9Swh MC_LOG("Mirror -> /LSB%d/B%d\n", mcp->mc_board_num, 2760d8a0cca9Swh bk); 276125cf1a30Sjl bankp->mcb_status |= BANK_MIRROR_MODE; 2762d8a0cca9Swh mirror_mode = 1; 276325cf1a30Sjl /* 276425cf1a30Sjl * The following bit is only used for 276525cf1a30Sjl * error injection. We should clear it 276625cf1a30Sjl */ 276725cf1a30Sjl if (mirr & MAC_MIRR_BANK_EXCLUSIVE) 2768d8a0cca9Swh ST_MAC_REG(MAC_MIRR(mcp, bk), 0); 276925cf1a30Sjl } 277025cf1a30Sjl 277125cf1a30Sjl /* 277225cf1a30Sjl * restart if not mirror mode or the other bank 277325cf1a30Sjl * of the mirror is not running 277425cf1a30Sjl */ 277525cf1a30Sjl if (!(mirr & MAC_MIRR_MIRROR_MODE) || 2776d8a0cca9Swh !(mcp->mc_bank[bk^1].mcb_status & BANK_PTRL_RUNNING)) { 2777d8a0cca9Swh MC_LOG("Starting up /LSB%d/B%d\n", mcp->mc_board_num, 2778d8a0cca9Swh bk); 2779738dd194Shyw get_ptrl_start_address(mcp, bk, &rsaddr.mi_restartaddr); 2780738dd194Shyw rsaddr.mi_valid = 0; 2781738dd194Shyw rsaddr.mi_injectrestart = 0; 2782738dd194Shyw restart_patrol(mcp, bk, &rsaddr); 278325cf1a30Sjl } else { 278425cf1a30Sjl MC_LOG("Not starting up /LSB%d/B%d\n", 2785d8a0cca9Swh mcp->mc_board_num, bk); 278625cf1a30Sjl } 278725cf1a30Sjl bankp->mcb_status |= BANK_PTRL_RUNNING; 278825cf1a30Sjl } 27890cc8ae86Sav if (len > 0) 27900cc8ae86Sav kmem_free(macaddr, len); 27910cc8ae86Sav 2792d8a0cca9Swh ret = ndi_prop_update_int(DDI_DEV_T_NONE, mcp->mc_dip, "mirror-mode", 2793d8a0cca9Swh mirror_mode); 2794d8a0cca9Swh if (ret != DDI_PROP_SUCCESS) { 2795d8a0cca9Swh cmn_err(CE_WARN, "Unable to update mirror-mode property"); 2796d8a0cca9Swh } 2797d8a0cca9Swh 27980cc8ae86Sav mcp->mc_dimm_list = mc_get_dimm_list(mcp); 279925cf1a30Sjl 280025cf1a30Sjl /* 280125cf1a30Sjl * set interval in HZ. 280225cf1a30Sjl */ 280325cf1a30Sjl mcp->mc_last_error = 0; 280425cf1a30Sjl 280525cf1a30Sjl /* restart memory patrol checking */ 280625cf1a30Sjl mcp->mc_status |= MC_POLL_RUNNING; 280725cf1a30Sjl 280825cf1a30Sjl return (DDI_SUCCESS); 280925cf1a30Sjl } 281025cf1a30Sjl 281125cf1a30Sjl int 281225cf1a30Sjl mc_board_del(mc_opl_t *mcp) 281325cf1a30Sjl { 281425cf1a30Sjl int i; 281525cf1a30Sjl scf_log_t *p; 281625cf1a30Sjl 281725cf1a30Sjl /* 281825cf1a30Sjl * cleanup mac state 281925cf1a30Sjl */ 282025cf1a30Sjl mutex_enter(&mcp->mc_lock); 28210cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 28220cc8ae86Sav mutex_exit(&mcp->mc_lock); 28230cc8ae86Sav mutex_destroy(&mcp->mc_lock); 28240cc8ae86Sav return (DDI_SUCCESS); 28250cc8ae86Sav } 282625cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 282725cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 282825cf1a30Sjl mcp->mc_bank[i].mcb_status &= ~BANK_INSTALLED; 282925cf1a30Sjl } 283025cf1a30Sjl } 283125cf1a30Sjl 283225cf1a30Sjl /* stop memory patrol checking */ 2833738dd194Shyw mcp->mc_status &= ~MC_POLL_RUNNING; 283425cf1a30Sjl 283525cf1a30Sjl /* just throw away all the scf logs */ 28360cc8ae86Sav for (i = 0; i < BANKNUM_PER_SB; i++) { 2837d8a0cca9Swh while ((p = mcp->mc_scf_log[i]) != NULL) { 2838d8a0cca9Swh mcp->mc_scf_log[i] = p->sl_next; 2839d8a0cca9Swh mcp->mc_scf_total[i]--; 2840d8a0cca9Swh kmem_free(p, sizeof (scf_log_t)); 2841d8a0cca9Swh } 284225cf1a30Sjl } 284325cf1a30Sjl 284425cf1a30Sjl if (mcp->mlist) 284525cf1a30Sjl mc_memlist_delete(mcp->mlist); 284625cf1a30Sjl 28470cc8ae86Sav if (mcp->mc_dimm_list) 28480cc8ae86Sav mc_free_dimm_list(mcp->mc_dimm_list); 28490cc8ae86Sav 285025cf1a30Sjl mutex_exit(&mcp->mc_lock); 285125cf1a30Sjl 285225cf1a30Sjl mutex_destroy(&mcp->mc_lock); 285325cf1a30Sjl return (DDI_SUCCESS); 285425cf1a30Sjl } 285525cf1a30Sjl 285625cf1a30Sjl int 285725cf1a30Sjl mc_suspend(mc_opl_t *mcp, uint32_t flag) 285825cf1a30Sjl { 285925cf1a30Sjl /* stop memory patrol checking */ 286025cf1a30Sjl mutex_enter(&mcp->mc_lock); 28610cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 28620cc8ae86Sav mutex_exit(&mcp->mc_lock); 28630cc8ae86Sav return (DDI_SUCCESS); 28640cc8ae86Sav } 28650cc8ae86Sav 2866738dd194Shyw mcp->mc_status &= ~MC_POLL_RUNNING; 2867738dd194Shyw 286825cf1a30Sjl mcp->mc_status |= flag; 286925cf1a30Sjl mutex_exit(&mcp->mc_lock); 287025cf1a30Sjl 287125cf1a30Sjl return (DDI_SUCCESS); 287225cf1a30Sjl } 287325cf1a30Sjl 287468ac2337Sjl void 287568ac2337Sjl opl_mc_update_mlist(void) 287668ac2337Sjl { 287768ac2337Sjl int i; 287868ac2337Sjl mc_opl_t *mcp; 287968ac2337Sjl 288068ac2337Sjl /* 288168ac2337Sjl * memory information is not updated until 288268ac2337Sjl * the post attach/detach stage during DR. 288368ac2337Sjl * This interface is used by dr_mem to inform 288468ac2337Sjl * mc-opl to update the mlist. 288568ac2337Sjl */ 288668ac2337Sjl 288768ac2337Sjl mutex_enter(&mcmutex); 288868ac2337Sjl for (i = 0; i < OPL_MAX_BOARDS; i++) { 288968ac2337Sjl if ((mcp = mc_instances[i]) == NULL) 289068ac2337Sjl continue; 289168ac2337Sjl mutex_enter(&mcp->mc_lock); 289268ac2337Sjl if (mcp->mlist) 289368ac2337Sjl mc_memlist_delete(mcp->mlist); 289468ac2337Sjl mcp->mlist = NULL; 289568ac2337Sjl mc_get_mlist(mcp); 289668ac2337Sjl mutex_exit(&mcp->mc_lock); 289768ac2337Sjl } 289868ac2337Sjl mutex_exit(&mcmutex); 289968ac2337Sjl } 290068ac2337Sjl 290125cf1a30Sjl /* caller must clear the SUSPEND bits or this will do nothing */ 290225cf1a30Sjl 290325cf1a30Sjl int 290425cf1a30Sjl mc_resume(mc_opl_t *mcp, uint32_t flag) 290525cf1a30Sjl { 290625cf1a30Sjl int i; 290725cf1a30Sjl uint64_t basepa; 290825cf1a30Sjl 290925cf1a30Sjl mutex_enter(&mcp->mc_lock); 29100cc8ae86Sav if (mcp->mc_status & MC_MEMORYLESS) { 29110cc8ae86Sav mutex_exit(&mcp->mc_lock); 29120cc8ae86Sav return (DDI_SUCCESS); 29130cc8ae86Sav } 291425cf1a30Sjl basepa = mcp->mc_start_address; 291525cf1a30Sjl if (get_base_address(mcp) == DDI_FAILURE) { 291625cf1a30Sjl mutex_exit(&mcp->mc_lock); 291725cf1a30Sjl return (DDI_FAILURE); 291825cf1a30Sjl } 291925cf1a30Sjl 292025cf1a30Sjl if (basepa != mcp->mc_start_address) { 292125cf1a30Sjl if (mcp->mlist) 292225cf1a30Sjl mc_memlist_delete(mcp->mlist); 292325cf1a30Sjl mcp->mlist = NULL; 292425cf1a30Sjl mc_get_mlist(mcp); 292525cf1a30Sjl } 292625cf1a30Sjl 292725cf1a30Sjl mcp->mc_status &= ~flag; 292825cf1a30Sjl 292925cf1a30Sjl if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 293025cf1a30Sjl mutex_exit(&mcp->mc_lock); 293125cf1a30Sjl return (DDI_SUCCESS); 293225cf1a30Sjl } 293325cf1a30Sjl 293425cf1a30Sjl if (!(mcp->mc_status & MC_POLL_RUNNING)) { 293525cf1a30Sjl /* restart memory patrol checking */ 293625cf1a30Sjl mcp->mc_status |= MC_POLL_RUNNING; 293725cf1a30Sjl for (i = 0; i < BANKNUM_PER_SB; i++) { 293825cf1a30Sjl if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 2939601c2e1eSdhain mc_check_errors_func(mcp); 294025cf1a30Sjl } 294125cf1a30Sjl } 294225cf1a30Sjl } 294325cf1a30Sjl mutex_exit(&mcp->mc_lock); 294425cf1a30Sjl 294525cf1a30Sjl return (DDI_SUCCESS); 294625cf1a30Sjl } 294725cf1a30Sjl 294825cf1a30Sjl static mc_opl_t * 294925cf1a30Sjl mc_pa_to_mcp(uint64_t pa) 295025cf1a30Sjl { 29510cc8ae86Sav mc_opl_t *mcp; 29520cc8ae86Sav int i; 29530cc8ae86Sav 295425cf1a30Sjl ASSERT(MUTEX_HELD(&mcmutex)); 29550cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 29560cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 29570cc8ae86Sav continue; 295825cf1a30Sjl /* if mac patrol is suspended, we cannot rely on it */ 29590cc8ae86Sav if (!(mcp->mc_status & MC_POLL_RUNNING) || 2960d8a0cca9Swh (mcp->mc_status & MC_SOFT_SUSPENDED)) 296125cf1a30Sjl continue; 2962738dd194Shyw if (mc_rangecheck_pa(mcp, pa)) { 29630cc8ae86Sav return (mcp); 296425cf1a30Sjl } 296525cf1a30Sjl } 296625cf1a30Sjl return (NULL); 296725cf1a30Sjl } 296825cf1a30Sjl 296925cf1a30Sjl /* 297025cf1a30Sjl * Get Physical Board number from Logical one. 297125cf1a30Sjl */ 297225cf1a30Sjl static int 297325cf1a30Sjl mc_opl_get_physical_board(int sb) 297425cf1a30Sjl { 297525cf1a30Sjl if (&opl_get_physical_board) { 297625cf1a30Sjl return (opl_get_physical_board(sb)); 297725cf1a30Sjl } 297825cf1a30Sjl 297925cf1a30Sjl cmn_err(CE_NOTE, "!opl_get_physical_board() not loaded\n"); 298025cf1a30Sjl return (-1); 298125cf1a30Sjl } 298225cf1a30Sjl 298325cf1a30Sjl /* ARGSUSED */ 298425cf1a30Sjl int 298525cf1a30Sjl mc_get_mem_unum(int synd_code, uint64_t flt_addr, char *buf, int buflen, 298625cf1a30Sjl int *lenp) 298725cf1a30Sjl { 29880cc8ae86Sav int i; 2989aeb241b2Sav int j; 299025cf1a30Sjl int sb; 29910cc8ae86Sav int bank; 2992aeb241b2Sav int cs; 299378ed97a7Sjl int rv = 0; 29940cc8ae86Sav mc_opl_t *mcp; 29950cc8ae86Sav char memb_num; 299625cf1a30Sjl 299725cf1a30Sjl mutex_enter(&mcmutex); 299825cf1a30Sjl 299925cf1a30Sjl if (((mcp = mc_pa_to_mcp(flt_addr)) == NULL) || 3000d8a0cca9Swh (!pa_is_valid(mcp, flt_addr))) { 300125cf1a30Sjl mutex_exit(&mcmutex); 300225cf1a30Sjl if (snprintf(buf, buflen, "UNKNOWN") >= buflen) { 300325cf1a30Sjl return (ENOSPC); 300425cf1a30Sjl } else { 300525cf1a30Sjl if (lenp) 300625cf1a30Sjl *lenp = strlen(buf); 300725cf1a30Sjl } 300825cf1a30Sjl return (0); 300925cf1a30Sjl } 301025cf1a30Sjl 301125cf1a30Sjl bank = pa_to_bank(mcp, flt_addr - mcp->mc_start_address); 3012aeb241b2Sav sb = mcp->mc_phys_board_num; 3013aeb241b2Sav cs = pa_to_cs(mcp, flt_addr - mcp->mc_start_address); 301425cf1a30Sjl 301525cf1a30Sjl if (sb == -1) { 301625cf1a30Sjl mutex_exit(&mcmutex); 301725cf1a30Sjl return (ENXIO); 301825cf1a30Sjl } 301925cf1a30Sjl 302078ed97a7Sjl switch (plat_model) { 302178ed97a7Sjl case MODEL_DC: 30220cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 3023aeb241b2Sav j = (cs == 0) ? i : i + 2; 3024aeb241b2Sav snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s", 30250cc8ae86Sav model_names[plat_model].unit_name, sb, 3026aeb241b2Sav mc_dc_dimm_unum_table[j], 3027aeb241b2Sav mc_dc_dimm_unum_table[j + 1]); 302878ed97a7Sjl break; 302978ed97a7Sjl case MODEL_FF2: 303078ed97a7Sjl case MODEL_FF1: 30310cc8ae86Sav i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 3032aeb241b2Sav j = (cs == 0) ? i : i + 2; 30330cc8ae86Sav memb_num = mc_ff_dimm_unum_table[i][0]; 3034aeb241b2Sav snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s", 30350cc8ae86Sav model_names[plat_model].unit_name, 30360cc8ae86Sav model_names[plat_model].mem_name, memb_num, 3037aeb241b2Sav &mc_ff_dimm_unum_table[j][1], 3038aeb241b2Sav &mc_ff_dimm_unum_table[j + 1][1]); 303978ed97a7Sjl break; 304078ed97a7Sjl case MODEL_IKKAKU: 304178ed97a7Sjl i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 304278ed97a7Sjl j = (cs == 0) ? i : i + 2; 304378ed97a7Sjl snprintf(buf, buflen, "/%s/MEM%s MEM%s", 304478ed97a7Sjl model_names[plat_model].unit_name, 304578ed97a7Sjl &mc_ff_dimm_unum_table[j][1], 304678ed97a7Sjl &mc_ff_dimm_unum_table[j + 1][1]); 304778ed97a7Sjl break; 304878ed97a7Sjl default: 304978ed97a7Sjl rv = ENXIO; 30500cc8ae86Sav } 30510cc8ae86Sav if (lenp) { 30520cc8ae86Sav *lenp = strlen(buf); 305325cf1a30Sjl } 305425cf1a30Sjl mutex_exit(&mcmutex); 305578ed97a7Sjl return (rv); 305625cf1a30Sjl } 305725cf1a30Sjl 305825cf1a30Sjl int 30590cc8ae86Sav opl_mc_suspend(void) 306025cf1a30Sjl { 306125cf1a30Sjl mc_opl_t *mcp; 30620cc8ae86Sav int i; 306325cf1a30Sjl 306425cf1a30Sjl mutex_enter(&mcmutex); 30650cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 30660cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 30670cc8ae86Sav continue; 30680cc8ae86Sav mc_suspend(mcp, MC_SOFT_SUSPENDED); 306925cf1a30Sjl } 307025cf1a30Sjl mutex_exit(&mcmutex); 30710cc8ae86Sav 307225cf1a30Sjl return (0); 307325cf1a30Sjl } 307425cf1a30Sjl 307525cf1a30Sjl int 30760cc8ae86Sav opl_mc_resume(void) 307725cf1a30Sjl { 307825cf1a30Sjl mc_opl_t *mcp; 30790cc8ae86Sav int i; 308025cf1a30Sjl 308125cf1a30Sjl mutex_enter(&mcmutex); 30820cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 30830cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 30840cc8ae86Sav continue; 30850cc8ae86Sav mc_resume(mcp, MC_SOFT_SUSPENDED); 308625cf1a30Sjl } 308725cf1a30Sjl mutex_exit(&mcmutex); 30880cc8ae86Sav 308925cf1a30Sjl return (0); 309025cf1a30Sjl } 309125cf1a30Sjl static void 309225cf1a30Sjl insert_mcp(mc_opl_t *mcp) 309325cf1a30Sjl { 309425cf1a30Sjl mutex_enter(&mcmutex); 30950cc8ae86Sav if (mc_instances[mcp->mc_board_num] != NULL) { 30960cc8ae86Sav MC_LOG("mc-opl instance for board# %d already exists\n", 3097d8a0cca9Swh mcp->mc_board_num); 30980cc8ae86Sav } 30990cc8ae86Sav mc_instances[mcp->mc_board_num] = mcp; 310025cf1a30Sjl mutex_exit(&mcmutex); 310125cf1a30Sjl } 310225cf1a30Sjl 310325cf1a30Sjl static void 310425cf1a30Sjl delete_mcp(mc_opl_t *mcp) 310525cf1a30Sjl { 31060cc8ae86Sav mutex_enter(&mcmutex); 31070cc8ae86Sav mc_instances[mcp->mc_board_num] = 0; 31080cc8ae86Sav mutex_exit(&mcmutex); 310925cf1a30Sjl } 311025cf1a30Sjl 311125cf1a30Sjl /* Error injection interface */ 311225cf1a30Sjl 3113cfb9e062Shyw static void 3114cfb9e062Shyw mc_lock_va(uint64_t pa, caddr_t new_va) 3115cfb9e062Shyw { 3116cfb9e062Shyw tte_t tte; 3117cfb9e062Shyw 3118738dd194Shyw vtag_flushpage(new_va, (uint64_t)ksfmmup); 3119d8a0cca9Swh sfmmu_memtte(&tte, pa >> PAGESHIFT, PROC_DATA|HAT_NOSYNC, TTE8K); 3120cfb9e062Shyw tte.tte_intlo |= TTE_LCK_INT; 3121cfb9e062Shyw sfmmu_dtlb_ld_kva(new_va, &tte); 3122cfb9e062Shyw } 3123cfb9e062Shyw 3124cfb9e062Shyw static void 3125cfb9e062Shyw mc_unlock_va(caddr_t va) 3126cfb9e062Shyw { 3127cfb9e062Shyw vtag_flushpage(va, (uint64_t)ksfmmup); 3128cfb9e062Shyw } 3129cfb9e062Shyw 313025cf1a30Sjl /* ARGSUSED */ 313125cf1a30Sjl int 313225cf1a30Sjl mc_inject_error(int error_type, uint64_t pa, uint32_t flags) 313325cf1a30Sjl { 313425cf1a30Sjl mc_opl_t *mcp; 313525cf1a30Sjl int bank; 313625cf1a30Sjl uint32_t dimm_addr; 313725cf1a30Sjl uint32_t cntl; 3138738dd194Shyw mc_rsaddr_info_t rsaddr; 313925cf1a30Sjl uint32_t data, stat; 314025cf1a30Sjl int both_sides = 0; 314125cf1a30Sjl uint64_t pa0; 3142cfb9e062Shyw int extra_injection_needed = 0; 314325cf1a30Sjl extern void cpu_flush_ecache(void); 314425cf1a30Sjl 314525cf1a30Sjl MC_LOG("HW mc_inject_error(%x, %lx, %x)\n", error_type, pa, flags); 314625cf1a30Sjl 314725cf1a30Sjl mutex_enter(&mcmutex); 314825cf1a30Sjl if ((mcp = mc_pa_to_mcp(pa)) == NULL) { 314925cf1a30Sjl mutex_exit(&mcmutex); 315025cf1a30Sjl MC_LOG("mc_inject_error: invalid pa\n"); 315125cf1a30Sjl return (ENOTSUP); 315225cf1a30Sjl } 315325cf1a30Sjl 315425cf1a30Sjl mutex_enter(&mcp->mc_lock); 315525cf1a30Sjl mutex_exit(&mcmutex); 315625cf1a30Sjl 315725cf1a30Sjl if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 315825cf1a30Sjl mutex_exit(&mcp->mc_lock); 315925cf1a30Sjl MC_LOG("mc-opl has been suspended. No error injection.\n"); 316025cf1a30Sjl return (EBUSY); 316125cf1a30Sjl } 316225cf1a30Sjl 316325cf1a30Sjl /* convert pa to offset within the board */ 316425cf1a30Sjl MC_LOG("pa %lx, offset %lx\n", pa, pa - mcp->mc_start_address); 316525cf1a30Sjl 316625cf1a30Sjl if (!pa_is_valid(mcp, pa)) { 316725cf1a30Sjl mutex_exit(&mcp->mc_lock); 316825cf1a30Sjl return (EINVAL); 316925cf1a30Sjl } 317025cf1a30Sjl 317125cf1a30Sjl pa0 = pa - mcp->mc_start_address; 317225cf1a30Sjl 317325cf1a30Sjl bank = pa_to_bank(mcp, pa0); 317425cf1a30Sjl 317525cf1a30Sjl if (flags & MC_INJECT_FLAG_OTHER) 317625cf1a30Sjl bank = bank ^ 1; 317725cf1a30Sjl 317825cf1a30Sjl if (MC_INJECT_MIRROR(error_type) && !IS_MIRROR(mcp, bank)) { 317925cf1a30Sjl mutex_exit(&mcp->mc_lock); 318025cf1a30Sjl MC_LOG("Not mirror mode\n"); 318125cf1a30Sjl return (EINVAL); 318225cf1a30Sjl } 318325cf1a30Sjl 318425cf1a30Sjl dimm_addr = pa_to_dimm(mcp, pa0); 318525cf1a30Sjl 3186d8a0cca9Swh MC_LOG("injecting error to /LSB%d/B%d/%x\n", mcp->mc_board_num, bank, 3187d8a0cca9Swh dimm_addr); 318825cf1a30Sjl 318925cf1a30Sjl 319025cf1a30Sjl switch (error_type) { 319125cf1a30Sjl case MC_INJECT_INTERMITTENT_MCE: 319225cf1a30Sjl case MC_INJECT_PERMANENT_MCE: 319325cf1a30Sjl case MC_INJECT_MUE: 319425cf1a30Sjl both_sides = 1; 319525cf1a30Sjl } 319625cf1a30Sjl 319725cf1a30Sjl if (flags & MC_INJECT_FLAG_RESET) 319825cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 0); 319925cf1a30Sjl 320025cf1a30Sjl ST_MAC_REG(MAC_EG_ADD(mcp, bank), dimm_addr & MAC_EG_ADD_MASK); 320125cf1a30Sjl 320225cf1a30Sjl if (both_sides) { 320325cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), 0); 3204d8a0cca9Swh ST_MAC_REG(MAC_EG_ADD(mcp, bank^1), dimm_addr & 3205d8a0cca9Swh MAC_EG_ADD_MASK); 320625cf1a30Sjl } 320725cf1a30Sjl 320825cf1a30Sjl switch (error_type) { 320925cf1a30Sjl case MC_INJECT_SUE: 3210cfb9e062Shyw extra_injection_needed = 1; 3211cfb9e062Shyw /*FALLTHROUGH*/ 3212cfb9e062Shyw case MC_INJECT_UE: 321325cf1a30Sjl case MC_INJECT_MUE: 321425cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 3215d8a0cca9Swh cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_READ00 | 3216d8a0cca9Swh MAC_EG_FORCE_READ16 | MAC_EG_RDERR_ONCE; 321725cf1a30Sjl } else { 3218d8a0cca9Swh cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_DERR00 | 3219d8a0cca9Swh MAC_EG_FORCE_DERR16 | MAC_EG_DERR_ONCE; 322025cf1a30Sjl } 322125cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 322225cf1a30Sjl break; 322325cf1a30Sjl case MC_INJECT_INTERMITTENT_CE: 322425cf1a30Sjl case MC_INJECT_INTERMITTENT_MCE: 322525cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 3226d8a0cca9Swh cntl = MAC_EG_ADD_FIX |MAC_EG_FORCE_READ00 | 3227d8a0cca9Swh MAC_EG_RDERR_ONCE; 322825cf1a30Sjl } else { 3229d8a0cca9Swh cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_DERR16 | 3230d8a0cca9Swh MAC_EG_DERR_ONCE; 323125cf1a30Sjl } 3232cfb9e062Shyw extra_injection_needed = 1; 323325cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 323425cf1a30Sjl break; 323525cf1a30Sjl case MC_INJECT_PERMANENT_CE: 323625cf1a30Sjl case MC_INJECT_PERMANENT_MCE: 323725cf1a30Sjl if (flags & MC_INJECT_FLAG_PATH) { 3238d8a0cca9Swh cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_READ00 | 3239d8a0cca9Swh MAC_EG_RDERR_ALWAYS; 324025cf1a30Sjl } else { 3241d8a0cca9Swh cntl = MAC_EG_ADD_FIX | MAC_EG_FORCE_DERR16 | 3242d8a0cca9Swh MAC_EG_DERR_ALWAYS; 324325cf1a30Sjl } 324425cf1a30Sjl flags |= MC_INJECT_FLAG_ST; 324525cf1a30Sjl break; 324625cf1a30Sjl case MC_INJECT_CMPE: 324725cf1a30Sjl data = 0xabcdefab; 324825cf1a30Sjl stphys(pa, data); 324925cf1a30Sjl cpu_flush_ecache(); 325025cf1a30Sjl MC_LOG("CMPE: writing data %x to %lx\n", data, pa); 325125cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bank), MAC_MIRR_BANK_EXCLUSIVE); 325225cf1a30Sjl stphys(pa, data ^ 0xffffffff); 3253738dd194Shyw membar_sync(); 325425cf1a30Sjl cpu_flush_ecache(); 325525cf1a30Sjl ST_MAC_REG(MAC_MIRR(mcp, bank), 0); 325625cf1a30Sjl MC_LOG("CMPE: write new data %xto %lx\n", data, pa); 325725cf1a30Sjl cntl = 0; 325825cf1a30Sjl break; 325925cf1a30Sjl case MC_INJECT_NOP: 326025cf1a30Sjl cntl = 0; 326125cf1a30Sjl break; 326225cf1a30Sjl default: 326325cf1a30Sjl MC_LOG("mc_inject_error: invalid option\n"); 326425cf1a30Sjl cntl = 0; 326525cf1a30Sjl } 326625cf1a30Sjl 326725cf1a30Sjl if (cntl) { 326825cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl & MAC_EG_SETUP_MASK); 326925cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl); 327025cf1a30Sjl 327125cf1a30Sjl if (both_sides) { 327225cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl & 3273d8a0cca9Swh MAC_EG_SETUP_MASK); 327425cf1a30Sjl ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl); 327525cf1a30Sjl } 327625cf1a30Sjl } 327725cf1a30Sjl 327825cf1a30Sjl /* 327925cf1a30Sjl * For all injection cases except compare error, we 328025cf1a30Sjl * must write to the PA to trigger the error. 328125cf1a30Sjl */ 328225cf1a30Sjl 328325cf1a30Sjl if (flags & MC_INJECT_FLAG_ST) { 328425cf1a30Sjl data = 0xf0e0d0c0; 328525cf1a30Sjl MC_LOG("Writing %x to %lx\n", data, pa); 328625cf1a30Sjl stphys(pa, data); 328725cf1a30Sjl cpu_flush_ecache(); 328825cf1a30Sjl } 328925cf1a30Sjl 329025cf1a30Sjl 329125cf1a30Sjl if (flags & MC_INJECT_FLAG_LD) { 3292cfb9e062Shyw if (flags & MC_INJECT_FLAG_PREFETCH) { 3293cfb9e062Shyw /* 3294cfb9e062Shyw * Use strong prefetch operation to 3295cfb9e062Shyw * inject MI errors. 3296cfb9e062Shyw */ 3297cfb9e062Shyw page_t *pp; 3298cfb9e062Shyw extern void mc_prefetch(caddr_t); 3299cfb9e062Shyw 3300cfb9e062Shyw MC_LOG("prefetch\n"); 3301cfb9e062Shyw 3302cfb9e062Shyw pp = page_numtopp_nolock(pa >> PAGESHIFT); 3303cfb9e062Shyw if (pp != NULL) { 3304cfb9e062Shyw caddr_t va, va1; 3305cfb9e062Shyw 3306cfb9e062Shyw va = ppmapin(pp, PROT_READ|PROT_WRITE, 3307d8a0cca9Swh (caddr_t)-1); 3308cfb9e062Shyw kpreempt_disable(); 3309cfb9e062Shyw mc_lock_va((uint64_t)pa, va); 3310cfb9e062Shyw va1 = va + (pa & (PAGESIZE - 1)); 3311cfb9e062Shyw mc_prefetch(va1); 3312cfb9e062Shyw mc_unlock_va(va); 3313cfb9e062Shyw kpreempt_enable(); 3314cfb9e062Shyw ppmapout(va); 3315cfb9e062Shyw 3316cfb9e062Shyw /* 3317cfb9e062Shyw * For MI errors, we need one extra 3318cfb9e062Shyw * injection for HW patrol to stop. 3319cfb9e062Shyw */ 3320cfb9e062Shyw extra_injection_needed = 1; 332125cf1a30Sjl } else { 3322cfb9e062Shyw cmn_err(CE_WARN, "Cannot find page structure" 3323d8a0cca9Swh " for PA %lx\n", pa); 332425cf1a30Sjl } 332525cf1a30Sjl } else { 332625cf1a30Sjl MC_LOG("Reading from %lx\n", pa); 332725cf1a30Sjl data = ldphys(pa); 332825cf1a30Sjl MC_LOG("data = %x\n", data); 332925cf1a30Sjl } 3330cfb9e062Shyw 3331cfb9e062Shyw if (extra_injection_needed) { 3332cfb9e062Shyw /* 3333cfb9e062Shyw * These are the injection cases where the 3334cfb9e062Shyw * requested injected errors will not cause the HW 3335cfb9e062Shyw * patrol to stop. For these cases, we need to inject 3336cfb9e062Shyw * an extra 'real' PTRL error to force the 3337cfb9e062Shyw * HW patrol to stop so that we can report the 3338cfb9e062Shyw * errors injected. Note that we cannot read 3339cfb9e062Shyw * and report error status while the HW patrol 3340cfb9e062Shyw * is running. 3341cfb9e062Shyw */ 3342cfb9e062Shyw ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 3343d8a0cca9Swh cntl & MAC_EG_SETUP_MASK); 3344cfb9e062Shyw ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl); 3345cfb9e062Shyw 3346cfb9e062Shyw if (both_sides) { 3347d8a0cca9Swh ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl & 3348d8a0cca9Swh MAC_EG_SETUP_MASK); 3349d8a0cca9Swh ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl); 3350cfb9e062Shyw } 3351cfb9e062Shyw data = 0xf0e0d0c0; 3352cfb9e062Shyw MC_LOG("Writing %x to %lx\n", data, pa); 3353cfb9e062Shyw stphys(pa, data); 3354cfb9e062Shyw cpu_flush_ecache(); 3355cfb9e062Shyw } 335625cf1a30Sjl } 335725cf1a30Sjl 335825cf1a30Sjl if (flags & MC_INJECT_FLAG_RESTART) { 335925cf1a30Sjl MC_LOG("Restart patrol\n"); 3360738dd194Shyw rsaddr.mi_restartaddr.ma_bd = mcp->mc_board_num; 3361738dd194Shyw rsaddr.mi_restartaddr.ma_bank = bank; 3362738dd194Shyw rsaddr.mi_restartaddr.ma_dimm_addr = dimm_addr; 3363738dd194Shyw rsaddr.mi_valid = 1; 3364738dd194Shyw rsaddr.mi_injectrestart = 1; 3365738dd194Shyw restart_patrol(mcp, bank, &rsaddr); 336625cf1a30Sjl } 336725cf1a30Sjl 336825cf1a30Sjl if (flags & MC_INJECT_FLAG_POLL) { 33690cc8ae86Sav int running; 337037afe445Shyw int ebank = (IS_MIRROR(mcp, bank)) ? MIRROR_IDX(bank) : bank; 337125cf1a30Sjl 337225cf1a30Sjl MC_LOG("Poll patrol error\n"); 337325cf1a30Sjl stat = LD_MAC_REG(MAC_PTRL_STAT(mcp, bank)); 337425cf1a30Sjl cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 33750cc8ae86Sav running = cntl & MAC_CNTL_PTRL_START; 337625cf1a30Sjl 3377cfb9e062Shyw if (!running && 3378cfb9e062Shyw (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS))) { 3379cfb9e062Shyw /* 3380cfb9e062Shyw * HW patrol stopped and we have errors to 3381cfb9e062Shyw * report. Do it. 3382cfb9e062Shyw */ 338337afe445Shyw mcp->mc_speedup_period[ebank] = 0; 3384738dd194Shyw rsaddr.mi_valid = 0; 3385738dd194Shyw rsaddr.mi_injectrestart = 0; 3386738dd194Shyw if (IS_MIRROR(mcp, bank)) { 3387738dd194Shyw mc_error_handler_mir(mcp, bank, &rsaddr); 3388738dd194Shyw } else { 3389738dd194Shyw mc_error_handler(mcp, bank, &rsaddr); 3390738dd194Shyw } 3391cfb9e062Shyw 3392738dd194Shyw restart_patrol(mcp, bank, &rsaddr); 3393cfb9e062Shyw } else { 3394cfb9e062Shyw /* 3395cfb9e062Shyw * We are expecting to report injected 3396cfb9e062Shyw * errors but the HW patrol is still running. 3397cfb9e062Shyw * Speed up the scanning 3398cfb9e062Shyw */ 339937afe445Shyw mcp->mc_speedup_period[ebank] = 2; 3400cfb9e062Shyw MAC_CMD(mcp, bank, 0); 340125cf1a30Sjl restart_patrol(mcp, bank, NULL); 3402cfb9e062Shyw } 340325cf1a30Sjl } 340425cf1a30Sjl 340525cf1a30Sjl mutex_exit(&mcp->mc_lock); 340625cf1a30Sjl return (0); 340725cf1a30Sjl } 3408cfb9e062Shyw 340925cf1a30Sjl void 341025cf1a30Sjl mc_stphysio(uint64_t pa, uint32_t data) 341125cf1a30Sjl { 341225cf1a30Sjl MC_LOG("0x%x -> pa(%lx)\n", data, pa); 341325cf1a30Sjl stphysio(pa, data); 34140cc8ae86Sav 34150cc8ae86Sav /* force the above write to be processed by mac patrol */ 3416cfb9e062Shyw data = ldphysio(pa); 3417cfb9e062Shyw MC_LOG("pa(%lx) = 0x%x\n", pa, data); 341825cf1a30Sjl } 341925cf1a30Sjl 342025cf1a30Sjl uint32_t 342125cf1a30Sjl mc_ldphysio(uint64_t pa) 342225cf1a30Sjl { 342325cf1a30Sjl uint32_t rv; 342425cf1a30Sjl 342525cf1a30Sjl rv = ldphysio(pa); 342625cf1a30Sjl MC_LOG("pa(%lx) = 0x%x\n", pa, rv); 342725cf1a30Sjl return (rv); 342825cf1a30Sjl } 34290cc8ae86Sav 34300cc8ae86Sav #define isdigit(ch) ((ch) >= '0' && (ch) <= '9') 34310cc8ae86Sav 34320cc8ae86Sav /* 34330cc8ae86Sav * parse_unum_memory -- extract the board number and the DIMM name from 34340cc8ae86Sav * the unum. 34350cc8ae86Sav * 34360cc8ae86Sav * Return 0 for success and non-zero for a failure. 34370cc8ae86Sav */ 34380cc8ae86Sav int 34390cc8ae86Sav parse_unum_memory(char *unum, int *board, char *dname) 34400cc8ae86Sav { 34410cc8ae86Sav char *c; 34420cc8ae86Sav char x, y, z; 34430cc8ae86Sav 34440cc8ae86Sav if ((c = strstr(unum, "CMU")) != NULL) { 34450cc8ae86Sav /* DC Model */ 34460cc8ae86Sav c += 3; 34470cc8ae86Sav *board = (uint8_t)stoi(&c); 34480cc8ae86Sav if ((c = strstr(c, "MEM")) == NULL) { 34490cc8ae86Sav return (1); 34500cc8ae86Sav } 34510cc8ae86Sav c += 3; 34520cc8ae86Sav if (strlen(c) < 3) { 34530cc8ae86Sav return (2); 34540cc8ae86Sav } 34550cc8ae86Sav if ((!isdigit(c[0])) || (!(isdigit(c[1]))) || 34560cc8ae86Sav ((c[2] != 'A') && (c[2] != 'B'))) { 34570cc8ae86Sav return (3); 34580cc8ae86Sav } 34590cc8ae86Sav x = c[0]; 34600cc8ae86Sav y = c[1]; 34610cc8ae86Sav z = c[2]; 34620cc8ae86Sav } else if ((c = strstr(unum, "MBU_")) != NULL) { 346378ed97a7Sjl /* FF1/FF2/Ikkaku Model */ 34640cc8ae86Sav c += 4; 34650cc8ae86Sav if ((c[0] != 'A') && (c[0] != 'B')) { 34660cc8ae86Sav return (4); 34670cc8ae86Sav } 346878ed97a7Sjl if (plat_model == MODEL_IKKAKU) { 346978ed97a7Sjl /* Ikkaku Model */ 347078ed97a7Sjl x = '0'; 347178ed97a7Sjl *board = 0; 347278ed97a7Sjl } else { 347378ed97a7Sjl /* FF1/FF2 Model */ 347478ed97a7Sjl if ((c = strstr(c, "MEMB")) == NULL) { 347578ed97a7Sjl return (5); 347678ed97a7Sjl } 347778ed97a7Sjl c += 4; 347878ed97a7Sjl 347978ed97a7Sjl x = c[0]; 348078ed97a7Sjl *board = ((uint8_t)stoi(&c)) / 4; 34810cc8ae86Sav } 34820cc8ae86Sav 34830cc8ae86Sav if ((c = strstr(c, "MEM")) == NULL) { 34840cc8ae86Sav return (6); 34850cc8ae86Sav } 34860cc8ae86Sav c += 3; 34870cc8ae86Sav if (strlen(c) < 2) { 34880cc8ae86Sav return (7); 34890cc8ae86Sav } 34900cc8ae86Sav if ((!isdigit(c[0])) || ((c[1] != 'A') && (c[1] != 'B'))) { 34910cc8ae86Sav return (8); 34920cc8ae86Sav } 34930cc8ae86Sav y = c[0]; 34940cc8ae86Sav z = c[1]; 34950cc8ae86Sav } else { 34960cc8ae86Sav return (9); 34970cc8ae86Sav } 34980cc8ae86Sav if (*board < 0) { 34990cc8ae86Sav return (10); 35000cc8ae86Sav } 35010cc8ae86Sav dname[0] = x; 35020cc8ae86Sav dname[1] = y; 35030cc8ae86Sav dname[2] = z; 35040cc8ae86Sav dname[3] = '\0'; 35050cc8ae86Sav return (0); 35060cc8ae86Sav } 35070cc8ae86Sav 35080cc8ae86Sav /* 35090cc8ae86Sav * mc_get_mem_sid_dimm -- Get the serial-ID for a given board and 35100cc8ae86Sav * the DIMM name. 35110cc8ae86Sav */ 35120cc8ae86Sav int 35130cc8ae86Sav mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 35140cc8ae86Sav int buflen, int *lenp) 35150cc8ae86Sav { 35160cc8ae86Sav int ret = ENODEV; 35170cc8ae86Sav mc_dimm_info_t *d = NULL; 35180cc8ae86Sav 35190cc8ae86Sav if ((d = mcp->mc_dimm_list) == NULL) 35200cc8ae86Sav return (ENOTSUP); 35210cc8ae86Sav 35220cc8ae86Sav for (; d != NULL; d = d->md_next) { 35230cc8ae86Sav if (strcmp(d->md_dimmname, dname) == 0) { 35240cc8ae86Sav break; 35250cc8ae86Sav } 35260cc8ae86Sav } 35270cc8ae86Sav if (d != NULL) { 35280cc8ae86Sav *lenp = strlen(d->md_serial) + strlen(d->md_partnum); 35290cc8ae86Sav if (buflen <= *lenp) { 35300cc8ae86Sav cmn_err(CE_WARN, "mc_get_mem_sid_dimm: " 35310cc8ae86Sav "buflen is smaller than %d\n", *lenp); 35320cc8ae86Sav ret = ENOSPC; 35330cc8ae86Sav } else { 35340cc8ae86Sav snprintf(buf, buflen, "%s:%s", 35350cc8ae86Sav d->md_serial, d->md_partnum); 35360cc8ae86Sav ret = 0; 35370cc8ae86Sav } 35380cc8ae86Sav } 35390cc8ae86Sav MC_LOG("mc_get_mem_sid_dimm: Ret=%d Name=%s Serial-ID=%s\n", 35400cc8ae86Sav ret, dname, (ret == 0) ? buf : ""); 35410cc8ae86Sav return (ret); 35420cc8ae86Sav } 35430cc8ae86Sav 35440cc8ae86Sav int 3545aeb241b2Sav mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int sb, 35460cc8ae86Sav int bank, uint32_t mf_type, uint32_t d_slot) 35470cc8ae86Sav { 35480cc8ae86Sav int lenp = buflen; 35490cc8ae86Sav int id; 35500cc8ae86Sav int ret; 35510cc8ae86Sav char *dimmnm; 35520cc8ae86Sav 3553056c948bStsien if (mf_type == FLT_TYPE_INTERMITTENT_CE || 3554056c948bStsien mf_type == FLT_TYPE_PERMANENT_CE) { 35550cc8ae86Sav if (plat_model == MODEL_DC) { 355678ed97a7Sjl /* 355778ed97a7Sjl * All DC models 355878ed97a7Sjl */ 35590cc8ae86Sav id = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 3560aeb241b2Sav dimmnm = mc_dc_dimm_unum_table[id]; 35610cc8ae86Sav } else { 356278ed97a7Sjl /* 356378ed97a7Sjl * All FF and Ikkaku models 356478ed97a7Sjl */ 35650cc8ae86Sav id = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 3566aeb241b2Sav dimmnm = mc_ff_dimm_unum_table[id]; 35670cc8ae86Sav } 35680cc8ae86Sav if ((ret = mc_get_mem_sid_dimm(mcp, dimmnm, buf, buflen, 35690cc8ae86Sav &lenp)) != 0) { 35700cc8ae86Sav return (ret); 35710cc8ae86Sav } 35720cc8ae86Sav } else { 35730cc8ae86Sav return (1); 35740cc8ae86Sav } 35750cc8ae86Sav 35760cc8ae86Sav return (0); 35770cc8ae86Sav } 35780cc8ae86Sav 35790cc8ae86Sav /* 35800cc8ae86Sav * mc_get_mem_sid -- get the DIMM serial-ID corresponding to the unum. 35810cc8ae86Sav */ 35820cc8ae86Sav int 35830cc8ae86Sav mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 35840cc8ae86Sav { 35850cc8ae86Sav int i; 35860cc8ae86Sav int ret = ENODEV; 35870cc8ae86Sav int board; 35880cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 35890cc8ae86Sav mc_opl_t *mcp; 35900cc8ae86Sav 35910cc8ae86Sav MC_LOG("mc_get_mem_sid: unum=%s buflen=%d\n", unum, buflen); 35920cc8ae86Sav if ((ret = parse_unum_memory(unum, &board, dname)) != 0) { 35930cc8ae86Sav MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 35940cc8ae86Sav unum, ret); 35950cc8ae86Sav return (EINVAL); 35960cc8ae86Sav } 35970cc8ae86Sav 35980cc8ae86Sav if (board < 0) { 35990cc8ae86Sav MC_LOG("mc_get_mem_sid: Invalid board=%d dimm=%s\n", 36000cc8ae86Sav board, dname); 36010cc8ae86Sav return (EINVAL); 36020cc8ae86Sav } 36030cc8ae86Sav 36040cc8ae86Sav mutex_enter(&mcmutex); 36051039f409Sav /* 36061039f409Sav * return ENOENT if we can not find the matching board. 36071039f409Sav */ 36081039f409Sav ret = ENOENT; 36090cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 36100cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 36110cc8ae86Sav continue; 36120cc8ae86Sav mutex_enter(&mcp->mc_lock); 3613aeb241b2Sav if (mcp->mc_phys_board_num != board) { 3614aeb241b2Sav mutex_exit(&mcp->mc_lock); 3615aeb241b2Sav continue; 3616aeb241b2Sav } 3617aeb241b2Sav ret = mc_get_mem_sid_dimm(mcp, dname, buf, buflen, lenp); 3618aeb241b2Sav if (ret == 0) { 36190cc8ae86Sav mutex_exit(&mcp->mc_lock); 36200cc8ae86Sav break; 36210cc8ae86Sav } 36220cc8ae86Sav mutex_exit(&mcp->mc_lock); 36230cc8ae86Sav } 36240cc8ae86Sav mutex_exit(&mcmutex); 36250cc8ae86Sav return (ret); 36260cc8ae86Sav } 36270cc8ae86Sav 36280cc8ae86Sav /* 36290cc8ae86Sav * mc_get_mem_offset -- get the offset in a DIMM for a given physical address. 36300cc8ae86Sav */ 36310cc8ae86Sav int 36320cc8ae86Sav mc_get_mem_offset(uint64_t paddr, uint64_t *offp) 36330cc8ae86Sav { 36340cc8ae86Sav int i; 36350cc8ae86Sav int ret = ENODEV; 36360cc8ae86Sav mc_addr_t maddr; 36370cc8ae86Sav mc_opl_t *mcp; 36380cc8ae86Sav 36390cc8ae86Sav mutex_enter(&mcmutex); 3640c964b0e6Sraghuram for (i = 0; ((i < OPL_MAX_BOARDS) && (ret != 0)); i++) { 36410cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 36420cc8ae86Sav continue; 36430cc8ae86Sav mutex_enter(&mcp->mc_lock); 36440cc8ae86Sav if (!pa_is_valid(mcp, paddr)) { 36450cc8ae86Sav mutex_exit(&mcp->mc_lock); 36460cc8ae86Sav continue; 36470cc8ae86Sav } 36480cc8ae86Sav if (pa_to_maddr(mcp, paddr, &maddr) == 0) { 36490cc8ae86Sav *offp = maddr.ma_dimm_addr; 36500cc8ae86Sav ret = 0; 36510cc8ae86Sav } 36520cc8ae86Sav mutex_exit(&mcp->mc_lock); 36530cc8ae86Sav } 36540cc8ae86Sav mutex_exit(&mcmutex); 36550cc8ae86Sav MC_LOG("mc_get_mem_offset: Ret=%d paddr=0x%lx offset=0x%lx\n", 36560cc8ae86Sav ret, paddr, *offp); 36570cc8ae86Sav return (ret); 36580cc8ae86Sav } 36590cc8ae86Sav 36600cc8ae86Sav /* 36610cc8ae86Sav * dname_to_bankslot - Get the bank and slot number from the DIMM name. 36620cc8ae86Sav */ 36630cc8ae86Sav int 36640cc8ae86Sav dname_to_bankslot(char *dname, int *bank, int *slot) 36650cc8ae86Sav { 36660cc8ae86Sav int i; 36670cc8ae86Sav int tsz; 36680cc8ae86Sav char **tbl; 36690cc8ae86Sav 367078ed97a7Sjl if (plat_model == MODEL_DC) { 367178ed97a7Sjl /* 367278ed97a7Sjl * All DC models 367378ed97a7Sjl */ 36740cc8ae86Sav tbl = mc_dc_dimm_unum_table; 36750cc8ae86Sav tsz = OPL_MAX_DIMMS; 36760cc8ae86Sav } else { 367778ed97a7Sjl /* 367878ed97a7Sjl * All FF and Ikkaku models 367978ed97a7Sjl */ 36800cc8ae86Sav tbl = mc_ff_dimm_unum_table; 36810cc8ae86Sav tsz = 2 * OPL_MAX_DIMMS; 36820cc8ae86Sav } 36830cc8ae86Sav 36840cc8ae86Sav for (i = 0; i < tsz; i++) { 36850cc8ae86Sav if (strcmp(dname, tbl[i]) == 0) { 36860cc8ae86Sav break; 36870cc8ae86Sav } 36880cc8ae86Sav } 36890cc8ae86Sav if (i == tsz) { 36900cc8ae86Sav return (1); 36910cc8ae86Sav } 36920cc8ae86Sav *bank = INDEX_TO_BANK(i); 36930cc8ae86Sav *slot = INDEX_TO_SLOT(i); 36940cc8ae86Sav return (0); 36950cc8ae86Sav } 36960cc8ae86Sav 36970cc8ae86Sav /* 36980cc8ae86Sav * mc_get_mem_addr -- get the physical address of a DIMM corresponding 36990cc8ae86Sav * to the unum and sid. 37000cc8ae86Sav */ 37010cc8ae86Sav int 37020cc8ae86Sav mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr) 37030cc8ae86Sav { 37040cc8ae86Sav int board; 37050cc8ae86Sav int bank; 37060cc8ae86Sav int slot; 37070cc8ae86Sav int i; 37080cc8ae86Sav int ret = ENODEV; 37090cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 37100cc8ae86Sav mc_addr_t maddr; 37110cc8ae86Sav mc_opl_t *mcp; 37120cc8ae86Sav 37130cc8ae86Sav MC_LOG("mc_get_mem_addr: unum=%s sid=%s offset=0x%lx\n", 37140cc8ae86Sav unum, sid, offset); 37150cc8ae86Sav if (parse_unum_memory(unum, &board, dname) != 0) { 37160cc8ae86Sav MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 37170cc8ae86Sav unum, ret); 37180cc8ae86Sav return (EINVAL); 37190cc8ae86Sav } 37200cc8ae86Sav 37210cc8ae86Sav if (board < 0) { 37220cc8ae86Sav MC_LOG("mc_get_mem_addr: Invalid board=%d dimm=%s\n", 37230cc8ae86Sav board, dname); 37240cc8ae86Sav return (EINVAL); 37250cc8ae86Sav } 37260cc8ae86Sav 37270cc8ae86Sav mutex_enter(&mcmutex); 37280cc8ae86Sav for (i = 0; i < OPL_MAX_BOARDS; i++) { 37290cc8ae86Sav if ((mcp = mc_instances[i]) == NULL) 37300cc8ae86Sav continue; 37310cc8ae86Sav mutex_enter(&mcp->mc_lock); 3732aeb241b2Sav if (mcp->mc_phys_board_num != board) { 37330cc8ae86Sav mutex_exit(&mcp->mc_lock); 37340cc8ae86Sav continue; 37350cc8ae86Sav } 37360cc8ae86Sav 37370cc8ae86Sav ret = dname_to_bankslot(dname, &bank, &slot); 37380cc8ae86Sav MC_LOG("mc_get_mem_addr: bank=%d slot=%d\n", bank, slot); 37390cc8ae86Sav if (ret != 0) { 37400cc8ae86Sav MC_LOG("mc_get_mem_addr: dname_to_bankslot failed\n"); 37410cc8ae86Sav ret = ENODEV; 37420cc8ae86Sav } else { 3743aeb241b2Sav maddr.ma_bd = mcp->mc_board_num; 37440cc8ae86Sav maddr.ma_bank = bank; 37450cc8ae86Sav maddr.ma_dimm_addr = offset; 37460cc8ae86Sav ret = mcaddr_to_pa(mcp, &maddr, paddr); 37470cc8ae86Sav if (ret != 0) { 37480cc8ae86Sav MC_LOG("mc_get_mem_addr: " 37490cc8ae86Sav "mcaddr_to_pa failed\n"); 37500cc8ae86Sav ret = ENODEV; 37510b240fcdSwh mutex_exit(&mcp->mc_lock); 37520b240fcdSwh continue; 37530cc8ae86Sav } 3754aeb241b2Sav mutex_exit(&mcp->mc_lock); 3755aeb241b2Sav break; 37560cc8ae86Sav } 37570cc8ae86Sav mutex_exit(&mcp->mc_lock); 37580cc8ae86Sav } 37590cc8ae86Sav mutex_exit(&mcmutex); 37600cc8ae86Sav MC_LOG("mc_get_mem_addr: Ret=%d, Paddr=0x%lx\n", ret, *paddr); 37610cc8ae86Sav return (ret); 37620cc8ae86Sav } 37630cc8ae86Sav 37640cc8ae86Sav static void 37650cc8ae86Sav mc_free_dimm_list(mc_dimm_info_t *d) 37660cc8ae86Sav { 37670cc8ae86Sav mc_dimm_info_t *next; 37680cc8ae86Sav 37690cc8ae86Sav while (d != NULL) { 37700cc8ae86Sav next = d->md_next; 37710cc8ae86Sav kmem_free(d, sizeof (mc_dimm_info_t)); 37720cc8ae86Sav d = next; 37730cc8ae86Sav } 37740cc8ae86Sav } 37750cc8ae86Sav 37760cc8ae86Sav /* 37770cc8ae86Sav * mc_get_dimm_list -- get the list of dimms with serial-id info 37780cc8ae86Sav * from the SP. 37790cc8ae86Sav */ 37800cc8ae86Sav mc_dimm_info_t * 37810cc8ae86Sav mc_get_dimm_list(mc_opl_t *mcp) 37820cc8ae86Sav { 37830cc8ae86Sav uint32_t bufsz; 37840cc8ae86Sav uint32_t maxbufsz; 37850cc8ae86Sav int ret; 37860cc8ae86Sav int sexp; 37870cc8ae86Sav board_dimm_info_t *bd_dimmp; 37880cc8ae86Sav mc_dimm_info_t *dimm_list = NULL; 37890cc8ae86Sav 37900cc8ae86Sav maxbufsz = bufsz = sizeof (board_dimm_info_t) + 37910cc8ae86Sav ((MCOPL_MAX_DIMMNAME + MCOPL_MAX_SERIAL + 37920cc8ae86Sav MCOPL_MAX_PARTNUM) * OPL_MAX_DIMMS); 37930cc8ae86Sav 37940cc8ae86Sav bd_dimmp = (board_dimm_info_t *)kmem_alloc(bufsz, KM_SLEEP); 37950cc8ae86Sav ret = scf_get_dimminfo(mcp->mc_board_num, (void *)bd_dimmp, &bufsz); 37960cc8ae86Sav 37970cc8ae86Sav MC_LOG("mc_get_dimm_list: scf_service_getinfo returned=%d\n", ret); 37980cc8ae86Sav if (ret == 0) { 37990cc8ae86Sav sexp = sizeof (board_dimm_info_t) + 38000cc8ae86Sav ((bd_dimmp->bd_dnamesz + bd_dimmp->bd_serialsz + 38010cc8ae86Sav bd_dimmp->bd_partnumsz) * bd_dimmp->bd_numdimms); 38020cc8ae86Sav 38030cc8ae86Sav if ((bd_dimmp->bd_version == OPL_DIMM_INFO_VERSION) && 38040cc8ae86Sav (bd_dimmp->bd_dnamesz <= MCOPL_MAX_DIMMNAME) && 38050cc8ae86Sav (bd_dimmp->bd_serialsz <= MCOPL_MAX_SERIAL) && 38060cc8ae86Sav (bd_dimmp->bd_partnumsz <= MCOPL_MAX_PARTNUM) && 38070cc8ae86Sav (sexp <= bufsz)) { 38080cc8ae86Sav 38090cc8ae86Sav #ifdef DEBUG 38100cc8ae86Sav if (oplmc_debug) 38110cc8ae86Sav mc_dump_dimm_info(bd_dimmp); 38120cc8ae86Sav #endif 38130cc8ae86Sav dimm_list = mc_prepare_dimmlist(bd_dimmp); 38140cc8ae86Sav 38150cc8ae86Sav } else { 38160cc8ae86Sav cmn_err(CE_WARN, "DIMM info version mismatch\n"); 38170cc8ae86Sav } 38180cc8ae86Sav } 38190cc8ae86Sav kmem_free(bd_dimmp, maxbufsz); 38200cc8ae86Sav MC_LOG("mc_get_dimm_list: dimmlist=0x%p\n", dimm_list); 38210cc8ae86Sav return (dimm_list); 38220cc8ae86Sav } 38230cc8ae86Sav 38240cc8ae86Sav /* 38251039f409Sav * mc_prepare_dimmlist - Prepare the dimm list from the information 38261039f409Sav * received from the SP. 38270cc8ae86Sav */ 38280cc8ae86Sav mc_dimm_info_t * 38290cc8ae86Sav mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp) 38300cc8ae86Sav { 38310cc8ae86Sav char *dimm_name; 38320cc8ae86Sav char *serial; 38330cc8ae86Sav char *part; 38340cc8ae86Sav int dimm; 38350cc8ae86Sav int dnamesz = bd_dimmp->bd_dnamesz; 38360cc8ae86Sav int sersz = bd_dimmp->bd_serialsz; 38370cc8ae86Sav int partsz = bd_dimmp->bd_partnumsz; 38380cc8ae86Sav mc_dimm_info_t *dimm_list = NULL; 38390cc8ae86Sav mc_dimm_info_t *d; 38400cc8ae86Sav 38410cc8ae86Sav dimm_name = (char *)(bd_dimmp + 1); 38420cc8ae86Sav for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 38430cc8ae86Sav 38440cc8ae86Sav d = (mc_dimm_info_t *)kmem_alloc(sizeof (mc_dimm_info_t), 38450cc8ae86Sav KM_SLEEP); 3846ad59b69dSbm 3847ad59b69dSbm bcopy(dimm_name, d->md_dimmname, dnamesz); 3848ad59b69dSbm d->md_dimmname[dnamesz] = 0; 3849ad59b69dSbm 38500cc8ae86Sav serial = dimm_name + dnamesz; 3851ad59b69dSbm bcopy(serial, d->md_serial, sersz); 3852ad59b69dSbm d->md_serial[sersz] = 0; 3853ad59b69dSbm 38540cc8ae86Sav part = serial + sersz; 3855ad59b69dSbm bcopy(part, d->md_partnum, partsz); 3856ad59b69dSbm d->md_partnum[partsz] = 0; 38570cc8ae86Sav 38580cc8ae86Sav d->md_next = dimm_list; 38590cc8ae86Sav dimm_list = d; 38600cc8ae86Sav dimm_name = part + partsz; 38610cc8ae86Sav } 38620cc8ae86Sav return (dimm_list); 38630cc8ae86Sav } 38640cc8ae86Sav 38650b240fcdSwh static int 38660b240fcdSwh mc_get_mem_fmri(mc_flt_page_t *fpag, char **unum) 38670b240fcdSwh { 38680b240fcdSwh if (fpag->fmri_addr == 0 || fpag->fmri_sz > MEM_FMRI_MAX_BUFSIZE) 38690b240fcdSwh return (EINVAL); 38700b240fcdSwh 38710b240fcdSwh *unum = kmem_alloc(fpag->fmri_sz, KM_SLEEP); 38720b240fcdSwh if (copyin((void *)fpag->fmri_addr, *unum, fpag->fmri_sz) != 0) { 38730b240fcdSwh kmem_free(*unum, fpag->fmri_sz); 38740b240fcdSwh return (EFAULT); 38750b240fcdSwh } 38760b240fcdSwh return (0); 38770b240fcdSwh } 38780b240fcdSwh 38790b240fcdSwh static int 38800b240fcdSwh mc_scf_log_event(mc_flt_page_t *flt_pag) 38810b240fcdSwh { 38820b240fcdSwh mc_opl_t *mcp; 38830b240fcdSwh int board, bank, slot; 38840b240fcdSwh int len, rv = 0; 38850b240fcdSwh char *unum, *sid; 38860b240fcdSwh char dname[MCOPL_MAX_DIMMNAME + 1]; 38870b240fcdSwh size_t sid_sz; 38880b240fcdSwh uint64_t pa; 38890b240fcdSwh mc_flt_stat_t flt_stat; 38900b240fcdSwh 38910b240fcdSwh if ((sid_sz = cpu_get_name_bufsize()) == 0) 38920b240fcdSwh return (ENOTSUP); 38930b240fcdSwh 38940b240fcdSwh if ((rv = mc_get_mem_fmri(flt_pag, &unum)) != 0) { 38950b240fcdSwh MC_LOG("mc_scf_log_event: mc_get_mem_fmri failed\n"); 38960b240fcdSwh return (rv); 38970b240fcdSwh } 38980b240fcdSwh 38990b240fcdSwh sid = kmem_zalloc(sid_sz, KM_SLEEP); 39000b240fcdSwh 39010b240fcdSwh if ((rv = mc_get_mem_sid(unum, sid, sid_sz, &len)) != 0) { 39020b240fcdSwh MC_LOG("mc_scf_log_event: mc_get_mem_sid failed\n"); 39030b240fcdSwh goto out; 39040b240fcdSwh } 39050b240fcdSwh 39060b240fcdSwh if ((rv = mc_get_mem_addr(unum, sid, (uint64_t)flt_pag->err_add, 39070b240fcdSwh &pa)) != 0) { 39080b240fcdSwh MC_LOG("mc_scf_log_event: mc_get_mem_addr failed\n"); 39090b240fcdSwh goto out; 39100b240fcdSwh } 39110b240fcdSwh 39120b240fcdSwh if (parse_unum_memory(unum, &board, dname) != 0) { 39130b240fcdSwh MC_LOG("mc_scf_log_event: parse_unum_memory failed\n"); 39140b240fcdSwh rv = EINVAL; 39150b240fcdSwh goto out; 39160b240fcdSwh } 39170b240fcdSwh 39180b240fcdSwh if (board < 0) { 39190b240fcdSwh MC_LOG("mc_scf_log_event: Invalid board=%d dimm=%s\n", 39200b240fcdSwh board, dname); 39210b240fcdSwh rv = EINVAL; 39220b240fcdSwh goto out; 39230b240fcdSwh } 39240b240fcdSwh 39250b240fcdSwh if (dname_to_bankslot(dname, &bank, &slot) != 0) { 39260b240fcdSwh MC_LOG("mc_scf_log_event: dname_to_bankslot failed\n"); 39270b240fcdSwh rv = EINVAL; 39280b240fcdSwh goto out; 39290b240fcdSwh } 39300b240fcdSwh 39310b240fcdSwh mutex_enter(&mcmutex); 39320b240fcdSwh 39330b240fcdSwh flt_stat.mf_err_add = flt_pag->err_add; 39340b240fcdSwh flt_stat.mf_err_log = flt_pag->err_log; 39350b240fcdSwh flt_stat.mf_flt_paddr = pa; 39360b240fcdSwh 39370b240fcdSwh if ((mcp = mc_pa_to_mcp(pa)) == NULL) { 39380b240fcdSwh mutex_exit(&mcmutex); 39390b240fcdSwh MC_LOG("mc_scf_log_event: invalid pa\n"); 39400b240fcdSwh rv = EINVAL; 39410b240fcdSwh goto out; 39420b240fcdSwh } 39430b240fcdSwh 39440b240fcdSwh MC_LOG("mc_scf_log_event: DIMM%s, /LSB%d/B%d/%x, pa %lx elog %x\n", 39450b240fcdSwh unum, mcp->mc_board_num, bank, flt_pag->err_add, pa, 39460b240fcdSwh flt_pag->err_log); 39470b240fcdSwh 39480b240fcdSwh mutex_enter(&mcp->mc_lock); 39490b240fcdSwh 39500b240fcdSwh if (!pa_is_valid(mcp, pa)) { 39510b240fcdSwh mutex_exit(&mcp->mc_lock); 39520b240fcdSwh mutex_exit(&mcmutex); 39530b240fcdSwh rv = EINVAL; 39540b240fcdSwh goto out; 39550b240fcdSwh } 39560b240fcdSwh 39570b240fcdSwh rv = 0; 39580b240fcdSwh 39590b240fcdSwh mc_queue_scf_log(mcp, &flt_stat, bank); 39600b240fcdSwh 39610b240fcdSwh mutex_exit(&mcp->mc_lock); 39620b240fcdSwh mutex_exit(&mcmutex); 39630b240fcdSwh 39640b240fcdSwh out: 39650b240fcdSwh kmem_free(unum, flt_pag->fmri_sz); 39660b240fcdSwh kmem_free(sid, sid_sz); 39670b240fcdSwh 39680b240fcdSwh return (rv); 39690b240fcdSwh } 39700b240fcdSwh 39710cc8ae86Sav #ifdef DEBUG 39720cc8ae86Sav void 39730cc8ae86Sav mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz) 39740cc8ae86Sav { 39750cc8ae86Sav char dname[MCOPL_MAX_DIMMNAME + 1]; 39760cc8ae86Sav char serial[MCOPL_MAX_SERIAL + 1]; 39770cc8ae86Sav char part[ MCOPL_MAX_PARTNUM + 1]; 39780cc8ae86Sav char *b; 39790cc8ae86Sav 39800cc8ae86Sav b = buf; 3981ad59b69dSbm bcopy(b, dname, dnamesz); 3982ad59b69dSbm dname[dnamesz] = 0; 3983ad59b69dSbm 39840cc8ae86Sav b += dnamesz; 3985ad59b69dSbm bcopy(b, serial, serialsz); 3986ad59b69dSbm serial[serialsz] = 0; 3987ad59b69dSbm 39880cc8ae86Sav b += serialsz; 3989ad59b69dSbm bcopy(b, part, partnumsz); 3990ad59b69dSbm part[partnumsz] = 0; 3991ad59b69dSbm 39920cc8ae86Sav printf("DIMM=%s Serial=%s PartNum=%s\n", dname, serial, part); 39930cc8ae86Sav } 39940cc8ae86Sav 39950cc8ae86Sav void 39960cc8ae86Sav mc_dump_dimm_info(board_dimm_info_t *bd_dimmp) 39970cc8ae86Sav { 39980cc8ae86Sav int dimm; 39990cc8ae86Sav int dnamesz = bd_dimmp->bd_dnamesz; 40000cc8ae86Sav int sersz = bd_dimmp->bd_serialsz; 40010cc8ae86Sav int partsz = bd_dimmp->bd_partnumsz; 40020cc8ae86Sav char *buf; 40030cc8ae86Sav 40040cc8ae86Sav printf("Version=%d Board=%02d DIMMs=%d NameSize=%d " 40050cc8ae86Sav "SerialSize=%d PartnumSize=%d\n", bd_dimmp->bd_version, 40060cc8ae86Sav bd_dimmp->bd_boardnum, bd_dimmp->bd_numdimms, bd_dimmp->bd_dnamesz, 40070cc8ae86Sav bd_dimmp->bd_serialsz, bd_dimmp->bd_partnumsz); 40080cc8ae86Sav printf("======================================================\n"); 40090cc8ae86Sav 40100cc8ae86Sav buf = (char *)(bd_dimmp + 1); 40110cc8ae86Sav for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 40120cc8ae86Sav mc_dump_dimm(buf, dnamesz, sersz, partsz); 40130cc8ae86Sav buf += dnamesz + sersz + partsz; 40140cc8ae86Sav } 40150cc8ae86Sav printf("======================================================\n"); 40160cc8ae86Sav } 40170cc8ae86Sav 40180cc8ae86Sav 40190cc8ae86Sav /* ARGSUSED */ 40200cc8ae86Sav static int 40210cc8ae86Sav mc_ioctl_debug(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 40220cc8ae86Sav int *rvalp) 40230cc8ae86Sav { 40240b240fcdSwh caddr_t buf, kbuf; 40250cc8ae86Sav uint64_t pa; 40260cc8ae86Sav int rv = 0; 40270cc8ae86Sav int i; 40280cc8ae86Sav uint32_t flags; 40290cc8ae86Sav static uint32_t offset = 0; 40300cc8ae86Sav 40310cc8ae86Sav 40320cc8ae86Sav flags = (cmd >> 4) & 0xfffffff; 40330cc8ae86Sav 40340cc8ae86Sav cmd &= 0xf; 40350cc8ae86Sav 40360cc8ae86Sav MC_LOG("mc_ioctl(cmd = %x, flags = %x)\n", cmd, flags); 40370cc8ae86Sav 40380cc8ae86Sav if (arg != NULL) { 40390cc8ae86Sav if (ddi_copyin((const void *)arg, (void *)&pa, 4040d8a0cca9Swh sizeof (uint64_t), 0) < 0) { 40410cc8ae86Sav rv = EFAULT; 40420cc8ae86Sav return (rv); 40430cc8ae86Sav } 40440cc8ae86Sav buf = NULL; 40450cc8ae86Sav } else { 40460cc8ae86Sav buf = (caddr_t)kmem_alloc(PAGESIZE, KM_SLEEP); 40470cc8ae86Sav 40480cc8ae86Sav pa = va_to_pa(buf); 40490cc8ae86Sav pa += offset; 40500cc8ae86Sav 40510cc8ae86Sav offset += 64; 40520cc8ae86Sav if (offset >= PAGESIZE) 40530cc8ae86Sav offset = 0; 40540cc8ae86Sav } 40550cc8ae86Sav 40560cc8ae86Sav switch (cmd) { 40570cc8ae86Sav case MCI_CE: 4058d8a0cca9Swh mc_inject_error(MC_INJECT_INTERMITTENT_CE, pa, flags); 40590cc8ae86Sav break; 40600cc8ae86Sav case MCI_PERM_CE: 4061d8a0cca9Swh mc_inject_error(MC_INJECT_PERMANENT_CE, pa, flags); 40620cc8ae86Sav break; 40630cc8ae86Sav case MCI_UE: 4064d8a0cca9Swh mc_inject_error(MC_INJECT_UE, pa, flags); 40650cc8ae86Sav break; 40660cc8ae86Sav case MCI_M_CE: 4067d8a0cca9Swh mc_inject_error(MC_INJECT_INTERMITTENT_MCE, pa, flags); 40680cc8ae86Sav break; 40690cc8ae86Sav case MCI_M_PCE: 4070d8a0cca9Swh mc_inject_error(MC_INJECT_PERMANENT_MCE, pa, flags); 40710cc8ae86Sav break; 40720cc8ae86Sav case MCI_M_UE: 4073d8a0cca9Swh mc_inject_error(MC_INJECT_MUE, pa, flags); 40740cc8ae86Sav break; 40750cc8ae86Sav case MCI_CMP: 4076d8a0cca9Swh mc_inject_error(MC_INJECT_CMPE, pa, flags); 40770cc8ae86Sav break; 40780cc8ae86Sav case MCI_NOP: 4079d8a0cca9Swh mc_inject_error(MC_INJECT_NOP, pa, flags); break; 40800cc8ae86Sav case MCI_SHOW_ALL: 40810cc8ae86Sav mc_debug_show_all = 1; 40820cc8ae86Sav break; 40830cc8ae86Sav case MCI_SHOW_NONE: 40840cc8ae86Sav mc_debug_show_all = 0; 40850cc8ae86Sav break; 40860cc8ae86Sav case MCI_ALLOC: 40870cc8ae86Sav /* 40880cc8ae86Sav * just allocate some kernel memory and never free it 40890cc8ae86Sav * 512 MB seems to be the maximum size supported. 40900cc8ae86Sav */ 40910cc8ae86Sav cmn_err(CE_NOTE, "Allocating kmem %d MB\n", flags * 512); 40920cc8ae86Sav for (i = 0; i < flags; i++) { 40930b240fcdSwh kbuf = kmem_alloc(512 * 1024 * 1024, KM_SLEEP); 40940cc8ae86Sav cmn_err(CE_NOTE, "kmem buf %llx PA %llx\n", 40950b240fcdSwh (u_longlong_t)kbuf, (u_longlong_t)va_to_pa(kbuf)); 40960cc8ae86Sav } 40970cc8ae86Sav break; 40980cc8ae86Sav case MCI_SUSPEND: 40990cc8ae86Sav (void) opl_mc_suspend(); 41000cc8ae86Sav break; 41010cc8ae86Sav case MCI_RESUME: 41020cc8ae86Sav (void) opl_mc_resume(); 41030cc8ae86Sav break; 41040cc8ae86Sav default: 41050cc8ae86Sav rv = ENXIO; 41060cc8ae86Sav } 41070b240fcdSwh if (buf) 41080b240fcdSwh kmem_free(buf, PAGESIZE); 41090b240fcdSwh 41100cc8ae86Sav return (rv); 41110cc8ae86Sav } 41120cc8ae86Sav 41130cc8ae86Sav #endif /* DEBUG */ 4114