xref: /illumos-gate/usr/src/uts/sun4u/io/pci/pci_pci.c (revision e51949e6)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  *	Sun4u PCI to PCI bus bridge nexus driver
30  */
31 
32 #include <sys/conf.h>
33 #include <sys/kmem.h>
34 #include <sys/debug.h>
35 #include <sys/modctl.h>
36 #include <sys/autoconf.h>
37 #include <sys/ddi_impldefs.h>
38 #include <sys/ddi_subrdefs.h>
39 #include <sys/pci.h>
40 #include <sys/pci_impl.h>
41 #include <sys/pci_cap.h>
42 #include <sys/pci/pci_nexus.h>
43 #include <sys/pci/pci_regs.h>
44 #include <sys/ddi.h>
45 #include <sys/sunndi.h>
46 #include <sys/sunddi.h>
47 #include <sys/fm/protocol.h>
48 #include <sys/ddifm.h>
49 #include <sys/pci/pci_pwr.h>
50 #include <sys/pci/pci_debug.h>
51 #include <sys/hotplug/pci/pcihp.h>
52 #include <sys/open.h>
53 #include <sys/stat.h>
54 #include <sys/file.h>
55 
56 #define	NUM_LOGICAL_SLOTS	32
57 
58 #define	PPB_RANGE_LEN 2
59 
60 #define	PPB_32BIT_IO 1
61 #define	PPB_32bit_MEM 1
62 
63 #define	PPB_MEMGRAIN 0x100000
64 #define	PPB_IOGRAIN 0x1000
65 
66 #define	PPB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8))
67 #define	PPB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo))
68 #define	PPB_32bit_MEMADDR(addr) (PPB_LADDR(0, ((uint16_t)(addr) & 0xFFF0)))
69 
70 typedef struct	slot_table {
71 	uchar_t		bus_id[128];
72 	uchar_t		slot_name[32];
73 	uint8_t		device_no;
74 	uint8_t		phys_slot_num;
75 } slot_table_t;
76 
77 /*
78  * The variable controls the default setting of the command register
79  * for pci devices.  See ppb_initchild() for details.
80  */
81 static ushort_t ppb_command_default = PCI_COMM_SERR_ENABLE |
82 					PCI_COMM_WAIT_CYC_ENAB |
83 					PCI_COMM_PARITY_DETECT |
84 					PCI_COMM_ME |
85 					PCI_COMM_MAE |
86 					PCI_COMM_IO;
87 
88 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
89 	off_t, off_t, caddr_t *);
90 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
91 	void *, void *);
92 static int ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip,
93 	ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result);
94 
95 /*
96  * fm_init busop to initialize our children
97  */
98 static int ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
99 		ddi_iblock_cookie_t *ibc);
100 static void ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle);
101 static void ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle);
102 static int ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op,
103     void *arg, void *result);
104 
105 struct bus_ops ppb_bus_ops = {
106 	BUSO_REV,
107 	ppb_bus_map,
108 	0,
109 	0,
110 	0,
111 	i_ddi_map_fault,
112 	ddi_dma_map,
113 	ddi_dma_allochdl,
114 	ddi_dma_freehdl,
115 	ddi_dma_bindhdl,
116 	ddi_dma_unbindhdl,
117 	ddi_dma_flush,
118 	ddi_dma_win,
119 	ddi_dma_mctl,
120 	ppb_ctlops,
121 	ddi_bus_prop_op,
122 	ndi_busop_get_eventcookie,	/* (*bus_get_eventcookie)();    */
123 	ndi_busop_add_eventcall,	/* (*bus_add_eventcall)();	*/
124 	ndi_busop_remove_eventcall,	/* (*bus_remove_eventcall)();   */
125 	ndi_post_event,			/* (*bus_post_event)();		*/
126 	0,				/* (*bus_intr_ctl)();		*/
127 	0,				/* (*bus_config)(); 		*/
128 	0,				/* (*bus_unconfig)(); 		*/
129 	ppb_fm_init_child,		/* (*bus_fm_init)(); 		*/
130 	NULL,				/* (*bus_fm_fini)(); 		*/
131 	ppb_bus_enter,			/* (*bus_enter)()		*/
132 	ppb_bus_exit,			/* (*bus_exit)()		*/
133 	ppb_bus_power,			/* (*bus_power)()		*/
134 	ppb_intr_ops			/* (*bus_intr_op)(); 		*/
135 };
136 
137 static int ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp);
138 static int ppb_close(dev_t dev, int flags, int otyp, cred_t *credp);
139 static int ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode,
140 						cred_t *credp, int *rvalp);
141 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
142     int flags, char *name, caddr_t valuep, int *lengthp);
143 static int ppb_get_bdf_from_dip(dev_info_t *dip, uint32_t *bdf);
144 
145 static struct cb_ops ppb_cb_ops = {
146 	ppb_open,			/* open */
147 	ppb_close,			/* close */
148 	nulldev,			/* strategy */
149 	nulldev,			/* print */
150 	nulldev,			/* dump */
151 	nulldev,			/* read */
152 	nulldev,			/* write */
153 	ppb_ioctl,			/* ioctl */
154 	nodev,				/* devmap */
155 	nodev,				/* mmap */
156 	nodev,				/* segmap */
157 	nochpoll,			/* poll */
158 	ppb_prop_op,			/* cb_prop_op */
159 	NULL,				/* streamtab */
160 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
161 	CB_REV,				/* rev */
162 	nodev,				/* int (*cb_aread)() */
163 	nodev				/* int (*cb_awrite)() */
164 };
165 
166 static int ppb_probe(dev_info_t *);
167 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
168 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
169 static int ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
170     void *arg, void **result);
171 static int ppb_pwr(dev_info_t *dip, int component, int level);
172 
173 struct dev_ops ppb_ops = {
174 	DEVO_REV,		/* devo_rev */
175 	0,			/* refcnt  */
176 	ppb_info,		/* info */
177 	nulldev,		/* identify */
178 	ppb_probe,		/* probe */
179 	ppb_attach,		/* attach */
180 	ppb_detach,		/* detach */
181 	nulldev,		/* reset */
182 	&ppb_cb_ops,		/* driver operations */
183 	&ppb_bus_ops,		/* bus operations */
184 	ppb_pwr
185 };
186 
187 /*
188  * Module linkage information for the kernel.
189  */
190 
191 static struct modldrv modldrv = {
192 	&mod_driverops, /* Type of module */
193 	"Standard PCI to PCI bridge nexus driver %I%",
194 	&ppb_ops,	/* driver ops */
195 };
196 
197 static struct modlinkage modlinkage = {
198 	MODREV_1,
199 	(void *)&modldrv,
200 	NULL
201 };
202 
203 /*
204  * soft state pointer and structure template:
205  */
206 static void *ppb_state;
207 
208 struct ppb_cfg_state {
209 	dev_info_t *dip;
210 	ushort_t command;
211 	uchar_t cache_line_size;
212 	uchar_t latency_timer;
213 	uchar_t header_type;
214 	uchar_t sec_latency_timer;
215 	ushort_t bridge_control;
216 };
217 
218 typedef struct {
219 
220 	dev_info_t *dip;
221 
222 	/*
223 	 * configuration register state for the bus:
224 	 */
225 	uchar_t ppb_cache_line_size;
226 	uchar_t ppb_latency_timer;
227 
228 	/*
229 	 * PM support
230 	 */
231 	ddi_acc_handle_t	ppb_conf_hdl;
232 	uint16_t		ppb_pm_cap_ptr;
233 	pci_pwr_t		*ppb_pwr_p;
234 
235 	/*
236 	 * HP support
237 	 */
238 	boolean_t		hotplug_capable;
239 
240 	kmutex_t ppb_mutex;
241 	uint_t ppb_soft_state;
242 #define	PPB_SOFT_STATE_CLOSED		0x00
243 #define	PPB_SOFT_STATE_OPEN		0x01
244 #define	PPB_SOFT_STATE_OPEN_EXCL	0x02
245 	int fm_cap;
246 	ddi_iblock_cookie_t fm_ibc;
247 } ppb_devstate_t;
248 
249 /*
250  * The following variable enables a workaround for the following obp bug:
251  *
252  *	1234181 - obp should set latency timer registers in pci
253  *		configuration header
254  *
255  * Until this bug gets fixed in the obp, the following workaround should
256  * be enabled.
257  */
258 static uint_t ppb_set_latency_timer_register = 1;
259 
260 /*
261  * The following variable enables a workaround for an obp bug to be
262  * submitted.  A bug requesting a workaround fof this problem has
263  * been filed:
264  *
265  *	1235094 - need workarounds on positron nexus drivers to set cache
266  *		line size registers
267  *
268  * Until this bug gets fixed in the obp, the following workaround should
269  * be enabled.
270  */
271 static uint_t ppb_set_cache_line_size_register = 1;
272 
273 /*
274  * forward function declarations:
275  */
276 
277 /*
278  * FMA error callback
279  * Register error handling callback with our parent. We will just call
280  * our children's error callbacks and return their status.
281  */
282 static int ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr,
283 		const void *impl_data);
284 
285 /*
286  * init/fini routines to alloc/dealloc fm structures and
287  * register/unregister our callback.
288  */
289 static void ppb_fm_init(ppb_devstate_t *ppb_p);
290 static void ppb_fm_fini(ppb_devstate_t *ppb_p);
291 
292 static void ppb_removechild(dev_info_t *);
293 static int ppb_initchild(dev_info_t *child);
294 static dev_info_t *get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
295 static void ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *dip);
296 static void ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip);
297 static void ppb_init_hotplug(ppb_devstate_t *ppb);
298 static void ppb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t);
299 uint64_t pci_debug_flags = 0;
300 
301 int
302 _init(void)
303 {
304 	int e;
305 	if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t),
306 	    1)) == 0 && (e = mod_install(&modlinkage)) != 0)
307 		ddi_soft_state_fini(&ppb_state);
308 	return (e);
309 }
310 
311 int
312 _fini(void)
313 {
314 	int e;
315 
316 	if ((e = mod_remove(&modlinkage)) == 0)
317 		ddi_soft_state_fini(&ppb_state);
318 	return (e);
319 }
320 
321 int
322 _info(struct modinfo *modinfop)
323 {
324 	return (mod_info(&modlinkage, modinfop));
325 }
326 
327 /*ARGSUSED*/
328 static int
329 ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
330 {
331 	ppb_devstate_t *ppb_p;	/* per ppb state pointer */
332 	minor_t		minor = getminor((dev_t)arg);
333 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
334 
335 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
336 	    instance);
337 
338 	switch (infocmd) {
339 	default:
340 		return (DDI_FAILURE);
341 
342 	case DDI_INFO_DEVT2INSTANCE:
343 		*result = (void *)(uintptr_t)instance;
344 		return (DDI_SUCCESS);
345 
346 	case DDI_INFO_DEVT2DEVINFO:
347 		if (ppb_p == NULL)
348 			return (DDI_FAILURE);
349 		*result = (void *)ppb_p->dip;
350 		return (DDI_SUCCESS);
351 	}
352 }
353 
354 /*ARGSUSED*/
355 static int
356 ppb_probe(register dev_info_t *devi)
357 {
358 	return (DDI_PROBE_SUCCESS);
359 }
360 
361 /*ARGSUSED*/
362 static int
363 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
364 {
365 	int instance;
366 	ppb_devstate_t *ppb;
367 	ddi_acc_handle_t config_handle;
368 
369 	switch (cmd) {
370 	case DDI_ATTACH:
371 
372 		/*
373 		 * Make sure the "device_type" property exists.
374 		 */
375 		(void) ddi_prop_update_string(DDI_DEV_T_NONE, devi,
376 		    "device_type", "pci");
377 
378 		/*
379 		 * Allocate and get soft state structure.
380 		 */
381 		instance = ddi_get_instance(devi);
382 		if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS)
383 			return (DDI_FAILURE);
384 		ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance);
385 		ppb->dip = devi;
386 		mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL);
387 		ppb->ppb_soft_state = PPB_SOFT_STATE_CLOSED;
388 		if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) {
389 			mutex_destroy(&ppb->ppb_mutex);
390 			ddi_soft_state_free(ppb_state, instance);
391 			return (DDI_FAILURE);
392 		}
393 		ppb_pwr_setup(ppb, devi);
394 
395 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {
396 			mutex_enter(&ppb->ppb_pwr_p->pwr_mutex);
397 
398 			/*
399 			 * Before reading config registers, make sure power is
400 			 * on, and remains on.
401 			 */
402 			ppb->ppb_pwr_p->pwr_fp++;
403 
404 			pci_pwr_change(ppb->ppb_pwr_p,
405 			    ppb->ppb_pwr_p->current_lvl,
406 			    pci_pwr_new_lvl(ppb->ppb_pwr_p));
407 		}
408 
409 		ppb->ppb_cache_line_size =
410 		    pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ);
411 		ppb->ppb_latency_timer =
412 		    pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER);
413 
414 		/*
415 		 * Check whether the "ranges" property is present.
416 		 * Otherwise create the ranges property by reading
417 		 * the configuration registers
418 		 */
419 		if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS,
420 		    "ranges") == 0) {
421 			ppb_create_ranges_prop(devi, config_handle);
422 		}
423 
424 		pci_config_teardown(&config_handle);
425 
426 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {
427 			ppb->ppb_pwr_p->pwr_fp--;
428 
429 			pci_pwr_change(ppb->ppb_pwr_p,
430 			    ppb->ppb_pwr_p->current_lvl,
431 			    pci_pwr_new_lvl(ppb->ppb_pwr_p));
432 
433 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
434 		}
435 
436 		/*
437 		 * Initialize hotplug support on this bus. At minimum
438 		 * (for non hotplug bus) this would create ":devctl" minor
439 		 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
440 		 * to this bus. This all takes place if this nexus has hot-plug
441 		 * slots and successfully initializes Hot Plug Framework.
442 		 */
443 		ppb->hotplug_capable = B_FALSE;
444 		ppb_init_hotplug(ppb);
445 		if (ppb->hotplug_capable == B_FALSE) {
446 			/*
447 			 * create minor node for devctl interfaces
448 			 */
449 			if (ddi_create_minor_node(devi, "devctl", S_IFCHR,
450 			    PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR),
451 			    DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
452 				if (ppb->ppb_pwr_p != NULL) {
453 					ppb_pwr_teardown(ppb, devi);
454 				}
455 				mutex_destroy(&ppb->ppb_mutex);
456 				ddi_soft_state_free(ppb_state, instance);
457 				return (DDI_FAILURE);
458 			}
459 		}
460 
461 		DEBUG1(DBG_ATTACH, devi,
462 			"ppb_attach(): this nexus %s hotplug slots\n",
463 			ppb->hotplug_capable == B_TRUE ? "has":"has no");
464 
465 		ppb_fm_init(ppb);
466 		ddi_report_dev(devi);
467 
468 		return (DDI_SUCCESS);
469 
470 	case DDI_RESUME:
471 		/*
472 		 * Get the soft state structure for the bridge.
473 		 */
474 		ppb = (ppb_devstate_t *)
475 			ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
476 
477 		pci_pwr_resume(devi, ppb->ppb_pwr_p);
478 
479 		return (DDI_SUCCESS);
480 	}
481 	return (DDI_FAILURE);
482 }
483 
484 /*ARGSUSED*/
485 static int
486 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
487 {
488 	ppb_devstate_t *ppb;
489 
490 	switch (cmd) {
491 	case DDI_DETACH:
492 		/*
493 		 * And finally free the per-pci soft state after
494 		 * uninitializing hotplug support for this bus.
495 		 */
496 		ppb = (ppb_devstate_t *)
497 		    ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
498 
499 		ppb_fm_fini(ppb);
500 
501 		if (ppb->hotplug_capable == B_TRUE)
502 			if (pcihp_uninit(devi) == DDI_FAILURE)
503 				return (DDI_FAILURE);
504 		else
505 			ddi_remove_minor_node(devi, "devctl");
506 
507 		(void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
508 
509 		if (ppb->ppb_pwr_p != NULL) {
510 			ppb_pwr_teardown(ppb, devi);
511 		}
512 		mutex_destroy(&ppb->ppb_mutex);
513 		ddi_soft_state_free(ppb_state, ddi_get_instance(devi));
514 
515 		return (DDI_SUCCESS);
516 
517 	case DDI_SUSPEND:
518 		ppb = (ppb_devstate_t *)
519 			ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
520 
521 		pci_pwr_suspend(devi, ppb->ppb_pwr_p);
522 
523 		return (DDI_SUCCESS);
524 	}
525 	return (DDI_FAILURE);
526 }
527 
528 /*ARGSUSED*/
529 static int
530 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
531 	off_t offset, off_t len, caddr_t *vaddrp)
532 {
533 	register dev_info_t *pdip;
534 
535 	pdip = (dev_info_t *)DEVI(dip)->devi_parent;
536 	return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)
537 	    (pdip, rdip, mp, offset, len, vaddrp));
538 }
539 
540 /*ARGSUSED*/
541 static int
542 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip,
543 	ddi_ctl_enum_t ctlop, void *arg, void *result)
544 {
545 	pci_regspec_t *drv_regp;
546 	int	reglen;
547 	int	rn;
548 
549 	int	totreg;
550 
551 	switch (ctlop) {
552 	case DDI_CTLOPS_REPORTDEV:
553 		if (rdip == (dev_info_t *)0)
554 			return (DDI_FAILURE);
555 		cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n",
556 		    ddi_node_name(rdip), ddi_get_name_addr(rdip),
557 		    ddi_driver_name(rdip),
558 		    ddi_get_instance(rdip));
559 		return (DDI_SUCCESS);
560 
561 	case DDI_CTLOPS_INITCHILD:
562 		return (ppb_initchild((dev_info_t *)arg));
563 
564 	case DDI_CTLOPS_UNINITCHILD:
565 		ppb_removechild((dev_info_t *)arg);
566 		return (DDI_SUCCESS);
567 
568 	case DDI_CTLOPS_SIDDEV:
569 		return (DDI_SUCCESS);
570 
571 	case DDI_CTLOPS_REGSIZE:
572 	case DDI_CTLOPS_NREGS:
573 		if (rdip == (dev_info_t *)0)
574 			return (DDI_FAILURE);
575 		break;
576 	default:
577 		return (ddi_ctlops(dip, rdip, ctlop, arg, result));
578 	}
579 
580 	*(int *)result = 0;
581 	if (ddi_getlongprop(DDI_DEV_T_ANY, rdip,
582 		DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg",
583 		(caddr_t)&drv_regp, &reglen) != DDI_SUCCESS)
584 		return (DDI_FAILURE);
585 
586 	totreg = reglen / sizeof (pci_regspec_t);
587 	if (ctlop == DDI_CTLOPS_NREGS)
588 		*(int *)result = totreg;
589 	else if (ctlop == DDI_CTLOPS_REGSIZE) {
590 		rn = *(int *)arg;
591 		if (rn >= totreg) {
592 			kmem_free(drv_regp, reglen);
593 			return (DDI_FAILURE);
594 		}
595 		*(off_t *)result = drv_regp[rn].pci_size_low |
596 			((uint64_t)drv_regp[rn].pci_size_hi << 32);
597 	}
598 
599 	kmem_free(drv_regp, reglen);
600 	return (DDI_SUCCESS);
601 }
602 
603 
604 static dev_info_t *
605 get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip)
606 {
607 	dev_info_t *cdip = rdip;
608 
609 	for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip))
610 		;
611 
612 	return (cdip);
613 }
614 
615 
616 static int
617 ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
618     ddi_intr_handle_impl_t *hdlp, void *result)
619 {
620 	dev_info_t	*cdip = rdip;
621 	pci_regspec_t	*pci_rp;
622 	int		reglen, len;
623 	uint32_t	d, intr;
624 
625 	if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
626 		goto done;
627 
628 	/*
629 	 * If the interrupt-map property is defined at this
630 	 * node, it will have performed the interrupt
631 	 * translation as part of the property, so no
632 	 * rotation needs to be done.
633 	 */
634 	if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
635 	    "interrupt-map", &len) == DDI_PROP_SUCCESS)
636 		goto done;
637 
638 	cdip = get_my_childs_dip(dip, rdip);
639 
640 	/*
641 	 * Use the devices reg property to determine its
642 	 * PCI bus number and device number.
643 	 */
644 	if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS,
645 	    "reg", (caddr_t)&pci_rp, &reglen) != DDI_SUCCESS)
646 		return (DDI_FAILURE);
647 
648 	intr = hdlp->ih_vector;
649 
650 	/* Spin the interrupt */
651 	d = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
652 
653 	if ((intr >= PCI_INTA) && (intr <= PCI_INTD))
654 		hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1);
655 	else
656 		cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range",
657 		    ddi_driver_name(rdip), ddi_get_instance(rdip),
658 		    ddi_driver_name(dip), intr);
659 
660 	kmem_free(pci_rp, reglen);
661 
662 done:
663 	/* Pass up the request to our parent. */
664 	return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result));
665 }
666 
667 static int
668 ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op,
669     void *arg, void *result)
670 {
671 	ppb_devstate_t *ppb;
672 
673 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
674 	    ddi_get_instance(dip));
675 
676 	return (pci_pwr_ops(ppb->ppb_pwr_p, dip, impl_arg, op, arg, result));
677 }
678 
679 
680 /*
681  * name_child
682  *
683  * This function is called from init_child to name a node. It is
684  * also passed as a callback for node merging functions.
685  *
686  * return value: DDI_SUCCESS, DDI_FAILURE
687  */
688 static int
689 ppb_name_child(dev_info_t *child, char *name, int namelen)
690 {
691 	pci_regspec_t *pci_rp;
692 	uint_t slot, func;
693 	char **unit_addr;
694 	uint_t n;
695 
696 	/*
697 	 * Pseudo nodes indicate a prototype node with per-instance
698 	 * properties to be merged into the real h/w device node.
699 	 * The interpretation of the unit-address is DD[,F]
700 	 * where DD is the device id and F is the function.
701 	 */
702 	if (ndi_dev_is_persistent_node(child) == 0) {
703 		if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
704 		    DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
705 		    DDI_PROP_SUCCESS) {
706 			cmn_err(CE_WARN, "cannot name node from %s.conf",
707 			    ddi_driver_name(child));
708 			return (DDI_FAILURE);
709 		}
710 		if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
711 			cmn_err(CE_WARN, "unit-address property in %s.conf"
712 			    " not well-formed", ddi_driver_name(child));
713 			ddi_prop_free(unit_addr);
714 			return (DDI_FAILURE);
715 		}
716 		(void) snprintf(name, namelen, "%s", *unit_addr);
717 		ddi_prop_free(unit_addr);
718 		return (DDI_SUCCESS);
719 	}
720 
721 	/*
722 	 * Get the address portion of the node name based on
723 	 * the function and device number.
724 	 */
725 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
726 	    "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
727 		return (DDI_FAILURE);
728 	}
729 
730 	slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
731 	func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
732 
733 	if (func != 0)
734 		(void) snprintf(name, namelen, "%x,%x", slot, func);
735 	else
736 		(void) snprintf(name, namelen, "%x", slot);
737 
738 	ddi_prop_free(pci_rp);
739 	return (DDI_SUCCESS);
740 }
741 
742 static int
743 ppb_initchild(dev_info_t *child)
744 {
745 	char name[MAXNAMELEN];
746 	ddi_acc_handle_t config_handle;
747 	ushort_t command_preserve, command;
748 	uint_t n;
749 	ushort_t bcr;
750 	uchar_t header_type;
751 	uchar_t min_gnt, latency_timer;
752 	ppb_devstate_t *ppb;
753 	pci_parent_data_t *pd_p;
754 
755 	/*
756 	 * Name the child
757 	 */
758 	if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS)
759 		return (DDI_FAILURE);
760 
761 	ddi_set_name_addr(child, name);
762 	ddi_set_parent_data(child, NULL);
763 
764 	/*
765 	 * Pseudo nodes indicate a prototype node with per-instance
766 	 * properties to be merged into the real h/w device node.
767 	 * The interpretation of the unit-address is DD[,F]
768 	 * where DD is the device id and F is the function.
769 	 */
770 	if (ndi_dev_is_persistent_node(child) == 0) {
771 		extern int pci_allow_pseudo_children;
772 
773 		/*
774 		 * Try to merge the properties from this prototype
775 		 * node into real h/w nodes.
776 		 */
777 		if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) {
778 			/*
779 			 * Merged ok - return failure to remove the node.
780 			 */
781 			ppb_removechild(child);
782 			return (DDI_FAILURE);
783 		}
784 
785 		/* workaround for ddivs to run under PCI */
786 		if (pci_allow_pseudo_children)
787 			return (DDI_SUCCESS);
788 
789 		/*
790 		 * The child was not merged into a h/w node,
791 		 * but there's not much we can do with it other
792 		 * than return failure to cause the node to be removed.
793 		 */
794 		cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
795 		    ddi_driver_name(child), ddi_get_name_addr(child),
796 		    ddi_driver_name(child));
797 		ppb_removechild(child);
798 		return (DDI_NOT_WELL_FORMED);
799 	}
800 
801 	ddi_set_parent_data(child, NULL);
802 
803 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
804 	    ddi_get_instance(ddi_get_parent(child)));
805 
806 	/*
807 	 * If hardware is PM capable, set up the power info structure.
808 	 * This also ensures the the bus will not be off (0MHz) otherwise
809 	 * system panics during a bus access.
810 	 */
811 	if (PM_CAPABLE(ppb->ppb_pwr_p)) {
812 		/*
813 		 * Create a pwr_info struct for child.  Bus will be
814 		 * at full speed after creating info.
815 		 */
816 		pci_pwr_create_info(ppb->ppb_pwr_p, child);
817 #ifdef DEBUG
818 		ASSERT(ppb->ppb_pwr_p->current_lvl == PM_LEVEL_B0);
819 #endif
820 	}
821 
822 	/*
823 	 * If configuration registers were previously saved by
824 	 * child (before it entered D3), then let the child do the
825 	 * restore to set up the config regs as it'll first need to
826 	 * power the device out of D3.
827 	 */
828 	if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
829 	    "config-regs-saved-by-child") == 1) {
830 		DEBUG2(DBG_PWR, ddi_get_parent(child),
831 			"INITCHILD: config regs to be restored by child"
832 			" for %s@%s\n", ddi_node_name(child),
833 				ddi_get_name_addr(child));
834 
835 		return (DDI_SUCCESS);
836 	}
837 
838 	DEBUG2(DBG_PWR, ddi_get_parent(child),
839 	    "INITCHILD: config regs setup for %s@%s\n",
840 	    ddi_node_name(child), ddi_get_name_addr(child));
841 
842 	if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) {
843 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {
844 			pci_pwr_rm_info(ppb->ppb_pwr_p, child);
845 		}
846 
847 		return (DDI_FAILURE);
848 	}
849 
850 	/*
851 	 * Determine the configuration header type.
852 	 */
853 	header_type = pci_config_get8(config_handle, PCI_CONF_HEADER);
854 
855 	/*
856 	 * Support for the "command-preserve" property.
857 	 */
858 	command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child,
859 		DDI_PROP_DONTPASS, "command-preserve", 0);
860 	command = pci_config_get16(config_handle, PCI_CONF_COMM);
861 	command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB);
862 	command |= (ppb_command_default & ~command_preserve);
863 	pci_config_put16(config_handle, PCI_CONF_COMM, command);
864 
865 	/*
866 	 * If the device has a bus control register then program it
867 	 * based on the settings in the command register.
868 	 */
869 	if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
870 		bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL);
871 		if (ppb_command_default & PCI_COMM_PARITY_DETECT)
872 			bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE;
873 		if (ppb_command_default & PCI_COMM_SERR_ENABLE)
874 			bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE;
875 		bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE;
876 		pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);
877 	}
878 
879 	/*
880 	 * Initialize cache-line-size configuration register if needed.
881 	 */
882 	if (ppb_set_cache_line_size_register &&
883 	    ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
884 		"cache-line-size", 0) == 0) {
885 		pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ,
886 			ppb->ppb_cache_line_size);
887 		n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ);
888 		if (n != 0) {
889 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, child,
890 					"cache-line-size", n);
891 		}
892 	}
893 
894 	/*
895 	 * Initialize latency timer configuration registers if needed.
896 	 */
897 	if (ppb_set_latency_timer_register &&
898 	    ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
899 		"latency-timer", 0) == 0) {
900 
901 		if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
902 			latency_timer = ppb->ppb_latency_timer;
903 			pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER,
904 				ppb->ppb_latency_timer);
905 		} else {
906 			min_gnt = pci_config_get8(config_handle,
907 				PCI_CONF_MIN_G);
908 			latency_timer = min_gnt * 8;
909 		}
910 		pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER,
911 			latency_timer);
912 		n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER);
913 		if (n != 0) {
914 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, child,
915 					"latency-timer", n);
916 		}
917 	}
918 
919 	/*
920 	 * Check to see if the XMITS/PCI-X workaround applies.
921 	 */
922 	n = ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_NOTPROM,
923 	    "pcix-update-cmd-reg", -1);
924 
925 	if (n != -1) {
926 		extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value);
927 		DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ "
928 		    "Workaround: value = %x\n", n);
929 		pcix_set_cmd_reg(child, n);
930 	}
931 
932 	/* Allocate memory for pci parent data */
933 	pd_p = kmem_zalloc(sizeof (pci_parent_data_t), KM_SLEEP);
934 
935 	/*
936 	 * Retrieve and save BDF and PCIE2PCI bridge's secondary bus
937 	 * information in the parent private data structure.
938 	 */
939 	if (ppb_get_bdf_from_dip(child, &pd_p->pci_bdf) != DDI_SUCCESS) {
940 		kmem_free(pd_p, sizeof (pci_parent_data_t));
941 		pci_config_teardown(&config_handle);
942 		return (DDI_FAILURE);
943 	}
944 
945 	pd_p->pci_sec_bus = ddi_prop_get_int(DDI_DEV_T_ANY, child, 0,
946 	    "pcie2pci-sec-bus", 0);
947 
948 	ddi_set_parent_data(child, (void *)pd_p);
949 	pci_config_teardown(&config_handle);
950 
951 	return (DDI_SUCCESS);
952 }
953 
954 static void
955 ppb_removechild(dev_info_t *dip)
956 {
957 	ppb_devstate_t *ppb;
958 	pci_parent_data_t *pd_p;
959 
960 	if (pd_p = ddi_get_parent_data(dip)) {
961 		ddi_set_parent_data(dip, NULL);
962 		kmem_free(pd_p, sizeof (pci_parent_data_t));
963 	}
964 
965 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
966 	    ddi_get_instance(ddi_get_parent(dip)));
967 
968 	if (PM_CAPABLE(ppb->ppb_pwr_p)) {
969 
970 		DEBUG2(DBG_PWR, ddi_get_parent(dip),
971 		    "UNINITCHILD: removing pwr_info for %s@%s\n",
972 		    ddi_node_name(dip), ddi_get_name_addr(dip));
973 		pci_pwr_rm_info(ppb->ppb_pwr_p, dip);
974 	}
975 
976 	ddi_set_name_addr(dip, NULL);
977 
978 	/*
979 	 * Strip the node to properly convert it back to prototype form
980 	 */
981 	ddi_remove_minor_node(dip, NULL);
982 
983 	impl_rem_dev_props(dip);
984 }
985 
986 /*
987  * If bridge is PM capable, set up PM state for nexus.
988  */
989 static void
990 ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip)
991 {
992 	char *comp_array[5];
993 	int i;
994 	ddi_acc_handle_t conf_hdl;
995 	uint8_t pmcsr_bse;
996 	uint16_t pmcap;
997 
998 	/*
999 	 * Determine if bridge is PM capable.  If not, leave ppb_pwr_p NULL
1000 	 * and return.
1001 	 */
1002 	if (pci_config_setup(pdip, &ppb->ppb_conf_hdl) != DDI_SUCCESS) {
1003 
1004 		return;
1005 	}
1006 
1007 	conf_hdl = ppb->ppb_conf_hdl;
1008 
1009 	/*
1010 	 * Locate and store the power management cap_ptr for future references.
1011 	 */
1012 	if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &ppb->ppb_pm_cap_ptr))
1013 		== DDI_FAILURE) {
1014 		DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI"
1015 		    " PM data structure not found in config header\n");
1016 		pci_config_teardown(&conf_hdl);
1017 
1018 		return;
1019 	}
1020 
1021 	/*
1022 	 * Allocate PM state structure for ppb.
1023 	 */
1024 	ppb->ppb_pwr_p = (pci_pwr_t *)
1025 	    kmem_zalloc(sizeof (pci_pwr_t), KM_SLEEP);
1026 	ppb->ppb_pwr_p->pwr_fp = 0;
1027 
1028 	pmcsr_bse = PCI_CAP_GET8(conf_hdl, NULL, ppb->ppb_pm_cap_ptr,
1029 		PCI_PMCSR_BSE);
1030 
1031 	pmcap = PCI_CAP_GET16(conf_hdl, NULL, ppb->ppb_pm_cap_ptr,
1032 		PCI_PMCAP);
1033 
1034 	if (pmcap == PCI_CAP_EINVAL16 || pmcsr_bse == PCI_CAP_EINVAL8) {
1035 		pci_config_teardown(&conf_hdl);
1036 		return;
1037 	}
1038 
1039 	if (pmcap & PCI_PMCAP_D1) {
1040 		DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n");
1041 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B1_CAPABLE;
1042 	} else {
1043 		DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n");
1044 	}
1045 	if (pmcap & PCI_PMCAP_D2) {
1046 		DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n");
1047 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE;
1048 	} else {
1049 		DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n");
1050 	}
1051 
1052 	if (pmcsr_bse & PCI_PMCSR_BSE_BPCC_EN) {
1053 		DEBUG0(DBG_PWR, pdip,
1054 		"setup: bridge power/clock control enable\n");
1055 	} else {
1056 		DEBUG0(DBG_PWR, pdip,
1057 		"setup: bridge power/clock control disabled\n");
1058 
1059 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1060 		ppb->ppb_pwr_p = NULL;
1061 		pci_config_teardown(&conf_hdl);
1062 
1063 		return;
1064 	}
1065 
1066 	/*
1067 	 * PCI states D0 and D3 always are supported for normal PCI
1068 	 * devices.  D1 and D2 are optional which are checked for above.
1069 	 * Bridge function states D0-D3 correspond to secondary bus states
1070 	 * B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set.  In this case, setting
1071 	 * the bridge function to D3 will set the bridge bus to state B2 instead
1072 	 * of B3.  D2 will not correspond to B2 (and in fact, probably
1073 	 * won't be D2 capable).  Implicitly, this means that if
1074 	 * PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable.
1075 	 */
1076 	if (pmcsr_bse & PCI_PMCSR_BSE_B2_B3) {
1077 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE;
1078 		DEBUG0(DBG_PWR, pdip, "B2 supported via D3\n");
1079 	} else {
1080 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B3_CAPABLE;
1081 		DEBUG0(DBG_PWR, pdip, "B3 supported via D3\n");
1082 	}
1083 
1084 	ppb->ppb_pwr_p->pwr_dip = pdip;
1085 	mutex_init(&ppb->ppb_pwr_p->pwr_mutex, NULL, MUTEX_DRIVER, NULL);
1086 
1087 	i = 0;
1088 	comp_array[i++] = "NAME=PCI bridge PM";
1089 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) {
1090 		comp_array[i++] = "0=Clock/Power Off (B3)";
1091 	}
1092 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) {
1093 		comp_array[i++] = "1=Clock Off (B2)";
1094 	}
1095 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) {
1096 		comp_array[i++] = "2=Bus Inactive (B1)";
1097 	}
1098 	comp_array[i++] = "3=Full Power (B0)";
1099 
1100 	/*
1101 	 * Create pm-components property. It does not already exist.
1102 	 */
1103 	if (ddi_prop_update_string_array(DDI_DEV_T_NONE, pdip,
1104 	    "pm-components", comp_array, i) != DDI_PROP_SUCCESS) {
1105 		cmn_err(CE_WARN,
1106 		    "%s%d pm-components prop update failed",
1107 		    ddi_driver_name(pdip), ddi_get_instance(pdip));
1108 		pci_config_teardown(&conf_hdl);
1109 		mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);
1110 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1111 		ppb->ppb_pwr_p = NULL;
1112 
1113 		return;
1114 	}
1115 
1116 	if (ddi_prop_create(DDI_DEV_T_NONE, pdip, DDI_PROP_CANSLEEP,
1117 	    "pm-want-child-notification?", NULL, NULL) != DDI_PROP_SUCCESS) {
1118 		cmn_err(CE_WARN,
1119 			"%s%d fail to create pm-want-child-notification? prop",
1120 			ddi_driver_name(pdip), ddi_get_instance(pdip));
1121 
1122 		(void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, "pm-components");
1123 		pci_config_teardown(&conf_hdl);
1124 		mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);
1125 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1126 		ppb->ppb_pwr_p = NULL;
1127 
1128 		return;
1129 	}
1130 
1131 	ppb->ppb_pwr_p->current_lvl =
1132 		pci_pwr_current_lvl(ppb->ppb_pwr_p);
1133 }
1134 
1135 /*
1136  * Remove PM state for nexus.
1137  */
1138 static void
1139 ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip)
1140 {
1141 	int low_lvl;
1142 
1143 	/*
1144 	 * Determine the lowest power level supported.
1145 	 */
1146 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) {
1147 		low_lvl = PM_LEVEL_B3;
1148 	} else {
1149 		low_lvl = PM_LEVEL_B2;
1150 	}
1151 
1152 	if (pm_lower_power(dip, PCI_PM_COMP_0, low_lvl) != DDI_SUCCESS) {
1153 		cmn_err(CE_WARN, "%s%d failed to lower power",
1154 		    ddi_driver_name(dip), ddi_get_instance(dip));
1155 	}
1156 
1157 	pci_config_teardown(&ppb->ppb_conf_hdl);
1158 	mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);
1159 	kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));
1160 
1161 	if (ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components") !=
1162 		DDI_PROP_SUCCESS) {
1163 		cmn_err(CE_WARN, "%s%d unable to remove prop pm-components",
1164 		    ddi_driver_name(dip), ddi_get_instance(dip));
1165 	}
1166 
1167 	if (ddi_prop_remove(DDI_DEV_T_NONE, dip,
1168 	    "pm-want-child-notification?") != DDI_PROP_SUCCESS) {
1169 		cmn_err(CE_WARN,
1170 		    "%s%d unable to remove prop pm-want_child_notification?",
1171 		    ddi_driver_name(dip), ddi_get_instance(dip));
1172 	}
1173 }
1174 
1175 /*
1176  * Examine the pmcsr register and return the software defined
1177  * state (the difference being whether D3 means B2 or B3).
1178  */
1179 int
1180 pci_pwr_current_lvl(pci_pwr_t *pwr_p)
1181 {
1182 	ppb_devstate_t *ppb;
1183 	uint16_t pmcsr;
1184 
1185 	/*
1186 	 * Find out current power level
1187 	 */
1188 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1189 	    ddi_get_instance(pwr_p->pwr_dip));
1190 
1191 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
1192 		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)
1193 		return (DDI_FAILURE);
1194 
1195 	switch (pmcsr & PCI_PMCSR_STATE_MASK) {
1196 	case PCI_PMCSR_D0:
1197 
1198 		return (PM_LEVEL_B0);
1199 	case PCI_PMCSR_D1:
1200 
1201 		return (PM_LEVEL_B1);
1202 	case PCI_PMCSR_D2:
1203 
1204 		return (PM_LEVEL_B2);
1205 	case PCI_PMCSR_D3HOT:
1206 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {
1207 
1208 			return (PM_LEVEL_B2);
1209 		} else {
1210 
1211 			return (PM_LEVEL_B3);
1212 		}
1213 	}
1214 	/*NOTREACHED*/
1215 	return (PM_LEVEL_B3);
1216 }
1217 
1218 /*
1219  * Power entry point.  Called by the PM framework to change the
1220  * current power state of the bus.  This function must first verify that
1221  * the requested power change is still valid.
1222  */
1223 /*ARGSUSED*/
1224 static int
1225 ppb_pwr(dev_info_t *dip, int component, int lvl)
1226 {
1227 	ppb_devstate_t *ppb;
1228 	uint16_t pmcsr;
1229 	char *str;
1230 	int lowest_lvl;
1231 	int old_lvl;
1232 	int new_lvl;
1233 
1234 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1235 	    ddi_get_instance(dip));
1236 	if (ppb == NULL) {
1237 		cmn_err(CE_WARN, "%s%d ppb_pwr: can't get soft state",
1238 		    ddi_driver_name(dip), ddi_get_instance(dip));
1239 
1240 		return (DDI_FAILURE);
1241 	}
1242 
1243 	DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl);
1244 
1245 	mutex_enter(&ppb->ppb_pwr_p->pwr_mutex);
1246 
1247 	/*
1248 	 * Find out if the power setting is possible.  If it is not,
1249 	 * set component busy and return failure.  If it is possible,
1250 	 * and it is the lowest pwr setting possible, set component
1251 	 * busy so that the framework does not try to lower any further.
1252 	 */
1253 	lowest_lvl = pci_pwr_new_lvl(ppb->ppb_pwr_p);
1254 	if (lowest_lvl > lvl) {
1255 		pci_pwr_component_busy(ppb->ppb_pwr_p);
1256 		DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request "
1257 			"lowest allowed is %d requested is %d\n",
1258 				lowest_lvl, lvl);
1259 		mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1260 
1261 		return (DDI_FAILURE);
1262 	} else if (lowest_lvl == lvl) {
1263 		pci_pwr_component_busy(ppb->ppb_pwr_p);
1264 	} else {
1265 		pci_pwr_component_idle(ppb->ppb_pwr_p);
1266 	}
1267 
1268 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL,
1269 		ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)
1270 		return (DDI_FAILURE);
1271 
1272 	/*
1273 	 * Save the current power level.  This is the actual function level,
1274 	 * not the translated bridge level stored in pwr_p->current_lvl
1275 	 */
1276 	old_lvl = pmcsr & PCI_PMCSR_STATE_MASK;
1277 
1278 	pmcsr &= ~PCI_PMCSR_STATE_MASK;
1279 	switch (lvl) {
1280 	case PM_LEVEL_B0:
1281 		str = "PM_LEVEL_B0 (full speed)";
1282 		pmcsr |= PCI_PMCSR_D0;
1283 		break;
1284 	case PM_LEVEL_B1:
1285 		str = "PM_LEVEL_B1 (light sleep. No bus traffic allowed)";
1286 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) == 0) {
1287 			cmn_err(CE_WARN, "%s%d PCI PM state B1 not supported",
1288 			    ddi_driver_name(dip), ddi_get_instance(dip));
1289 
1290 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1291 			return (DDI_FAILURE);
1292 		}
1293 		pmcsr |= PCI_PMCSR_D1;
1294 		break;
1295 	case PM_LEVEL_B2:
1296 		str = "PM_LEVEL_B2 (clock off)";
1297 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) == 0) {
1298 			cmn_err(CE_WARN, "%s%d PM state B2 not supported...",
1299 			    ddi_driver_name(dip),
1300 			    ddi_get_instance(dip));
1301 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1302 
1303 			return (DDI_FAILURE);
1304 		}
1305 
1306 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {
1307 			/*
1308 			 * If B3 isn't supported, use D3 for B2 to avoid the
1309 			 * possible case that D2 for B2 isn't supported.
1310 			 * Saves and extra check and state flag..
1311 			 */
1312 			pmcsr |= PCI_PMCSR_D3HOT;
1313 		} else {
1314 			pmcsr |= PCI_PMCSR_D2;
1315 		}
1316 		break;
1317 	case PM_LEVEL_B3:
1318 		str = "PM_LEVEL_B30 (clock and power off)";
1319 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {
1320 			cmn_err(CE_WARN, "%s%d PM state B3 not supported...",
1321 			    ddi_driver_name(dip),
1322 			    ddi_get_instance(dip));
1323 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1324 
1325 			return (DDI_FAILURE);
1326 		}
1327 		pmcsr |= PCI_PMCSR_D3HOT;
1328 
1329 		break;
1330 
1331 	default:
1332 		cmn_err(CE_WARN, "%s%d Unknown PM state %d",
1333 		    ddi_driver_name(dip), ddi_get_instance(dip), lvl);
1334 		mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1335 
1336 		return (DDI_FAILURE);
1337 	}
1338 
1339 	new_lvl = pmcsr & PCI_PMCSR_STATE_MASK;
1340 
1341 	/*
1342 	 * Save config regs if going into HW state D3 (B2 or B3)
1343 	 */
1344 	if ((old_lvl != PCI_PMCSR_D3HOT) && (new_lvl == PCI_PMCSR_D3HOT)) {
1345 		DEBUG0(DBG_PWR, dip, "ppb_pwr(): SAVING CONFIG REGS\n");
1346 		if (pci_save_config_regs(dip) != DDI_SUCCESS) {
1347 			cmn_err(CE_WARN, "%s%d Save config regs failed",
1348 				ddi_driver_name(dip), ddi_get_instance(dip));
1349 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1350 
1351 			return (DDI_FAILURE);
1352 		}
1353 	}
1354 
1355 	PCI_CAP_PUT16(ppb->ppb_conf_hdl, NULL, ppb->ppb_pm_cap_ptr, PCI_PMCSR,
1356 		pmcsr);
1357 
1358 	/*
1359 	 * No bus transactions should occur without waiting for
1360 	 * settle time specified in PCI PM spec rev 2.1 sec 5.6.1
1361 	 * To make things simple, just use the max time specified for
1362 	 * all state transitions.
1363 	 */
1364 	delay(drv_usectohz(PCI_CLK_SETTLE_TIME));
1365 
1366 	/*
1367 	 * Restore configuration registers if coming out of HW state D3
1368 	 */
1369 	if ((old_lvl == PCI_PMCSR_D3HOT) && (new_lvl != PCI_PMCSR_D3HOT)) {
1370 		DEBUG0(DBG_PWR, dip, "ppb_pwr(): RESTORING CONFIG REGS\n");
1371 		if (pci_restore_config_regs(dip) != DDI_SUCCESS) {
1372 			panic("%s%d restore config regs failed",
1373 			    ddi_driver_name(dip), ddi_get_instance(dip));
1374 		}
1375 		/*NOTREACHED*/
1376 	}
1377 
1378 	ppb->ppb_pwr_p->current_lvl = lvl;
1379 
1380 	mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
1381 
1382 	DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str);
1383 
1384 	return (DDI_SUCCESS);
1385 }
1386 
1387 /*
1388  * Initialize hotplug framework if we are hotpluggable.
1389  * Sets flag in the soft state if Hot Plug is supported and initialized
1390  * properly.
1391  */
1392 /*ARGSUSED*/
1393 static void
1394 ppb_init_hotplug(ppb_devstate_t *ppb)
1395 {
1396 	if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS,
1397 	    "hotplug-capable")) {
1398 		(void) modload("misc", "pcihp");
1399 
1400 		if (pcihp_init(ppb->dip) != DDI_SUCCESS) {
1401 			cmn_err(CE_WARN,
1402 			    "%s #%d: Failed setting hotplug framework",
1403 			    ddi_driver_name(ppb->dip),
1404 			    ddi_get_instance(ppb->dip));
1405 		} else
1406 			ppb->hotplug_capable = B_TRUE;
1407 	}
1408 
1409 }
1410 
1411 static void
1412 ppb_create_ranges_prop(dev_info_t *dip,
1413 	ddi_acc_handle_t config_handle)
1414 {
1415 	uint32_t base, limit;
1416 	ppb_ranges_t	ranges[PPB_RANGE_LEN];
1417 	uint8_t io_base_lo, io_limit_lo;
1418 	uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit;
1419 	int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int);
1420 
1421 	io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW);
1422 	io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW);
1423 	io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI);
1424 	io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI);
1425 	mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE);
1426 	mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT);
1427 
1428 	/*
1429 	 * Create ranges for IO space
1430 	 */
1431 	ranges[i].size_low = ranges[i].size_high = 0;
1432 	ranges[i].parent_mid = ranges[i].child_mid =
1433 		ranges[i].parent_high = 0;
1434 	ranges[i].child_high = ranges[i].parent_high |=
1435 		(PCI_REG_REL_M | PCI_ADDR_IO);
1436 	base = PPB_16bit_IOADDR(io_base_lo);
1437 	limit = PPB_16bit_IOADDR(io_limit_lo);
1438 
1439 	if ((io_base_lo & 0xf) == PPB_32BIT_IO) {
1440 		base = PPB_LADDR(base, io_base_hi);
1441 	}
1442 	if ((io_limit_lo & 0xf) == PPB_32BIT_IO) {
1443 		limit = PPB_LADDR(limit, io_limit_hi);
1444 	}
1445 
1446 	if ((io_base_lo & PPB_32BIT_IO) && (io_limit_hi > 0)) {
1447 		base = PPB_LADDR(base, io_base_hi);
1448 		limit = PPB_LADDR(limit, io_limit_hi);
1449 	}
1450 
1451 	/*
1452 	 * Create ranges for 32bit memory space
1453 	 */
1454 	base = PPB_32bit_MEMADDR(mem_base);
1455 	limit = PPB_32bit_MEMADDR(mem_limit);
1456 	ranges[i].size_low = ranges[i].size_high = 0;
1457 	ranges[i].parent_mid = ranges[i].child_mid =
1458 		ranges[i].parent_high = 0;
1459 	ranges[i].child_high = ranges[i].parent_high |=
1460 		(PCI_REG_REL_M | PCI_ADDR_MEM32);
1461 	ranges[i].child_low = ranges[i].parent_low = base;
1462 	if (limit >= base) {
1463 		ranges[i].size_low = limit - base + PPB_MEMGRAIN;
1464 		i++;
1465 	}
1466 
1467 	if (i) {
1468 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges",
1469 		    (int *)ranges, i * rangelen);
1470 	}
1471 }
1472 
1473 /* ARGSUSED */
1474 static int
1475 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
1476 {
1477 	ppb_devstate_t *ppb_p;
1478 	minor_t		minor = getminor(*devp);
1479 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1480 
1481 	/*
1482 	 * Make sure the open is for the right file type.
1483 	 */
1484 	if (otyp != OTYP_CHR)
1485 		return (EINVAL);
1486 
1487 	/*
1488 	 * Get the soft state structure for the device.
1489 	 */
1490 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1491 	    instance);
1492 
1493 	if (ppb_p == NULL)
1494 		return (ENXIO);
1495 
1496 	if (ppb_p->hotplug_capable == B_TRUE)
1497 		return ((pcihp_get_cb_ops())->cb_open(devp, flags,
1498 		    otyp, credp));
1499 
1500 	/*
1501 	 * Handle the open by tracking the device state.
1502 	 */
1503 	mutex_enter(&ppb_p->ppb_mutex);
1504 	if (flags & FEXCL) {
1505 		if (ppb_p->ppb_soft_state != PPB_SOFT_STATE_CLOSED) {
1506 			mutex_exit(&ppb_p->ppb_mutex);
1507 			return (EBUSY);
1508 		}
1509 		ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN_EXCL;
1510 	} else {
1511 		if (ppb_p->ppb_soft_state == PPB_SOFT_STATE_OPEN_EXCL) {
1512 			mutex_exit(&ppb_p->ppb_mutex);
1513 			return (EBUSY);
1514 		}
1515 		ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN;
1516 	}
1517 	mutex_exit(&ppb_p->ppb_mutex);
1518 	return (0);
1519 }
1520 
1521 
1522 /* ARGSUSED */
1523 static int
1524 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp)
1525 {
1526 	ppb_devstate_t *ppb_p;
1527 	minor_t		minor = getminor(dev);
1528 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1529 
1530 	if (otyp != OTYP_CHR)
1531 		return (EINVAL);
1532 
1533 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1534 	    instance);
1535 
1536 	if (ppb_p == NULL)
1537 		return (ENXIO);
1538 
1539 	if (ppb_p->hotplug_capable == B_TRUE)
1540 		return ((pcihp_get_cb_ops())->cb_close(dev, flags,
1541 		    otyp, credp));
1542 
1543 	mutex_enter(&ppb_p->ppb_mutex);
1544 	ppb_p->ppb_soft_state = PPB_SOFT_STATE_CLOSED;
1545 	mutex_exit(&ppb_p->ppb_mutex);
1546 	return (0);
1547 }
1548 
1549 
1550 /*
1551  * ppb_ioctl: devctl hotplug controls
1552  */
1553 /* ARGSUSED */
1554 static int
1555 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1556 	int *rvalp)
1557 {
1558 	ppb_devstate_t *ppb_p;
1559 	dev_info_t *self;
1560 	struct devctl_iocdata *dcp;
1561 	uint_t bus_state;
1562 	int rv = 0;
1563 	minor_t		minor = getminor(dev);
1564 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1565 
1566 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1567 	    instance);
1568 
1569 	if (ppb_p == NULL)
1570 		return (ENXIO);
1571 
1572 	if (ppb_p->hotplug_capable == B_TRUE)
1573 		return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd,
1574 		    arg, mode, credp, rvalp));
1575 
1576 	self = ppb_p->dip;
1577 
1578 	/*
1579 	 * We can use the generic implementation for these ioctls
1580 	 */
1581 	switch (cmd) {
1582 	case DEVCTL_DEVICE_GETSTATE:
1583 	case DEVCTL_DEVICE_ONLINE:
1584 	case DEVCTL_DEVICE_OFFLINE:
1585 	case DEVCTL_BUS_GETSTATE:
1586 		return (ndi_devctl_ioctl(self, cmd, arg, mode, 0));
1587 	}
1588 
1589 	/*
1590 	 * read devctl ioctl data
1591 	 */
1592 	if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS)
1593 		return (EFAULT);
1594 
1595 	switch (cmd) {
1596 
1597 	case DEVCTL_DEVICE_RESET:
1598 		rv = ENOTSUP;
1599 		break;
1600 
1601 	case DEVCTL_BUS_QUIESCE:
1602 		if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS)
1603 			if (bus_state == BUS_QUIESCED)
1604 				break;
1605 		(void) ndi_set_bus_state(self, BUS_QUIESCED);
1606 		break;
1607 
1608 	case DEVCTL_BUS_UNQUIESCE:
1609 		if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS)
1610 			if (bus_state == BUS_ACTIVE)
1611 				break;
1612 		(void) ndi_set_bus_state(self, BUS_ACTIVE);
1613 		break;
1614 
1615 	case DEVCTL_BUS_RESET:
1616 		rv = ENOTSUP;
1617 		break;
1618 
1619 	case DEVCTL_BUS_RESETALL:
1620 		rv = ENOTSUP;
1621 		break;
1622 
1623 	default:
1624 		rv = ENOTTY;
1625 	}
1626 
1627 	ndi_dc_freehdl(dcp);
1628 	return (rv);
1629 }
1630 
1631 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
1632     int flags, char *name, caddr_t valuep, int *lengthp)
1633 {
1634 	ppb_devstate_t *ppb_p;
1635 	minor_t		minor = getminor(dev);
1636 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1637 
1638 	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1639 	    instance);
1640 
1641 	if (ppb_p == NULL)
1642 		return (ENXIO);
1643 
1644 	if (ppb_p->hotplug_capable == B_TRUE)
1645 		return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op,
1646 		    flags, name, valuep, lengthp));
1647 
1648 	return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp));
1649 }
1650 
1651 static int
1652 ppb_get_bdf_from_dip(dev_info_t *dip, uint32_t *bdf)
1653 {
1654 	pci_regspec_t	*regspec;
1655 	int		reglen;
1656 
1657 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1658 	    "reg", (int **)&regspec, (uint_t *)&reglen) != DDI_SUCCESS)
1659 		return (DDI_FAILURE);
1660 
1661 	if (reglen < (sizeof (pci_regspec_t) / sizeof (int))) {
1662 		ddi_prop_free(regspec);
1663 		return (DDI_FAILURE);
1664 	}
1665 
1666 	/* Get phys_hi from first element.  All have same bdf. */
1667 	*bdf = (regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M)) >> 8;
1668 
1669 	ddi_prop_free(regspec);
1670 	return (DDI_SUCCESS);
1671 }
1672 
1673 /*
1674  * Initialize our FMA resources
1675  */
1676 static void
1677 ppb_fm_init(ppb_devstate_t *ppb_p)
1678 {
1679 	ppb_p->fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE |
1680 		DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE;
1681 
1682 	/*
1683 	 * Request our capability level and get our parents capability
1684 	 * and ibc.
1685 	 */
1686 	ddi_fm_init(ppb_p->dip, &ppb_p->fm_cap, &ppb_p->fm_ibc);
1687 	ASSERT((ppb_p->fm_cap & DDI_FM_EREPORT_CAPABLE) &&
1688 	    (ppb_p->fm_cap & DDI_FM_ERRCB_CAPABLE));
1689 
1690 	pci_ereport_setup(ppb_p->dip);
1691 
1692 	/*
1693 	 * Register error callback with our parent.
1694 	 */
1695 	ddi_fm_handler_register(ppb_p->dip, ppb_err_callback, NULL);
1696 }
1697 
1698 /*
1699  * Breakdown our FMA resources
1700  */
1701 static void
1702 ppb_fm_fini(ppb_devstate_t *ppb_p)
1703 {
1704 	/*
1705 	 * Clean up allocated fm structures
1706 	 */
1707 	ddi_fm_handler_unregister(ppb_p->dip);
1708 	pci_ereport_teardown(ppb_p->dip);
1709 	ddi_fm_fini(ppb_p->dip);
1710 }
1711 
1712 /*
1713  * Initialize FMA resources for children devices. Called when
1714  * child calls ddi_fm_init().
1715  */
1716 /*ARGSUSED*/
1717 static int
1718 ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
1719 		ddi_iblock_cookie_t *ibc)
1720 {
1721 	ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
1722 			ddi_get_instance(dip));
1723 	*ibc = ppb_p->fm_ibc;
1724 	return (ppb_p->fm_cap);
1725 }
1726 
1727 /*
1728  * FMA registered error callback
1729  */
1730 static int
1731 ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data)
1732 {
1733 	ASSERT(impl_data == NULL);
1734 	pci_ereport_post(dip, derr, NULL);
1735 	return (derr->fme_status);
1736 }
1737 
1738 static void
1739 ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle)
1740 {
1741 	i_ndi_busop_access_enter(dip, handle);
1742 }
1743 
1744 /* ARGSUSED */
1745 static void
1746 ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle)
1747 {
1748 	i_ndi_busop_access_exit(dip, handle);
1749 }
1750