17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5d48713b8Sesolom * Common Development and Distribution License (the "License"). 6d48713b8Sesolom * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22d48713b8Sesolom * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate /* 297c478bd9Sstevel@tonic-gate * PCI nexus interrupt handling: 307c478bd9Sstevel@tonic-gate * PCI device interrupt handler wrapper 317c478bd9Sstevel@tonic-gate * pil lookup routine 327c478bd9Sstevel@tonic-gate * PCI device interrupt related initchild code 337c478bd9Sstevel@tonic-gate */ 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate #include <sys/types.h> 367c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 377c478bd9Sstevel@tonic-gate #include <sys/async.h> 387c478bd9Sstevel@tonic-gate #include <sys/spl.h> 397c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 407c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 417c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 427c478bd9Sstevel@tonic-gate #include <sys/pci/pci_obj.h> 437c478bd9Sstevel@tonic-gate #include <sys/sdt.h> 446d44af1bSesolom #include <sys/clock.h> 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 477c478bd9Sstevel@tonic-gate #include <sys/starfire.h> 487c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 497c478bd9Sstevel@tonic-gate 507c478bd9Sstevel@tonic-gate /* 517c478bd9Sstevel@tonic-gate * interrupt jabber: 527c478bd9Sstevel@tonic-gate * 537c478bd9Sstevel@tonic-gate * When an interrupt line is jabbering, every time the state machine for the 547c478bd9Sstevel@tonic-gate * associated ino is idled, a new mondo will be sent and the ino will go into 557c478bd9Sstevel@tonic-gate * the pending state again. The mondo will cause a new call to 567c478bd9Sstevel@tonic-gate * pci_intr_wrapper() which normally idles the ino's state machine which would 577c478bd9Sstevel@tonic-gate * precipitate another trip round the loop. 587c478bd9Sstevel@tonic-gate * The loop can be broken by preventing the ino's state machine from being 597c478bd9Sstevel@tonic-gate * idled when an interrupt line is jabbering. See the comment at the 607c478bd9Sstevel@tonic-gate * beginning of pci_intr_wrapper() explaining how the 'interrupt jabber 617c478bd9Sstevel@tonic-gate * protection' code does this. 627c478bd9Sstevel@tonic-gate */ 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate #ifdef NOT_DEFINED 677c478bd9Sstevel@tonic-gate /* 687c478bd9Sstevel@tonic-gate * This array is used to determine the sparc PIL at the which the 697c478bd9Sstevel@tonic-gate * handler for a given INO will execute. This table is for onboard 707c478bd9Sstevel@tonic-gate * devices only. A different scheme will be used for plug-in cards. 717c478bd9Sstevel@tonic-gate */ 727c478bd9Sstevel@tonic-gate 737c478bd9Sstevel@tonic-gate uint_t ino_to_pil[] = { 747c478bd9Sstevel@tonic-gate 757c478bd9Sstevel@tonic-gate /* pil */ /* ino */ 767c478bd9Sstevel@tonic-gate 777c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x00 - 0x03: bus A slot 0 int#A, B, C, D */ 787c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x04 - 0x07: bus A slot 1 int#A, B, C, D */ 797c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x08 - 0x0B: unused */ 807c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x0C - 0x0F: unused */ 817c478bd9Sstevel@tonic-gate 827c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x10 - 0x13: bus B slot 0 int#A, B, C, D */ 837c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x14 - 0x17: bus B slot 1 int#A, B, C, D */ 847c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x18 - 0x1B: bus B slot 2 int#A, B, C, D */ 857c478bd9Sstevel@tonic-gate 4, 0, 0, 0, /* 0x1C - 0x1F: bus B slot 3 int#A, B, C, D */ 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate 4, /* 0x20: SCSI */ 887c478bd9Sstevel@tonic-gate 6, /* 0x21: ethernet */ 897c478bd9Sstevel@tonic-gate 3, /* 0x22: parallel port */ 907c478bd9Sstevel@tonic-gate 9, /* 0x23: audio record */ 917c478bd9Sstevel@tonic-gate 9, /* 0x24: audio playback */ 927c478bd9Sstevel@tonic-gate 14, /* 0x25: power fail */ 937c478bd9Sstevel@tonic-gate 4, /* 0x26: 2nd SCSI */ 947c478bd9Sstevel@tonic-gate 8, /* 0x27: floppy */ 957c478bd9Sstevel@tonic-gate 14, /* 0x28: thermal warning */ 967c478bd9Sstevel@tonic-gate 12, /* 0x29: keyboard */ 977c478bd9Sstevel@tonic-gate 12, /* 0x2A: mouse */ 987c478bd9Sstevel@tonic-gate 12, /* 0x2B: serial */ 997c478bd9Sstevel@tonic-gate 0, /* 0x2C: timer/counter 0 */ 1007c478bd9Sstevel@tonic-gate 0, /* 0x2D: timer/counter 1 */ 1017c478bd9Sstevel@tonic-gate 14, /* 0x2E: uncorrectable ECC errors */ 1027c478bd9Sstevel@tonic-gate 14, /* 0x2F: correctable ECC errors */ 1037c478bd9Sstevel@tonic-gate 14, /* 0x30: PCI bus A error */ 1047c478bd9Sstevel@tonic-gate 14, /* 0x31: PCI bus B error */ 1057c478bd9Sstevel@tonic-gate 14, /* 0x32: power management wakeup */ 1067c478bd9Sstevel@tonic-gate 14, /* 0x33 */ 1077c478bd9Sstevel@tonic-gate 14, /* 0x34 */ 1087c478bd9Sstevel@tonic-gate 14, /* 0x35 */ 1097c478bd9Sstevel@tonic-gate 14, /* 0x36 */ 1107c478bd9Sstevel@tonic-gate 14, /* 0x37 */ 1117c478bd9Sstevel@tonic-gate 14, /* 0x38 */ 1127c478bd9Sstevel@tonic-gate 14, /* 0x39 */ 1137c478bd9Sstevel@tonic-gate 14, /* 0x3a */ 1147c478bd9Sstevel@tonic-gate 14, /* 0x3b */ 1157c478bd9Sstevel@tonic-gate 14, /* 0x3c */ 1167c478bd9Sstevel@tonic-gate 14, /* 0x3d */ 1177c478bd9Sstevel@tonic-gate 14, /* 0x3e */ 1187c478bd9Sstevel@tonic-gate 14, /* 0x3f */ 1197c478bd9Sstevel@tonic-gate 14 /* 0x40 */ 1207c478bd9Sstevel@tonic-gate }; 1217c478bd9Sstevel@tonic-gate #endif /* NOT_DEFINED */ 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate 1247c478bd9Sstevel@tonic-gate #define PCI_SIMBA_VENID 0x108e /* vendor id for simba */ 1257c478bd9Sstevel@tonic-gate #define PCI_SIMBA_DEVID 0x5000 /* device id for simba */ 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate /* 1287c478bd9Sstevel@tonic-gate * map_pcidev_cfg_reg - create mapping to pci device configuration registers 1297c478bd9Sstevel@tonic-gate * if we have a simba AND a pci to pci bridge along the 1307c478bd9Sstevel@tonic-gate * device path. 1317c478bd9Sstevel@tonic-gate * Called with corresponding mutexes held!! 1327c478bd9Sstevel@tonic-gate * 1337c478bd9Sstevel@tonic-gate * XXX XXX XXX The purpose of this routine is to overcome a hardware 1347c478bd9Sstevel@tonic-gate * defect in Sabre CPU and Simba bridge configuration 1357c478bd9Sstevel@tonic-gate * which does not drain DMA write data stalled in 1367c478bd9Sstevel@tonic-gate * PCI to PCI bridges (such as the DEC bridge) beyond 1377c478bd9Sstevel@tonic-gate * Simba. This routine will setup the data structures 1387c478bd9Sstevel@tonic-gate * to allow the pci_intr_wrapper to perform a manual 1397c478bd9Sstevel@tonic-gate * drain data operation before passing the control to 1407c478bd9Sstevel@tonic-gate * interrupt handlers of device drivers. 1417c478bd9Sstevel@tonic-gate * return value: 1427c478bd9Sstevel@tonic-gate * DDI_SUCCESS 1437c478bd9Sstevel@tonic-gate * DDI_FAILURE if unable to create mapping 1447c478bd9Sstevel@tonic-gate */ 1457c478bd9Sstevel@tonic-gate static int 1467c478bd9Sstevel@tonic-gate map_pcidev_cfg_reg(dev_info_t *dip, dev_info_t *rdip, ddi_acc_handle_t *hdl_p) 1477c478bd9Sstevel@tonic-gate { 1487c478bd9Sstevel@tonic-gate dev_info_t *cdip; 1497c478bd9Sstevel@tonic-gate dev_info_t *pci_dip = NULL; 1507c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1517c478bd9Sstevel@tonic-gate int simba_found = 0, pci_bridge_found = 0; 1527c478bd9Sstevel@tonic-gate 1537c478bd9Sstevel@tonic-gate for (cdip = rdip; cdip && cdip != dip; cdip = ddi_get_parent(cdip)) { 1547c478bd9Sstevel@tonic-gate ddi_acc_handle_t config_handle; 1557c478bd9Sstevel@tonic-gate uint32_t vendor_id = ddi_getprop(DDI_DEV_T_ANY, cdip, 1567c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "vendor-id", 0xffff); 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate DEBUG4(DBG_A_INTX, pci_p->pci_dip, 1597c478bd9Sstevel@tonic-gate "map dev cfg reg for %s%d: @%s%d\n", 1607c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 1617c478bd9Sstevel@tonic-gate ddi_driver_name(cdip), ddi_get_instance(cdip)); 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate if (ddi_prop_exists(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 1647c478bd9Sstevel@tonic-gate "no-dma-interrupt-sync")) 1657c478bd9Sstevel@tonic-gate continue; 1667c478bd9Sstevel@tonic-gate 1677c478bd9Sstevel@tonic-gate /* continue to search up-stream if not a PCI device */ 1687c478bd9Sstevel@tonic-gate if (vendor_id == 0xffff) 1697c478bd9Sstevel@tonic-gate continue; 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate /* record the deepest pci device */ 1727c478bd9Sstevel@tonic-gate if (!pci_dip) 1737c478bd9Sstevel@tonic-gate pci_dip = cdip; 1747c478bd9Sstevel@tonic-gate 1757c478bd9Sstevel@tonic-gate /* look for simba */ 1767c478bd9Sstevel@tonic-gate if (vendor_id == PCI_SIMBA_VENID) { 1777c478bd9Sstevel@tonic-gate uint32_t device_id = ddi_getprop(DDI_DEV_T_ANY, 1787c478bd9Sstevel@tonic-gate cdip, DDI_PROP_DONTPASS, "device-id", -1); 1797c478bd9Sstevel@tonic-gate if (device_id == PCI_SIMBA_DEVID) { 1807c478bd9Sstevel@tonic-gate simba_found = 1; 1817c478bd9Sstevel@tonic-gate DEBUG0(DBG_A_INTX, pci_p->pci_dip, 1827c478bd9Sstevel@tonic-gate "\tFound simba\n"); 1837c478bd9Sstevel@tonic-gate continue; /* do not check bridge if simba */ 1847c478bd9Sstevel@tonic-gate } 1857c478bd9Sstevel@tonic-gate } 1867c478bd9Sstevel@tonic-gate 1877c478bd9Sstevel@tonic-gate /* look for pci to pci bridge */ 1887c478bd9Sstevel@tonic-gate if (pci_config_setup(cdip, &config_handle) != DDI_SUCCESS) { 1897c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, 1907c478bd9Sstevel@tonic-gate "%s%d: can't get brdg cfg space for %s%d\n", 1917c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 1927c478bd9Sstevel@tonic-gate ddi_driver_name(cdip), ddi_get_instance(cdip)); 1937c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 1947c478bd9Sstevel@tonic-gate } 1957c478bd9Sstevel@tonic-gate if (pci_config_get8(config_handle, PCI_CONF_BASCLASS) 1967c478bd9Sstevel@tonic-gate == PCI_CLASS_BRIDGE) { 1977c478bd9Sstevel@tonic-gate DEBUG0(DBG_A_INTX, pci_p->pci_dip, 1987c478bd9Sstevel@tonic-gate "\tFound PCI to xBus bridge\n"); 1997c478bd9Sstevel@tonic-gate pci_bridge_found = 1; 2007c478bd9Sstevel@tonic-gate } 2017c478bd9Sstevel@tonic-gate pci_config_teardown(&config_handle); 2027c478bd9Sstevel@tonic-gate } 2037c478bd9Sstevel@tonic-gate 2047c478bd9Sstevel@tonic-gate if (!pci_bridge_found) 2057c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 2067c478bd9Sstevel@tonic-gate if (!simba_found && (CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO)) 2077c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 2087c478bd9Sstevel@tonic-gate if (pci_config_setup(pci_dip, hdl_p) != DDI_SUCCESS) { 2097c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: can not get config space for %s%d\n", 2107c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 2117c478bd9Sstevel@tonic-gate ddi_driver_name(cdip), ddi_get_instance(cdip)); 2127c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 2137c478bd9Sstevel@tonic-gate } 2147c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 2157c478bd9Sstevel@tonic-gate } 2167c478bd9Sstevel@tonic-gate 2177c478bd9Sstevel@tonic-gate /* 2187c478bd9Sstevel@tonic-gate * If the unclaimed interrupt count has reached the limit set by 2197c478bd9Sstevel@tonic-gate * pci_unclaimed_intr_max within the time limit, then all interrupts 2207c478bd9Sstevel@tonic-gate * on this ino is blocked by not idling the interrupt state machine. 2217c478bd9Sstevel@tonic-gate */ 2227c478bd9Sstevel@tonic-gate static int 2237c478bd9Sstevel@tonic-gate pci_spurintr(ib_ino_info_t *ino_p) { 2247c478bd9Sstevel@tonic-gate int i; 2257c478bd9Sstevel@tonic-gate ih_t *ih_p = ino_p->ino_ih_start; 2267c478bd9Sstevel@tonic-gate pci_t *pci_p = ino_p->ino_ib_p->ib_pci_p; 2277c478bd9Sstevel@tonic-gate char *err_fmt_str; 228*aa01ff85Sdanice boolean_t blocked = B_FALSE; 2297c478bd9Sstevel@tonic-gate 2307c478bd9Sstevel@tonic-gate if (ino_p->ino_unclaimed > pci_unclaimed_intr_max) 2317c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate if (!ino_p->ino_unclaimed) 2347c478bd9Sstevel@tonic-gate ino_p->ino_spurintr_begin = ddi_get_lbolt(); 2357c478bd9Sstevel@tonic-gate 2367c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed++; 2377c478bd9Sstevel@tonic-gate 2387c478bd9Sstevel@tonic-gate if (ino_p->ino_unclaimed <= pci_unclaimed_intr_max) 2397c478bd9Sstevel@tonic-gate goto clear; 2407c478bd9Sstevel@tonic-gate 2417c478bd9Sstevel@tonic-gate if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 2427c478bd9Sstevel@tonic-gate > pci_spurintr_duration) { 2437c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 2447c478bd9Sstevel@tonic-gate goto clear; 2457c478bd9Sstevel@tonic-gate } 2467c478bd9Sstevel@tonic-gate err_fmt_str = "%s%d: ino 0x%x blocked"; 247*aa01ff85Sdanice blocked = B_TRUE; 2487c478bd9Sstevel@tonic-gate goto warn; 2497c478bd9Sstevel@tonic-gate clear: 250*aa01ff85Sdanice if (!pci_spurintr_msgs) { /* tomatillo errata #71 spurious mondo */ 251*aa01ff85Sdanice /* clear the pending state */ 252*aa01ff85Sdanice IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); 2537c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 254*aa01ff85Sdanice } 2557c478bd9Sstevel@tonic-gate 2567c478bd9Sstevel@tonic-gate err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 2577c478bd9Sstevel@tonic-gate warn: 2587c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, err_fmt_str, NAMEINST(pci_p->pci_dip), ino_p->ino_ino); 2597c478bd9Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) 2607c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 2617c478bd9Sstevel@tonic-gate ih_p->ih_inum); 2627c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!\n"); 263*aa01ff85Sdanice if (blocked == B_FALSE) /* clear the pending state */ 264*aa01ff85Sdanice IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); 265*aa01ff85Sdanice 2667c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 2677c478bd9Sstevel@tonic-gate } 2687c478bd9Sstevel@tonic-gate 2697c478bd9Sstevel@tonic-gate /* 2707c478bd9Sstevel@tonic-gate * pci_intr_wrapper 2717c478bd9Sstevel@tonic-gate * 2727c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 2737c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 2747c478bd9Sstevel@tonic-gate * examines the return codes. 2757c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 2767c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 2777c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 2787c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 2797c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 2807c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 2817c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 2827c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 2837c478bd9Sstevel@tonic-gate * 2847c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 2857c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 2867c478bd9Sstevel@tonic-gate */ 2877c478bd9Sstevel@tonic-gate 2887c478bd9Sstevel@tonic-gate extern uint64_t intr_get_time(void); 2897c478bd9Sstevel@tonic-gate 2907c478bd9Sstevel@tonic-gate uint_t 2917c478bd9Sstevel@tonic-gate pci_intr_wrapper(caddr_t arg) 2927c478bd9Sstevel@tonic-gate { 2937c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p = (ib_ino_info_t *)arg; 2947c478bd9Sstevel@tonic-gate uint_t result = 0, r; 2957c478bd9Sstevel@tonic-gate pci_t *pci_p = ino_p->ino_ib_p->ib_pci_p; 2967c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 2977c478bd9Sstevel@tonic-gate ih_t *ih_p = ino_p->ino_ih_start; 2987c478bd9Sstevel@tonic-gate int i; 2997c478bd9Sstevel@tonic-gate 3007c478bd9Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) { 3017c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 3027c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 3037c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 3047c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 3057c478bd9Sstevel@tonic-gate ddi_acc_handle_t cfg_hdl = ih_p->ih_config_handle; 3067c478bd9Sstevel@tonic-gate 3077c478bd9Sstevel@tonic-gate if (pci_intr_dma_sync && cfg_hdl && pbm_p->pbm_sync_reg_pa) { 3087c478bd9Sstevel@tonic-gate (void) pci_config_get16(cfg_hdl, PCI_CONF_VENID); 3097c478bd9Sstevel@tonic-gate pci_pbm_dma_sync(pbm_p, ino_p->ino_ino); 3107c478bd9Sstevel@tonic-gate } 3117c478bd9Sstevel@tonic-gate 3127c478bd9Sstevel@tonic-gate if (ih_p->ih_intr_state == PCI_INTR_STATE_DISABLE) { 3137c478bd9Sstevel@tonic-gate DEBUG3(DBG_INTR, pci_p->pci_dip, 3147c478bd9Sstevel@tonic-gate "pci_intr_wrapper: %s%d interrupt %d is disabled\n", 3157c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 3167c478bd9Sstevel@tonic-gate ino_p->ino_ino); 3177c478bd9Sstevel@tonic-gate 3187c478bd9Sstevel@tonic-gate continue; 3197c478bd9Sstevel@tonic-gate } 3207c478bd9Sstevel@tonic-gate 3217c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 3227c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 3237c478bd9Sstevel@tonic-gate 3247c478bd9Sstevel@tonic-gate r = (*handler)(arg1, arg2); 3257c478bd9Sstevel@tonic-gate 3267c478bd9Sstevel@tonic-gate /* 3277c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect against 3287c478bd9Sstevel@tonic-gate * conflicting writes to ih_ticks from ib_intr_dist_all() by 3297c478bd9Sstevel@tonic-gate * using atomic ops. 3307c478bd9Sstevel@tonic-gate */ 3317c478bd9Sstevel@tonic-gate 3327c478bd9Sstevel@tonic-gate if (ino_p->ino_pil <= LOCK_LEVEL) 3337c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 3347c478bd9Sstevel@tonic-gate 3357c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 3367c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, r); 3377c478bd9Sstevel@tonic-gate 3387c478bd9Sstevel@tonic-gate result += r; 3397c478bd9Sstevel@tonic-gate 3407c478bd9Sstevel@tonic-gate if (pci_check_all_handlers) 3417c478bd9Sstevel@tonic-gate continue; 3427c478bd9Sstevel@tonic-gate if (result) 3437c478bd9Sstevel@tonic-gate break; 3447c478bd9Sstevel@tonic-gate } 3457c478bd9Sstevel@tonic-gate 3467c478bd9Sstevel@tonic-gate if (!result) 3477c478bd9Sstevel@tonic-gate return (pci_spurintr(ino_p)); 3487c478bd9Sstevel@tonic-gate 3497c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 3507c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); /* clear the pending state */ 3517c478bd9Sstevel@tonic-gate 3527c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3537c478bd9Sstevel@tonic-gate } 3547c478bd9Sstevel@tonic-gate 3557c478bd9Sstevel@tonic-gate dev_info_t * 3567c478bd9Sstevel@tonic-gate get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 3577c478bd9Sstevel@tonic-gate { 3587c478bd9Sstevel@tonic-gate dev_info_t *cdip = rdip; 3597c478bd9Sstevel@tonic-gate 3607c478bd9Sstevel@tonic-gate for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 3617c478bd9Sstevel@tonic-gate ; 3627c478bd9Sstevel@tonic-gate 3637c478bd9Sstevel@tonic-gate return (cdip); 3647c478bd9Sstevel@tonic-gate } 3657c478bd9Sstevel@tonic-gate 3667c478bd9Sstevel@tonic-gate /* default class to pil value mapping */ 3677c478bd9Sstevel@tonic-gate pci_class_val_t pci_default_pil [] = { 3687c478bd9Sstevel@tonic-gate {0x000000, 0xff0000, 0x1}, /* Class code for pre-2.0 devices */ 3697c478bd9Sstevel@tonic-gate {0x010000, 0xff0000, 0x4}, /* Mass Storage Controller */ 3707c478bd9Sstevel@tonic-gate {0x020000, 0xff0000, 0x6}, /* Network Controller */ 3717c478bd9Sstevel@tonic-gate {0x030000, 0xff0000, 0x9}, /* Display Controller */ 3727c478bd9Sstevel@tonic-gate {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ 3737c478bd9Sstevel@tonic-gate {0x050000, 0xff0000, 0xb}, /* Memory Controller */ 3747c478bd9Sstevel@tonic-gate {0x060000, 0xff0000, 0xb}, /* Bridge Controller */ 3757c478bd9Sstevel@tonic-gate {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ 3767c478bd9Sstevel@tonic-gate {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ 3777c478bd9Sstevel@tonic-gate {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ 3787c478bd9Sstevel@tonic-gate {0x0c0300, 0xffff00, 0x9}, /* Serial Bus Universal Serial Bus */ 3797c478bd9Sstevel@tonic-gate {0x0c0400, 0xffff00, 0x6}, /* Serial Bus, Fibre Channel */ 3807c478bd9Sstevel@tonic-gate {0x0c0600, 0xffff00, 0x6} /* Serial Bus, Infiniband */ 3817c478bd9Sstevel@tonic-gate }; 3827c478bd9Sstevel@tonic-gate 3837c478bd9Sstevel@tonic-gate /* 3847c478bd9Sstevel@tonic-gate * Default class to intr_weight value mapping (% of CPU). A driver.conf 3857c478bd9Sstevel@tonic-gate * entry on or above the pci node like 3867c478bd9Sstevel@tonic-gate * 3877c478bd9Sstevel@tonic-gate * pci-class-intr-weights= 0x020000, 0xff0000, 30; 3887c478bd9Sstevel@tonic-gate * 3897c478bd9Sstevel@tonic-gate * can be used to augment or override entries in the default table below. 3907c478bd9Sstevel@tonic-gate * 3917c478bd9Sstevel@tonic-gate * NB: The values below give NICs preference on redistribution, and provide 3927c478bd9Sstevel@tonic-gate * NICs some isolation from other interrupt sources. We need better interfaces 3937c478bd9Sstevel@tonic-gate * that allow the NIC driver to identify a specific NIC instance as high 3947c478bd9Sstevel@tonic-gate * bandwidth, and thus deserving of separation from other low bandwidth 3957c478bd9Sstevel@tonic-gate * NICs additional isolation from other interrupt sources. 3967c478bd9Sstevel@tonic-gate * 3977c478bd9Sstevel@tonic-gate * NB: We treat Infiniband like a NIC. 3987c478bd9Sstevel@tonic-gate */ 3997c478bd9Sstevel@tonic-gate pci_class_val_t pci_default_intr_weight [] = { 4007c478bd9Sstevel@tonic-gate {0x020000, 0xff0000, 35}, /* Network Controller */ 4017c478bd9Sstevel@tonic-gate {0x010000, 0xff0000, 10}, /* Mass Storage Controller */ 4027c478bd9Sstevel@tonic-gate {0x0c0400, 0xffff00, 10}, /* Serial Bus, Fibre Channel */ 4037c478bd9Sstevel@tonic-gate {0x0c0600, 0xffff00, 50} /* Serial Bus, Infiniband */ 4047c478bd9Sstevel@tonic-gate }; 4057c478bd9Sstevel@tonic-gate 4067c478bd9Sstevel@tonic-gate static uint32_t 4077c478bd9Sstevel@tonic-gate pci_match_class_val(uint32_t key, pci_class_val_t *rec_p, int nrec, 4087c478bd9Sstevel@tonic-gate uint32_t default_val) 4097c478bd9Sstevel@tonic-gate { 4107c478bd9Sstevel@tonic-gate int i; 4117c478bd9Sstevel@tonic-gate 4127c478bd9Sstevel@tonic-gate for (i = 0; i < nrec; rec_p++, i++) { 4137c478bd9Sstevel@tonic-gate if ((rec_p->class_code & rec_p->class_mask) == 4147c478bd9Sstevel@tonic-gate (key & rec_p->class_mask)) 4157c478bd9Sstevel@tonic-gate return (rec_p->class_val); 4167c478bd9Sstevel@tonic-gate } 4177c478bd9Sstevel@tonic-gate 4187c478bd9Sstevel@tonic-gate return (default_val); 4197c478bd9Sstevel@tonic-gate } 4207c478bd9Sstevel@tonic-gate 4217c478bd9Sstevel@tonic-gate /* 4227c478bd9Sstevel@tonic-gate * Return the configuration value, based on class code and sub class code, 4237c478bd9Sstevel@tonic-gate * from the specified property based or default pci_class_val_t table. 4247c478bd9Sstevel@tonic-gate */ 4257c478bd9Sstevel@tonic-gate uint32_t 4267c478bd9Sstevel@tonic-gate pci_class_to_val(dev_info_t *rdip, char *property_name, pci_class_val_t *rec_p, 4277c478bd9Sstevel@tonic-gate int nrec, uint32_t default_val) 4287c478bd9Sstevel@tonic-gate { 4297c478bd9Sstevel@tonic-gate int property_len; 4307c478bd9Sstevel@tonic-gate uint32_t class_code; 4317c478bd9Sstevel@tonic-gate pci_class_val_t *conf; 4327c478bd9Sstevel@tonic-gate uint32_t val = default_val; 4337c478bd9Sstevel@tonic-gate 4347c478bd9Sstevel@tonic-gate /* 4357c478bd9Sstevel@tonic-gate * Use the "class-code" property to get the base and sub class 4367c478bd9Sstevel@tonic-gate * codes for the requesting device. 4377c478bd9Sstevel@tonic-gate */ 4387c478bd9Sstevel@tonic-gate class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 4397c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "class-code", -1); 4407c478bd9Sstevel@tonic-gate 4417c478bd9Sstevel@tonic-gate if (class_code == -1) 4427c478bd9Sstevel@tonic-gate return (val); 4437c478bd9Sstevel@tonic-gate 4447c478bd9Sstevel@tonic-gate /* look up the val from the default table */ 4457c478bd9Sstevel@tonic-gate val = pci_match_class_val(class_code, rec_p, nrec, val); 4467c478bd9Sstevel@tonic-gate 4477c478bd9Sstevel@tonic-gate 4487c478bd9Sstevel@tonic-gate /* see if there is a more specific property specified value */ 4497c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM, 4507c478bd9Sstevel@tonic-gate property_name, (caddr_t)&conf, &property_len)) 4517c478bd9Sstevel@tonic-gate return (val); 4527c478bd9Sstevel@tonic-gate 4537c478bd9Sstevel@tonic-gate if ((property_len % sizeof (pci_class_val_t)) == 0) 4547c478bd9Sstevel@tonic-gate val = pci_match_class_val(class_code, conf, 4557c478bd9Sstevel@tonic-gate property_len / sizeof (pci_class_val_t), val); 4567c478bd9Sstevel@tonic-gate kmem_free(conf, property_len); 4577c478bd9Sstevel@tonic-gate return (val); 4587c478bd9Sstevel@tonic-gate } 4597c478bd9Sstevel@tonic-gate 4607c478bd9Sstevel@tonic-gate /* pci_class_to_pil: return the pil for a given PCI device. */ 4617c478bd9Sstevel@tonic-gate uint32_t 4627c478bd9Sstevel@tonic-gate pci_class_to_pil(dev_info_t *rdip) 4637c478bd9Sstevel@tonic-gate { 4647c478bd9Sstevel@tonic-gate uint32_t pil; 4657c478bd9Sstevel@tonic-gate 4667c478bd9Sstevel@tonic-gate /* default pil is 0 (uninitialized) */ 4677c478bd9Sstevel@tonic-gate pil = pci_class_to_val(rdip, 4687c478bd9Sstevel@tonic-gate "pci-class-priorities", pci_default_pil, 4697c478bd9Sstevel@tonic-gate sizeof (pci_default_pil) / sizeof (pci_class_val_t), 0); 4707c478bd9Sstevel@tonic-gate 4717c478bd9Sstevel@tonic-gate /* range check the result */ 4727c478bd9Sstevel@tonic-gate if (pil >= 0xf) 4737c478bd9Sstevel@tonic-gate pil = 0; 4747c478bd9Sstevel@tonic-gate 4757c478bd9Sstevel@tonic-gate return (pil); 4767c478bd9Sstevel@tonic-gate } 4777c478bd9Sstevel@tonic-gate 4787c478bd9Sstevel@tonic-gate /* pci_class_to_intr_weight: return the intr_weight for a given PCI device. */ 4797c478bd9Sstevel@tonic-gate int32_t 4807c478bd9Sstevel@tonic-gate pci_class_to_intr_weight(dev_info_t *rdip) 4817c478bd9Sstevel@tonic-gate { 4827c478bd9Sstevel@tonic-gate int32_t intr_weight; 4837c478bd9Sstevel@tonic-gate 4847c478bd9Sstevel@tonic-gate /* default weight is 0% */ 4857c478bd9Sstevel@tonic-gate intr_weight = pci_class_to_val(rdip, 4867c478bd9Sstevel@tonic-gate "pci-class-intr-weights", pci_default_intr_weight, 4877c478bd9Sstevel@tonic-gate sizeof (pci_default_intr_weight) / sizeof (pci_class_val_t), 0); 4887c478bd9Sstevel@tonic-gate 4897c478bd9Sstevel@tonic-gate /* range check the result */ 4907c478bd9Sstevel@tonic-gate if (intr_weight < 0) 4917c478bd9Sstevel@tonic-gate intr_weight = 0; 4927c478bd9Sstevel@tonic-gate if (intr_weight > 1000) 4937c478bd9Sstevel@tonic-gate intr_weight = 1000; 4947c478bd9Sstevel@tonic-gate 4957c478bd9Sstevel@tonic-gate return (intr_weight); 4967c478bd9Sstevel@tonic-gate } 4977c478bd9Sstevel@tonic-gate 4986d44af1bSesolom static struct { 4996d44af1bSesolom kstat_named_t pciintr_ks_name; 5006d44af1bSesolom kstat_named_t pciintr_ks_type; 5016d44af1bSesolom kstat_named_t pciintr_ks_cpu; 5026d44af1bSesolom kstat_named_t pciintr_ks_pil; 5036d44af1bSesolom kstat_named_t pciintr_ks_time; 5046d44af1bSesolom kstat_named_t pciintr_ks_ino; 5056d44af1bSesolom kstat_named_t pciintr_ks_cookie; 5066d44af1bSesolom kstat_named_t pciintr_ks_devpath; 5076d44af1bSesolom kstat_named_t pciintr_ks_buspath; 5086d44af1bSesolom } pciintr_ks_template = { 5096d44af1bSesolom { "name", KSTAT_DATA_CHAR }, 5106d44af1bSesolom { "type", KSTAT_DATA_CHAR }, 5116d44af1bSesolom { "cpu", KSTAT_DATA_UINT64 }, 5126d44af1bSesolom { "pil", KSTAT_DATA_UINT64 }, 5136d44af1bSesolom { "time", KSTAT_DATA_UINT64 }, 5146d44af1bSesolom { "ino", KSTAT_DATA_UINT64 }, 5156d44af1bSesolom { "cookie", KSTAT_DATA_UINT64 }, 5166d44af1bSesolom { "devpath", KSTAT_DATA_STRING }, 5176d44af1bSesolom { "buspath", KSTAT_DATA_STRING }, 5186d44af1bSesolom }; 5196d44af1bSesolom static uint32_t pciintr_ks_instance; 520d48713b8Sesolom static char ih_devpath[MAXPATHLEN]; 521d48713b8Sesolom static char ih_buspath[MAXPATHLEN]; 5226d44af1bSesolom 5236d44af1bSesolom kmutex_t pciintr_ks_template_lock; 5246d44af1bSesolom 5256d44af1bSesolom int 5266d44af1bSesolom pci_ks_update(kstat_t *ksp, int rw) 5276d44af1bSesolom { 5286d44af1bSesolom ih_t *ih_p = ksp->ks_private; 5296d44af1bSesolom int maxlen = sizeof (pciintr_ks_template.pciintr_ks_name.value.c); 5306d44af1bSesolom ib_t *ib_p = ih_p->ih_ino_p->ino_ib_p; 5316d44af1bSesolom pci_t *pci_p = ib_p->ib_pci_p; 5326d44af1bSesolom ib_ino_t ino; 5336d44af1bSesolom 5346d44af1bSesolom ino = ih_p->ih_ino_p->ino_ino; 5356d44af1bSesolom 5366d44af1bSesolom (void) snprintf(pciintr_ks_template.pciintr_ks_name.value.c, maxlen, 5376d44af1bSesolom "%s%d", ddi_driver_name(ih_p->ih_dip), 5386d44af1bSesolom ddi_get_instance(ih_p->ih_dip)); 5396d44af1bSesolom 5406d44af1bSesolom (void) ddi_pathname(ih_p->ih_dip, ih_devpath); 5416d44af1bSesolom (void) ddi_pathname(pci_p->pci_dip, ih_buspath); 5426d44af1bSesolom kstat_named_setstr(&pciintr_ks_template.pciintr_ks_devpath, ih_devpath); 5436d44af1bSesolom kstat_named_setstr(&pciintr_ks_template.pciintr_ks_buspath, ih_buspath); 5446d44af1bSesolom 545e1d9f4e6Sschwartz if (ih_p->ih_intr_state == PCI_INTR_STATE_ENABLE) { 546e1d9f4e6Sschwartz (void) strcpy(pciintr_ks_template.pciintr_ks_type.value.c, 547e1d9f4e6Sschwartz "fixed"); 548e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_cpu.value.ui64 = 549e1d9f4e6Sschwartz ih_p->ih_ino_p->ino_cpuid; 550e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_pil.value.ui64 = 551e1d9f4e6Sschwartz ih_p->ih_ino_p->ino_pil; 552e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_time.value.ui64 = ih_p->ih_nsec + 553e1d9f4e6Sschwartz (uint64_t)tick2ns((hrtime_t)ih_p->ih_ticks, 554e1d9f4e6Sschwartz ih_p->ih_ino_p->ino_cpuid); 555e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_ino.value.ui64 = ino; 556e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_cookie.value.ui64 = 557e1d9f4e6Sschwartz IB_INO_TO_MONDO(ib_p, ino); 558e1d9f4e6Sschwartz } else { 559e1d9f4e6Sschwartz (void) strcpy(pciintr_ks_template.pciintr_ks_type.value.c, 560e1d9f4e6Sschwartz "disabled"); 561e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_cpu.value.ui64 = 0; 562e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_pil.value.ui64 = 0; 563e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_time.value.ui64 = 0; 564e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_ino.value.ui64 = 0; 565e1d9f4e6Sschwartz pciintr_ks_template.pciintr_ks_cookie.value.ui64 = 0; 566e1d9f4e6Sschwartz } 567e1d9f4e6Sschwartz 5686d44af1bSesolom return (0); 5696d44af1bSesolom } 5706d44af1bSesolom 5717c478bd9Sstevel@tonic-gate int 5727c478bd9Sstevel@tonic-gate pci_add_intr(dev_info_t *dip, dev_info_t *rdip, ddi_intr_handle_impl_t *hdlp) 5737c478bd9Sstevel@tonic-gate { 5747c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 5757c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 5767c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 5777c478bd9Sstevel@tonic-gate ih_t *ih_p; 5787c478bd9Sstevel@tonic-gate ib_ino_t ino; 5797c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p; /* pulse interrupts have no ino */ 5807c478bd9Sstevel@tonic-gate ib_mondo_t mondo; 5817c478bd9Sstevel@tonic-gate uint32_t cpu_id; 5827c478bd9Sstevel@tonic-gate int ret; 5837c478bd9Sstevel@tonic-gate int32_t weight; 5847c478bd9Sstevel@tonic-gate 5857c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(hdlp->ih_vector); 5867c478bd9Sstevel@tonic-gate 5877c478bd9Sstevel@tonic-gate DEBUG3(DBG_A_INTX, dip, "pci_add_intr: rdip=%s%d ino=%x\n", 5887c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 5897c478bd9Sstevel@tonic-gate 5907c478bd9Sstevel@tonic-gate if (ino > ib_p->ib_max_ino) { 5917c478bd9Sstevel@tonic-gate DEBUG1(DBG_A_INTX, dip, "ino %x is invalid\n", ino); 5927c478bd9Sstevel@tonic-gate return (DDI_INTR_NOTFOUND); 5937c478bd9Sstevel@tonic-gate } 5947c478bd9Sstevel@tonic-gate 5957c478bd9Sstevel@tonic-gate if (hdlp->ih_vector & PCI_PULSE_INO) { 5967c478bd9Sstevel@tonic-gate volatile uint64_t *map_reg_addr; 5977c478bd9Sstevel@tonic-gate map_reg_addr = ib_intr_map_reg_addr(ib_p, ino); 5987c478bd9Sstevel@tonic-gate 5997c478bd9Sstevel@tonic-gate mondo = pci_xlate_intr(dip, rdip, ib_p, ino); 6007c478bd9Sstevel@tonic-gate if (mondo == 0) 6017c478bd9Sstevel@tonic-gate goto fail1; 6027c478bd9Sstevel@tonic-gate 6037c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 6047c478bd9Sstevel@tonic-gate 6057c478bd9Sstevel@tonic-gate if (i_ddi_add_ivintr(hdlp) != DDI_SUCCESS) 6067c478bd9Sstevel@tonic-gate goto fail1; 6077c478bd9Sstevel@tonic-gate 6087c478bd9Sstevel@tonic-gate /* 6097c478bd9Sstevel@tonic-gate * Select cpu and program. 6107c478bd9Sstevel@tonic-gate * 6117c478bd9Sstevel@tonic-gate * Since there is no good way to always derive cpuid in 6127c478bd9Sstevel@tonic-gate * pci_remove_intr for PCI_PULSE_INO (esp. for STARFIRE), we 6137c478bd9Sstevel@tonic-gate * don't add (or remove) device weight for pulsed interrupt 6147c478bd9Sstevel@tonic-gate * sources. 6157c478bd9Sstevel@tonic-gate */ 6167c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_intr_lock); 6177c478bd9Sstevel@tonic-gate cpu_id = intr_dist_cpuid(); 6187c478bd9Sstevel@tonic-gate *map_reg_addr = ib_get_map_reg(mondo, cpu_id); 6197c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_intr_lock); 6207c478bd9Sstevel@tonic-gate *map_reg_addr; /* flush previous write */ 6217c478bd9Sstevel@tonic-gate goto done; 6227c478bd9Sstevel@tonic-gate } 6237c478bd9Sstevel@tonic-gate 6247c478bd9Sstevel@tonic-gate if ((mondo = pci_xlate_intr(dip, rdip, pci_p->pci_ib_p, ino)) == 0) 6257c478bd9Sstevel@tonic-gate goto fail1; 6267c478bd9Sstevel@tonic-gate 6277c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(mondo); 6287c478bd9Sstevel@tonic-gate 6297c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 6307c478bd9Sstevel@tonic-gate ih_p = ib_alloc_ih(rdip, hdlp->ih_inum, 6317c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 6327c478bd9Sstevel@tonic-gate if (map_pcidev_cfg_reg(dip, rdip, &ih_p->ih_config_handle)) 6337c478bd9Sstevel@tonic-gate goto fail2; 6347c478bd9Sstevel@tonic-gate 6357c478bd9Sstevel@tonic-gate if (ino_p = ib_locate_ino(ib_p, ino)) { /* sharing ino */ 6367c478bd9Sstevel@tonic-gate uint32_t intr_index = hdlp->ih_inum; 6377c478bd9Sstevel@tonic-gate if (ib_ino_locate_intr(ino_p, rdip, intr_index)) { 6387c478bd9Sstevel@tonic-gate DEBUG1(DBG_A_INTX, dip, "dup intr #%d\n", intr_index); 6397c478bd9Sstevel@tonic-gate goto fail3; 6407c478bd9Sstevel@tonic-gate } 6417c478bd9Sstevel@tonic-gate 6427c478bd9Sstevel@tonic-gate /* add weight to the cpu that we are already targeting */ 6437c478bd9Sstevel@tonic-gate cpu_id = ino_p->ino_cpuid; 6447c478bd9Sstevel@tonic-gate weight = pci_class_to_intr_weight(rdip); 6457c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(cpu_id, rdip, weight); 6467c478bd9Sstevel@tonic-gate 6477c478bd9Sstevel@tonic-gate ib_ino_add_intr(pci_p, ino_p, ih_p); 6487c478bd9Sstevel@tonic-gate goto ino_done; 6497c478bd9Sstevel@tonic-gate } 6507c478bd9Sstevel@tonic-gate 6517c478bd9Sstevel@tonic-gate ino_p = ib_new_ino(ib_p, ino, ih_p); 6527c478bd9Sstevel@tonic-gate 6537c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 6547c478bd9Sstevel@tonic-gate hdlp->ih_pri = pci_class_to_pil(rdip); 6557c478bd9Sstevel@tonic-gate 6567c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 6577c478bd9Sstevel@tonic-gate 65836fe4a92Segillett /* Store this global mondo */ 65936fe4a92Segillett ino_p->ino_mondo = hdlp->ih_vector; 66036fe4a92Segillett 6617c478bd9Sstevel@tonic-gate DEBUG2(DBG_A_INTX, dip, "pci_add_intr: pil=0x%x mondo=0x%x\n", 6627c478bd9Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 6637c478bd9Sstevel@tonic-gate 6647c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 6657c478bd9Sstevel@tonic-gate (ddi_intr_handler_t *)pci_intr_wrapper, (caddr_t)ino_p, NULL); 6667c478bd9Sstevel@tonic-gate 6677c478bd9Sstevel@tonic-gate ret = i_ddi_add_ivintr(hdlp); 6687c478bd9Sstevel@tonic-gate 6697c478bd9Sstevel@tonic-gate /* 6707c478bd9Sstevel@tonic-gate * Restore original interrupt handler 6717c478bd9Sstevel@tonic-gate * and arguments in interrupt handle. 6727c478bd9Sstevel@tonic-gate */ 6737c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 6747c478bd9Sstevel@tonic-gate ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 6757c478bd9Sstevel@tonic-gate 6767c478bd9Sstevel@tonic-gate if (ret != DDI_SUCCESS) 6777c478bd9Sstevel@tonic-gate goto fail4; 6787c478bd9Sstevel@tonic-gate 6797c478bd9Sstevel@tonic-gate /* Save the pil for this ino */ 6807c478bd9Sstevel@tonic-gate ino_p->ino_pil = hdlp->ih_pri; 6817c478bd9Sstevel@tonic-gate 6827c478bd9Sstevel@tonic-gate /* clear and enable interrupt */ 6837c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); 6847c478bd9Sstevel@tonic-gate 6857c478bd9Sstevel@tonic-gate /* select cpu and compute weight, saving both for sharing and removal */ 6867c478bd9Sstevel@tonic-gate cpu_id = pci_intr_dist_cpuid(ib_p, ino_p); 6877c478bd9Sstevel@tonic-gate ino_p->ino_cpuid = cpu_id; 6887c478bd9Sstevel@tonic-gate ino_p->ino_established = 1; 6897c478bd9Sstevel@tonic-gate weight = pci_class_to_intr_weight(rdip); 6907c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(cpu_id, rdip, weight); 6917c478bd9Sstevel@tonic-gate 6927c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 6937c478bd9Sstevel@tonic-gate cpu_id = pc_translate_tgtid(cb_p->cb_ittrans_cookie, cpu_id, 6947c478bd9Sstevel@tonic-gate IB_GET_MAPREG_INO(ino)); 6957c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 6967c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg = ib_get_map_reg(mondo, cpu_id); 6977c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg; 6987c478bd9Sstevel@tonic-gate ino_done: 6997c478bd9Sstevel@tonic-gate ih_p->ih_ino_p = ino_p; 7006d44af1bSesolom ih_p->ih_ksp = kstat_create("pci_intrs", 7016d44af1bSesolom atomic_inc_32_nv(&pciintr_ks_instance), "config", "interrupts", 7026d44af1bSesolom KSTAT_TYPE_NAMED, 7036d44af1bSesolom sizeof (pciintr_ks_template) / sizeof (kstat_named_t), 7046d44af1bSesolom KSTAT_FLAG_VIRTUAL); 7056d44af1bSesolom if (ih_p->ih_ksp != NULL) { 7066d44af1bSesolom ih_p->ih_ksp->ks_data_size += MAXPATHLEN * 2; 7076d44af1bSesolom ih_p->ih_ksp->ks_lock = &pciintr_ks_template_lock; 7086d44af1bSesolom ih_p->ih_ksp->ks_data = &pciintr_ks_template; 7096d44af1bSesolom ih_p->ih_ksp->ks_private = ih_p; 7106d44af1bSesolom ih_p->ih_ksp->ks_update = pci_ks_update; 7117c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 7126d44af1bSesolom } 7137c478bd9Sstevel@tonic-gate ib_ino_map_reg_share(ib_p, ino, ino_p); 7147c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 7157c478bd9Sstevel@tonic-gate done: 7167c478bd9Sstevel@tonic-gate DEBUG2(DBG_A_INTX, dip, "done! Interrupt 0x%x pil=%x\n", 7177c478bd9Sstevel@tonic-gate hdlp->ih_vector, hdlp->ih_pri); 7187c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 7197c478bd9Sstevel@tonic-gate fail4: 7207c478bd9Sstevel@tonic-gate ib_delete_ino(ib_p, ino_p); 7217c478bd9Sstevel@tonic-gate fail3: 7227c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 7237c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 7247c478bd9Sstevel@tonic-gate fail2: 7257c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 7267c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (ih_t)); 7277c478bd9Sstevel@tonic-gate fail1: 7287c478bd9Sstevel@tonic-gate DEBUG2(DBG_A_INTX, dip, "Failed! Interrupt 0x%x pil=%x\n", 7297c478bd9Sstevel@tonic-gate hdlp->ih_vector, hdlp->ih_pri); 7307c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 7317c478bd9Sstevel@tonic-gate } 7327c478bd9Sstevel@tonic-gate 7337c478bd9Sstevel@tonic-gate int 7347c478bd9Sstevel@tonic-gate pci_remove_intr(dev_info_t *dip, dev_info_t *rdip, ddi_intr_handle_impl_t *hdlp) 7357c478bd9Sstevel@tonic-gate { 7367c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 7377c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 7387c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 7397c478bd9Sstevel@tonic-gate ib_ino_t ino; 7407c478bd9Sstevel@tonic-gate ib_mondo_t mondo; 7417c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p; /* non-pulse only */ 7427c478bd9Sstevel@tonic-gate ih_t *ih_p; /* non-pulse only */ 7437c478bd9Sstevel@tonic-gate 7447c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(hdlp->ih_vector); 7457c478bd9Sstevel@tonic-gate 7467c478bd9Sstevel@tonic-gate DEBUG3(DBG_R_INTX, dip, "pci_rem_intr: rdip=%s%d ino=%x\n", 7477c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate if (hdlp->ih_vector & PCI_PULSE_INO) { /* pulse interrupt */ 7507c478bd9Sstevel@tonic-gate volatile uint64_t *map_reg_addr; 7517c478bd9Sstevel@tonic-gate 7527c478bd9Sstevel@tonic-gate /* 7537c478bd9Sstevel@tonic-gate * No weight was added by pci_add_intr for PCI_PULSE_INO 7547c478bd9Sstevel@tonic-gate * because it is difficult to determine cpuid here. 7557c478bd9Sstevel@tonic-gate */ 7567c478bd9Sstevel@tonic-gate map_reg_addr = ib_intr_map_reg_addr(ib_p, ino); 7577c478bd9Sstevel@tonic-gate IB_INO_INTR_RESET(map_reg_addr); /* disable intr */ 7587c478bd9Sstevel@tonic-gate *map_reg_addr; 7597c478bd9Sstevel@tonic-gate 7607c478bd9Sstevel@tonic-gate mondo = pci_xlate_intr(dip, rdip, ib_p, ino); 7617c478bd9Sstevel@tonic-gate if (mondo == 0) { 7627c478bd9Sstevel@tonic-gate DEBUG1(DBG_R_INTX, dip, 7637c478bd9Sstevel@tonic-gate "can't get mondo for ino %x\n", ino); 7647c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 7657c478bd9Sstevel@tonic-gate } 7667c478bd9Sstevel@tonic-gate 7677c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 7687c478bd9Sstevel@tonic-gate hdlp->ih_pri = pci_class_to_pil(rdip); 7697c478bd9Sstevel@tonic-gate 7707c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 7717c478bd9Sstevel@tonic-gate 7727c478bd9Sstevel@tonic-gate DEBUG2(DBG_R_INTX, dip, "pci_rem_intr: pil=0x%x mondo=0x%x\n", 7737c478bd9Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 7747c478bd9Sstevel@tonic-gate 7757c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 7767c478bd9Sstevel@tonic-gate 7777c478bd9Sstevel@tonic-gate DEBUG2(DBG_R_INTX, dip, "pulse success mondo=%x reg=%p\n", 7787c478bd9Sstevel@tonic-gate mondo, map_reg_addr); 7797c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 7807c478bd9Sstevel@tonic-gate } 7817c478bd9Sstevel@tonic-gate 7827c478bd9Sstevel@tonic-gate /* Translate the interrupt property */ 7837c478bd9Sstevel@tonic-gate mondo = pci_xlate_intr(dip, rdip, pci_p->pci_ib_p, ino); 7847c478bd9Sstevel@tonic-gate if (mondo == 0) { 7857c478bd9Sstevel@tonic-gate DEBUG1(DBG_R_INTX, dip, "can't get mondo for ino %x\n", ino); 7867c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 7877c478bd9Sstevel@tonic-gate } 7887c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(mondo); 7897c478bd9Sstevel@tonic-gate 7907c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 7917c478bd9Sstevel@tonic-gate ino_p = ib_locate_ino(ib_p, ino); 7927c478bd9Sstevel@tonic-gate if (!ino_p) { 7937c478bd9Sstevel@tonic-gate int r = cb_remove_xintr(pci_p, dip, rdip, ino, mondo); 7947c478bd9Sstevel@tonic-gate if (r != DDI_SUCCESS) 7957c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d-xintr: ino %x is invalid", 7967c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), ino); 7977c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 7987c478bd9Sstevel@tonic-gate return (r); 7997c478bd9Sstevel@tonic-gate } 8007c478bd9Sstevel@tonic-gate 8017c478bd9Sstevel@tonic-gate ih_p = ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum); 8027c478bd9Sstevel@tonic-gate ib_ino_rem_intr(pci_p, ino_p, ih_p); 8037c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 8047c478bd9Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) { 8057c478bd9Sstevel@tonic-gate IB_INO_INTR_PEND(ib_clear_intr_reg_addr(ib_p, ino)); 8067c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 8077c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 8087c478bd9Sstevel@tonic-gate hdlp->ih_pri = pci_class_to_pil(rdip); 8097c478bd9Sstevel@tonic-gate 8107c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 8117c478bd9Sstevel@tonic-gate ib_delete_ino(ib_p, ino_p); 8127c478bd9Sstevel@tonic-gate } 8137c478bd9Sstevel@tonic-gate 8147c478bd9Sstevel@tonic-gate /* re-enable interrupt only if mapping register still shared */ 8157c478bd9Sstevel@tonic-gate if (ib_ino_map_reg_unshare(ib_p, ino, ino_p)) { 8167c478bd9Sstevel@tonic-gate IB_INO_INTR_ON(ino_p->ino_map_reg); 8177c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg; 8187c478bd9Sstevel@tonic-gate } 8197c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 8207c478bd9Sstevel@tonic-gate 8217c478bd9Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) 8227c478bd9Sstevel@tonic-gate kmem_free(ino_p, sizeof (ib_ino_info_t)); 8237c478bd9Sstevel@tonic-gate 8247c478bd9Sstevel@tonic-gate DEBUG1(DBG_R_INTX, dip, "success! mondo=%x\n", mondo); 8257c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 8267c478bd9Sstevel@tonic-gate } 8277c478bd9Sstevel@tonic-gate 8287c478bd9Sstevel@tonic-gate /* 8297c478bd9Sstevel@tonic-gate * free the pci_inos array allocated during pci_intr_setup. the actual 8307c478bd9Sstevel@tonic-gate * interrupts are torn down by their respective block destroy routines: 8317c478bd9Sstevel@tonic-gate * cb_destroy, pbm_destroy, and ib_destroy. 8327c478bd9Sstevel@tonic-gate */ 8337c478bd9Sstevel@tonic-gate void 8347c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_t *pci_p) 8357c478bd9Sstevel@tonic-gate { 8367c478bd9Sstevel@tonic-gate kmem_free(pci_p->pci_inos, pci_p->pci_inos_len); 8377c478bd9Sstevel@tonic-gate pci_p->pci_inos = NULL; 8387c478bd9Sstevel@tonic-gate pci_p->pci_inos_len = 0; 8397c478bd9Sstevel@tonic-gate } 840