1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*7c478bd9Sstevel@tonic-gate 29*7c478bd9Sstevel@tonic-gate /* 30*7c478bd9Sstevel@tonic-gate * PCI nexus interrupt handling: 31*7c478bd9Sstevel@tonic-gate * PCI device interrupt handler wrapper 32*7c478bd9Sstevel@tonic-gate * pil lookup routine 33*7c478bd9Sstevel@tonic-gate * PCI device interrupt related initchild code 34*7c478bd9Sstevel@tonic-gate */ 35*7c478bd9Sstevel@tonic-gate 36*7c478bd9Sstevel@tonic-gate #include <sys/types.h> 37*7c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 38*7c478bd9Sstevel@tonic-gate #include <sys/async.h> 39*7c478bd9Sstevel@tonic-gate #include <sys/spl.h> 40*7c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 41*7c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 42*7c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 43*7c478bd9Sstevel@tonic-gate #include <sys/pci/pci_obj.h> 44*7c478bd9Sstevel@tonic-gate #include <sys/sdt.h> 45*7c478bd9Sstevel@tonic-gate 46*7c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 47*7c478bd9Sstevel@tonic-gate #include <sys/starfire.h> 48*7c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 49*7c478bd9Sstevel@tonic-gate 50*7c478bd9Sstevel@tonic-gate /* 51*7c478bd9Sstevel@tonic-gate * interrupt jabber: 52*7c478bd9Sstevel@tonic-gate * 53*7c478bd9Sstevel@tonic-gate * When an interrupt line is jabbering, every time the state machine for the 54*7c478bd9Sstevel@tonic-gate * associated ino is idled, a new mondo will be sent and the ino will go into 55*7c478bd9Sstevel@tonic-gate * the pending state again. The mondo will cause a new call to 56*7c478bd9Sstevel@tonic-gate * pci_intr_wrapper() which normally idles the ino's state machine which would 57*7c478bd9Sstevel@tonic-gate * precipitate another trip round the loop. 58*7c478bd9Sstevel@tonic-gate * The loop can be broken by preventing the ino's state machine from being 59*7c478bd9Sstevel@tonic-gate * idled when an interrupt line is jabbering. See the comment at the 60*7c478bd9Sstevel@tonic-gate * beginning of pci_intr_wrapper() explaining how the 'interrupt jabber 61*7c478bd9Sstevel@tonic-gate * protection' code does this. 62*7c478bd9Sstevel@tonic-gate */ 63*7c478bd9Sstevel@tonic-gate 64*7c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 65*7c478bd9Sstevel@tonic-gate 66*7c478bd9Sstevel@tonic-gate #ifdef NOT_DEFINED 67*7c478bd9Sstevel@tonic-gate /* 68*7c478bd9Sstevel@tonic-gate * This array is used to determine the sparc PIL at the which the 69*7c478bd9Sstevel@tonic-gate * handler for a given INO will execute. This table is for onboard 70*7c478bd9Sstevel@tonic-gate * devices only. A different scheme will be used for plug-in cards. 71*7c478bd9Sstevel@tonic-gate */ 72*7c478bd9Sstevel@tonic-gate 73*7c478bd9Sstevel@tonic-gate uint_t ino_to_pil[] = { 74*7c478bd9Sstevel@tonic-gate 75*7c478bd9Sstevel@tonic-gate /* pil */ /* ino */ 76*7c478bd9Sstevel@tonic-gate 77*7c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x00 - 0x03: bus A slot 0 int#A, B, C, D */ 78*7c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x04 - 0x07: bus A slot 1 int#A, B, C, D */ 79*7c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x08 - 0x0B: unused */ 80*7c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x0C - 0x0F: unused */ 81*7c478bd9Sstevel@tonic-gate 82*7c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x10 - 0x13: bus B slot 0 int#A, B, C, D */ 83*7c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x14 - 0x17: bus B slot 1 int#A, B, C, D */ 84*7c478bd9Sstevel@tonic-gate 0, 0, 0, 0, /* 0x18 - 0x1B: bus B slot 2 int#A, B, C, D */ 85*7c478bd9Sstevel@tonic-gate 4, 0, 0, 0, /* 0x1C - 0x1F: bus B slot 3 int#A, B, C, D */ 86*7c478bd9Sstevel@tonic-gate 87*7c478bd9Sstevel@tonic-gate 4, /* 0x20: SCSI */ 88*7c478bd9Sstevel@tonic-gate 6, /* 0x21: ethernet */ 89*7c478bd9Sstevel@tonic-gate 3, /* 0x22: parallel port */ 90*7c478bd9Sstevel@tonic-gate 9, /* 0x23: audio record */ 91*7c478bd9Sstevel@tonic-gate 9, /* 0x24: audio playback */ 92*7c478bd9Sstevel@tonic-gate 14, /* 0x25: power fail */ 93*7c478bd9Sstevel@tonic-gate 4, /* 0x26: 2nd SCSI */ 94*7c478bd9Sstevel@tonic-gate 8, /* 0x27: floppy */ 95*7c478bd9Sstevel@tonic-gate 14, /* 0x28: thermal warning */ 96*7c478bd9Sstevel@tonic-gate 12, /* 0x29: keyboard */ 97*7c478bd9Sstevel@tonic-gate 12, /* 0x2A: mouse */ 98*7c478bd9Sstevel@tonic-gate 12, /* 0x2B: serial */ 99*7c478bd9Sstevel@tonic-gate 0, /* 0x2C: timer/counter 0 */ 100*7c478bd9Sstevel@tonic-gate 0, /* 0x2D: timer/counter 1 */ 101*7c478bd9Sstevel@tonic-gate 14, /* 0x2E: uncorrectable ECC errors */ 102*7c478bd9Sstevel@tonic-gate 14, /* 0x2F: correctable ECC errors */ 103*7c478bd9Sstevel@tonic-gate 14, /* 0x30: PCI bus A error */ 104*7c478bd9Sstevel@tonic-gate 14, /* 0x31: PCI bus B error */ 105*7c478bd9Sstevel@tonic-gate 14, /* 0x32: power management wakeup */ 106*7c478bd9Sstevel@tonic-gate 14, /* 0x33 */ 107*7c478bd9Sstevel@tonic-gate 14, /* 0x34 */ 108*7c478bd9Sstevel@tonic-gate 14, /* 0x35 */ 109*7c478bd9Sstevel@tonic-gate 14, /* 0x36 */ 110*7c478bd9Sstevel@tonic-gate 14, /* 0x37 */ 111*7c478bd9Sstevel@tonic-gate 14, /* 0x38 */ 112*7c478bd9Sstevel@tonic-gate 14, /* 0x39 */ 113*7c478bd9Sstevel@tonic-gate 14, /* 0x3a */ 114*7c478bd9Sstevel@tonic-gate 14, /* 0x3b */ 115*7c478bd9Sstevel@tonic-gate 14, /* 0x3c */ 116*7c478bd9Sstevel@tonic-gate 14, /* 0x3d */ 117*7c478bd9Sstevel@tonic-gate 14, /* 0x3e */ 118*7c478bd9Sstevel@tonic-gate 14, /* 0x3f */ 119*7c478bd9Sstevel@tonic-gate 14 /* 0x40 */ 120*7c478bd9Sstevel@tonic-gate }; 121*7c478bd9Sstevel@tonic-gate #endif /* NOT_DEFINED */ 122*7c478bd9Sstevel@tonic-gate 123*7c478bd9Sstevel@tonic-gate 124*7c478bd9Sstevel@tonic-gate #define PCI_SIMBA_VENID 0x108e /* vendor id for simba */ 125*7c478bd9Sstevel@tonic-gate #define PCI_SIMBA_DEVID 0x5000 /* device id for simba */ 126*7c478bd9Sstevel@tonic-gate 127*7c478bd9Sstevel@tonic-gate /* 128*7c478bd9Sstevel@tonic-gate * map_pcidev_cfg_reg - create mapping to pci device configuration registers 129*7c478bd9Sstevel@tonic-gate * if we have a simba AND a pci to pci bridge along the 130*7c478bd9Sstevel@tonic-gate * device path. 131*7c478bd9Sstevel@tonic-gate * Called with corresponding mutexes held!! 132*7c478bd9Sstevel@tonic-gate * 133*7c478bd9Sstevel@tonic-gate * XXX XXX XXX The purpose of this routine is to overcome a hardware 134*7c478bd9Sstevel@tonic-gate * defect in Sabre CPU and Simba bridge configuration 135*7c478bd9Sstevel@tonic-gate * which does not drain DMA write data stalled in 136*7c478bd9Sstevel@tonic-gate * PCI to PCI bridges (such as the DEC bridge) beyond 137*7c478bd9Sstevel@tonic-gate * Simba. This routine will setup the data structures 138*7c478bd9Sstevel@tonic-gate * to allow the pci_intr_wrapper to perform a manual 139*7c478bd9Sstevel@tonic-gate * drain data operation before passing the control to 140*7c478bd9Sstevel@tonic-gate * interrupt handlers of device drivers. 141*7c478bd9Sstevel@tonic-gate * return value: 142*7c478bd9Sstevel@tonic-gate * DDI_SUCCESS 143*7c478bd9Sstevel@tonic-gate * DDI_FAILURE if unable to create mapping 144*7c478bd9Sstevel@tonic-gate */ 145*7c478bd9Sstevel@tonic-gate static int 146*7c478bd9Sstevel@tonic-gate map_pcidev_cfg_reg(dev_info_t *dip, dev_info_t *rdip, ddi_acc_handle_t *hdl_p) 147*7c478bd9Sstevel@tonic-gate { 148*7c478bd9Sstevel@tonic-gate dev_info_t *cdip; 149*7c478bd9Sstevel@tonic-gate dev_info_t *pci_dip = NULL; 150*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 151*7c478bd9Sstevel@tonic-gate int simba_found = 0, pci_bridge_found = 0; 152*7c478bd9Sstevel@tonic-gate 153*7c478bd9Sstevel@tonic-gate for (cdip = rdip; cdip && cdip != dip; cdip = ddi_get_parent(cdip)) { 154*7c478bd9Sstevel@tonic-gate ddi_acc_handle_t config_handle; 155*7c478bd9Sstevel@tonic-gate uint32_t vendor_id = ddi_getprop(DDI_DEV_T_ANY, cdip, 156*7c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "vendor-id", 0xffff); 157*7c478bd9Sstevel@tonic-gate 158*7c478bd9Sstevel@tonic-gate DEBUG4(DBG_A_INTX, pci_p->pci_dip, 159*7c478bd9Sstevel@tonic-gate "map dev cfg reg for %s%d: @%s%d\n", 160*7c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 161*7c478bd9Sstevel@tonic-gate ddi_driver_name(cdip), ddi_get_instance(cdip)); 162*7c478bd9Sstevel@tonic-gate 163*7c478bd9Sstevel@tonic-gate if (ddi_prop_exists(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 164*7c478bd9Sstevel@tonic-gate "no-dma-interrupt-sync")) 165*7c478bd9Sstevel@tonic-gate continue; 166*7c478bd9Sstevel@tonic-gate 167*7c478bd9Sstevel@tonic-gate /* continue to search up-stream if not a PCI device */ 168*7c478bd9Sstevel@tonic-gate if (vendor_id == 0xffff) 169*7c478bd9Sstevel@tonic-gate continue; 170*7c478bd9Sstevel@tonic-gate 171*7c478bd9Sstevel@tonic-gate /* record the deepest pci device */ 172*7c478bd9Sstevel@tonic-gate if (!pci_dip) 173*7c478bd9Sstevel@tonic-gate pci_dip = cdip; 174*7c478bd9Sstevel@tonic-gate 175*7c478bd9Sstevel@tonic-gate /* look for simba */ 176*7c478bd9Sstevel@tonic-gate if (vendor_id == PCI_SIMBA_VENID) { 177*7c478bd9Sstevel@tonic-gate uint32_t device_id = ddi_getprop(DDI_DEV_T_ANY, 178*7c478bd9Sstevel@tonic-gate cdip, DDI_PROP_DONTPASS, "device-id", -1); 179*7c478bd9Sstevel@tonic-gate if (device_id == PCI_SIMBA_DEVID) { 180*7c478bd9Sstevel@tonic-gate simba_found = 1; 181*7c478bd9Sstevel@tonic-gate DEBUG0(DBG_A_INTX, pci_p->pci_dip, 182*7c478bd9Sstevel@tonic-gate "\tFound simba\n"); 183*7c478bd9Sstevel@tonic-gate continue; /* do not check bridge if simba */ 184*7c478bd9Sstevel@tonic-gate } 185*7c478bd9Sstevel@tonic-gate } 186*7c478bd9Sstevel@tonic-gate 187*7c478bd9Sstevel@tonic-gate /* look for pci to pci bridge */ 188*7c478bd9Sstevel@tonic-gate if (pci_config_setup(cdip, &config_handle) != DDI_SUCCESS) { 189*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, 190*7c478bd9Sstevel@tonic-gate "%s%d: can't get brdg cfg space for %s%d\n", 191*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 192*7c478bd9Sstevel@tonic-gate ddi_driver_name(cdip), ddi_get_instance(cdip)); 193*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 194*7c478bd9Sstevel@tonic-gate } 195*7c478bd9Sstevel@tonic-gate if (pci_config_get8(config_handle, PCI_CONF_BASCLASS) 196*7c478bd9Sstevel@tonic-gate == PCI_CLASS_BRIDGE) { 197*7c478bd9Sstevel@tonic-gate DEBUG0(DBG_A_INTX, pci_p->pci_dip, 198*7c478bd9Sstevel@tonic-gate "\tFound PCI to xBus bridge\n"); 199*7c478bd9Sstevel@tonic-gate pci_bridge_found = 1; 200*7c478bd9Sstevel@tonic-gate } 201*7c478bd9Sstevel@tonic-gate pci_config_teardown(&config_handle); 202*7c478bd9Sstevel@tonic-gate } 203*7c478bd9Sstevel@tonic-gate 204*7c478bd9Sstevel@tonic-gate if (!pci_bridge_found) 205*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 206*7c478bd9Sstevel@tonic-gate if (!simba_found && (CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO)) 207*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 208*7c478bd9Sstevel@tonic-gate if (pci_config_setup(pci_dip, hdl_p) != DDI_SUCCESS) { 209*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: can not get config space for %s%d\n", 210*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 211*7c478bd9Sstevel@tonic-gate ddi_driver_name(cdip), ddi_get_instance(cdip)); 212*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 213*7c478bd9Sstevel@tonic-gate } 214*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 215*7c478bd9Sstevel@tonic-gate } 216*7c478bd9Sstevel@tonic-gate 217*7c478bd9Sstevel@tonic-gate /* 218*7c478bd9Sstevel@tonic-gate * If the unclaimed interrupt count has reached the limit set by 219*7c478bd9Sstevel@tonic-gate * pci_unclaimed_intr_max within the time limit, then all interrupts 220*7c478bd9Sstevel@tonic-gate * on this ino is blocked by not idling the interrupt state machine. 221*7c478bd9Sstevel@tonic-gate */ 222*7c478bd9Sstevel@tonic-gate static int 223*7c478bd9Sstevel@tonic-gate pci_spurintr(ib_ino_info_t *ino_p) { 224*7c478bd9Sstevel@tonic-gate int i; 225*7c478bd9Sstevel@tonic-gate ih_t *ih_p = ino_p->ino_ih_start; 226*7c478bd9Sstevel@tonic-gate pci_t *pci_p = ino_p->ino_ib_p->ib_pci_p; 227*7c478bd9Sstevel@tonic-gate char *err_fmt_str; 228*7c478bd9Sstevel@tonic-gate 229*7c478bd9Sstevel@tonic-gate if (ino_p->ino_unclaimed > pci_unclaimed_intr_max) 230*7c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 231*7c478bd9Sstevel@tonic-gate 232*7c478bd9Sstevel@tonic-gate if (!ino_p->ino_unclaimed) 233*7c478bd9Sstevel@tonic-gate ino_p->ino_spurintr_begin = ddi_get_lbolt(); 234*7c478bd9Sstevel@tonic-gate 235*7c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed++; 236*7c478bd9Sstevel@tonic-gate 237*7c478bd9Sstevel@tonic-gate if (ino_p->ino_unclaimed <= pci_unclaimed_intr_max) 238*7c478bd9Sstevel@tonic-gate goto clear; 239*7c478bd9Sstevel@tonic-gate 240*7c478bd9Sstevel@tonic-gate if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 241*7c478bd9Sstevel@tonic-gate > pci_spurintr_duration) { 242*7c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 243*7c478bd9Sstevel@tonic-gate goto clear; 244*7c478bd9Sstevel@tonic-gate } 245*7c478bd9Sstevel@tonic-gate err_fmt_str = "%s%d: ino 0x%x blocked"; 246*7c478bd9Sstevel@tonic-gate goto warn; 247*7c478bd9Sstevel@tonic-gate clear: 248*7c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); /* clear the pending state */ 249*7c478bd9Sstevel@tonic-gate if (!pci_spurintr_msgs) /* tomatillo errata #71 spurious mondo */ 250*7c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 251*7c478bd9Sstevel@tonic-gate 252*7c478bd9Sstevel@tonic-gate err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 253*7c478bd9Sstevel@tonic-gate warn: 254*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, err_fmt_str, NAMEINST(pci_p->pci_dip), ino_p->ino_ino); 255*7c478bd9Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) 256*7c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 257*7c478bd9Sstevel@tonic-gate ih_p->ih_inum); 258*7c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!\n"); 259*7c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 260*7c478bd9Sstevel@tonic-gate } 261*7c478bd9Sstevel@tonic-gate 262*7c478bd9Sstevel@tonic-gate /* 263*7c478bd9Sstevel@tonic-gate * pci_intr_wrapper 264*7c478bd9Sstevel@tonic-gate * 265*7c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 266*7c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 267*7c478bd9Sstevel@tonic-gate * examines the return codes. 268*7c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 269*7c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 270*7c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 271*7c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 272*7c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 273*7c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 274*7c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 275*7c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 276*7c478bd9Sstevel@tonic-gate * 277*7c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 278*7c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 279*7c478bd9Sstevel@tonic-gate */ 280*7c478bd9Sstevel@tonic-gate 281*7c478bd9Sstevel@tonic-gate extern uint64_t intr_get_time(void); 282*7c478bd9Sstevel@tonic-gate 283*7c478bd9Sstevel@tonic-gate uint_t 284*7c478bd9Sstevel@tonic-gate pci_intr_wrapper(caddr_t arg) 285*7c478bd9Sstevel@tonic-gate { 286*7c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p = (ib_ino_info_t *)arg; 287*7c478bd9Sstevel@tonic-gate uint_t result = 0, r; 288*7c478bd9Sstevel@tonic-gate pci_t *pci_p = ino_p->ino_ib_p->ib_pci_p; 289*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 290*7c478bd9Sstevel@tonic-gate ih_t *ih_p = ino_p->ino_ih_start; 291*7c478bd9Sstevel@tonic-gate int i; 292*7c478bd9Sstevel@tonic-gate 293*7c478bd9Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) { 294*7c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 295*7c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 296*7c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 297*7c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 298*7c478bd9Sstevel@tonic-gate ddi_acc_handle_t cfg_hdl = ih_p->ih_config_handle; 299*7c478bd9Sstevel@tonic-gate 300*7c478bd9Sstevel@tonic-gate if (pci_intr_dma_sync && cfg_hdl && pbm_p->pbm_sync_reg_pa) { 301*7c478bd9Sstevel@tonic-gate (void) pci_config_get16(cfg_hdl, PCI_CONF_VENID); 302*7c478bd9Sstevel@tonic-gate pci_pbm_dma_sync(pbm_p, ino_p->ino_ino); 303*7c478bd9Sstevel@tonic-gate } 304*7c478bd9Sstevel@tonic-gate 305*7c478bd9Sstevel@tonic-gate if (ih_p->ih_intr_state == PCI_INTR_STATE_DISABLE) { 306*7c478bd9Sstevel@tonic-gate DEBUG3(DBG_INTR, pci_p->pci_dip, 307*7c478bd9Sstevel@tonic-gate "pci_intr_wrapper: %s%d interrupt %d is disabled\n", 308*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 309*7c478bd9Sstevel@tonic-gate ino_p->ino_ino); 310*7c478bd9Sstevel@tonic-gate 311*7c478bd9Sstevel@tonic-gate continue; 312*7c478bd9Sstevel@tonic-gate } 313*7c478bd9Sstevel@tonic-gate 314*7c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 315*7c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 316*7c478bd9Sstevel@tonic-gate 317*7c478bd9Sstevel@tonic-gate r = (*handler)(arg1, arg2); 318*7c478bd9Sstevel@tonic-gate 319*7c478bd9Sstevel@tonic-gate /* 320*7c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect against 321*7c478bd9Sstevel@tonic-gate * conflicting writes to ih_ticks from ib_intr_dist_all() by 322*7c478bd9Sstevel@tonic-gate * using atomic ops. 323*7c478bd9Sstevel@tonic-gate */ 324*7c478bd9Sstevel@tonic-gate 325*7c478bd9Sstevel@tonic-gate if (ino_p->ino_pil <= LOCK_LEVEL) 326*7c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 327*7c478bd9Sstevel@tonic-gate 328*7c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 329*7c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, r); 330*7c478bd9Sstevel@tonic-gate 331*7c478bd9Sstevel@tonic-gate result += r; 332*7c478bd9Sstevel@tonic-gate 333*7c478bd9Sstevel@tonic-gate if (pci_check_all_handlers) 334*7c478bd9Sstevel@tonic-gate continue; 335*7c478bd9Sstevel@tonic-gate if (result) 336*7c478bd9Sstevel@tonic-gate break; 337*7c478bd9Sstevel@tonic-gate } 338*7c478bd9Sstevel@tonic-gate 339*7c478bd9Sstevel@tonic-gate if (!result) 340*7c478bd9Sstevel@tonic-gate return (pci_spurintr(ino_p)); 341*7c478bd9Sstevel@tonic-gate 342*7c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 343*7c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); /* clear the pending state */ 344*7c478bd9Sstevel@tonic-gate 345*7c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 346*7c478bd9Sstevel@tonic-gate } 347*7c478bd9Sstevel@tonic-gate 348*7c478bd9Sstevel@tonic-gate dev_info_t * 349*7c478bd9Sstevel@tonic-gate get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 350*7c478bd9Sstevel@tonic-gate { 351*7c478bd9Sstevel@tonic-gate dev_info_t *cdip = rdip; 352*7c478bd9Sstevel@tonic-gate 353*7c478bd9Sstevel@tonic-gate for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 354*7c478bd9Sstevel@tonic-gate ; 355*7c478bd9Sstevel@tonic-gate 356*7c478bd9Sstevel@tonic-gate return (cdip); 357*7c478bd9Sstevel@tonic-gate } 358*7c478bd9Sstevel@tonic-gate 359*7c478bd9Sstevel@tonic-gate /* default class to pil value mapping */ 360*7c478bd9Sstevel@tonic-gate pci_class_val_t pci_default_pil [] = { 361*7c478bd9Sstevel@tonic-gate {0x000000, 0xff0000, 0x1}, /* Class code for pre-2.0 devices */ 362*7c478bd9Sstevel@tonic-gate {0x010000, 0xff0000, 0x4}, /* Mass Storage Controller */ 363*7c478bd9Sstevel@tonic-gate {0x020000, 0xff0000, 0x6}, /* Network Controller */ 364*7c478bd9Sstevel@tonic-gate {0x030000, 0xff0000, 0x9}, /* Display Controller */ 365*7c478bd9Sstevel@tonic-gate {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ 366*7c478bd9Sstevel@tonic-gate {0x050000, 0xff0000, 0xb}, /* Memory Controller */ 367*7c478bd9Sstevel@tonic-gate {0x060000, 0xff0000, 0xb}, /* Bridge Controller */ 368*7c478bd9Sstevel@tonic-gate {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ 369*7c478bd9Sstevel@tonic-gate {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ 370*7c478bd9Sstevel@tonic-gate {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ 371*7c478bd9Sstevel@tonic-gate {0x0c0300, 0xffff00, 0x9}, /* Serial Bus Universal Serial Bus */ 372*7c478bd9Sstevel@tonic-gate {0x0c0400, 0xffff00, 0x6}, /* Serial Bus, Fibre Channel */ 373*7c478bd9Sstevel@tonic-gate {0x0c0600, 0xffff00, 0x6} /* Serial Bus, Infiniband */ 374*7c478bd9Sstevel@tonic-gate }; 375*7c478bd9Sstevel@tonic-gate 376*7c478bd9Sstevel@tonic-gate /* 377*7c478bd9Sstevel@tonic-gate * Default class to intr_weight value mapping (% of CPU). A driver.conf 378*7c478bd9Sstevel@tonic-gate * entry on or above the pci node like 379*7c478bd9Sstevel@tonic-gate * 380*7c478bd9Sstevel@tonic-gate * pci-class-intr-weights= 0x020000, 0xff0000, 30; 381*7c478bd9Sstevel@tonic-gate * 382*7c478bd9Sstevel@tonic-gate * can be used to augment or override entries in the default table below. 383*7c478bd9Sstevel@tonic-gate * 384*7c478bd9Sstevel@tonic-gate * NB: The values below give NICs preference on redistribution, and provide 385*7c478bd9Sstevel@tonic-gate * NICs some isolation from other interrupt sources. We need better interfaces 386*7c478bd9Sstevel@tonic-gate * that allow the NIC driver to identify a specific NIC instance as high 387*7c478bd9Sstevel@tonic-gate * bandwidth, and thus deserving of separation from other low bandwidth 388*7c478bd9Sstevel@tonic-gate * NICs additional isolation from other interrupt sources. 389*7c478bd9Sstevel@tonic-gate * 390*7c478bd9Sstevel@tonic-gate * NB: We treat Infiniband like a NIC. 391*7c478bd9Sstevel@tonic-gate */ 392*7c478bd9Sstevel@tonic-gate pci_class_val_t pci_default_intr_weight [] = { 393*7c478bd9Sstevel@tonic-gate {0x020000, 0xff0000, 35}, /* Network Controller */ 394*7c478bd9Sstevel@tonic-gate {0x010000, 0xff0000, 10}, /* Mass Storage Controller */ 395*7c478bd9Sstevel@tonic-gate {0x0c0400, 0xffff00, 10}, /* Serial Bus, Fibre Channel */ 396*7c478bd9Sstevel@tonic-gate {0x0c0600, 0xffff00, 50} /* Serial Bus, Infiniband */ 397*7c478bd9Sstevel@tonic-gate }; 398*7c478bd9Sstevel@tonic-gate 399*7c478bd9Sstevel@tonic-gate static uint32_t 400*7c478bd9Sstevel@tonic-gate pci_match_class_val(uint32_t key, pci_class_val_t *rec_p, int nrec, 401*7c478bd9Sstevel@tonic-gate uint32_t default_val) 402*7c478bd9Sstevel@tonic-gate { 403*7c478bd9Sstevel@tonic-gate int i; 404*7c478bd9Sstevel@tonic-gate 405*7c478bd9Sstevel@tonic-gate for (i = 0; i < nrec; rec_p++, i++) { 406*7c478bd9Sstevel@tonic-gate if ((rec_p->class_code & rec_p->class_mask) == 407*7c478bd9Sstevel@tonic-gate (key & rec_p->class_mask)) 408*7c478bd9Sstevel@tonic-gate return (rec_p->class_val); 409*7c478bd9Sstevel@tonic-gate } 410*7c478bd9Sstevel@tonic-gate 411*7c478bd9Sstevel@tonic-gate return (default_val); 412*7c478bd9Sstevel@tonic-gate } 413*7c478bd9Sstevel@tonic-gate 414*7c478bd9Sstevel@tonic-gate /* 415*7c478bd9Sstevel@tonic-gate * Return the configuration value, based on class code and sub class code, 416*7c478bd9Sstevel@tonic-gate * from the specified property based or default pci_class_val_t table. 417*7c478bd9Sstevel@tonic-gate */ 418*7c478bd9Sstevel@tonic-gate uint32_t 419*7c478bd9Sstevel@tonic-gate pci_class_to_val(dev_info_t *rdip, char *property_name, pci_class_val_t *rec_p, 420*7c478bd9Sstevel@tonic-gate int nrec, uint32_t default_val) 421*7c478bd9Sstevel@tonic-gate { 422*7c478bd9Sstevel@tonic-gate int property_len; 423*7c478bd9Sstevel@tonic-gate uint32_t class_code; 424*7c478bd9Sstevel@tonic-gate pci_class_val_t *conf; 425*7c478bd9Sstevel@tonic-gate uint32_t val = default_val; 426*7c478bd9Sstevel@tonic-gate 427*7c478bd9Sstevel@tonic-gate /* 428*7c478bd9Sstevel@tonic-gate * Use the "class-code" property to get the base and sub class 429*7c478bd9Sstevel@tonic-gate * codes for the requesting device. 430*7c478bd9Sstevel@tonic-gate */ 431*7c478bd9Sstevel@tonic-gate class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 432*7c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "class-code", -1); 433*7c478bd9Sstevel@tonic-gate 434*7c478bd9Sstevel@tonic-gate if (class_code == -1) 435*7c478bd9Sstevel@tonic-gate return (val); 436*7c478bd9Sstevel@tonic-gate 437*7c478bd9Sstevel@tonic-gate /* look up the val from the default table */ 438*7c478bd9Sstevel@tonic-gate val = pci_match_class_val(class_code, rec_p, nrec, val); 439*7c478bd9Sstevel@tonic-gate 440*7c478bd9Sstevel@tonic-gate 441*7c478bd9Sstevel@tonic-gate /* see if there is a more specific property specified value */ 442*7c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM, 443*7c478bd9Sstevel@tonic-gate property_name, (caddr_t)&conf, &property_len)) 444*7c478bd9Sstevel@tonic-gate return (val); 445*7c478bd9Sstevel@tonic-gate 446*7c478bd9Sstevel@tonic-gate if ((property_len % sizeof (pci_class_val_t)) == 0) 447*7c478bd9Sstevel@tonic-gate val = pci_match_class_val(class_code, conf, 448*7c478bd9Sstevel@tonic-gate property_len / sizeof (pci_class_val_t), val); 449*7c478bd9Sstevel@tonic-gate kmem_free(conf, property_len); 450*7c478bd9Sstevel@tonic-gate return (val); 451*7c478bd9Sstevel@tonic-gate } 452*7c478bd9Sstevel@tonic-gate 453*7c478bd9Sstevel@tonic-gate /* pci_class_to_pil: return the pil for a given PCI device. */ 454*7c478bd9Sstevel@tonic-gate uint32_t 455*7c478bd9Sstevel@tonic-gate pci_class_to_pil(dev_info_t *rdip) 456*7c478bd9Sstevel@tonic-gate { 457*7c478bd9Sstevel@tonic-gate uint32_t pil; 458*7c478bd9Sstevel@tonic-gate 459*7c478bd9Sstevel@tonic-gate /* default pil is 0 (uninitialized) */ 460*7c478bd9Sstevel@tonic-gate pil = pci_class_to_val(rdip, 461*7c478bd9Sstevel@tonic-gate "pci-class-priorities", pci_default_pil, 462*7c478bd9Sstevel@tonic-gate sizeof (pci_default_pil) / sizeof (pci_class_val_t), 0); 463*7c478bd9Sstevel@tonic-gate 464*7c478bd9Sstevel@tonic-gate /* range check the result */ 465*7c478bd9Sstevel@tonic-gate if (pil >= 0xf) 466*7c478bd9Sstevel@tonic-gate pil = 0; 467*7c478bd9Sstevel@tonic-gate 468*7c478bd9Sstevel@tonic-gate return (pil); 469*7c478bd9Sstevel@tonic-gate } 470*7c478bd9Sstevel@tonic-gate 471*7c478bd9Sstevel@tonic-gate /* pci_class_to_intr_weight: return the intr_weight for a given PCI device. */ 472*7c478bd9Sstevel@tonic-gate int32_t 473*7c478bd9Sstevel@tonic-gate pci_class_to_intr_weight(dev_info_t *rdip) 474*7c478bd9Sstevel@tonic-gate { 475*7c478bd9Sstevel@tonic-gate int32_t intr_weight; 476*7c478bd9Sstevel@tonic-gate 477*7c478bd9Sstevel@tonic-gate /* default weight is 0% */ 478*7c478bd9Sstevel@tonic-gate intr_weight = pci_class_to_val(rdip, 479*7c478bd9Sstevel@tonic-gate "pci-class-intr-weights", pci_default_intr_weight, 480*7c478bd9Sstevel@tonic-gate sizeof (pci_default_intr_weight) / sizeof (pci_class_val_t), 0); 481*7c478bd9Sstevel@tonic-gate 482*7c478bd9Sstevel@tonic-gate /* range check the result */ 483*7c478bd9Sstevel@tonic-gate if (intr_weight < 0) 484*7c478bd9Sstevel@tonic-gate intr_weight = 0; 485*7c478bd9Sstevel@tonic-gate if (intr_weight > 1000) 486*7c478bd9Sstevel@tonic-gate intr_weight = 1000; 487*7c478bd9Sstevel@tonic-gate 488*7c478bd9Sstevel@tonic-gate return (intr_weight); 489*7c478bd9Sstevel@tonic-gate } 490*7c478bd9Sstevel@tonic-gate 491*7c478bd9Sstevel@tonic-gate int 492*7c478bd9Sstevel@tonic-gate pci_add_intr(dev_info_t *dip, dev_info_t *rdip, ddi_intr_handle_impl_t *hdlp) 493*7c478bd9Sstevel@tonic-gate { 494*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 495*7c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 496*7c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 497*7c478bd9Sstevel@tonic-gate ih_t *ih_p; 498*7c478bd9Sstevel@tonic-gate ib_ino_t ino; 499*7c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p; /* pulse interrupts have no ino */ 500*7c478bd9Sstevel@tonic-gate ib_mondo_t mondo; 501*7c478bd9Sstevel@tonic-gate uint32_t cpu_id; 502*7c478bd9Sstevel@tonic-gate int ret; 503*7c478bd9Sstevel@tonic-gate int32_t weight; 504*7c478bd9Sstevel@tonic-gate 505*7c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(hdlp->ih_vector); 506*7c478bd9Sstevel@tonic-gate 507*7c478bd9Sstevel@tonic-gate DEBUG3(DBG_A_INTX, dip, "pci_add_intr: rdip=%s%d ino=%x\n", 508*7c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 509*7c478bd9Sstevel@tonic-gate 510*7c478bd9Sstevel@tonic-gate if (ino > ib_p->ib_max_ino) { 511*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_A_INTX, dip, "ino %x is invalid\n", ino); 512*7c478bd9Sstevel@tonic-gate return (DDI_INTR_NOTFOUND); 513*7c478bd9Sstevel@tonic-gate } 514*7c478bd9Sstevel@tonic-gate 515*7c478bd9Sstevel@tonic-gate if (hdlp->ih_vector & PCI_PULSE_INO) { 516*7c478bd9Sstevel@tonic-gate volatile uint64_t *map_reg_addr; 517*7c478bd9Sstevel@tonic-gate map_reg_addr = ib_intr_map_reg_addr(ib_p, ino); 518*7c478bd9Sstevel@tonic-gate 519*7c478bd9Sstevel@tonic-gate mondo = pci_xlate_intr(dip, rdip, ib_p, ino); 520*7c478bd9Sstevel@tonic-gate if (mondo == 0) 521*7c478bd9Sstevel@tonic-gate goto fail1; 522*7c478bd9Sstevel@tonic-gate 523*7c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 524*7c478bd9Sstevel@tonic-gate 525*7c478bd9Sstevel@tonic-gate if (i_ddi_add_ivintr(hdlp) != DDI_SUCCESS) 526*7c478bd9Sstevel@tonic-gate goto fail1; 527*7c478bd9Sstevel@tonic-gate 528*7c478bd9Sstevel@tonic-gate /* 529*7c478bd9Sstevel@tonic-gate * Select cpu and program. 530*7c478bd9Sstevel@tonic-gate * 531*7c478bd9Sstevel@tonic-gate * Since there is no good way to always derive cpuid in 532*7c478bd9Sstevel@tonic-gate * pci_remove_intr for PCI_PULSE_INO (esp. for STARFIRE), we 533*7c478bd9Sstevel@tonic-gate * don't add (or remove) device weight for pulsed interrupt 534*7c478bd9Sstevel@tonic-gate * sources. 535*7c478bd9Sstevel@tonic-gate */ 536*7c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_intr_lock); 537*7c478bd9Sstevel@tonic-gate cpu_id = intr_dist_cpuid(); 538*7c478bd9Sstevel@tonic-gate *map_reg_addr = ib_get_map_reg(mondo, cpu_id); 539*7c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_intr_lock); 540*7c478bd9Sstevel@tonic-gate *map_reg_addr; /* flush previous write */ 541*7c478bd9Sstevel@tonic-gate goto done; 542*7c478bd9Sstevel@tonic-gate } 543*7c478bd9Sstevel@tonic-gate 544*7c478bd9Sstevel@tonic-gate if ((mondo = pci_xlate_intr(dip, rdip, pci_p->pci_ib_p, ino)) == 0) 545*7c478bd9Sstevel@tonic-gate goto fail1; 546*7c478bd9Sstevel@tonic-gate 547*7c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(mondo); 548*7c478bd9Sstevel@tonic-gate 549*7c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 550*7c478bd9Sstevel@tonic-gate ih_p = ib_alloc_ih(rdip, hdlp->ih_inum, 551*7c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 552*7c478bd9Sstevel@tonic-gate if (map_pcidev_cfg_reg(dip, rdip, &ih_p->ih_config_handle)) 553*7c478bd9Sstevel@tonic-gate goto fail2; 554*7c478bd9Sstevel@tonic-gate 555*7c478bd9Sstevel@tonic-gate if (ino_p = ib_locate_ino(ib_p, ino)) { /* sharing ino */ 556*7c478bd9Sstevel@tonic-gate uint32_t intr_index = hdlp->ih_inum; 557*7c478bd9Sstevel@tonic-gate if (ib_ino_locate_intr(ino_p, rdip, intr_index)) { 558*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_A_INTX, dip, "dup intr #%d\n", intr_index); 559*7c478bd9Sstevel@tonic-gate goto fail3; 560*7c478bd9Sstevel@tonic-gate } 561*7c478bd9Sstevel@tonic-gate 562*7c478bd9Sstevel@tonic-gate /* add weight to the cpu that we are already targeting */ 563*7c478bd9Sstevel@tonic-gate cpu_id = ino_p->ino_cpuid; 564*7c478bd9Sstevel@tonic-gate weight = pci_class_to_intr_weight(rdip); 565*7c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(cpu_id, rdip, weight); 566*7c478bd9Sstevel@tonic-gate 567*7c478bd9Sstevel@tonic-gate ib_ino_add_intr(pci_p, ino_p, ih_p); 568*7c478bd9Sstevel@tonic-gate goto ino_done; 569*7c478bd9Sstevel@tonic-gate } 570*7c478bd9Sstevel@tonic-gate 571*7c478bd9Sstevel@tonic-gate ino_p = ib_new_ino(ib_p, ino, ih_p); 572*7c478bd9Sstevel@tonic-gate 573*7c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 574*7c478bd9Sstevel@tonic-gate hdlp->ih_pri = pci_class_to_pil(rdip); 575*7c478bd9Sstevel@tonic-gate 576*7c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 577*7c478bd9Sstevel@tonic-gate 578*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_A_INTX, dip, "pci_add_intr: pil=0x%x mondo=0x%x\n", 579*7c478bd9Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 580*7c478bd9Sstevel@tonic-gate 581*7c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 582*7c478bd9Sstevel@tonic-gate (ddi_intr_handler_t *)pci_intr_wrapper, (caddr_t)ino_p, NULL); 583*7c478bd9Sstevel@tonic-gate 584*7c478bd9Sstevel@tonic-gate ret = i_ddi_add_ivintr(hdlp); 585*7c478bd9Sstevel@tonic-gate 586*7c478bd9Sstevel@tonic-gate /* 587*7c478bd9Sstevel@tonic-gate * Restore original interrupt handler 588*7c478bd9Sstevel@tonic-gate * and arguments in interrupt handle. 589*7c478bd9Sstevel@tonic-gate */ 590*7c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 591*7c478bd9Sstevel@tonic-gate ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 592*7c478bd9Sstevel@tonic-gate 593*7c478bd9Sstevel@tonic-gate if (ret != DDI_SUCCESS) 594*7c478bd9Sstevel@tonic-gate goto fail4; 595*7c478bd9Sstevel@tonic-gate 596*7c478bd9Sstevel@tonic-gate /* Save the pil for this ino */ 597*7c478bd9Sstevel@tonic-gate ino_p->ino_pil = hdlp->ih_pri; 598*7c478bd9Sstevel@tonic-gate 599*7c478bd9Sstevel@tonic-gate /* clear and enable interrupt */ 600*7c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); 601*7c478bd9Sstevel@tonic-gate 602*7c478bd9Sstevel@tonic-gate /* select cpu and compute weight, saving both for sharing and removal */ 603*7c478bd9Sstevel@tonic-gate cpu_id = pci_intr_dist_cpuid(ib_p, ino_p); 604*7c478bd9Sstevel@tonic-gate ino_p->ino_cpuid = cpu_id; 605*7c478bd9Sstevel@tonic-gate ino_p->ino_established = 1; 606*7c478bd9Sstevel@tonic-gate weight = pci_class_to_intr_weight(rdip); 607*7c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(cpu_id, rdip, weight); 608*7c478bd9Sstevel@tonic-gate 609*7c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 610*7c478bd9Sstevel@tonic-gate cpu_id = pc_translate_tgtid(cb_p->cb_ittrans_cookie, cpu_id, 611*7c478bd9Sstevel@tonic-gate IB_GET_MAPREG_INO(ino)); 612*7c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 613*7c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg = ib_get_map_reg(mondo, cpu_id); 614*7c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg; 615*7c478bd9Sstevel@tonic-gate ino_done: 616*7c478bd9Sstevel@tonic-gate ih_p->ih_ino_p = ino_p; 617*7c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp) 618*7c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 619*7c478bd9Sstevel@tonic-gate ib_ino_map_reg_share(ib_p, ino, ino_p); 620*7c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 621*7c478bd9Sstevel@tonic-gate done: 622*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_A_INTX, dip, "done! Interrupt 0x%x pil=%x\n", 623*7c478bd9Sstevel@tonic-gate hdlp->ih_vector, hdlp->ih_pri); 624*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 625*7c478bd9Sstevel@tonic-gate fail4: 626*7c478bd9Sstevel@tonic-gate ib_delete_ino(ib_p, ino_p); 627*7c478bd9Sstevel@tonic-gate fail3: 628*7c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 629*7c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 630*7c478bd9Sstevel@tonic-gate fail2: 631*7c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 632*7c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (ih_t)); 633*7c478bd9Sstevel@tonic-gate fail1: 634*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_A_INTX, dip, "Failed! Interrupt 0x%x pil=%x\n", 635*7c478bd9Sstevel@tonic-gate hdlp->ih_vector, hdlp->ih_pri); 636*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 637*7c478bd9Sstevel@tonic-gate } 638*7c478bd9Sstevel@tonic-gate 639*7c478bd9Sstevel@tonic-gate int 640*7c478bd9Sstevel@tonic-gate pci_remove_intr(dev_info_t *dip, dev_info_t *rdip, ddi_intr_handle_impl_t *hdlp) 641*7c478bd9Sstevel@tonic-gate { 642*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 643*7c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 644*7c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 645*7c478bd9Sstevel@tonic-gate ib_ino_t ino; 646*7c478bd9Sstevel@tonic-gate ib_mondo_t mondo; 647*7c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p; /* non-pulse only */ 648*7c478bd9Sstevel@tonic-gate ih_t *ih_p; /* non-pulse only */ 649*7c478bd9Sstevel@tonic-gate 650*7c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(hdlp->ih_vector); 651*7c478bd9Sstevel@tonic-gate 652*7c478bd9Sstevel@tonic-gate DEBUG3(DBG_R_INTX, dip, "pci_rem_intr: rdip=%s%d ino=%x\n", 653*7c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 654*7c478bd9Sstevel@tonic-gate 655*7c478bd9Sstevel@tonic-gate if (hdlp->ih_vector & PCI_PULSE_INO) { /* pulse interrupt */ 656*7c478bd9Sstevel@tonic-gate volatile uint64_t *map_reg_addr; 657*7c478bd9Sstevel@tonic-gate 658*7c478bd9Sstevel@tonic-gate /* 659*7c478bd9Sstevel@tonic-gate * No weight was added by pci_add_intr for PCI_PULSE_INO 660*7c478bd9Sstevel@tonic-gate * because it is difficult to determine cpuid here. 661*7c478bd9Sstevel@tonic-gate */ 662*7c478bd9Sstevel@tonic-gate map_reg_addr = ib_intr_map_reg_addr(ib_p, ino); 663*7c478bd9Sstevel@tonic-gate IB_INO_INTR_RESET(map_reg_addr); /* disable intr */ 664*7c478bd9Sstevel@tonic-gate *map_reg_addr; 665*7c478bd9Sstevel@tonic-gate 666*7c478bd9Sstevel@tonic-gate mondo = pci_xlate_intr(dip, rdip, ib_p, ino); 667*7c478bd9Sstevel@tonic-gate if (mondo == 0) { 668*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_R_INTX, dip, 669*7c478bd9Sstevel@tonic-gate "can't get mondo for ino %x\n", ino); 670*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 671*7c478bd9Sstevel@tonic-gate } 672*7c478bd9Sstevel@tonic-gate 673*7c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 674*7c478bd9Sstevel@tonic-gate hdlp->ih_pri = pci_class_to_pil(rdip); 675*7c478bd9Sstevel@tonic-gate 676*7c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 677*7c478bd9Sstevel@tonic-gate 678*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_R_INTX, dip, "pci_rem_intr: pil=0x%x mondo=0x%x\n", 679*7c478bd9Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 680*7c478bd9Sstevel@tonic-gate 681*7c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 682*7c478bd9Sstevel@tonic-gate 683*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_R_INTX, dip, "pulse success mondo=%x reg=%p\n", 684*7c478bd9Sstevel@tonic-gate mondo, map_reg_addr); 685*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 686*7c478bd9Sstevel@tonic-gate } 687*7c478bd9Sstevel@tonic-gate 688*7c478bd9Sstevel@tonic-gate /* Translate the interrupt property */ 689*7c478bd9Sstevel@tonic-gate mondo = pci_xlate_intr(dip, rdip, pci_p->pci_ib_p, ino); 690*7c478bd9Sstevel@tonic-gate if (mondo == 0) { 691*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_R_INTX, dip, "can't get mondo for ino %x\n", ino); 692*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 693*7c478bd9Sstevel@tonic-gate } 694*7c478bd9Sstevel@tonic-gate ino = IB_MONDO_TO_INO(mondo); 695*7c478bd9Sstevel@tonic-gate 696*7c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 697*7c478bd9Sstevel@tonic-gate ino_p = ib_locate_ino(ib_p, ino); 698*7c478bd9Sstevel@tonic-gate if (!ino_p) { 699*7c478bd9Sstevel@tonic-gate int r = cb_remove_xintr(pci_p, dip, rdip, ino, mondo); 700*7c478bd9Sstevel@tonic-gate if (r != DDI_SUCCESS) 701*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d-xintr: ino %x is invalid", 702*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), ino); 703*7c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 704*7c478bd9Sstevel@tonic-gate return (r); 705*7c478bd9Sstevel@tonic-gate } 706*7c478bd9Sstevel@tonic-gate 707*7c478bd9Sstevel@tonic-gate ih_p = ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum); 708*7c478bd9Sstevel@tonic-gate ib_ino_rem_intr(pci_p, ino_p, ih_p); 709*7c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 710*7c478bd9Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) { 711*7c478bd9Sstevel@tonic-gate IB_INO_INTR_PEND(ib_clear_intr_reg_addr(ib_p, ino)); 712*7c478bd9Sstevel@tonic-gate hdlp->ih_vector = CB_MONDO_TO_XMONDO(cb_p, mondo); 713*7c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 714*7c478bd9Sstevel@tonic-gate hdlp->ih_pri = pci_class_to_pil(rdip); 715*7c478bd9Sstevel@tonic-gate 716*7c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 717*7c478bd9Sstevel@tonic-gate ib_delete_ino(ib_p, ino_p); 718*7c478bd9Sstevel@tonic-gate } 719*7c478bd9Sstevel@tonic-gate 720*7c478bd9Sstevel@tonic-gate /* re-enable interrupt only if mapping register still shared */ 721*7c478bd9Sstevel@tonic-gate if (ib_ino_map_reg_unshare(ib_p, ino, ino_p)) { 722*7c478bd9Sstevel@tonic-gate IB_INO_INTR_ON(ino_p->ino_map_reg); 723*7c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg; 724*7c478bd9Sstevel@tonic-gate } 725*7c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 726*7c478bd9Sstevel@tonic-gate 727*7c478bd9Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) 728*7c478bd9Sstevel@tonic-gate kmem_free(ino_p, sizeof (ib_ino_info_t)); 729*7c478bd9Sstevel@tonic-gate 730*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_R_INTX, dip, "success! mondo=%x\n", mondo); 731*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 732*7c478bd9Sstevel@tonic-gate } 733*7c478bd9Sstevel@tonic-gate 734*7c478bd9Sstevel@tonic-gate /* 735*7c478bd9Sstevel@tonic-gate * free the pci_inos array allocated during pci_intr_setup. the actual 736*7c478bd9Sstevel@tonic-gate * interrupts are torn down by their respective block destroy routines: 737*7c478bd9Sstevel@tonic-gate * cb_destroy, pbm_destroy, and ib_destroy. 738*7c478bd9Sstevel@tonic-gate */ 739*7c478bd9Sstevel@tonic-gate void 740*7c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_t *pci_p) 741*7c478bd9Sstevel@tonic-gate { 742*7c478bd9Sstevel@tonic-gate kmem_free(pci_p->pci_inos, pci_p->pci_inos_len); 743*7c478bd9Sstevel@tonic-gate pci_p->pci_inos = NULL; 744*7c478bd9Sstevel@tonic-gate pci_p->pci_inos_len = 0; 745*7c478bd9Sstevel@tonic-gate } 746