xref: /illumos-gate/usr/src/uts/sun4u/io/pci/pci_ib.c (revision 2a1fd0ff)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5b0fc0e77Sgovinda  * Common Development and Distribution License (the "License").
6b0fc0e77Sgovinda  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
2209b1eac2SEvan Yan  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
25*2a1fd0ffSPeter Tribble /*
26*2a1fd0ffSPeter Tribble  * Copyright 2019 Peter Tribble.
27*2a1fd0ffSPeter Tribble  */
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate /*
307c478bd9Sstevel@tonic-gate  * PCI Interrupt Block (RISCx) implementation
317c478bd9Sstevel@tonic-gate  *	initialization
327c478bd9Sstevel@tonic-gate  *	interrupt enable/disable/clear and mapping register manipulation
337c478bd9Sstevel@tonic-gate  */
347c478bd9Sstevel@tonic-gate 
357c478bd9Sstevel@tonic-gate #include <sys/types.h>
367c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
377c478bd9Sstevel@tonic-gate #include <sys/async.h>
387c478bd9Sstevel@tonic-gate #include <sys/systm.h>		/* panicstr */
397c478bd9Sstevel@tonic-gate #include <sys/spl.h>
407c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
417c478bd9Sstevel@tonic-gate #include <sys/machsystm.h>	/* intr_dist_add */
427c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h>
437c478bd9Sstevel@tonic-gate #include <sys/clock.h>
447c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h>
457c478bd9Sstevel@tonic-gate #include <sys/pci/pci_obj.h>
467c478bd9Sstevel@tonic-gate 
477c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/
487c478bd9Sstevel@tonic-gate static uint_t ib_intr_reset(void *arg);
497c478bd9Sstevel@tonic-gate 
507c478bd9Sstevel@tonic-gate void
ib_create(pci_t * pci_p)517c478bd9Sstevel@tonic-gate ib_create(pci_t *pci_p)
527c478bd9Sstevel@tonic-gate {
537c478bd9Sstevel@tonic-gate 	dev_info_t *dip = pci_p->pci_dip;
547c478bd9Sstevel@tonic-gate 	ib_t *ib_p;
557c478bd9Sstevel@tonic-gate 	uintptr_t a;
567c478bd9Sstevel@tonic-gate 	int i;
577c478bd9Sstevel@tonic-gate 
587c478bd9Sstevel@tonic-gate 	/*
597c478bd9Sstevel@tonic-gate 	 * Allocate interrupt block state structure and link it to
607c478bd9Sstevel@tonic-gate 	 * the pci state structure.
617c478bd9Sstevel@tonic-gate 	 */
627c478bd9Sstevel@tonic-gate 	ib_p = kmem_zalloc(sizeof (ib_t), KM_SLEEP);
637c478bd9Sstevel@tonic-gate 	pci_p->pci_ib_p = ib_p;
647c478bd9Sstevel@tonic-gate 	ib_p->ib_pci_p = pci_p;
657c478bd9Sstevel@tonic-gate 
667c478bd9Sstevel@tonic-gate 	a = pci_ib_setup(ib_p);
677c478bd9Sstevel@tonic-gate 
687c478bd9Sstevel@tonic-gate 	/*
697c478bd9Sstevel@tonic-gate 	 * Determine virtual addresses of interrupt mapping, clear and diag
707c478bd9Sstevel@tonic-gate 	 * registers that have common offsets.
717c478bd9Sstevel@tonic-gate 	 */
727c478bd9Sstevel@tonic-gate 	ib_p->ib_slot_clear_intr_regs =
73f0d69850Srameshc 	    a + COMMON_IB_SLOT_CLEAR_INTR_REG_OFFSET;
747c478bd9Sstevel@tonic-gate 	ib_p->ib_intr_retry_timer_reg =
75f0d69850Srameshc 	    (uint64_t *)(a + COMMON_IB_INTR_RETRY_TIMER_OFFSET);
767c478bd9Sstevel@tonic-gate 	ib_p->ib_slot_intr_state_diag_reg =
77f0d69850Srameshc 	    (uint64_t *)(a + COMMON_IB_SLOT_INTR_STATE_DIAG_REG);
787c478bd9Sstevel@tonic-gate 	ib_p->ib_obio_intr_state_diag_reg =
79f0d69850Srameshc 	    (uint64_t *)(a + COMMON_IB_OBIO_INTR_STATE_DIAG_REG);
807c478bd9Sstevel@tonic-gate 
817c478bd9Sstevel@tonic-gate 	if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) {
827c478bd9Sstevel@tonic-gate 		ib_p->ib_upa_imr[0] = (volatile uint64_t *)
83f0d69850Srameshc 		    (a + COMMON_IB_UPA0_INTR_MAP_REG_OFFSET);
847c478bd9Sstevel@tonic-gate 		ib_p->ib_upa_imr[1] = (volatile uint64_t *)
85f0d69850Srameshc 		    (a + COMMON_IB_UPA1_INTR_MAP_REG_OFFSET);
867c478bd9Sstevel@tonic-gate 	}
877c478bd9Sstevel@tonic-gate 
887c478bd9Sstevel@tonic-gate 	DEBUG2(DBG_ATTACH, dip, "ib_create: slot_imr=%x, slot_cir=%x\n",
89f0d69850Srameshc 	    ib_p->ib_slot_intr_map_regs, ib_p->ib_obio_intr_map_regs);
907c478bd9Sstevel@tonic-gate 	DEBUG2(DBG_ATTACH, dip, "ib_create: obio_imr=%x, obio_cir=%x\n",
91f0d69850Srameshc 	    ib_p->ib_slot_clear_intr_regs, ib_p->ib_obio_clear_intr_regs);
927c478bd9Sstevel@tonic-gate 	DEBUG2(DBG_ATTACH, dip, "ib_create: upa0_imr=%x, upa1_imr=%x\n",
93f0d69850Srameshc 	    ib_p->ib_upa_imr[0], ib_p->ib_upa_imr[1]);
947c478bd9Sstevel@tonic-gate 	DEBUG3(DBG_ATTACH, dip,
95f0d69850Srameshc 	    "ib_create: retry_timer=%x, obio_diag=%x slot_diag=%x\n",
96f0d69850Srameshc 	    ib_p->ib_intr_retry_timer_reg,
97f0d69850Srameshc 	    ib_p->ib_obio_intr_state_diag_reg,
98f0d69850Srameshc 	    ib_p->ib_slot_intr_state_diag_reg);
997c478bd9Sstevel@tonic-gate 
1007c478bd9Sstevel@tonic-gate 	ib_p->ib_ino_lst = (ib_ino_info_t *)NULL;
1017c478bd9Sstevel@tonic-gate 	mutex_init(&ib_p->ib_intr_lock, NULL, MUTEX_DRIVER, NULL);
1027c478bd9Sstevel@tonic-gate 	mutex_init(&ib_p->ib_ino_lst_mutex, NULL, MUTEX_DRIVER, NULL);
1037c478bd9Sstevel@tonic-gate 
1047c478bd9Sstevel@tonic-gate 	DEBUG1(DBG_ATTACH, dip, "ib_create: numproxy=%x\n",
105f0d69850Srameshc 	    pci_p->pci_numproxy);
1067c478bd9Sstevel@tonic-gate 	for (i = 1; i <= pci_p->pci_numproxy; i++) {
1077c478bd9Sstevel@tonic-gate 		set_intr_mapping_reg(pci_p->pci_id,
108f0d69850Srameshc 		    (uint64_t *)ib_p->ib_upa_imr[i - 1], i);
1097c478bd9Sstevel@tonic-gate 	}
1107c478bd9Sstevel@tonic-gate 
1117c478bd9Sstevel@tonic-gate 	ib_configure(ib_p);
1127c478bd9Sstevel@tonic-gate 	bus_func_register(BF_TYPE_RESINTR, ib_intr_reset, ib_p);
1137c478bd9Sstevel@tonic-gate }
1147c478bd9Sstevel@tonic-gate 
1157c478bd9Sstevel@tonic-gate void
ib_destroy(pci_t * pci_p)1167c478bd9Sstevel@tonic-gate ib_destroy(pci_t *pci_p)
1177c478bd9Sstevel@tonic-gate {
1187c478bd9Sstevel@tonic-gate 	ib_t *ib_p = pci_p->pci_ib_p;
1197c478bd9Sstevel@tonic-gate 	dev_info_t *dip = pci_p->pci_dip;
1207c478bd9Sstevel@tonic-gate 
1217c478bd9Sstevel@tonic-gate 	DEBUG0(DBG_IB, dip, "ib_destroy\n");
1227c478bd9Sstevel@tonic-gate 	bus_func_unregister(BF_TYPE_RESINTR, ib_intr_reset, ib_p);
1237c478bd9Sstevel@tonic-gate 
1247c478bd9Sstevel@tonic-gate 	intr_dist_rem_weighted(ib_intr_dist_all, ib_p);
1257c478bd9Sstevel@tonic-gate 	mutex_destroy(&ib_p->ib_ino_lst_mutex);
1267c478bd9Sstevel@tonic-gate 	mutex_destroy(&ib_p->ib_intr_lock);
1277c478bd9Sstevel@tonic-gate 
1287c478bd9Sstevel@tonic-gate 	ib_free_ino_all(ib_p);
1297c478bd9Sstevel@tonic-gate 
1307c478bd9Sstevel@tonic-gate 	kmem_free(ib_p, sizeof (ib_t));
1317c478bd9Sstevel@tonic-gate 	pci_p->pci_ib_p = NULL;
1327c478bd9Sstevel@tonic-gate }
1337c478bd9Sstevel@tonic-gate 
1347c478bd9Sstevel@tonic-gate void
ib_configure(ib_t * ib_p)1357c478bd9Sstevel@tonic-gate ib_configure(ib_t *ib_p)
1367c478bd9Sstevel@tonic-gate {
1377c478bd9Sstevel@tonic-gate 	/* XXX could be different between psycho and schizo */
1387c478bd9Sstevel@tonic-gate 	*ib_p->ib_intr_retry_timer_reg = pci_intr_retry_intv;
1397c478bd9Sstevel@tonic-gate }
1407c478bd9Sstevel@tonic-gate 
1417c478bd9Sstevel@tonic-gate /*
1427c478bd9Sstevel@tonic-gate  * can only used for psycho internal interrupts thermal, power,
1437c478bd9Sstevel@tonic-gate  * ue, ce, pbm
1447c478bd9Sstevel@tonic-gate  */
1457c478bd9Sstevel@tonic-gate void
ib_intr_enable(pci_t * pci_p,ib_ino_t ino)1467c478bd9Sstevel@tonic-gate ib_intr_enable(pci_t *pci_p, ib_ino_t ino)
1477c478bd9Sstevel@tonic-gate {
1487c478bd9Sstevel@tonic-gate 	ib_t *ib_p = pci_p->pci_ib_p;
1497c478bd9Sstevel@tonic-gate 	ib_mondo_t mondo = IB_INO_TO_MONDO(ib_p, ino);
1507c478bd9Sstevel@tonic-gate 	volatile uint64_t *imr_p = ib_intr_map_reg_addr(ib_p, ino);
1517c478bd9Sstevel@tonic-gate 	uint_t cpu_id;
1527c478bd9Sstevel@tonic-gate 
1537c478bd9Sstevel@tonic-gate 	/*
1547c478bd9Sstevel@tonic-gate 	 * Determine the cpu for the interrupt.
1557c478bd9Sstevel@tonic-gate 	 */
1567c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_intr_lock);
1577c478bd9Sstevel@tonic-gate 	cpu_id = intr_dist_cpuid();
1587c478bd9Sstevel@tonic-gate 	DEBUG2(DBG_IB, pci_p->pci_dip,
159f0d69850Srameshc 	    "ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id);
1607c478bd9Sstevel@tonic-gate 
1617c478bd9Sstevel@tonic-gate 	*imr_p = ib_get_map_reg(mondo, cpu_id);
1627c478bd9Sstevel@tonic-gate 	IB_INO_INTR_CLEAR(ib_clear_intr_reg_addr(ib_p, ino));
1637c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_intr_lock);
1647c478bd9Sstevel@tonic-gate }
1657c478bd9Sstevel@tonic-gate 
1667c478bd9Sstevel@tonic-gate /*
1677c478bd9Sstevel@tonic-gate  * Disable the interrupt via its interrupt mapping register.
1687c478bd9Sstevel@tonic-gate  * Can only be used for internal interrupts: thermal, power, ue, ce, pbm.
1697c478bd9Sstevel@tonic-gate  * If called under interrupt context, wait should be set to 0
1707c478bd9Sstevel@tonic-gate  */
1717c478bd9Sstevel@tonic-gate void
ib_intr_disable(ib_t * ib_p,ib_ino_t ino,int wait)1727c478bd9Sstevel@tonic-gate ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait)
1737c478bd9Sstevel@tonic-gate {
1747c478bd9Sstevel@tonic-gate 	volatile uint64_t *imr_p = ib_intr_map_reg_addr(ib_p, ino);
1757c478bd9Sstevel@tonic-gate 	volatile uint64_t *state_reg_p = IB_INO_INTR_STATE_REG(ib_p, ino);
1767c478bd9Sstevel@tonic-gate 	hrtime_t start_time;
1777c478bd9Sstevel@tonic-gate 
1787c478bd9Sstevel@tonic-gate 	/* disable the interrupt */
1797c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_intr_lock);
1807c478bd9Sstevel@tonic-gate 	IB_INO_INTR_OFF(imr_p);
1817c478bd9Sstevel@tonic-gate 	*imr_p;	/* flush previous write */
1827c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_intr_lock);
1837c478bd9Sstevel@tonic-gate 
1847c478bd9Sstevel@tonic-gate 	if (!wait)
1857c478bd9Sstevel@tonic-gate 		goto wait_done;
1867c478bd9Sstevel@tonic-gate 
1877c478bd9Sstevel@tonic-gate 	start_time = gethrtime();
1887c478bd9Sstevel@tonic-gate 	/* busy wait if there is interrupt being processed */
1897c478bd9Sstevel@tonic-gate 	while (IB_INO_INTR_PENDING(state_reg_p, ino) && !panicstr) {
1907c478bd9Sstevel@tonic-gate 		if (gethrtime() - start_time > pci_intrpend_timeout) {
1917c478bd9Sstevel@tonic-gate 			pbm_t *pbm_p = ib_p->ib_pci_p->pci_pbm_p;
1927c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s:%s: ib_intr_disable timeout %x",
193f0d69850Srameshc 			    pbm_p->pbm_nameinst_str,
194f0d69850Srameshc 			    pbm_p->pbm_nameaddr_str, ino);
1957c478bd9Sstevel@tonic-gate 				break;
1967c478bd9Sstevel@tonic-gate 		}
1977c478bd9Sstevel@tonic-gate 	}
1987c478bd9Sstevel@tonic-gate wait_done:
1997c478bd9Sstevel@tonic-gate 	IB_INO_INTR_PEND(ib_clear_intr_reg_addr(ib_p, ino));
2007c478bd9Sstevel@tonic-gate }
2017c478bd9Sstevel@tonic-gate 
2027c478bd9Sstevel@tonic-gate /* can only used for psycho internal interrupts thermal, power, ue, ce, pbm */
2037c478bd9Sstevel@tonic-gate void
ib_nintr_clear(ib_t * ib_p,ib_ino_t ino)2047c478bd9Sstevel@tonic-gate ib_nintr_clear(ib_t *ib_p, ib_ino_t ino)
2057c478bd9Sstevel@tonic-gate {
2067c478bd9Sstevel@tonic-gate 	uint64_t *clr_reg = ib_clear_intr_reg_addr(ib_p, ino);
2077c478bd9Sstevel@tonic-gate 	IB_INO_INTR_CLEAR(clr_reg);
2087c478bd9Sstevel@tonic-gate }
2097c478bd9Sstevel@tonic-gate 
2107c478bd9Sstevel@tonic-gate /*
2117c478bd9Sstevel@tonic-gate  * distribute PBM and UPA interrupts. ino is set to 0 by caller if we
2127c478bd9Sstevel@tonic-gate  * are dealing with UPA interrupts (without inos).
2137c478bd9Sstevel@tonic-gate  */
2147c478bd9Sstevel@tonic-gate void
ib_intr_dist_nintr(ib_t * ib_p,ib_ino_t ino,volatile uint64_t * imr_p)2157c478bd9Sstevel@tonic-gate ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino, volatile uint64_t *imr_p)
2167c478bd9Sstevel@tonic-gate {
2177c478bd9Sstevel@tonic-gate 	volatile uint64_t imr = *imr_p;
2187c478bd9Sstevel@tonic-gate 	uint32_t cpu_id;
2197c478bd9Sstevel@tonic-gate 
2207c478bd9Sstevel@tonic-gate 	if (!IB_INO_INTR_ISON(imr))
2217c478bd9Sstevel@tonic-gate 		return;
2227c478bd9Sstevel@tonic-gate 
2237c478bd9Sstevel@tonic-gate 	cpu_id = intr_dist_cpuid();
2247c478bd9Sstevel@tonic-gate 
2257c478bd9Sstevel@tonic-gate 	if (ib_map_reg_get_cpu(*imr_p) == cpu_id)
2267c478bd9Sstevel@tonic-gate 		return;
2277c478bd9Sstevel@tonic-gate 
2287c478bd9Sstevel@tonic-gate 	*imr_p = ib_get_map_reg(IB_IMR2MONDO(imr), cpu_id);
2297c478bd9Sstevel@tonic-gate 	imr = *imr_p;	/* flush previous write */
2307c478bd9Sstevel@tonic-gate }
2317c478bd9Sstevel@tonic-gate 
2327851eb82Sschwartz /*
2337851eb82Sschwartz  * Converts into nsec, ticks logged with a given CPU.  Adds nsec to ih.
2347851eb82Sschwartz  */
2357851eb82Sschwartz /*ARGSUSED*/
2367851eb82Sschwartz void
ib_cpu_ticks_to_ih_nsec(ib_t * ib_p,ih_t * ih_p,uint32_t cpu_id)2377851eb82Sschwartz ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id)
2387851eb82Sschwartz {
2397851eb82Sschwartz 	extern kmutex_t pciintr_ks_template_lock;
2407851eb82Sschwartz 	hrtime_t ticks;
2417851eb82Sschwartz 
2427851eb82Sschwartz 	/*
2437851eb82Sschwartz 	 * Because we are updating two fields in ih_t we must lock
2447851eb82Sschwartz 	 * pciintr_ks_template_lock to prevent someone from reading the
2457851eb82Sschwartz 	 * kstats after we set ih_ticks to 0 and before we increment
2467851eb82Sschwartz 	 * ih_nsec to compensate.
2477851eb82Sschwartz 	 *
2487851eb82Sschwartz 	 * We must also protect against the interrupt arriving and incrementing
2497851eb82Sschwartz 	 * ih_ticks between the time we read it and when we reset it to 0.
2507851eb82Sschwartz 	 * To do this we use atomic_swap.
2517851eb82Sschwartz 	 */
2527851eb82Sschwartz 
2537851eb82Sschwartz 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
2547851eb82Sschwartz 
2557851eb82Sschwartz 	mutex_enter(&pciintr_ks_template_lock);
2567851eb82Sschwartz 	ticks = atomic_swap_64(&ih_p->ih_ticks, 0);
2577851eb82Sschwartz 	ih_p->ih_nsec += (uint64_t)tick2ns(ticks, cpu_id);
2587851eb82Sschwartz 	mutex_exit(&pciintr_ks_template_lock);
2597851eb82Sschwartz }
2607851eb82Sschwartz 
2617c478bd9Sstevel@tonic-gate static void
ib_intr_dist(ib_t * ib_p,ib_ino_info_t * ino_p)2627c478bd9Sstevel@tonic-gate ib_intr_dist(ib_t *ib_p, ib_ino_info_t *ino_p)
2637c478bd9Sstevel@tonic-gate {
2647c478bd9Sstevel@tonic-gate 	uint32_t cpu_id = ino_p->ino_cpuid;
2657c478bd9Sstevel@tonic-gate 	ib_ino_t ino = ino_p->ino_ino;
2667c478bd9Sstevel@tonic-gate 	volatile uint64_t imr, *imr_p, *state_reg;
2677c478bd9Sstevel@tonic-gate 	hrtime_t start_time;
2687c478bd9Sstevel@tonic-gate 
2697c478bd9Sstevel@tonic-gate 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
2707c478bd9Sstevel@tonic-gate 	imr_p = ib_intr_map_reg_addr(ib_p, ino);
2717c478bd9Sstevel@tonic-gate 	state_reg = IB_INO_INTR_STATE_REG(ib_p, ino);
2727c478bd9Sstevel@tonic-gate 
2737c478bd9Sstevel@tonic-gate 	if (ib_map_reg_get_cpu(*imr_p) == cpu_id) /* same cpu, no reprog */
2747c478bd9Sstevel@tonic-gate 		return;
2757c478bd9Sstevel@tonic-gate 
2767c478bd9Sstevel@tonic-gate 	/* disable interrupt, this could disrupt devices sharing our slot */
2777c478bd9Sstevel@tonic-gate 	IB_INO_INTR_OFF(imr_p);
2787c478bd9Sstevel@tonic-gate 	imr = *imr_p;	/* flush previous write */
2797c478bd9Sstevel@tonic-gate 
2807c478bd9Sstevel@tonic-gate 	/* busy wait if there is interrupt being processed */
2817c478bd9Sstevel@tonic-gate 	start_time = gethrtime();
2827c478bd9Sstevel@tonic-gate 	while (IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
2837c478bd9Sstevel@tonic-gate 		if (gethrtime() - start_time > pci_intrpend_timeout) {
2847c478bd9Sstevel@tonic-gate 			pbm_t *pbm_p = ib_p->ib_pci_p->pci_pbm_p;
2857c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s:%s: ib_intr_dist(%p,%x) timeout",
286f0d69850Srameshc 			    pbm_p->pbm_nameinst_str,
287f0d69850Srameshc 			    pbm_p->pbm_nameaddr_str,
288f0d69850Srameshc 			    imr_p, IB_INO_TO_MONDO(ib_p, ino));
2897c478bd9Sstevel@tonic-gate 			break;
2907c478bd9Sstevel@tonic-gate 		}
2917c478bd9Sstevel@tonic-gate 	}
2927c478bd9Sstevel@tonic-gate 	*imr_p = ib_get_map_reg(IB_IMR2MONDO(imr), cpu_id);
2937c478bd9Sstevel@tonic-gate 	imr = *imr_p;	/* flush previous write */
2947c478bd9Sstevel@tonic-gate }
2957c478bd9Sstevel@tonic-gate 
2967c478bd9Sstevel@tonic-gate /*
2977c478bd9Sstevel@tonic-gate  * Redistribute interrupts of the specified weight. The first call has a weight
2987c478bd9Sstevel@tonic-gate  * of weight_max, which can be used to trigger initialization for
2997c478bd9Sstevel@tonic-gate  * redistribution. The inos with weight [weight_max, inf.) should be processed
3007c478bd9Sstevel@tonic-gate  * on the "weight == weight_max" call.  This first call is followed by calls
3017c478bd9Sstevel@tonic-gate  * of decreasing weights, inos of that weight should be processed.  The final
3027c478bd9Sstevel@tonic-gate  * call specifies a weight of zero, this can be used to trigger processing of
3037c478bd9Sstevel@tonic-gate  * stragglers.
3047c478bd9Sstevel@tonic-gate  */
3057c478bd9Sstevel@tonic-gate void
ib_intr_dist_all(void * arg,int32_t weight_max,int32_t weight)3067c478bd9Sstevel@tonic-gate ib_intr_dist_all(void *arg, int32_t weight_max, int32_t weight)
3077c478bd9Sstevel@tonic-gate {
3087c478bd9Sstevel@tonic-gate 	ib_t *ib_p = (ib_t *)arg;
3097c478bd9Sstevel@tonic-gate 	pci_t *pci_p = ib_p->ib_pci_p;
3107c478bd9Sstevel@tonic-gate 	ib_ino_info_t *ino_p;
311b0fc0e77Sgovinda 	ib_ino_pil_t *ipil_p;
3127c478bd9Sstevel@tonic-gate 	ih_t *ih_lst;
3137c478bd9Sstevel@tonic-gate 	int32_t dweight;
3147c478bd9Sstevel@tonic-gate 	int i;
3157c478bd9Sstevel@tonic-gate 
3167c478bd9Sstevel@tonic-gate 	if (weight == 0) {
3177c478bd9Sstevel@tonic-gate 		mutex_enter(&ib_p->ib_intr_lock);
3187c478bd9Sstevel@tonic-gate 		if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) {
3197c478bd9Sstevel@tonic-gate 			for (i = 0; i < 2; i++)
3207c478bd9Sstevel@tonic-gate 				ib_intr_dist_nintr(ib_p, 0,
3217c478bd9Sstevel@tonic-gate 				    ib_p->ib_upa_imr[i]);
3227c478bd9Sstevel@tonic-gate 		}
3237c478bd9Sstevel@tonic-gate 		mutex_exit(&ib_p->ib_intr_lock);
3247c478bd9Sstevel@tonic-gate 	}
3257c478bd9Sstevel@tonic-gate 
3267c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
3277c478bd9Sstevel@tonic-gate 
3287c478bd9Sstevel@tonic-gate 	/* Perform special processing for first call of a redistribution. */
3297c478bd9Sstevel@tonic-gate 	if (weight == weight_max) {
330b0fc0e77Sgovinda 		for (ino_p = ib_p->ib_ino_lst; ino_p;
331b0fc0e77Sgovinda 		    ino_p = ino_p->ino_next_p) {
3327c478bd9Sstevel@tonic-gate 
3337c478bd9Sstevel@tonic-gate 			/*
3347c478bd9Sstevel@tonic-gate 			 * Clear ino_established of each ino on first call.
3357c478bd9Sstevel@tonic-gate 			 * The ino_established field may be used by a pci
3367c478bd9Sstevel@tonic-gate 			 * nexus driver's pci_intr_dist_cpuid implementation
3377c478bd9Sstevel@tonic-gate 			 * when detection of established pci slot-cpu binding
3387c478bd9Sstevel@tonic-gate 			 * for multi function pci cards.
3397c478bd9Sstevel@tonic-gate 			 */
3407c478bd9Sstevel@tonic-gate 			ino_p->ino_established = 0;
3417c478bd9Sstevel@tonic-gate 
3427c478bd9Sstevel@tonic-gate 			/*
3437c478bd9Sstevel@tonic-gate 			 * recompute the ino_intr_weight based on the device
3447c478bd9Sstevel@tonic-gate 			 * weight of all devinfo nodes sharing the ino (this
3457c478bd9Sstevel@tonic-gate 			 * will allow us to pick up new weights established by
3467c478bd9Sstevel@tonic-gate 			 * i_ddi_set_intr_weight()).
3477c478bd9Sstevel@tonic-gate 			 */
3487c478bd9Sstevel@tonic-gate 			ino_p->ino_intr_weight = 0;
349b0fc0e77Sgovinda 
350b0fc0e77Sgovinda 			for (ipil_p = ino_p->ino_ipil_p; ipil_p;
351b0fc0e77Sgovinda 			    ipil_p = ipil_p->ipil_next_p) {
352b0fc0e77Sgovinda 				for (i = 0, ih_lst = ipil_p->ipil_ih_head;
353b0fc0e77Sgovinda 				    i < ipil_p->ipil_ih_size; i++,
354b0fc0e77Sgovinda 				    ih_lst = ih_lst->ih_next) {
355b0fc0e77Sgovinda 					dweight = i_ddi_get_intr_weight
356b0fc0e77Sgovinda 					    (ih_lst->ih_dip);
357b0fc0e77Sgovinda 					if (dweight > 0)
358b0fc0e77Sgovinda 						ino_p->ino_intr_weight +=
359b0fc0e77Sgovinda 						    dweight;
360b0fc0e77Sgovinda 				}
3617c478bd9Sstevel@tonic-gate 			}
3627c478bd9Sstevel@tonic-gate 		}
3637c478bd9Sstevel@tonic-gate 	}
3647c478bd9Sstevel@tonic-gate 
365b0fc0e77Sgovinda 	for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) {
3667c478bd9Sstevel@tonic-gate 		uint32_t orig_cpuid;
3677c478bd9Sstevel@tonic-gate 
3687c478bd9Sstevel@tonic-gate 		/*
3697c478bd9Sstevel@tonic-gate 		 * Get the weight of the ino and determine if we are going to
3707c478bd9Sstevel@tonic-gate 		 * process call.  We wait until an ib_intr_dist_all call of
3717c478bd9Sstevel@tonic-gate 		 * the proper weight occurs to support redistribution of all
3727c478bd9Sstevel@tonic-gate 		 * heavy weighted interrupts first (across all nexus driver
3737c478bd9Sstevel@tonic-gate 		 * instances).  This is done to ensure optimal
3747c478bd9Sstevel@tonic-gate 		 * INTR_WEIGHTED_DIST behavior.
3757c478bd9Sstevel@tonic-gate 		 */
3767c478bd9Sstevel@tonic-gate 		if ((weight == ino_p->ino_intr_weight) ||
3777c478bd9Sstevel@tonic-gate 		    ((weight >= weight_max) &&
3787c478bd9Sstevel@tonic-gate 		    (ino_p->ino_intr_weight >= weight_max))) {
3797c478bd9Sstevel@tonic-gate 			/* select cpuid to target and mark ino established */
3807c478bd9Sstevel@tonic-gate 			orig_cpuid = ino_p->ino_cpuid;
3817c478bd9Sstevel@tonic-gate 			if (cpu[orig_cpuid] == NULL)
3827c478bd9Sstevel@tonic-gate 				orig_cpuid = CPU->cpu_id;
3837c478bd9Sstevel@tonic-gate 			ino_p->ino_cpuid = pci_intr_dist_cpuid(ib_p, ino_p);
3847c478bd9Sstevel@tonic-gate 			ino_p->ino_established = 1;
3857c478bd9Sstevel@tonic-gate 
3867c478bd9Sstevel@tonic-gate 			/* Add device weight of ino devinfos to targeted cpu. */
387b0fc0e77Sgovinda 			for (ipil_p = ino_p->ino_ipil_p; ipil_p;
388b0fc0e77Sgovinda 			    ipil_p = ipil_p->ipil_next_p) {
389b0fc0e77Sgovinda 				for (i = 0, ih_lst = ipil_p->ipil_ih_head;
390b0fc0e77Sgovinda 				    i < ipil_p->ipil_ih_size; i++,
391b0fc0e77Sgovinda 				    ih_lst = ih_lst->ih_next) {
392b0fc0e77Sgovinda 
393b0fc0e77Sgovinda 					dweight = i_ddi_get_intr_weight(
394b0fc0e77Sgovinda 					    ih_lst->ih_dip);
395b0fc0e77Sgovinda 					intr_dist_cpuid_add_device_weight(
396b0fc0e77Sgovinda 					    ino_p->ino_cpuid, ih_lst->ih_dip,
397b0fc0e77Sgovinda 					    dweight);
398b0fc0e77Sgovinda 
399b0fc0e77Sgovinda 					/*
400b0fc0e77Sgovinda 					 * Different cpus may have different
401b0fc0e77Sgovinda 					 * clock speeds. to account for this,
402b0fc0e77Sgovinda 					 * whenever an interrupt is moved to a
403b0fc0e77Sgovinda 					 * new CPU, we convert the accumulated
404b0fc0e77Sgovinda 					 * ticks into nsec, based upon the clock
405b0fc0e77Sgovinda 					 * rate of the prior CPU.
406b0fc0e77Sgovinda 					 *
407b0fc0e77Sgovinda 					 * It is possible that the prior CPU no
408b0fc0e77Sgovinda 					 * longer exists. In this case, fall
409b0fc0e77Sgovinda 					 * back to using this CPU's clock rate.
410b0fc0e77Sgovinda 					 *
411b0fc0e77Sgovinda 					 * Note that the value in ih_ticks has
412b0fc0e77Sgovinda 					 * already been corrected for any power
413b0fc0e77Sgovinda 					 * savings mode which might have been
414b0fc0e77Sgovinda 					 * in effect.
415b0fc0e77Sgovinda 					 */
416b0fc0e77Sgovinda 					ib_cpu_ticks_to_ih_nsec(ib_p, ih_lst,
417b0fc0e77Sgovinda 					    orig_cpuid);
418b0fc0e77Sgovinda 				}
4197c478bd9Sstevel@tonic-gate 			}
4207c478bd9Sstevel@tonic-gate 
4217c478bd9Sstevel@tonic-gate 			/* program the hardware */
4227c478bd9Sstevel@tonic-gate 			ib_intr_dist(ib_p, ino_p);
4237c478bd9Sstevel@tonic-gate 		}
4247c478bd9Sstevel@tonic-gate 	}
4257c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
4267c478bd9Sstevel@tonic-gate }
4277c478bd9Sstevel@tonic-gate 
4287c478bd9Sstevel@tonic-gate /*
4297c478bd9Sstevel@tonic-gate  * Reset interrupts to IDLE.  This function is called during
4307c478bd9Sstevel@tonic-gate  * panic handling after redistributing interrupts; it's needed to
4317c478bd9Sstevel@tonic-gate  * support dumping to network devices after 'sync' from OBP.
4327c478bd9Sstevel@tonic-gate  *
4337c478bd9Sstevel@tonic-gate  * N.B.  This routine runs in a context where all other threads
4347c478bd9Sstevel@tonic-gate  * are permanently suspended.
4357c478bd9Sstevel@tonic-gate  */
4367c478bd9Sstevel@tonic-gate static uint_t
ib_intr_reset(void * arg)4377c478bd9Sstevel@tonic-gate ib_intr_reset(void *arg)
4387c478bd9Sstevel@tonic-gate {
4397c478bd9Sstevel@tonic-gate 	ib_t *ib_p = (ib_t *)arg;
4407c478bd9Sstevel@tonic-gate 	ib_ino_t ino;
4417c478bd9Sstevel@tonic-gate 	uint64_t *clr_reg;
4427c478bd9Sstevel@tonic-gate 
4437c478bd9Sstevel@tonic-gate 	/*
4447c478bd9Sstevel@tonic-gate 	 * Note that we only actually care about interrupts that are
4457c478bd9Sstevel@tonic-gate 	 * potentially from network devices.
4467c478bd9Sstevel@tonic-gate 	 */
4477c478bd9Sstevel@tonic-gate 	for (ino = 0; ino <= ib_p->ib_max_ino; ino++) {
4487c478bd9Sstevel@tonic-gate 		clr_reg = ib_clear_intr_reg_addr(ib_p, ino);
4497c478bd9Sstevel@tonic-gate 		IB_INO_INTR_CLEAR(clr_reg);
4507c478bd9Sstevel@tonic-gate 	}
4517c478bd9Sstevel@tonic-gate 
4527c478bd9Sstevel@tonic-gate 	return (BF_NONE);
4537c478bd9Sstevel@tonic-gate }
4547c478bd9Sstevel@tonic-gate 
4557c478bd9Sstevel@tonic-gate void
ib_suspend(ib_t * ib_p)4567c478bd9Sstevel@tonic-gate ib_suspend(ib_t *ib_p)
4577c478bd9Sstevel@tonic-gate {
4587c478bd9Sstevel@tonic-gate 	ib_ino_info_t *ip;
4597c478bd9Sstevel@tonic-gate 	pci_t *pci_p = ib_p->ib_pci_p;
4607c478bd9Sstevel@tonic-gate 
4617c478bd9Sstevel@tonic-gate 	/* save ino_lst interrupts' mapping registers content */
4627c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
463b0fc0e77Sgovinda 	for (ip = ib_p->ib_ino_lst; ip; ip = ip->ino_next_p)
4647c478bd9Sstevel@tonic-gate 		ip->ino_map_reg_save = *ip->ino_map_reg;
4657c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
4667c478bd9Sstevel@tonic-gate 
4677c478bd9Sstevel@tonic-gate 	if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) {
4687c478bd9Sstevel@tonic-gate 		ib_p->ib_upa_imr_state[0] = *ib_p->ib_upa_imr[0];
4697c478bd9Sstevel@tonic-gate 		ib_p->ib_upa_imr_state[1] = *ib_p->ib_upa_imr[1];
4707c478bd9Sstevel@tonic-gate 	}
4717c478bd9Sstevel@tonic-gate }
4727c478bd9Sstevel@tonic-gate 
4737c478bd9Sstevel@tonic-gate void
ib_resume(ib_t * ib_p)4747c478bd9Sstevel@tonic-gate ib_resume(ib_t *ib_p)
4757c478bd9Sstevel@tonic-gate {
4767c478bd9Sstevel@tonic-gate 	ib_ino_info_t *ip;
4777c478bd9Sstevel@tonic-gate 	pci_t *pci_p = ib_p->ib_pci_p;
4787c478bd9Sstevel@tonic-gate 
4797c478bd9Sstevel@tonic-gate 	/* restore ino_lst interrupts' mapping registers content */
4807c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
481b0fc0e77Sgovinda 	for (ip = ib_p->ib_ino_lst; ip; ip = ip->ino_next_p) {
4827c478bd9Sstevel@tonic-gate 		IB_INO_INTR_CLEAR(ip->ino_clr_reg);	 /* set intr to idle */
4837c478bd9Sstevel@tonic-gate 		*ip->ino_map_reg = ip->ino_map_reg_save; /* restore IMR */
4847c478bd9Sstevel@tonic-gate 	}
4857c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
4867c478bd9Sstevel@tonic-gate 
4877c478bd9Sstevel@tonic-gate 	if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) {
4887c478bd9Sstevel@tonic-gate 		*ib_p->ib_upa_imr[0] = ib_p->ib_upa_imr_state[0];
4897c478bd9Sstevel@tonic-gate 		*ib_p->ib_upa_imr[1] = ib_p->ib_upa_imr_state[1];
4907c478bd9Sstevel@tonic-gate 	}
4917c478bd9Sstevel@tonic-gate }
4927c478bd9Sstevel@tonic-gate 
4937c478bd9Sstevel@tonic-gate /*
4947c478bd9Sstevel@tonic-gate  * locate ino_info structure on ib_p->ib_ino_lst according to ino#
4957c478bd9Sstevel@tonic-gate  * returns NULL if not found.
4967c478bd9Sstevel@tonic-gate  */
4977c478bd9Sstevel@tonic-gate ib_ino_info_t *
ib_locate_ino(ib_t * ib_p,ib_ino_t ino_num)4987c478bd9Sstevel@tonic-gate ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num)
4997c478bd9Sstevel@tonic-gate {
5007c478bd9Sstevel@tonic-gate 	ib_ino_info_t *ino_p = ib_p->ib_ino_lst;
5017c478bd9Sstevel@tonic-gate 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
5027c478bd9Sstevel@tonic-gate 
503f0d69850Srameshc 	for (; ino_p && ino_p->ino_ino != ino_num; ino_p = ino_p->ino_next_p)
504f0d69850Srameshc 		;
5057c478bd9Sstevel@tonic-gate 	return (ino_p);
5067c478bd9Sstevel@tonic-gate }
5077c478bd9Sstevel@tonic-gate 
5087c478bd9Sstevel@tonic-gate #define	IB_INO_TO_SLOT(ino) (IB_IS_OBIO_INO(ino) ? 0xff : ((ino) & 0x1f) >> 2)
5097c478bd9Sstevel@tonic-gate 
510b0fc0e77Sgovinda ib_ino_pil_t *
ib_new_ino_pil(ib_t * ib_p,ib_ino_t ino_num,uint_t pil,ih_t * ih_p)511b0fc0e77Sgovinda ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil, ih_t *ih_p)
5127c478bd9Sstevel@tonic-gate {
513b0fc0e77Sgovinda 	ib_ino_pil_t	*ipil_p = kmem_zalloc(sizeof (ib_ino_pil_t), KM_SLEEP);
514b0fc0e77Sgovinda 	ib_ino_info_t	*ino_p;
5157c478bd9Sstevel@tonic-gate 
516b0fc0e77Sgovinda 	if ((ino_p = ib_locate_ino(ib_p, ino_num)) == NULL) {
517b0fc0e77Sgovinda 		ino_p = kmem_zalloc(sizeof (ib_ino_info_t), KM_SLEEP);
518b0fc0e77Sgovinda 
519b0fc0e77Sgovinda 		ino_p->ino_next_p = ib_p->ib_ino_lst;
520b0fc0e77Sgovinda 		ib_p->ib_ino_lst = ino_p;
521b0fc0e77Sgovinda 
522b0fc0e77Sgovinda 		ino_p->ino_ino = ino_num;
523b0fc0e77Sgovinda 		ino_p->ino_slot_no = IB_INO_TO_SLOT(ino_num);
524b0fc0e77Sgovinda 		ino_p->ino_ib_p = ib_p;
525b0fc0e77Sgovinda 		ino_p->ino_clr_reg = ib_clear_intr_reg_addr(ib_p, ino_num);
526b0fc0e77Sgovinda 		ino_p->ino_map_reg = ib_intr_map_reg_addr(ib_p, ino_num);
527b0fc0e77Sgovinda 		ino_p->ino_unclaimed_intrs = 0;
528b0fc0e77Sgovinda 		ino_p->ino_lopil = pil;
529b0fc0e77Sgovinda 	}
5307c478bd9Sstevel@tonic-gate 
5317c478bd9Sstevel@tonic-gate 	ih_p->ih_next = ih_p;
532b0fc0e77Sgovinda 	ipil_p->ipil_pil = pil;
533b0fc0e77Sgovinda 	ipil_p->ipil_ih_head = ih_p;
534b0fc0e77Sgovinda 	ipil_p->ipil_ih_tail = ih_p;
535b0fc0e77Sgovinda 	ipil_p->ipil_ih_start = ih_p;
536b0fc0e77Sgovinda 	ipil_p->ipil_ih_size = 1;
537b0fc0e77Sgovinda 	ipil_p->ipil_ino_p = ino_p;
5387c478bd9Sstevel@tonic-gate 
539b0fc0e77Sgovinda 	ipil_p->ipil_next_p = ino_p->ino_ipil_p;
540b0fc0e77Sgovinda 	ino_p->ino_ipil_p = ipil_p;
541b0fc0e77Sgovinda 	ino_p->ino_ipil_size++;
542b0fc0e77Sgovinda 
543b0fc0e77Sgovinda 	if (ino_p->ino_lopil > pil)
544b0fc0e77Sgovinda 		ino_p->ino_lopil = pil;
545b0fc0e77Sgovinda 
546b0fc0e77Sgovinda 	return (ipil_p);
5477c478bd9Sstevel@tonic-gate }
5487c478bd9Sstevel@tonic-gate 
5497c478bd9Sstevel@tonic-gate void
ib_delete_ino_pil(ib_t * ib_p,ib_ino_pil_t * ipil_p)550b0fc0e77Sgovinda ib_delete_ino_pil(ib_t *ib_p, ib_ino_pil_t *ipil_p)
5517c478bd9Sstevel@tonic-gate {
552b0fc0e77Sgovinda 	ib_ino_info_t	*ino_p = ipil_p->ipil_ino_p;
553b0fc0e77Sgovinda 	ib_ino_pil_t	*prev, *next;
554b0fc0e77Sgovinda 	ushort_t	pil = ipil_p->ipil_pil;
555b0fc0e77Sgovinda 
5567c478bd9Sstevel@tonic-gate 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
557b0fc0e77Sgovinda 
558b0fc0e77Sgovinda 	if (ino_p->ino_ipil_p == ipil_p)
559b0fc0e77Sgovinda 		ino_p->ino_ipil_p = ipil_p->ipil_next_p;
5607c478bd9Sstevel@tonic-gate 	else {
561b0fc0e77Sgovinda 		for (prev = next = ino_p->ino_ipil_p; next != ipil_p;
562f0d69850Srameshc 		    prev = next, next = next->ipil_next_p)
563f0d69850Srameshc 			;
564b0fc0e77Sgovinda 
565b0fc0e77Sgovinda 		if (prev)
566b0fc0e77Sgovinda 			prev->ipil_next_p = ipil_p->ipil_next_p;
567b0fc0e77Sgovinda 	}
568b0fc0e77Sgovinda 
569b0fc0e77Sgovinda 	kmem_free(ipil_p, sizeof (ib_ino_pil_t));
570b0fc0e77Sgovinda 
571e4517573Srameshc 	if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) {
572e4517573Srameshc 		for (next = ino_p->ino_ipil_p, pil = next->ipil_pil;
573e4517573Srameshc 		    next; next = next->ipil_next_p) {
574e4517573Srameshc 
575b0fc0e77Sgovinda 			if (pil > next->ipil_pil)
576b0fc0e77Sgovinda 				pil = next->ipil_pil;
577b0fc0e77Sgovinda 		}
578e4517573Srameshc 		/*
579e4517573Srameshc 		 * Value stored in pil should be the lowest pil.
580e4517573Srameshc 		 */
581b0fc0e77Sgovinda 		ino_p->ino_lopil = pil;
582b0fc0e77Sgovinda 	}
583b0fc0e77Sgovinda 
584e4517573Srameshc 	if (ino_p->ino_ipil_size)
585b0fc0e77Sgovinda 		return;
586b0fc0e77Sgovinda 
587b0fc0e77Sgovinda 	if (ib_p->ib_ino_lst == ino_p)
588b0fc0e77Sgovinda 		ib_p->ib_ino_lst = ino_p->ino_next_p;
589b0fc0e77Sgovinda 	else {
590b0fc0e77Sgovinda 		ib_ino_info_t	*list = ib_p->ib_ino_lst;
591b0fc0e77Sgovinda 
592f0d69850Srameshc 		for (; list->ino_next_p != ino_p; list = list->ino_next_p)
593f0d69850Srameshc 			;
594b0fc0e77Sgovinda 		list->ino_next_p = ino_p->ino_next_p;
5957c478bd9Sstevel@tonic-gate 	}
5967c478bd9Sstevel@tonic-gate }
5977c478bd9Sstevel@tonic-gate 
5987c478bd9Sstevel@tonic-gate /* free all ino when we are detaching */
5997c478bd9Sstevel@tonic-gate void
ib_free_ino_all(ib_t * ib_p)6007c478bd9Sstevel@tonic-gate ib_free_ino_all(ib_t *ib_p)
6017c478bd9Sstevel@tonic-gate {
602b0fc0e77Sgovinda 	ib_ino_info_t *ino_p = ib_p->ib_ino_lst;
6037c478bd9Sstevel@tonic-gate 	ib_ino_info_t *next = NULL;
604b0fc0e77Sgovinda 
605b0fc0e77Sgovinda 	while (ino_p) {
606b0fc0e77Sgovinda 		next = ino_p->ino_next_p;
607b0fc0e77Sgovinda 		kmem_free(ino_p, sizeof (ib_ino_info_t));
608b0fc0e77Sgovinda 		ino_p = next;
6097c478bd9Sstevel@tonic-gate 	}
6107c478bd9Sstevel@tonic-gate }
6117c478bd9Sstevel@tonic-gate 
612b0fc0e77Sgovinda /*
613b0fc0e77Sgovinda  * Locate ib_ino_pil_t structure on ino_p->ino_ipil_p according to ino#
614b0fc0e77Sgovinda  * returns NULL if not found.
615b0fc0e77Sgovinda  */
616b0fc0e77Sgovinda ib_ino_pil_t *
ib_ino_locate_ipil(ib_ino_info_t * ino_p,uint_t pil)617b0fc0e77Sgovinda ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil)
618b0fc0e77Sgovinda {
619b0fc0e77Sgovinda 	ib_ino_pil_t	*ipil_p = ino_p->ino_ipil_p;
620b0fc0e77Sgovinda 
621f0d69850Srameshc 	for (; ipil_p && ipil_p->ipil_pil != pil; ipil_p = ipil_p->ipil_next_p)
622f0d69850Srameshc 		;
623b0fc0e77Sgovinda 
624b0fc0e77Sgovinda 	return (ipil_p);
625b0fc0e77Sgovinda }
626b0fc0e77Sgovinda 
6277c478bd9Sstevel@tonic-gate void
ib_ino_add_intr(pci_t * pci_p,ib_ino_pil_t * ipil_p,ih_t * ih_p)628b0fc0e77Sgovinda ib_ino_add_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p)
6297c478bd9Sstevel@tonic-gate {
630b0fc0e77Sgovinda 	ib_ino_info_t *ino_p = ipil_p->ipil_ino_p;
6317c478bd9Sstevel@tonic-gate 	ib_ino_t ino = ino_p->ino_ino;
6327c478bd9Sstevel@tonic-gate 	ib_t *ib_p = ino_p->ino_ib_p;
6337c478bd9Sstevel@tonic-gate 	volatile uint64_t *state_reg = IB_INO_INTR_STATE_REG(ib_p, ino);
6347c478bd9Sstevel@tonic-gate 	hrtime_t start_time;
6357c478bd9Sstevel@tonic-gate 
6367c478bd9Sstevel@tonic-gate 	ASSERT(ib_p == pci_p->pci_ib_p);
6377c478bd9Sstevel@tonic-gate 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
6387c478bd9Sstevel@tonic-gate 
6397c478bd9Sstevel@tonic-gate 	/* disable interrupt, this could disrupt devices sharing our slot */
6407c478bd9Sstevel@tonic-gate 	IB_INO_INTR_OFF(ino_p->ino_map_reg);
6417c478bd9Sstevel@tonic-gate 	*ino_p->ino_map_reg;
6427c478bd9Sstevel@tonic-gate 
6437c478bd9Sstevel@tonic-gate 	/* do NOT modify the link list until after the busy wait */
6447c478bd9Sstevel@tonic-gate 
6457c478bd9Sstevel@tonic-gate 	/*
6467c478bd9Sstevel@tonic-gate 	 * busy wait if there is interrupt being processed.
6477c478bd9Sstevel@tonic-gate 	 * either the pending state will be cleared by the interrupt wrapper
6487c478bd9Sstevel@tonic-gate 	 * or the interrupt will be marked as blocked indicating that it was
6497c478bd9Sstevel@tonic-gate 	 * jabbering.
6507c478bd9Sstevel@tonic-gate 	 */
6517c478bd9Sstevel@tonic-gate 	start_time = gethrtime();
652b0fc0e77Sgovinda 	while ((ino_p->ino_unclaimed_intrs <= pci_unclaimed_intr_max) &&
653f0d69850Srameshc 	    IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
6547c478bd9Sstevel@tonic-gate 		if (gethrtime() - start_time > pci_intrpend_timeout) {
6557c478bd9Sstevel@tonic-gate 			pbm_t *pbm_p = pci_p->pci_pbm_p;
6567c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s:%s: ib_ino_add_intr %x timeout",
657f0d69850Srameshc 			    pbm_p->pbm_nameinst_str,
658f0d69850Srameshc 			    pbm_p->pbm_nameaddr_str, ino);
6597c478bd9Sstevel@tonic-gate 			break;
6607c478bd9Sstevel@tonic-gate 		}
6617c478bd9Sstevel@tonic-gate 	}
6627c478bd9Sstevel@tonic-gate 
663b0fc0e77Sgovinda 	/* link up ih_t */
664b0fc0e77Sgovinda 	ih_p->ih_next = ipil_p->ipil_ih_head;
665b0fc0e77Sgovinda 	ipil_p->ipil_ih_tail->ih_next = ih_p;
666b0fc0e77Sgovinda 	ipil_p->ipil_ih_tail = ih_p;
6677c478bd9Sstevel@tonic-gate 
668b0fc0e77Sgovinda 	ipil_p->ipil_ih_start = ipil_p->ipil_ih_head;
669b0fc0e77Sgovinda 	ipil_p->ipil_ih_size++;
6707c478bd9Sstevel@tonic-gate 
6717c478bd9Sstevel@tonic-gate 	/*
6727c478bd9Sstevel@tonic-gate 	 * if the interrupt was previously blocked (left in pending state)
6737c478bd9Sstevel@tonic-gate 	 * because of jabber we need to clear the pending state in case the
6747c478bd9Sstevel@tonic-gate 	 * jabber has gone away.
6757c478bd9Sstevel@tonic-gate 	 */
676b0fc0e77Sgovinda 	if (ino_p->ino_unclaimed_intrs > pci_unclaimed_intr_max) {
6777c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN,
6787c478bd9Sstevel@tonic-gate 		    "%s%d: ib_ino_add_intr: ino 0x%x has been unblocked",
6797c478bd9Sstevel@tonic-gate 		    ddi_driver_name(pci_p->pci_dip),
6807c478bd9Sstevel@tonic-gate 		    ddi_get_instance(pci_p->pci_dip),
6817c478bd9Sstevel@tonic-gate 		    ino_p->ino_ino);
682b0fc0e77Sgovinda 		ino_p->ino_unclaimed_intrs = 0;
6837c478bd9Sstevel@tonic-gate 		IB_INO_INTR_CLEAR(ino_p->ino_clr_reg);
6847c478bd9Sstevel@tonic-gate 	}
6857c478bd9Sstevel@tonic-gate 
6867c478bd9Sstevel@tonic-gate 	/* re-enable interrupt */
6877c478bd9Sstevel@tonic-gate 	IB_INO_INTR_ON(ino_p->ino_map_reg);
6887c478bd9Sstevel@tonic-gate 	*ino_p->ino_map_reg;
6897c478bd9Sstevel@tonic-gate }
6907c478bd9Sstevel@tonic-gate 
6917c478bd9Sstevel@tonic-gate /*
6927c478bd9Sstevel@tonic-gate  * removes pci_ispec_t from the ino's link list.
6937c478bd9Sstevel@tonic-gate  * uses hardware mutex to lock out interrupt threads.
6947c478bd9Sstevel@tonic-gate  * Side effects: interrupt belongs to that ino is turned off on return.
6957c478bd9Sstevel@tonic-gate  * if we are sharing PCI slot with other inos, the caller needs
6967c478bd9Sstevel@tonic-gate  * to turn it back on.
6977c478bd9Sstevel@tonic-gate  */
6987c478bd9Sstevel@tonic-gate void
ib_ino_rem_intr(pci_t * pci_p,ib_ino_pil_t * ipil_p,ih_t * ih_p)699b0fc0e77Sgovinda ib_ino_rem_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p)
7007c478bd9Sstevel@tonic-gate {
701b0fc0e77Sgovinda 	ib_ino_info_t *ino_p = ipil_p->ipil_ino_p;
7027c478bd9Sstevel@tonic-gate 	int i;
7037c478bd9Sstevel@tonic-gate 	ib_ino_t ino = ino_p->ino_ino;
704b0fc0e77Sgovinda 	ih_t *ih_lst = ipil_p->ipil_ih_head;
7057c478bd9Sstevel@tonic-gate 	volatile uint64_t *state_reg =
706f0d69850Srameshc 	    IB_INO_INTR_STATE_REG(ino_p->ino_ib_p, ino);
7077c478bd9Sstevel@tonic-gate 	hrtime_t start_time;
7087c478bd9Sstevel@tonic-gate 
7097c478bd9Sstevel@tonic-gate 	ASSERT(MUTEX_HELD(&ino_p->ino_ib_p->ib_ino_lst_mutex));
7107c478bd9Sstevel@tonic-gate 	/* disable interrupt, this could disrupt devices sharing our slot */
7117c478bd9Sstevel@tonic-gate 	IB_INO_INTR_OFF(ino_p->ino_map_reg);
7127c478bd9Sstevel@tonic-gate 	*ino_p->ino_map_reg;
7137c478bd9Sstevel@tonic-gate 
7147c478bd9Sstevel@tonic-gate 	/* do NOT modify the link list until after the busy wait */
7157c478bd9Sstevel@tonic-gate 
7167c478bd9Sstevel@tonic-gate 	/*
7177c478bd9Sstevel@tonic-gate 	 * busy wait if there is interrupt being processed.
7187c478bd9Sstevel@tonic-gate 	 * either the pending state will be cleared by the interrupt wrapper
7197c478bd9Sstevel@tonic-gate 	 * or the interrupt will be marked as blocked indicating that it was
7207c478bd9Sstevel@tonic-gate 	 * jabbering.
7217c478bd9Sstevel@tonic-gate 	 */
7227c478bd9Sstevel@tonic-gate 	start_time = gethrtime();
723b0fc0e77Sgovinda 	while ((ino_p->ino_unclaimed_intrs <= pci_unclaimed_intr_max) &&
724f0d69850Srameshc 	    IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) {
7257c478bd9Sstevel@tonic-gate 		if (gethrtime() - start_time > pci_intrpend_timeout) {
7267c478bd9Sstevel@tonic-gate 			pbm_t *pbm_p = pci_p->pci_pbm_p;
7277c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s:%s: ib_ino_rem_intr %x timeout",
728f0d69850Srameshc 			    pbm_p->pbm_nameinst_str,
729f0d69850Srameshc 			    pbm_p->pbm_nameaddr_str, ino);
7307c478bd9Sstevel@tonic-gate 			break;
7317c478bd9Sstevel@tonic-gate 		}
7327c478bd9Sstevel@tonic-gate 	}
7337c478bd9Sstevel@tonic-gate 
734b0fc0e77Sgovinda 	if (ipil_p->ipil_ih_size == 1) {
7357c478bd9Sstevel@tonic-gate 		if (ih_lst != ih_p)
7367c478bd9Sstevel@tonic-gate 			goto not_found;
7377c478bd9Sstevel@tonic-gate 		/* no need to set head/tail as ino_p will be freed */
7387c478bd9Sstevel@tonic-gate 		goto reset;
7397c478bd9Sstevel@tonic-gate 	}
7407c478bd9Sstevel@tonic-gate 
7417c478bd9Sstevel@tonic-gate 	/*
7427c478bd9Sstevel@tonic-gate 	 * if the interrupt was previously blocked (left in pending state)
7437c478bd9Sstevel@tonic-gate 	 * because of jabber we need to clear the pending state in case the
7447c478bd9Sstevel@tonic-gate 	 * jabber has gone away.
7457c478bd9Sstevel@tonic-gate 	 */
746b0fc0e77Sgovinda 	if (ino_p->ino_unclaimed_intrs > pci_unclaimed_intr_max) {
7477c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN,
7487c478bd9Sstevel@tonic-gate 		    "%s%d: ib_ino_rem_intr: ino 0x%x has been unblocked",
7497c478bd9Sstevel@tonic-gate 		    ddi_driver_name(pci_p->pci_dip),
7507c478bd9Sstevel@tonic-gate 		    ddi_get_instance(pci_p->pci_dip),
7517c478bd9Sstevel@tonic-gate 		    ino_p->ino_ino);
752b0fc0e77Sgovinda 		ino_p->ino_unclaimed_intrs = 0;
7537c478bd9Sstevel@tonic-gate 		IB_INO_INTR_CLEAR(ino_p->ino_clr_reg);
7547c478bd9Sstevel@tonic-gate 	}
7557c478bd9Sstevel@tonic-gate 
7567c478bd9Sstevel@tonic-gate 	/* search the link list for ih_p */
7577c478bd9Sstevel@tonic-gate 	for (i = 0;
758f0d69850Srameshc 	    (i < ipil_p->ipil_ih_size) && (ih_lst->ih_next != ih_p);
759f0d69850Srameshc 	    i++, ih_lst = ih_lst->ih_next)
760f0d69850Srameshc 		;
7617c478bd9Sstevel@tonic-gate 	if (ih_lst->ih_next != ih_p)
7627c478bd9Sstevel@tonic-gate 		goto not_found;
7637c478bd9Sstevel@tonic-gate 
7647c478bd9Sstevel@tonic-gate 	/* remove ih_p from the link list and maintain the head/tail */
7657c478bd9Sstevel@tonic-gate 	ih_lst->ih_next = ih_p->ih_next;
766b0fc0e77Sgovinda 	if (ipil_p->ipil_ih_head == ih_p)
767b0fc0e77Sgovinda 		ipil_p->ipil_ih_head = ih_p->ih_next;
768b0fc0e77Sgovinda 	if (ipil_p->ipil_ih_tail == ih_p)
769b0fc0e77Sgovinda 		ipil_p->ipil_ih_tail = ih_lst;
770b0fc0e77Sgovinda 	ipil_p->ipil_ih_start = ipil_p->ipil_ih_head;
7717c478bd9Sstevel@tonic-gate reset:
7727c478bd9Sstevel@tonic-gate 	if (ih_p->ih_config_handle)
7737c478bd9Sstevel@tonic-gate 		pci_config_teardown(&ih_p->ih_config_handle);
7747c478bd9Sstevel@tonic-gate 	if (ih_p->ih_ksp != NULL)
7757c478bd9Sstevel@tonic-gate 		kstat_delete(ih_p->ih_ksp);
7767c478bd9Sstevel@tonic-gate 	kmem_free(ih_p, sizeof (ih_t));
777b0fc0e77Sgovinda 	ipil_p->ipil_ih_size--;
7787c478bd9Sstevel@tonic-gate 
7797c478bd9Sstevel@tonic-gate 	return;
7807c478bd9Sstevel@tonic-gate not_found:
7817c478bd9Sstevel@tonic-gate 	DEBUG2(DBG_R_INTX, ino_p->ino_ib_p->ib_pci_p->pci_dip,
782f0d69850Srameshc 	    "ino_p=%x does not have ih_p=%x\n", ino_p, ih_p);
7837c478bd9Sstevel@tonic-gate }
7847c478bd9Sstevel@tonic-gate 
7857c478bd9Sstevel@tonic-gate ih_t *
ib_intr_locate_ih(ib_ino_pil_t * ipil_p,dev_info_t * rdip,uint32_t inum)786b0fc0e77Sgovinda ib_intr_locate_ih(ib_ino_pil_t *ipil_p, dev_info_t *rdip, uint32_t inum)
7877c478bd9Sstevel@tonic-gate {
788b0fc0e77Sgovinda 	ih_t *ih_p = ipil_p->ipil_ih_head;
7897c478bd9Sstevel@tonic-gate 	int i;
790b0fc0e77Sgovinda 
791b0fc0e77Sgovinda 	for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) {
792b0fc0e77Sgovinda 		if (ih_p->ih_dip == rdip && ih_p->ih_inum == inum)
793b0fc0e77Sgovinda 			return (ih_p);
7947c478bd9Sstevel@tonic-gate 	}
795b0fc0e77Sgovinda 
7967c478bd9Sstevel@tonic-gate 	return ((ih_t *)NULL);
7977c478bd9Sstevel@tonic-gate }
7987c478bd9Sstevel@tonic-gate 
7997c478bd9Sstevel@tonic-gate ih_t *
ib_alloc_ih(dev_info_t * rdip,uint32_t inum,uint_t (* int_handler)(caddr_t int_handler_arg1,caddr_t int_handler_arg2),caddr_t int_handler_arg1,caddr_t int_handler_arg2)8007c478bd9Sstevel@tonic-gate ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
8017851eb82Sschwartz 	uint_t (*int_handler)(caddr_t int_handler_arg1,
8027851eb82Sschwartz 	caddr_t int_handler_arg2),
8037851eb82Sschwartz 	caddr_t int_handler_arg1,
8047851eb82Sschwartz 	caddr_t int_handler_arg2)
8057c478bd9Sstevel@tonic-gate {
8067c478bd9Sstevel@tonic-gate 	ih_t *ih_p;
8077c478bd9Sstevel@tonic-gate 
8087c478bd9Sstevel@tonic-gate 	ih_p = kmem_alloc(sizeof (ih_t), KM_SLEEP);
8097c478bd9Sstevel@tonic-gate 	ih_p->ih_dip = rdip;
8107c478bd9Sstevel@tonic-gate 	ih_p->ih_inum = inum;
8117c478bd9Sstevel@tonic-gate 	ih_p->ih_intr_state = PCI_INTR_STATE_DISABLE;
8127c478bd9Sstevel@tonic-gate 	ih_p->ih_handler = int_handler;
8137c478bd9Sstevel@tonic-gate 	ih_p->ih_handler_arg1 = int_handler_arg1;
8147c478bd9Sstevel@tonic-gate 	ih_p->ih_handler_arg2 = int_handler_arg2;
8157c478bd9Sstevel@tonic-gate 	ih_p->ih_config_handle = NULL;
8167c478bd9Sstevel@tonic-gate 	ih_p->ih_nsec = 0;
8177c478bd9Sstevel@tonic-gate 	ih_p->ih_ticks = 0;
8186d44af1bSesolom 	ih_p->ih_ksp = NULL;
8197c478bd9Sstevel@tonic-gate 
8207c478bd9Sstevel@tonic-gate 	return (ih_p);
8217c478bd9Sstevel@tonic-gate }
8227c478bd9Sstevel@tonic-gate 
8237c478bd9Sstevel@tonic-gate int
ib_update_intr_state(pci_t * pci_p,dev_info_t * rdip,ddi_intr_handle_impl_t * hdlp,uint_t new_intr_state)8247c478bd9Sstevel@tonic-gate ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip,
8257851eb82Sschwartz 	ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state)
8267c478bd9Sstevel@tonic-gate {
8277c478bd9Sstevel@tonic-gate 	ib_t		*ib_p = pci_p->pci_ib_p;
8287c478bd9Sstevel@tonic-gate 	ib_ino_info_t	*ino_p;
829b0fc0e77Sgovinda 	ib_ino_pil_t	*ipil_p;
8307c478bd9Sstevel@tonic-gate 	ib_mondo_t	mondo;
8317c478bd9Sstevel@tonic-gate 	ih_t		*ih_p;
8327c478bd9Sstevel@tonic-gate 	int		ret = DDI_FAILURE;
8337c478bd9Sstevel@tonic-gate 
834f910463cSgovinda 	/*
835f910463cSgovinda 	 * For PULSE interrupts, pci driver don't allocate
836f910463cSgovinda 	 * ib_ino_info_t and ih_t data structures and also,
837f910463cSgovinda 	 * not maintains any interrupt state information.
838f910463cSgovinda 	 * So, just return success from here.
839f910463cSgovinda 	 */
840f910463cSgovinda 	if (hdlp->ih_vector & PCI_PULSE_INO) {
841f910463cSgovinda 		DEBUG0(DBG_IB, ib_p->ib_pci_p->pci_dip,
842f910463cSgovinda 		    "ib_update_intr_state: PULSE interrupt, return success\n");
843f910463cSgovinda 
844f910463cSgovinda 		return (DDI_SUCCESS);
845f910463cSgovinda 	}
846f910463cSgovinda 
8477c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
8487c478bd9Sstevel@tonic-gate 
8497c478bd9Sstevel@tonic-gate 	if ((mondo = pci_xlate_intr(pci_p->pci_dip, rdip, pci_p->pci_ib_p,
850a195726fSgovinda 	    IB_MONDO_TO_INO(hdlp->ih_vector))) == 0) {
8517c478bd9Sstevel@tonic-gate 		mutex_exit(&ib_p->ib_ino_lst_mutex);
8527c478bd9Sstevel@tonic-gate 		return (ret);
8537c478bd9Sstevel@tonic-gate 	}
8547c478bd9Sstevel@tonic-gate 
855b0fc0e77Sgovinda 	ino_p = ib_locate_ino(ib_p, IB_MONDO_TO_INO(mondo));
856b0fc0e77Sgovinda 	if (ino_p && (ipil_p = ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) {
857b0fc0e77Sgovinda 		if (ih_p = ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum)) {
8587c478bd9Sstevel@tonic-gate 			ih_p->ih_intr_state = new_intr_state;
8597c478bd9Sstevel@tonic-gate 			ret = DDI_SUCCESS;
8607c478bd9Sstevel@tonic-gate 		}
8617c478bd9Sstevel@tonic-gate 	}
8627c478bd9Sstevel@tonic-gate 
8637c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
8647c478bd9Sstevel@tonic-gate 	return (ret);
8657c478bd9Sstevel@tonic-gate }
86609b1eac2SEvan Yan 
86709b1eac2SEvan Yan /*
86809b1eac2SEvan Yan  * Get interrupt CPU for a given ino.
86909b1eac2SEvan Yan  * Return info only for inos which are already mapped to devices.
87009b1eac2SEvan Yan  */
87109b1eac2SEvan Yan /*ARGSUSED*/
87209b1eac2SEvan Yan int
ib_get_intr_target(pci_t * pci_p,ib_ino_t ino,int * cpu_id_p)87309b1eac2SEvan Yan ib_get_intr_target(pci_t *pci_p, ib_ino_t ino, int *cpu_id_p)
87409b1eac2SEvan Yan {
87509b1eac2SEvan Yan 	dev_info_t		*dip = pci_p->pci_dip;
87609b1eac2SEvan Yan 	ib_t			*ib_p = pci_p->pci_ib_p;
87709b1eac2SEvan Yan 	volatile uint64_t	*imregp;
87809b1eac2SEvan Yan 	uint64_t		imregval;
87909b1eac2SEvan Yan 
88009b1eac2SEvan Yan 	DEBUG1(DBG_IB, dip, "ib_get_intr_target: ino %x\n", ino);
88109b1eac2SEvan Yan 
88209b1eac2SEvan Yan 	imregp = ib_intr_map_reg_addr(ib_p, ino);
88309b1eac2SEvan Yan 	imregval = *imregp;
88409b1eac2SEvan Yan 
88509b1eac2SEvan Yan 	*cpu_id_p = ib_map_reg_get_cpu(imregval);
88609b1eac2SEvan Yan 
88709b1eac2SEvan Yan 	DEBUG1(DBG_IB, dip, "ib_get_intr_target: cpu_id %x\n", *cpu_id_p);
88809b1eac2SEvan Yan 
88909b1eac2SEvan Yan 	return (DDI_SUCCESS);
89009b1eac2SEvan Yan }
89109b1eac2SEvan Yan 
89209b1eac2SEvan Yan /*
89309b1eac2SEvan Yan  * Associate a new CPU with a given ino.
89409b1eac2SEvan Yan  * Operate only on inos which are already mapped to devices.
89509b1eac2SEvan Yan  */
89609b1eac2SEvan Yan int
ib_set_intr_target(pci_t * pci_p,ib_ino_t ino,int cpu_id)89709b1eac2SEvan Yan ib_set_intr_target(pci_t *pci_p, ib_ino_t ino, int cpu_id)
89809b1eac2SEvan Yan {
89909b1eac2SEvan Yan 	dev_info_t		*dip = pci_p->pci_dip;
90009b1eac2SEvan Yan 	ib_t			*ib_p = pci_p->pci_ib_p;
90109b1eac2SEvan Yan 	int			ret = DDI_SUCCESS;
90209b1eac2SEvan Yan 	uint32_t		old_cpu_id;
90309b1eac2SEvan Yan 	hrtime_t		start_time;
90409b1eac2SEvan Yan 	uint64_t		imregval;
90509b1eac2SEvan Yan 	uint64_t		new_imregval;
90609b1eac2SEvan Yan 	volatile uint64_t	*imregp;
90709b1eac2SEvan Yan 	volatile uint64_t	*idregp;
90809b1eac2SEvan Yan 	extern const int	_ncpu;
90909b1eac2SEvan Yan 	extern cpu_t		*cpu[];
91009b1eac2SEvan Yan 
91109b1eac2SEvan Yan 	DEBUG2(DBG_IB, dip, "ib_set_intr_target: ino %x cpu_id %x\n",
91209b1eac2SEvan Yan 	    ino, cpu_id);
91309b1eac2SEvan Yan 
91409b1eac2SEvan Yan 	imregp = (uint64_t *)ib_intr_map_reg_addr(ib_p, ino);
91509b1eac2SEvan Yan 	idregp = IB_INO_INTR_STATE_REG(ib_p, ino);
91609b1eac2SEvan Yan 
91709b1eac2SEvan Yan 	/* Save original mapreg value. */
91809b1eac2SEvan Yan 	imregval = *imregp;
91909b1eac2SEvan Yan 	DEBUG1(DBG_IB, dip, "ib_set_intr_target: orig mapreg value: 0x%llx\n",
92009b1eac2SEvan Yan 	    imregval);
92109b1eac2SEvan Yan 
92209b1eac2SEvan Yan 	/* Operate only on inos which are already enabled. */
92309b1eac2SEvan Yan 	if (!(imregval & COMMON_INTR_MAP_REG_VALID))
92409b1eac2SEvan Yan 		return (DDI_FAILURE);
92509b1eac2SEvan Yan 
92609b1eac2SEvan Yan 	/* Is this request a noop? */
92709b1eac2SEvan Yan 	if ((old_cpu_id = ib_map_reg_get_cpu(imregval)) == cpu_id)
92809b1eac2SEvan Yan 		return (DDI_SUCCESS);
92909b1eac2SEvan Yan 
93009b1eac2SEvan Yan 	/* Clear the interrupt valid/enable bit for particular ino. */
93109b1eac2SEvan Yan 	DEBUG0(DBG_IB, dip, "Clearing intr_enabled...\n");
93209b1eac2SEvan Yan 	*imregp = imregval & ~COMMON_INTR_MAP_REG_VALID;
93309b1eac2SEvan Yan 
93409b1eac2SEvan Yan 	/* Wait until there are no more pending interrupts. */
93509b1eac2SEvan Yan 	start_time = gethrtime();
93609b1eac2SEvan Yan 
93709b1eac2SEvan Yan 	DEBUG0(DBG_IB, dip, "About to check for pending interrupts...\n");
93809b1eac2SEvan Yan 
93909b1eac2SEvan Yan 	while (IB_INO_INTR_PENDING(idregp, ino)) {
94009b1eac2SEvan Yan 		DEBUG0(DBG_IB, dip, "Waiting for pending ints to clear\n");
94109b1eac2SEvan Yan 		if ((gethrtime() - start_time) < pci_intrpend_timeout) {
94209b1eac2SEvan Yan 			continue;
94309b1eac2SEvan Yan 		} else { /* Timed out waiting. */
94409b1eac2SEvan Yan 			DEBUG0(DBG_IB, dip, "Timed out waiting \n");
94509b1eac2SEvan Yan 			return (DDI_EPENDING);
94609b1eac2SEvan Yan 		}
94709b1eac2SEvan Yan 	}
94809b1eac2SEvan Yan 
94909b1eac2SEvan Yan 	new_imregval = *imregp;
95009b1eac2SEvan Yan 
95109b1eac2SEvan Yan 	DEBUG1(DBG_IB, dip,
95209b1eac2SEvan Yan 	    "after disabling intr, mapreg value: 0x%llx\n", new_imregval);
95309b1eac2SEvan Yan 
95409b1eac2SEvan Yan 	/*
95509b1eac2SEvan Yan 	 * Get lock, validate cpu and write new mapreg value.
95609b1eac2SEvan Yan 	 */
95709b1eac2SEvan Yan 	mutex_enter(&cpu_lock);
95809b1eac2SEvan Yan 	if ((cpu_id < _ncpu) && (cpu[cpu_id] && cpu_is_online(cpu[cpu_id]))) {
95909b1eac2SEvan Yan 		/* Prepare new mapreg value with intr enabled and new cpu_id. */
96009b1eac2SEvan Yan 		new_imregval &=
96109b1eac2SEvan Yan 		    COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO;
96209b1eac2SEvan Yan 		new_imregval = ib_get_map_reg(new_imregval, cpu_id);
96309b1eac2SEvan Yan 
96409b1eac2SEvan Yan 		DEBUG1(DBG_IB, dip, "Writing new mapreg value:0x%llx\n",
96509b1eac2SEvan Yan 		    new_imregval);
96609b1eac2SEvan Yan 
96709b1eac2SEvan Yan 		*imregp = new_imregval;
96809b1eac2SEvan Yan 
96909b1eac2SEvan Yan 		ib_log_new_cpu(ib_p, old_cpu_id, cpu_id, ino);
97009b1eac2SEvan Yan 	} else {	/* Invalid cpu.  Restore original register image. */
97109b1eac2SEvan Yan 		DEBUG0(DBG_IB, dip,
97209b1eac2SEvan Yan 		    "Invalid cpuid: writing orig mapreg value\n");
97309b1eac2SEvan Yan 
97409b1eac2SEvan Yan 		*imregp = imregval;
97509b1eac2SEvan Yan 		ret = DDI_EINVAL;
97609b1eac2SEvan Yan 	}
97709b1eac2SEvan Yan 	mutex_exit(&cpu_lock);
97809b1eac2SEvan Yan 
97909b1eac2SEvan Yan 	return (ret);
98009b1eac2SEvan Yan }
98109b1eac2SEvan Yan 
9827851eb82Sschwartz 
9837851eb82Sschwartz /*
9847851eb82Sschwartz  * Return the dips or number of dips associated with a given interrupt block.
9857851eb82Sschwartz  * Size of dips array arg is passed in as dips_ret arg.
9867851eb82Sschwartz  * Number of dips returned is returned in dips_ret arg.
9877851eb82Sschwartz  * Array of dips gets returned in the dips argument.
9887851eb82Sschwartz  * Function returns number of dips existing for the given interrupt block.
9897851eb82Sschwartz  *
9907851eb82Sschwartz  */
9917851eb82Sschwartz uint8_t
ib_get_ino_devs(ib_t * ib_p,uint32_t ino,uint8_t * devs_ret,pcitool_intr_dev_t * devs)9927851eb82Sschwartz ib_get_ino_devs(
9937851eb82Sschwartz 	ib_t *ib_p, uint32_t ino, uint8_t *devs_ret, pcitool_intr_dev_t *devs)
9947851eb82Sschwartz {
995b0fc0e77Sgovinda 	ib_ino_info_t	*ino_p;
996b0fc0e77Sgovinda 	ib_ino_pil_t	*ipil_p;
997b0fc0e77Sgovinda 	ih_t		*ih_p;
998b0fc0e77Sgovinda 	uint32_t	num_devs = 0;
999