17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*b0fc0e77Sgovinda * Common Development and Distribution License (the "License"). 6*b0fc0e77Sgovinda * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22f910463cSgovinda * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate /* 297c478bd9Sstevel@tonic-gate * PCI Interrupt Block (RISCx) implementation 307c478bd9Sstevel@tonic-gate * initialization 317c478bd9Sstevel@tonic-gate * interrupt enable/disable/clear and mapping register manipulation 327c478bd9Sstevel@tonic-gate */ 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate #include <sys/types.h> 357c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 367c478bd9Sstevel@tonic-gate #include <sys/async.h> 377c478bd9Sstevel@tonic-gate #include <sys/systm.h> /* panicstr */ 387c478bd9Sstevel@tonic-gate #include <sys/spl.h> 397c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 407c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* intr_dist_add */ 417c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 427c478bd9Sstevel@tonic-gate #include <sys/clock.h> 437c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 447c478bd9Sstevel@tonic-gate #include <sys/pci/pci_obj.h> 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 477c478bd9Sstevel@tonic-gate #include <sys/starfire.h> 487c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 497c478bd9Sstevel@tonic-gate 507c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 517c478bd9Sstevel@tonic-gate static uint_t ib_intr_reset(void *arg); 527c478bd9Sstevel@tonic-gate 537c478bd9Sstevel@tonic-gate void 547c478bd9Sstevel@tonic-gate ib_create(pci_t *pci_p) 557c478bd9Sstevel@tonic-gate { 567c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 577c478bd9Sstevel@tonic-gate ib_t *ib_p; 587c478bd9Sstevel@tonic-gate uintptr_t a; 597c478bd9Sstevel@tonic-gate int i; 607c478bd9Sstevel@tonic-gate 617c478bd9Sstevel@tonic-gate /* 627c478bd9Sstevel@tonic-gate * Allocate interrupt block state structure and link it to 637c478bd9Sstevel@tonic-gate * the pci state structure. 647c478bd9Sstevel@tonic-gate */ 657c478bd9Sstevel@tonic-gate ib_p = kmem_zalloc(sizeof (ib_t), KM_SLEEP); 667c478bd9Sstevel@tonic-gate pci_p->pci_ib_p = ib_p; 677c478bd9Sstevel@tonic-gate ib_p->ib_pci_p = pci_p; 687c478bd9Sstevel@tonic-gate 697c478bd9Sstevel@tonic-gate a = pci_ib_setup(ib_p); 707c478bd9Sstevel@tonic-gate 717c478bd9Sstevel@tonic-gate /* 727c478bd9Sstevel@tonic-gate * Determine virtual addresses of interrupt mapping, clear and diag 737c478bd9Sstevel@tonic-gate * registers that have common offsets. 747c478bd9Sstevel@tonic-gate */ 757c478bd9Sstevel@tonic-gate ib_p->ib_slot_clear_intr_regs = 767c478bd9Sstevel@tonic-gate a + COMMON_IB_SLOT_CLEAR_INTR_REG_OFFSET; 777c478bd9Sstevel@tonic-gate ib_p->ib_intr_retry_timer_reg = 787c478bd9Sstevel@tonic-gate (uint64_t *)(a + COMMON_IB_INTR_RETRY_TIMER_OFFSET); 797c478bd9Sstevel@tonic-gate ib_p->ib_slot_intr_state_diag_reg = 807c478bd9Sstevel@tonic-gate (uint64_t *)(a + COMMON_IB_SLOT_INTR_STATE_DIAG_REG); 817c478bd9Sstevel@tonic-gate ib_p->ib_obio_intr_state_diag_reg = 827c478bd9Sstevel@tonic-gate (uint64_t *)(a + COMMON_IB_OBIO_INTR_STATE_DIAG_REG); 837c478bd9Sstevel@tonic-gate 847c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) { 857c478bd9Sstevel@tonic-gate ib_p->ib_upa_imr[0] = (volatile uint64_t *) 867c478bd9Sstevel@tonic-gate (a + COMMON_IB_UPA0_INTR_MAP_REG_OFFSET); 877c478bd9Sstevel@tonic-gate ib_p->ib_upa_imr[1] = (volatile uint64_t *) 887c478bd9Sstevel@tonic-gate (a + COMMON_IB_UPA1_INTR_MAP_REG_OFFSET); 897c478bd9Sstevel@tonic-gate } 907c478bd9Sstevel@tonic-gate 917c478bd9Sstevel@tonic-gate DEBUG2(DBG_ATTACH, dip, "ib_create: slot_imr=%x, slot_cir=%x\n", 927c478bd9Sstevel@tonic-gate ib_p->ib_slot_intr_map_regs, ib_p->ib_obio_intr_map_regs); 937c478bd9Sstevel@tonic-gate DEBUG2(DBG_ATTACH, dip, "ib_create: obio_imr=%x, obio_cir=%x\n", 947c478bd9Sstevel@tonic-gate ib_p->ib_slot_clear_intr_regs, ib_p->ib_obio_clear_intr_regs); 957c478bd9Sstevel@tonic-gate DEBUG2(DBG_ATTACH, dip, "ib_create: upa0_imr=%x, upa1_imr=%x\n", 967c478bd9Sstevel@tonic-gate ib_p->ib_upa_imr[0], ib_p->ib_upa_imr[1]); 977c478bd9Sstevel@tonic-gate DEBUG3(DBG_ATTACH, dip, 987c478bd9Sstevel@tonic-gate "ib_create: retry_timer=%x, obio_diag=%x slot_diag=%x\n", 997c478bd9Sstevel@tonic-gate ib_p->ib_intr_retry_timer_reg, 1007c478bd9Sstevel@tonic-gate ib_p->ib_obio_intr_state_diag_reg, 1017c478bd9Sstevel@tonic-gate ib_p->ib_slot_intr_state_diag_reg); 1027c478bd9Sstevel@tonic-gate 1037c478bd9Sstevel@tonic-gate ib_p->ib_ino_lst = (ib_ino_info_t *)NULL; 1047c478bd9Sstevel@tonic-gate mutex_init(&ib_p->ib_intr_lock, NULL, MUTEX_DRIVER, NULL); 1057c478bd9Sstevel@tonic-gate mutex_init(&ib_p->ib_ino_lst_mutex, NULL, MUTEX_DRIVER, NULL); 1067c478bd9Sstevel@tonic-gate 1077c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "ib_create: numproxy=%x\n", 1087c478bd9Sstevel@tonic-gate pci_p->pci_numproxy); 1097c478bd9Sstevel@tonic-gate for (i = 1; i <= pci_p->pci_numproxy; i++) { 1107c478bd9Sstevel@tonic-gate set_intr_mapping_reg(pci_p->pci_id, 1117c478bd9Sstevel@tonic-gate (uint64_t *)ib_p->ib_upa_imr[i - 1], i); 1127c478bd9Sstevel@tonic-gate } 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate ib_configure(ib_p); 1157c478bd9Sstevel@tonic-gate bus_func_register(BF_TYPE_RESINTR, ib_intr_reset, ib_p); 1167c478bd9Sstevel@tonic-gate } 1177c478bd9Sstevel@tonic-gate 1187c478bd9Sstevel@tonic-gate void 1197c478bd9Sstevel@tonic-gate ib_destroy(pci_t *pci_p) 1207c478bd9Sstevel@tonic-gate { 1217c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 1227c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 1237c478bd9Sstevel@tonic-gate 1247c478bd9Sstevel@tonic-gate DEBUG0(DBG_IB, dip, "ib_destroy\n"); 1257c478bd9Sstevel@tonic-gate bus_func_unregister(BF_TYPE_RESINTR, ib_intr_reset, ib_p); 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate intr_dist_rem_weighted(ib_intr_dist_all, ib_p); 1287c478bd9Sstevel@tonic-gate mutex_destroy(&ib_p->ib_ino_lst_mutex); 1297c478bd9Sstevel@tonic-gate mutex_destroy(&ib_p->ib_intr_lock); 1307c478bd9Sstevel@tonic-gate 1317c478bd9Sstevel@tonic-gate ib_free_ino_all(ib_p); 1327c478bd9Sstevel@tonic-gate 1337c478bd9Sstevel@tonic-gate kmem_free(ib_p, sizeof (ib_t)); 1347c478bd9Sstevel@tonic-gate pci_p->pci_ib_p = NULL; 1357c478bd9Sstevel@tonic-gate } 1367c478bd9Sstevel@tonic-gate 1377c478bd9Sstevel@tonic-gate void 1387c478bd9Sstevel@tonic-gate ib_configure(ib_t *ib_p) 1397c478bd9Sstevel@tonic-gate { 1407c478bd9Sstevel@tonic-gate /* XXX could be different between psycho and schizo */ 1417c478bd9Sstevel@tonic-gate *ib_p->ib_intr_retry_timer_reg = pci_intr_retry_intv; 1427c478bd9Sstevel@tonic-gate } 1437c478bd9Sstevel@tonic-gate 1447c478bd9Sstevel@tonic-gate /* 1457c478bd9Sstevel@tonic-gate * can only used for psycho internal interrupts thermal, power, 1467c478bd9Sstevel@tonic-gate * ue, ce, pbm 1477c478bd9Sstevel@tonic-gate */ 1487c478bd9Sstevel@tonic-gate void 1497c478bd9Sstevel@tonic-gate ib_intr_enable(pci_t *pci_p, ib_ino_t ino) 1507c478bd9Sstevel@tonic-gate { 1517c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 1527c478bd9Sstevel@tonic-gate ib_mondo_t mondo = IB_INO_TO_MONDO(ib_p, ino); 1537c478bd9Sstevel@tonic-gate volatile uint64_t *imr_p = ib_intr_map_reg_addr(ib_p, ino); 1547c478bd9Sstevel@tonic-gate uint_t cpu_id; 1557c478bd9Sstevel@tonic-gate 1567c478bd9Sstevel@tonic-gate /* 1577c478bd9Sstevel@tonic-gate * Determine the cpu for the interrupt. 1587c478bd9Sstevel@tonic-gate */ 1597c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_intr_lock); 1607c478bd9Sstevel@tonic-gate cpu_id = intr_dist_cpuid(); 1617c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 1627c478bd9Sstevel@tonic-gate cpu_id = pc_translate_tgtid(IB2CB(ib_p)->cb_ittrans_cookie, cpu_id, 1637c478bd9Sstevel@tonic-gate IB_GET_MAPREG_INO(ino)); 1647c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 1657c478bd9Sstevel@tonic-gate DEBUG2(DBG_IB, pci_p->pci_dip, 1667c478bd9Sstevel@tonic-gate "ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id); 1677c478bd9Sstevel@tonic-gate 1687c478bd9Sstevel@tonic-gate *imr_p = ib_get_map_reg(mondo, cpu_id); 1697c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ib_clear_intr_reg_addr(ib_p, ino)); 1707c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_intr_lock); 1717c478bd9Sstevel@tonic-gate } 1727c478bd9Sstevel@tonic-gate 1737c478bd9Sstevel@tonic-gate /* 1747c478bd9Sstevel@tonic-gate * Disable the interrupt via its interrupt mapping register. 1757c478bd9Sstevel@tonic-gate * Can only be used for internal interrupts: thermal, power, ue, ce, pbm. 1767c478bd9Sstevel@tonic-gate * If called under interrupt context, wait should be set to 0 1777c478bd9Sstevel@tonic-gate */ 1787c478bd9Sstevel@tonic-gate void 1797c478bd9Sstevel@tonic-gate ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait) 1807c478bd9Sstevel@tonic-gate { 1817c478bd9Sstevel@tonic-gate volatile uint64_t *imr_p = ib_intr_map_reg_addr(ib_p, ino); 1827c478bd9Sstevel@tonic-gate volatile uint64_t *state_reg_p = IB_INO_INTR_STATE_REG(ib_p, ino); 1837c478bd9Sstevel@tonic-gate hrtime_t start_time; 1847c478bd9Sstevel@tonic-gate 1857c478bd9Sstevel@tonic-gate /* disable the interrupt */ 1867c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_intr_lock); 1877c478bd9Sstevel@tonic-gate IB_INO_INTR_OFF(imr_p); 1887c478bd9Sstevel@tonic-gate *imr_p; /* flush previous write */ 1897c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_intr_lock); 1907c478bd9Sstevel@tonic-gate 1917c478bd9Sstevel@tonic-gate if (!wait) 1927c478bd9Sstevel@tonic-gate goto wait_done; 1937c478bd9Sstevel@tonic-gate 1947c478bd9Sstevel@tonic-gate start_time = gethrtime(); 1957c478bd9Sstevel@tonic-gate /* busy wait if there is interrupt being processed */ 1967c478bd9Sstevel@tonic-gate while (IB_INO_INTR_PENDING(state_reg_p, ino) && !panicstr) { 1977c478bd9Sstevel@tonic-gate if (gethrtime() - start_time > pci_intrpend_timeout) { 1987c478bd9Sstevel@tonic-gate pbm_t *pbm_p = ib_p->ib_pci_p->pci_pbm_p; 1997c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s:%s: ib_intr_disable timeout %x", 2007c478bd9Sstevel@tonic-gate pbm_p->pbm_nameinst_str, 2017c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, ino); 2027c478bd9Sstevel@tonic-gate break; 2037c478bd9Sstevel@tonic-gate } 2047c478bd9Sstevel@tonic-gate } 2057c478bd9Sstevel@tonic-gate wait_done: 2067c478bd9Sstevel@tonic-gate IB_INO_INTR_PEND(ib_clear_intr_reg_addr(ib_p, ino)); 2077c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 2087c478bd9Sstevel@tonic-gate pc_ittrans_cleanup(IB2CB(ib_p)->cb_ittrans_cookie, 209f47a9c50Smathue (volatile uint64_t *)(uintptr_t)ino); 2107c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 2117c478bd9Sstevel@tonic-gate } 2127c478bd9Sstevel@tonic-gate 2137c478bd9Sstevel@tonic-gate /* can only used for psycho internal interrupts thermal, power, ue, ce, pbm */ 2147c478bd9Sstevel@tonic-gate void 2157c478bd9Sstevel@tonic-gate ib_nintr_clear(ib_t *ib_p, ib_ino_t ino) 2167c478bd9Sstevel@tonic-gate { 2177c478bd9Sstevel@tonic-gate uint64_t *clr_reg = ib_clear_intr_reg_addr(ib_p, ino); 2187c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(clr_reg); 2197c478bd9Sstevel@tonic-gate } 2207c478bd9Sstevel@tonic-gate 2217c478bd9Sstevel@tonic-gate /* 2227c478bd9Sstevel@tonic-gate * distribute PBM and UPA interrupts. ino is set to 0 by caller if we 2237c478bd9Sstevel@tonic-gate * are dealing with UPA interrupts (without inos). 2247c478bd9Sstevel@tonic-gate */ 2257c478bd9Sstevel@tonic-gate void 2267c478bd9Sstevel@tonic-gate ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino, volatile uint64_t *imr_p) 2277c478bd9Sstevel@tonic-gate { 2287c478bd9Sstevel@tonic-gate volatile uint64_t imr = *imr_p; 2297c478bd9Sstevel@tonic-gate uint32_t cpu_id; 2307c478bd9Sstevel@tonic-gate 2317c478bd9Sstevel@tonic-gate if (!IB_INO_INTR_ISON(imr)) 2327c478bd9Sstevel@tonic-gate return; 2337c478bd9Sstevel@tonic-gate 2347c478bd9Sstevel@tonic-gate cpu_id = intr_dist_cpuid(); 2357c478bd9Sstevel@tonic-gate 2367c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 2377c478bd9Sstevel@tonic-gate if (ino) { 2387c478bd9Sstevel@tonic-gate cpu_id = pc_translate_tgtid(IB2CB(ib_p)->cb_ittrans_cookie, 2397c478bd9Sstevel@tonic-gate cpu_id, IB_GET_MAPREG_INO(ino)); 2407c478bd9Sstevel@tonic-gate } 2417c478bd9Sstevel@tonic-gate #else /* _STARFIRE */ 2427c478bd9Sstevel@tonic-gate if (ib_map_reg_get_cpu(*imr_p) == cpu_id) 2437c478bd9Sstevel@tonic-gate return; 2447c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 2457c478bd9Sstevel@tonic-gate 2467c478bd9Sstevel@tonic-gate *imr_p = ib_get_map_reg(IB_IMR2MONDO(imr), cpu_id); 2477c478bd9Sstevel@tonic-gate imr = *imr_p; /* flush previous write */ 2487c478bd9Sstevel@tonic-gate } 2497c478bd9Sstevel@tonic-gate 2507851eb82Sschwartz /* 2517851eb82Sschwartz * Converts into nsec, ticks logged with a given CPU. Adds nsec to ih. 2527851eb82Sschwartz */ 2537851eb82Sschwartz /*ARGSUSED*/ 2547851eb82Sschwartz void 2557851eb82Sschwartz ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id) 2567851eb82Sschwartz { 2577851eb82Sschwartz extern kmutex_t pciintr_ks_template_lock; 2587851eb82Sschwartz hrtime_t ticks; 2597851eb82Sschwartz 2607851eb82Sschwartz /* 2617851eb82Sschwartz * Because we are updating two fields in ih_t we must lock 2627851eb82Sschwartz * pciintr_ks_template_lock to prevent someone from reading the 2637851eb82Sschwartz * kstats after we set ih_ticks to 0 and before we increment 2647851eb82Sschwartz * ih_nsec to compensate. 2657851eb82Sschwartz * 2667851eb82Sschwartz * We must also protect against the interrupt arriving and incrementing 2677851eb82Sschwartz * ih_ticks between the time we read it and when we reset it to 0. 2687851eb82Sschwartz * To do this we use atomic_swap. 2697851eb82Sschwartz */ 2707851eb82Sschwartz 2717851eb82Sschwartz ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex)); 2727851eb82Sschwartz 2737851eb82Sschwartz mutex_enter(&pciintr_ks_template_lock); 2747851eb82Sschwartz ticks = atomic_swap_64(&ih_p->ih_ticks, 0); 2757851eb82Sschwartz ih_p->ih_nsec += (uint64_t)tick2ns(ticks, cpu_id); 2767851eb82Sschwartz mutex_exit(&pciintr_ks_template_lock); 2777851eb82Sschwartz } 2787851eb82Sschwartz 2797c478bd9Sstevel@tonic-gate static void 2807c478bd9Sstevel@tonic-gate ib_intr_dist(ib_t *ib_p, ib_ino_info_t *ino_p) 2817c478bd9Sstevel@tonic-gate { 2827c478bd9Sstevel@tonic-gate uint32_t cpu_id = ino_p->ino_cpuid; 2837c478bd9Sstevel@tonic-gate ib_ino_t ino = ino_p->ino_ino; 2847c478bd9Sstevel@tonic-gate volatile uint64_t imr, *imr_p, *state_reg; 2857c478bd9Sstevel@tonic-gate hrtime_t start_time; 2867c478bd9Sstevel@tonic-gate 2877c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex)); 2887c478bd9Sstevel@tonic-gate imr_p = ib_intr_map_reg_addr(ib_p, ino); 2897c478bd9Sstevel@tonic-gate state_reg = IB_INO_INTR_STATE_REG(ib_p, ino); 2907c478bd9Sstevel@tonic-gate 2917c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 2927c478bd9Sstevel@tonic-gate /* 2937c478bd9Sstevel@tonic-gate * For Starfire it is a pain to check the current target for 2947c478bd9Sstevel@tonic-gate * the mondo since we have to read the PC asics ITTR slot 2957c478bd9Sstevel@tonic-gate * assigned to this mondo. It will be much easier to assume 2967c478bd9Sstevel@tonic-gate * the current target is always different and do the target 2977c478bd9Sstevel@tonic-gate * reprogram all the time. 2987c478bd9Sstevel@tonic-gate */ 2997c478bd9Sstevel@tonic-gate cpu_id = pc_translate_tgtid(IB2CB(ib_p)->cb_ittrans_cookie, cpu_id, 3007c478bd9Sstevel@tonic-gate IB_GET_MAPREG_INO(ino)); 3017c478bd9Sstevel@tonic-gate #else 3027c478bd9Sstevel@tonic-gate if (ib_map_reg_get_cpu(*imr_p) == cpu_id) /* same cpu, no reprog */ 3037c478bd9Sstevel@tonic-gate return; 3047c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 3057c478bd9Sstevel@tonic-gate 3067c478bd9Sstevel@tonic-gate /* disable interrupt, this could disrupt devices sharing our slot */ 3077c478bd9Sstevel@tonic-gate IB_INO_INTR_OFF(imr_p); 3087c478bd9Sstevel@tonic-gate imr = *imr_p; /* flush previous write */ 3097c478bd9Sstevel@tonic-gate 3107c478bd9Sstevel@tonic-gate /* busy wait if there is interrupt being processed */ 3117c478bd9Sstevel@tonic-gate start_time = gethrtime(); 3127c478bd9Sstevel@tonic-gate while (IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) { 3137c478bd9Sstevel@tonic-gate if (gethrtime() - start_time > pci_intrpend_timeout) { 3147c478bd9Sstevel@tonic-gate pbm_t *pbm_p = ib_p->ib_pci_p->pci_pbm_p; 3157c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s:%s: ib_intr_dist(%p,%x) timeout", 3167c478bd9Sstevel@tonic-gate pbm_p->pbm_nameinst_str, 3177c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, 3187c478bd9Sstevel@tonic-gate imr_p, IB_INO_TO_MONDO(ib_p, ino)); 3197c478bd9Sstevel@tonic-gate break; 3207c478bd9Sstevel@tonic-gate } 3217c478bd9Sstevel@tonic-gate } 3227c478bd9Sstevel@tonic-gate *imr_p = ib_get_map_reg(IB_IMR2MONDO(imr), cpu_id); 3237c478bd9Sstevel@tonic-gate imr = *imr_p; /* flush previous write */ 3247c478bd9Sstevel@tonic-gate } 3257c478bd9Sstevel@tonic-gate 3267c478bd9Sstevel@tonic-gate /* 3277c478bd9Sstevel@tonic-gate * Redistribute interrupts of the specified weight. The first call has a weight 3287c478bd9Sstevel@tonic-gate * of weight_max, which can be used to trigger initialization for 3297c478bd9Sstevel@tonic-gate * redistribution. The inos with weight [weight_max, inf.) should be processed 3307c478bd9Sstevel@tonic-gate * on the "weight == weight_max" call. This first call is followed by calls 3317c478bd9Sstevel@tonic-gate * of decreasing weights, inos of that weight should be processed. The final 3327c478bd9Sstevel@tonic-gate * call specifies a weight of zero, this can be used to trigger processing of 3337c478bd9Sstevel@tonic-gate * stragglers. 3347c478bd9Sstevel@tonic-gate */ 3357c478bd9Sstevel@tonic-gate void 3367c478bd9Sstevel@tonic-gate ib_intr_dist_all(void *arg, int32_t weight_max, int32_t weight) 3377c478bd9Sstevel@tonic-gate { 3387c478bd9Sstevel@tonic-gate ib_t *ib_p = (ib_t *)arg; 3397c478bd9Sstevel@tonic-gate pci_t *pci_p = ib_p->ib_pci_p; 3407c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p; 341*b0fc0e77Sgovinda ib_ino_pil_t *ipil_p; 3427c478bd9Sstevel@tonic-gate ih_t *ih_lst; 3437c478bd9Sstevel@tonic-gate int32_t dweight; 3447c478bd9Sstevel@tonic-gate int i; 3457c478bd9Sstevel@tonic-gate 3467c478bd9Sstevel@tonic-gate if (weight == 0) { 3477c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_intr_lock); 3487c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) { 3497c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) 3507c478bd9Sstevel@tonic-gate ib_intr_dist_nintr(ib_p, 0, 3517c478bd9Sstevel@tonic-gate ib_p->ib_upa_imr[i]); 3527c478bd9Sstevel@tonic-gate } 3537c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_intr_lock); 3547c478bd9Sstevel@tonic-gate } 3557c478bd9Sstevel@tonic-gate 3567c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 3577c478bd9Sstevel@tonic-gate 3587c478bd9Sstevel@tonic-gate /* Perform special processing for first call of a redistribution. */ 3597c478bd9Sstevel@tonic-gate if (weight == weight_max) { 360*b0fc0e77Sgovinda for (ino_p = ib_p->ib_ino_lst; ino_p; 361*b0fc0e77Sgovinda ino_p = ino_p->ino_next_p) { 3627c478bd9Sstevel@tonic-gate 3637c478bd9Sstevel@tonic-gate /* 3647c478bd9Sstevel@tonic-gate * Clear ino_established of each ino on first call. 3657c478bd9Sstevel@tonic-gate * The ino_established field may be used by a pci 3667c478bd9Sstevel@tonic-gate * nexus driver's pci_intr_dist_cpuid implementation 3677c478bd9Sstevel@tonic-gate * when detection of established pci slot-cpu binding 3687c478bd9Sstevel@tonic-gate * for multi function pci cards. 3697c478bd9Sstevel@tonic-gate */ 3707c478bd9Sstevel@tonic-gate ino_p->ino_established = 0; 3717c478bd9Sstevel@tonic-gate 3727c478bd9Sstevel@tonic-gate /* 3737c478bd9Sstevel@tonic-gate * recompute the ino_intr_weight based on the device 3747c478bd9Sstevel@tonic-gate * weight of all devinfo nodes sharing the ino (this 3757c478bd9Sstevel@tonic-gate * will allow us to pick up new weights established by 3767c478bd9Sstevel@tonic-gate * i_ddi_set_intr_weight()). 3777c478bd9Sstevel@tonic-gate */ 3787c478bd9Sstevel@tonic-gate ino_p->ino_intr_weight = 0; 379*b0fc0e77Sgovinda 380*b0fc0e77Sgovinda for (ipil_p = ino_p->ino_ipil_p; ipil_p; 381*b0fc0e77Sgovinda ipil_p = ipil_p->ipil_next_p) { 382*b0fc0e77Sgovinda for (i = 0, ih_lst = ipil_p->ipil_ih_head; 383*b0fc0e77Sgovinda i < ipil_p->ipil_ih_size; i++, 384*b0fc0e77Sgovinda ih_lst = ih_lst->ih_next) { 385*b0fc0e77Sgovinda dweight = i_ddi_get_intr_weight 386*b0fc0e77Sgovinda (ih_lst->ih_dip); 387*b0fc0e77Sgovinda if (dweight > 0) 388*b0fc0e77Sgovinda ino_p->ino_intr_weight += 389*b0fc0e77Sgovinda dweight; 390*b0fc0e77Sgovinda } 3917c478bd9Sstevel@tonic-gate } 3927c478bd9Sstevel@tonic-gate } 3937c478bd9Sstevel@tonic-gate } 3947c478bd9Sstevel@tonic-gate 395*b0fc0e77Sgovinda for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 3967c478bd9Sstevel@tonic-gate uint32_t orig_cpuid; 3977c478bd9Sstevel@tonic-gate 3987c478bd9Sstevel@tonic-gate /* 3997c478bd9Sstevel@tonic-gate * Get the weight of the ino and determine if we are going to 4007c478bd9Sstevel@tonic-gate * process call. We wait until an ib_intr_dist_all call of 4017c478bd9Sstevel@tonic-gate * the proper weight occurs to support redistribution of all 4027c478bd9Sstevel@tonic-gate * heavy weighted interrupts first (across all nexus driver 4037c478bd9Sstevel@tonic-gate * instances). This is done to ensure optimal 4047c478bd9Sstevel@tonic-gate * INTR_WEIGHTED_DIST behavior. 4057c478bd9Sstevel@tonic-gate */ 4067c478bd9Sstevel@tonic-gate if ((weight == ino_p->ino_intr_weight) || 4077c478bd9Sstevel@tonic-gate ((weight >= weight_max) && 4087c478bd9Sstevel@tonic-gate (ino_p->ino_intr_weight >= weight_max))) { 4097c478bd9Sstevel@tonic-gate /* select cpuid to target and mark ino established */ 4107c478bd9Sstevel@tonic-gate orig_cpuid = ino_p->ino_cpuid; 4117c478bd9Sstevel@tonic-gate if (cpu[orig_cpuid] == NULL) 4127c478bd9Sstevel@tonic-gate orig_cpuid = CPU->cpu_id; 4137c478bd9Sstevel@tonic-gate ino_p->ino_cpuid = pci_intr_dist_cpuid(ib_p, ino_p); 4147c478bd9Sstevel@tonic-gate ino_p->ino_established = 1; 4157c478bd9Sstevel@tonic-gate 4167c478bd9Sstevel@tonic-gate /* Add device weight of ino devinfos to targeted cpu. */ 417*b0fc0e77Sgovinda for (ipil_p = ino_p->ino_ipil_p; ipil_p; 418*b0fc0e77Sgovinda ipil_p = ipil_p->ipil_next_p) { 419*b0fc0e77Sgovinda for (i = 0, ih_lst = ipil_p->ipil_ih_head; 420*b0fc0e77Sgovinda i < ipil_p->ipil_ih_size; i++, 421*b0fc0e77Sgovinda ih_lst = ih_lst->ih_next) { 422*b0fc0e77Sgovinda 423*b0fc0e77Sgovinda dweight = i_ddi_get_intr_weight( 424*b0fc0e77Sgovinda ih_lst->ih_dip); 425*b0fc0e77Sgovinda intr_dist_cpuid_add_device_weight( 426*b0fc0e77Sgovinda ino_p->ino_cpuid, ih_lst->ih_dip, 427*b0fc0e77Sgovinda dweight); 428*b0fc0e77Sgovinda 429*b0fc0e77Sgovinda /* 430*b0fc0e77Sgovinda * Different cpus may have different 431*b0fc0e77Sgovinda * clock speeds. to account for this, 432*b0fc0e77Sgovinda * whenever an interrupt is moved to a 433*b0fc0e77Sgovinda * new CPU, we convert the accumulated 434*b0fc0e77Sgovinda * ticks into nsec, based upon the clock 435*b0fc0e77Sgovinda * rate of the prior CPU. 436*b0fc0e77Sgovinda * 437*b0fc0e77Sgovinda * It is possible that the prior CPU no 438*b0fc0e77Sgovinda * longer exists. In this case, fall 439*b0fc0e77Sgovinda * back to using this CPU's clock rate. 440*b0fc0e77Sgovinda * 441*b0fc0e77Sgovinda * Note that the value in ih_ticks has 442*b0fc0e77Sgovinda * already been corrected for any power 443*b0fc0e77Sgovinda * savings mode which might have been 444*b0fc0e77Sgovinda * in effect. 445*b0fc0e77Sgovinda */ 446*b0fc0e77Sgovinda ib_cpu_ticks_to_ih_nsec(ib_p, ih_lst, 447*b0fc0e77Sgovinda orig_cpuid); 448*b0fc0e77Sgovinda } 4497c478bd9Sstevel@tonic-gate } 4507c478bd9Sstevel@tonic-gate 4517c478bd9Sstevel@tonic-gate /* program the hardware */ 4527c478bd9Sstevel@tonic-gate ib_intr_dist(ib_p, ino_p); 4537c478bd9Sstevel@tonic-gate } 4547c478bd9Sstevel@tonic-gate } 4557c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 4567c478bd9Sstevel@tonic-gate } 4577c478bd9Sstevel@tonic-gate 4587c478bd9Sstevel@tonic-gate /* 4597c478bd9Sstevel@tonic-gate * Reset interrupts to IDLE. This function is called during 4607c478bd9Sstevel@tonic-gate * panic handling after redistributing interrupts; it's needed to 4617c478bd9Sstevel@tonic-gate * support dumping to network devices after 'sync' from OBP. 4627c478bd9Sstevel@tonic-gate * 4637c478bd9Sstevel@tonic-gate * N.B. This routine runs in a context where all other threads 4647c478bd9Sstevel@tonic-gate * are permanently suspended. 4657c478bd9Sstevel@tonic-gate */ 4667c478bd9Sstevel@tonic-gate static uint_t 4677c478bd9Sstevel@tonic-gate ib_intr_reset(void *arg) 4687c478bd9Sstevel@tonic-gate { 4697c478bd9Sstevel@tonic-gate ib_t *ib_p = (ib_t *)arg; 4707c478bd9Sstevel@tonic-gate ib_ino_t ino; 4717c478bd9Sstevel@tonic-gate uint64_t *clr_reg; 4727c478bd9Sstevel@tonic-gate 4737c478bd9Sstevel@tonic-gate /* 4747c478bd9Sstevel@tonic-gate * Note that we only actually care about interrupts that are 4757c478bd9Sstevel@tonic-gate * potentially from network devices. 4767c478bd9Sstevel@tonic-gate */ 4777c478bd9Sstevel@tonic-gate for (ino = 0; ino <= ib_p->ib_max_ino; ino++) { 4787c478bd9Sstevel@tonic-gate clr_reg = ib_clear_intr_reg_addr(ib_p, ino); 4797c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(clr_reg); 4807c478bd9Sstevel@tonic-gate } 4817c478bd9Sstevel@tonic-gate 4827c478bd9Sstevel@tonic-gate return (BF_NONE); 4837c478bd9Sstevel@tonic-gate } 4847c478bd9Sstevel@tonic-gate 4857c478bd9Sstevel@tonic-gate void 4867c478bd9Sstevel@tonic-gate ib_suspend(ib_t *ib_p) 4877c478bd9Sstevel@tonic-gate { 4887c478bd9Sstevel@tonic-gate ib_ino_info_t *ip; 4897c478bd9Sstevel@tonic-gate pci_t *pci_p = ib_p->ib_pci_p; 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate /* save ino_lst interrupts' mapping registers content */ 4927c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 493*b0fc0e77Sgovinda for (ip = ib_p->ib_ino_lst; ip; ip = ip->ino_next_p) 4947c478bd9Sstevel@tonic-gate ip->ino_map_reg_save = *ip->ino_map_reg; 4957c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 4967c478bd9Sstevel@tonic-gate 4977c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) { 4987c478bd9Sstevel@tonic-gate ib_p->ib_upa_imr_state[0] = *ib_p->ib_upa_imr[0]; 4997c478bd9Sstevel@tonic-gate ib_p->ib_upa_imr_state[1] = *ib_p->ib_upa_imr[1]; 5007c478bd9Sstevel@tonic-gate } 5017c478bd9Sstevel@tonic-gate } 5027c478bd9Sstevel@tonic-gate 5037c478bd9Sstevel@tonic-gate void 5047c478bd9Sstevel@tonic-gate ib_resume(ib_t *ib_p) 5057c478bd9Sstevel@tonic-gate { 5067c478bd9Sstevel@tonic-gate ib_ino_info_t *ip; 5077c478bd9Sstevel@tonic-gate pci_t *pci_p = ib_p->ib_pci_p; 5087c478bd9Sstevel@tonic-gate 5097c478bd9Sstevel@tonic-gate /* restore ino_lst interrupts' mapping registers content */ 5107c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 511*b0fc0e77Sgovinda for (ip = ib_p->ib_ino_lst; ip; ip = ip->ino_next_p) { 5127c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ip->ino_clr_reg); /* set intr to idle */ 5137c478bd9Sstevel@tonic-gate *ip->ino_map_reg = ip->ino_map_reg_save; /* restore IMR */ 5147c478bd9Sstevel@tonic-gate } 5157c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 5167c478bd9Sstevel@tonic-gate 5177c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_XMITS) { 5187c478bd9Sstevel@tonic-gate *ib_p->ib_upa_imr[0] = ib_p->ib_upa_imr_state[0]; 5197c478bd9Sstevel@tonic-gate *ib_p->ib_upa_imr[1] = ib_p->ib_upa_imr_state[1]; 5207c478bd9Sstevel@tonic-gate } 5217c478bd9Sstevel@tonic-gate } 5227c478bd9Sstevel@tonic-gate 5237c478bd9Sstevel@tonic-gate /* 5247c478bd9Sstevel@tonic-gate * locate ino_info structure on ib_p->ib_ino_lst according to ino# 5257c478bd9Sstevel@tonic-gate * returns NULL if not found. 5267c478bd9Sstevel@tonic-gate */ 5277c478bd9Sstevel@tonic-gate ib_ino_info_t * 5287c478bd9Sstevel@tonic-gate ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num) 5297c478bd9Sstevel@tonic-gate { 5307c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p = ib_p->ib_ino_lst; 5317c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex)); 5327c478bd9Sstevel@tonic-gate 533*b0fc0e77Sgovinda for (; ino_p && ino_p->ino_ino != ino_num; ino_p = ino_p->ino_next_p); 5347c478bd9Sstevel@tonic-gate return (ino_p); 5357c478bd9Sstevel@tonic-gate } 5367c478bd9Sstevel@tonic-gate 5377c478bd9Sstevel@tonic-gate #define IB_INO_TO_SLOT(ino) (IB_IS_OBIO_INO(ino) ? 0xff : ((ino) & 0x1f) >> 2) 5387c478bd9Sstevel@tonic-gate 539*b0fc0e77Sgovinda ib_ino_pil_t * 540*b0fc0e77Sgovinda ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil, ih_t *ih_p) 5417c478bd9Sstevel@tonic-gate { 542*b0fc0e77Sgovinda ib_ino_pil_t *ipil_p = kmem_zalloc(sizeof (ib_ino_pil_t), KM_SLEEP); 543*b0fc0e77Sgovinda ib_ino_info_t *ino_p; 5447c478bd9Sstevel@tonic-gate 545*b0fc0e77Sgovinda if ((ino_p = ib_locate_ino(ib_p, ino_num)) == NULL) { 546*b0fc0e77Sgovinda ino_p = kmem_zalloc(sizeof (ib_ino_info_t), KM_SLEEP); 547*b0fc0e77Sgovinda 548*b0fc0e77Sgovinda ino_p->ino_next_p = ib_p->ib_ino_lst; 549*b0fc0e77Sgovinda ib_p->ib_ino_lst = ino_p; 550*b0fc0e77Sgovinda 551*b0fc0e77Sgovinda ino_p->ino_ino = ino_num; 552*b0fc0e77Sgovinda ino_p->ino_slot_no = IB_INO_TO_SLOT(ino_num); 553*b0fc0e77Sgovinda ino_p->ino_ib_p = ib_p; 554*b0fc0e77Sgovinda ino_p->ino_clr_reg = ib_clear_intr_reg_addr(ib_p, ino_num); 555*b0fc0e77Sgovinda ino_p->ino_map_reg = ib_intr_map_reg_addr(ib_p, ino_num); 556*b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs = 0; 557*b0fc0e77Sgovinda ino_p->ino_lopil = pil; 558*b0fc0e77Sgovinda } 5597c478bd9Sstevel@tonic-gate 5607c478bd9Sstevel@tonic-gate ih_p->ih_next = ih_p; 561*b0fc0e77Sgovinda ipil_p->ipil_pil = pil; 562*b0fc0e77Sgovinda ipil_p->ipil_ih_head = ih_p; 563*b0fc0e77Sgovinda ipil_p->ipil_ih_tail = ih_p; 564*b0fc0e77Sgovinda ipil_p->ipil_ih_start = ih_p; 565*b0fc0e77Sgovinda ipil_p->ipil_ih_size = 1; 566*b0fc0e77Sgovinda ipil_p->ipil_ino_p = ino_p; 5677c478bd9Sstevel@tonic-gate 568*b0fc0e77Sgovinda ipil_p->ipil_next_p = ino_p->ino_ipil_p; 569*b0fc0e77Sgovinda ino_p->ino_ipil_p = ipil_p; 570*b0fc0e77Sgovinda ino_p->ino_ipil_size++; 571*b0fc0e77Sgovinda 572*b0fc0e77Sgovinda if (ino_p->ino_lopil > pil) 573*b0fc0e77Sgovinda ino_p->ino_lopil = pil; 574*b0fc0e77Sgovinda 575*b0fc0e77Sgovinda return (ipil_p); 5767c478bd9Sstevel@tonic-gate } 5777c478bd9Sstevel@tonic-gate 5787c478bd9Sstevel@tonic-gate void 579*b0fc0e77Sgovinda ib_delete_ino_pil(ib_t *ib_p, ib_ino_pil_t *ipil_p) 5807c478bd9Sstevel@tonic-gate { 581*b0fc0e77Sgovinda ib_ino_info_t *ino_p = ipil_p->ipil_ino_p; 582*b0fc0e77Sgovinda ib_ino_pil_t *prev, *next; 583*b0fc0e77Sgovinda ushort_t pil = ipil_p->ipil_pil; 584*b0fc0e77Sgovinda 5857c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex)); 586*b0fc0e77Sgovinda 587*b0fc0e77Sgovinda if (ino_p->ino_ipil_p == ipil_p) 588*b0fc0e77Sgovinda ino_p->ino_ipil_p = ipil_p->ipil_next_p; 5897c478bd9Sstevel@tonic-gate else { 590*b0fc0e77Sgovinda for (prev = next = ino_p->ino_ipil_p; next != ipil_p; 591*b0fc0e77Sgovinda prev = next, next = next->ipil_next_p); 592*b0fc0e77Sgovinda 593*b0fc0e77Sgovinda if (prev) 594*b0fc0e77Sgovinda prev->ipil_next_p = ipil_p->ipil_next_p; 595*b0fc0e77Sgovinda } 596*b0fc0e77Sgovinda 597*b0fc0e77Sgovinda kmem_free(ipil_p, sizeof (ib_ino_pil_t)); 598*b0fc0e77Sgovinda 599*b0fc0e77Sgovinda if (ino_p->ino_lopil == pil) { 600*b0fc0e77Sgovinda for (pil = 0, next = ino_p->ino_ipil_p; next; 601*b0fc0e77Sgovinda next = next->ipil_next_p) { 602*b0fc0e77Sgovinda if (pil > next->ipil_pil) 603*b0fc0e77Sgovinda pil = next->ipil_pil; 604*b0fc0e77Sgovinda } 605*b0fc0e77Sgovinda 606*b0fc0e77Sgovinda ino_p->ino_lopil = pil; 607*b0fc0e77Sgovinda } 608*b0fc0e77Sgovinda 609*b0fc0e77Sgovinda if (--ino_p->ino_ipil_size) 610*b0fc0e77Sgovinda return; 611*b0fc0e77Sgovinda 612*b0fc0e77Sgovinda if (ib_p->ib_ino_lst == ino_p) 613*b0fc0e77Sgovinda ib_p->ib_ino_lst = ino_p->ino_next_p; 614*b0fc0e77Sgovinda else { 615*b0fc0e77Sgovinda ib_ino_info_t *list = ib_p->ib_ino_lst; 616*b0fc0e77Sgovinda 617*b0fc0e77Sgovinda for (; list->ino_next_p != ino_p; list = list->ino_next_p); 618*b0fc0e77Sgovinda list->ino_next_p = ino_p->ino_next_p; 6197c478bd9Sstevel@tonic-gate } 6207c478bd9Sstevel@tonic-gate } 6217c478bd9Sstevel@tonic-gate 6227c478bd9Sstevel@tonic-gate /* free all ino when we are detaching */ 6237c478bd9Sstevel@tonic-gate void 6247c478bd9Sstevel@tonic-gate ib_free_ino_all(ib_t *ib_p) 6257c478bd9Sstevel@tonic-gate { 626*b0fc0e77Sgovinda ib_ino_info_t *ino_p = ib_p->ib_ino_lst; 6277c478bd9Sstevel@tonic-gate ib_ino_info_t *next = NULL; 628*b0fc0e77Sgovinda 629*b0fc0e77Sgovinda while (ino_p) { 630*b0fc0e77Sgovinda next = ino_p->ino_next_p; 631*b0fc0e77Sgovinda kmem_free(ino_p, sizeof (ib_ino_info_t)); 632*b0fc0e77Sgovinda ino_p = next; 6337c478bd9Sstevel@tonic-gate } 6347c478bd9Sstevel@tonic-gate } 6357c478bd9Sstevel@tonic-gate 636*b0fc0e77Sgovinda /* 637*b0fc0e77Sgovinda * Locate ib_ino_pil_t structure on ino_p->ino_ipil_p according to ino# 638*b0fc0e77Sgovinda * returns NULL if not found. 639*b0fc0e77Sgovinda */ 640*b0fc0e77Sgovinda ib_ino_pil_t * 641*b0fc0e77Sgovinda ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil) 642*b0fc0e77Sgovinda { 643*b0fc0e77Sgovinda ib_ino_pil_t *ipil_p = ino_p->ino_ipil_p; 644*b0fc0e77Sgovinda 645*b0fc0e77Sgovinda for (; ipil_p && ipil_p->ipil_pil != pil; ipil_p = ipil_p->ipil_next_p); 646*b0fc0e77Sgovinda 647*b0fc0e77Sgovinda return (ipil_p); 648*b0fc0e77Sgovinda } 649*b0fc0e77Sgovinda 6507c478bd9Sstevel@tonic-gate void 651*b0fc0e77Sgovinda ib_ino_add_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p) 6527c478bd9Sstevel@tonic-gate { 653*b0fc0e77Sgovinda ib_ino_info_t *ino_p = ipil_p->ipil_ino_p; 6547c478bd9Sstevel@tonic-gate ib_ino_t ino = ino_p->ino_ino; 6557c478bd9Sstevel@tonic-gate ib_t *ib_p = ino_p->ino_ib_p; 6567c478bd9Sstevel@tonic-gate volatile uint64_t *state_reg = IB_INO_INTR_STATE_REG(ib_p, ino); 6577c478bd9Sstevel@tonic-gate hrtime_t start_time; 6587c478bd9Sstevel@tonic-gate 6597c478bd9Sstevel@tonic-gate ASSERT(ib_p == pci_p->pci_ib_p); 6607c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex)); 6617c478bd9Sstevel@tonic-gate 6627c478bd9Sstevel@tonic-gate /* disable interrupt, this could disrupt devices sharing our slot */ 6637c478bd9Sstevel@tonic-gate IB_INO_INTR_OFF(ino_p->ino_map_reg); 6647c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg; 6657c478bd9Sstevel@tonic-gate 6667c478bd9Sstevel@tonic-gate /* do NOT modify the link list until after the busy wait */ 6677c478bd9Sstevel@tonic-gate 6687c478bd9Sstevel@tonic-gate /* 6697c478bd9Sstevel@tonic-gate * busy wait if there is interrupt being processed. 6707c478bd9Sstevel@tonic-gate * either the pending state will be cleared by the interrupt wrapper 6717c478bd9Sstevel@tonic-gate * or the interrupt will be marked as blocked indicating that it was 6727c478bd9Sstevel@tonic-gate * jabbering. 6737c478bd9Sstevel@tonic-gate */ 6747c478bd9Sstevel@tonic-gate start_time = gethrtime(); 675*b0fc0e77Sgovinda while ((ino_p->ino_unclaimed_intrs <= pci_unclaimed_intr_max) && 6767c478bd9Sstevel@tonic-gate IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) { 6777c478bd9Sstevel@tonic-gate if (gethrtime() - start_time > pci_intrpend_timeout) { 6787c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 6797c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s:%s: ib_ino_add_intr %x timeout", 6807c478bd9Sstevel@tonic-gate pbm_p->pbm_nameinst_str, 6817c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, ino); 6827c478bd9Sstevel@tonic-gate break; 6837c478bd9Sstevel@tonic-gate } 6847c478bd9Sstevel@tonic-gate } 6857c478bd9Sstevel@tonic-gate 686*b0fc0e77Sgovinda /* link up ih_t */ 687*b0fc0e77Sgovinda ih_p->ih_next = ipil_p->ipil_ih_head; 688*b0fc0e77Sgovinda ipil_p->ipil_ih_tail->ih_next = ih_p; 689*b0fc0e77Sgovinda ipil_p->ipil_ih_tail = ih_p; 6907c478bd9Sstevel@tonic-gate 691*b0fc0e77Sgovinda ipil_p->ipil_ih_start = ipil_p->ipil_ih_head; 692*b0fc0e77Sgovinda ipil_p->ipil_ih_size++; 6937c478bd9Sstevel@tonic-gate 6947c478bd9Sstevel@tonic-gate /* 6957c478bd9Sstevel@tonic-gate * if the interrupt was previously blocked (left in pending state) 6967c478bd9Sstevel@tonic-gate * because of jabber we need to clear the pending state in case the 6977c478bd9Sstevel@tonic-gate * jabber has gone away. 6987c478bd9Sstevel@tonic-gate */ 699*b0fc0e77Sgovinda if (ino_p->ino_unclaimed_intrs > pci_unclaimed_intr_max) { 7007c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, 7017c478bd9Sstevel@tonic-gate "%s%d: ib_ino_add_intr: ino 0x%x has been unblocked", 7027c478bd9Sstevel@tonic-gate ddi_driver_name(pci_p->pci_dip), 7037c478bd9Sstevel@tonic-gate ddi_get_instance(pci_p->pci_dip), 7047c478bd9Sstevel@tonic-gate ino_p->ino_ino); 705*b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs = 0; 7067c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); 7077c478bd9Sstevel@tonic-gate } 7087c478bd9Sstevel@tonic-gate 7097c478bd9Sstevel@tonic-gate /* re-enable interrupt */ 7107c478bd9Sstevel@tonic-gate IB_INO_INTR_ON(ino_p->ino_map_reg); 7117c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg; 7127c478bd9Sstevel@tonic-gate } 7137c478bd9Sstevel@tonic-gate 7147c478bd9Sstevel@tonic-gate /* 7157c478bd9Sstevel@tonic-gate * removes pci_ispec_t from the ino's link list. 7167c478bd9Sstevel@tonic-gate * uses hardware mutex to lock out interrupt threads. 7177c478bd9Sstevel@tonic-gate * Side effects: interrupt belongs to that ino is turned off on return. 7187c478bd9Sstevel@tonic-gate * if we are sharing PCI slot with other inos, the caller needs 7197c478bd9Sstevel@tonic-gate * to turn it back on. 7207c478bd9Sstevel@tonic-gate */ 7217c478bd9Sstevel@tonic-gate void 722*b0fc0e77Sgovinda ib_ino_rem_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p) 7237c478bd9Sstevel@tonic-gate { 724*b0fc0e77Sgovinda ib_ino_info_t *ino_p = ipil_p->ipil_ino_p; 7257c478bd9Sstevel@tonic-gate int i; 7267c478bd9Sstevel@tonic-gate ib_ino_t ino = ino_p->ino_ino; 727*b0fc0e77Sgovinda ih_t *ih_lst = ipil_p->ipil_ih_head; 7287c478bd9Sstevel@tonic-gate volatile uint64_t *state_reg = 7297c478bd9Sstevel@tonic-gate IB_INO_INTR_STATE_REG(ino_p->ino_ib_p, ino); 7307c478bd9Sstevel@tonic-gate hrtime_t start_time; 7317c478bd9Sstevel@tonic-gate 7327c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&ino_p->ino_ib_p->ib_ino_lst_mutex)); 7337c478bd9Sstevel@tonic-gate /* disable interrupt, this could disrupt devices sharing our slot */ 7347c478bd9Sstevel@tonic-gate IB_INO_INTR_OFF(ino_p->ino_map_reg); 7357c478bd9Sstevel@tonic-gate *ino_p->ino_map_reg; 7367c478bd9Sstevel@tonic-gate 7377c478bd9Sstevel@tonic-gate /* do NOT modify the link list until after the busy wait */ 7387c478bd9Sstevel@tonic-gate 7397c478bd9Sstevel@tonic-gate /* 7407c478bd9Sstevel@tonic-gate * busy wait if there is interrupt being processed. 7417c478bd9Sstevel@tonic-gate * either the pending state will be cleared by the interrupt wrapper 7427c478bd9Sstevel@tonic-gate * or the interrupt will be marked as blocked indicating that it was 7437c478bd9Sstevel@tonic-gate * jabbering. 7447c478bd9Sstevel@tonic-gate */ 7457c478bd9Sstevel@tonic-gate start_time = gethrtime(); 746*b0fc0e77Sgovinda while ((ino_p->ino_unclaimed_intrs <= pci_unclaimed_intr_max) && 7477c478bd9Sstevel@tonic-gate IB_INO_INTR_PENDING(state_reg, ino) && !panicstr) { 7487c478bd9Sstevel@tonic-gate if (gethrtime() - start_time > pci_intrpend_timeout) { 7497c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 7507c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s:%s: ib_ino_rem_intr %x timeout", 7517c478bd9Sstevel@tonic-gate pbm_p->pbm_nameinst_str, 7527c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, ino); 7537c478bd9Sstevel@tonic-gate break; 7547c478bd9Sstevel@tonic-gate } 7557c478bd9Sstevel@tonic-gate } 7567c478bd9Sstevel@tonic-gate 757*b0fc0e77Sgovinda if (ipil_p->ipil_ih_size == 1) { 7587c478bd9Sstevel@tonic-gate if (ih_lst != ih_p) 7597c478bd9Sstevel@tonic-gate goto not_found; 7607c478bd9Sstevel@tonic-gate /* no need to set head/tail as ino_p will be freed */ 7617c478bd9Sstevel@tonic-gate goto reset; 7627c478bd9Sstevel@tonic-gate } 7637c478bd9Sstevel@tonic-gate 7647c478bd9Sstevel@tonic-gate /* 7657c478bd9Sstevel@tonic-gate * if the interrupt was previously blocked (left in pending state) 7667c478bd9Sstevel@tonic-gate * because of jabber we need to clear the pending state in case the 7677c478bd9Sstevel@tonic-gate * jabber has gone away. 7687c478bd9Sstevel@tonic-gate */ 769*b0fc0e77Sgovinda if (ino_p->ino_unclaimed_intrs > pci_unclaimed_intr_max) { 7707c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, 7717c478bd9Sstevel@tonic-gate "%s%d: ib_ino_rem_intr: ino 0x%x has been unblocked", 7727c478bd9Sstevel@tonic-gate ddi_driver_name(pci_p->pci_dip), 7737c478bd9Sstevel@tonic-gate ddi_get_instance(pci_p->pci_dip), 7747c478bd9Sstevel@tonic-gate ino_p->ino_ino); 775*b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs = 0; 7767c478bd9Sstevel@tonic-gate IB_INO_INTR_CLEAR(ino_p->ino_clr_reg); 7777c478bd9Sstevel@tonic-gate } 7787c478bd9Sstevel@tonic-gate 7797c478bd9Sstevel@tonic-gate /* search the link list for ih_p */ 7807c478bd9Sstevel@tonic-gate for (i = 0; 781*b0fc0e77Sgovinda (i < ipil_p->ipil_ih_size) && (ih_lst->ih_next != ih_p); 7827c478bd9Sstevel@tonic-gate i++, ih_lst = ih_lst->ih_next); 7837c478bd9Sstevel@tonic-gate if (ih_lst->ih_next != ih_p) 7847c478bd9Sstevel@tonic-gate goto not_found; 7857c478bd9Sstevel@tonic-gate 7867c478bd9Sstevel@tonic-gate /* remove ih_p from the link list and maintain the head/tail */ 7877c478bd9Sstevel@tonic-gate ih_lst->ih_next = ih_p->ih_next; 788*b0fc0e77Sgovinda if (ipil_p->ipil_ih_head == ih_p) 789*b0fc0e77Sgovinda ipil_p->ipil_ih_head = ih_p->ih_next; 790*b0fc0e77Sgovinda if (ipil_p->ipil_ih_tail == ih_p) 791*b0fc0e77Sgovinda ipil_p->ipil_ih_tail = ih_lst; 792*b0fc0e77Sgovinda ipil_p->ipil_ih_start = ipil_p->ipil_ih_head; 7937c478bd9Sstevel@tonic-gate reset: 7947c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 7957c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 7967c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp != NULL) 7977c478bd9Sstevel@tonic-gate kstat_delete(ih_p->ih_ksp); 7987c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (ih_t)); 799*b0fc0e77Sgovinda ipil_p->ipil_ih_size--; 8007c478bd9Sstevel@tonic-gate 8017c478bd9Sstevel@tonic-gate return; 8027c478bd9Sstevel@tonic-gate not_found: 8037c478bd9Sstevel@tonic-gate DEBUG2(DBG_R_INTX, ino_p->ino_ib_p->ib_pci_p->pci_dip, 8047c478bd9Sstevel@tonic-gate "ino_p=%x does not have ih_p=%x\n", ino_p, ih_p); 8057c478bd9Sstevel@tonic-gate } 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate ih_t * 808*b0fc0e77Sgovinda ib_intr_locate_ih(ib_ino_pil_t *ipil_p, dev_info_t *rdip, uint32_t inum) 8097c478bd9Sstevel@tonic-gate { 810*b0fc0e77Sgovinda ih_t *ih_p = ipil_p->ipil_ih_head; 8117c478bd9Sstevel@tonic-gate int i; 812*b0fc0e77Sgovinda 813*b0fc0e77Sgovinda for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) { 814*b0fc0e77Sgovinda if (ih_p->ih_dip == rdip && ih_p->ih_inum == inum) 815*b0fc0e77Sgovinda return (ih_p); 8167c478bd9Sstevel@tonic-gate } 817*b0fc0e77Sgovinda 8187c478bd9Sstevel@tonic-gate return ((ih_t *)NULL); 8197c478bd9Sstevel@tonic-gate } 8207c478bd9Sstevel@tonic-gate 8217c478bd9Sstevel@tonic-gate ih_t * 8227c478bd9Sstevel@tonic-gate ib_alloc_ih(dev_info_t *rdip, uint32_t inum, 8237851eb82Sschwartz uint_t (*int_handler)(caddr_t int_handler_arg1, 8247851eb82Sschwartz caddr_t int_handler_arg2), 8257851eb82Sschwartz caddr_t int_handler_arg1, 8267851eb82Sschwartz caddr_t int_handler_arg2) 8277c478bd9Sstevel@tonic-gate { 8287c478bd9Sstevel@tonic-gate ih_t *ih_p; 8297c478bd9Sstevel@tonic-gate 8307c478bd9Sstevel@tonic-gate ih_p = kmem_alloc(sizeof (ih_t), KM_SLEEP); 8317c478bd9Sstevel@tonic-gate ih_p->ih_dip = rdip; 8327c478bd9Sstevel@tonic-gate ih_p->ih_inum = inum; 8337c478bd9Sstevel@tonic-gate ih_p->ih_intr_state = PCI_INTR_STATE_DISABLE; 8347c478bd9Sstevel@tonic-gate ih_p->ih_handler = int_handler; 8357c478bd9Sstevel@tonic-gate ih_p->ih_handler_arg1 = int_handler_arg1; 8367c478bd9Sstevel@tonic-gate ih_p->ih_handler_arg2 = int_handler_arg2; 8377c478bd9Sstevel@tonic-gate ih_p->ih_config_handle = NULL; 8387c478bd9Sstevel@tonic-gate ih_p->ih_nsec = 0; 8397c478bd9Sstevel@tonic-gate ih_p->ih_ticks = 0; 8406d44af1bSesolom ih_p->ih_ksp = NULL; 8417c478bd9Sstevel@tonic-gate 8427c478bd9Sstevel@tonic-gate return (ih_p); 8437c478bd9Sstevel@tonic-gate } 8447c478bd9Sstevel@tonic-gate 8457c478bd9Sstevel@tonic-gate int 8467c478bd9Sstevel@tonic-gate ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip, 8477851eb82Sschwartz ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state) 8487c478bd9Sstevel@tonic-gate { 8497c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 8507c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p; 851*b0fc0e77Sgovinda ib_ino_pil_t *ipil_p; 8527c478bd9Sstevel@tonic-gate ib_mondo_t mondo; 8537c478bd9Sstevel@tonic-gate ih_t *ih_p; 8547c478bd9Sstevel@tonic-gate int ret = DDI_FAILURE; 8557c478bd9Sstevel@tonic-gate 856f910463cSgovinda /* 857f910463cSgovinda * For PULSE interrupts, pci driver don't allocate 858f910463cSgovinda * ib_ino_info_t and ih_t data structures and also, 859f910463cSgovinda * not maintains any interrupt state information. 860f910463cSgovinda * So, just return success from here. 861f910463cSgovinda */ 862f910463cSgovinda if (hdlp->ih_vector & PCI_PULSE_INO) { 863f910463cSgovinda DEBUG0(DBG_IB, ib_p->ib_pci_p->pci_dip, 864f910463cSgovinda "ib_update_intr_state: PULSE interrupt, return success\n"); 865f910463cSgovinda 866f910463cSgovinda return (DDI_SUCCESS); 867f910463cSgovinda } 868f910463cSgovinda 8697c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 8707c478bd9Sstevel@tonic-gate 8717c478bd9Sstevel@tonic-gate if ((mondo = pci_xlate_intr(pci_p->pci_dip, rdip, pci_p->pci_ib_p, 872a195726fSgovinda IB_MONDO_TO_INO(hdlp->ih_vector))) == 0) { 8737c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 8747c478bd9Sstevel@tonic-gate return (ret); 8757c478bd9Sstevel@tonic-gate } 8767c478bd9Sstevel@tonic-gate 877*b0fc0e77Sgovinda ino_p = ib_locate_ino(ib_p, IB_MONDO_TO_INO(mondo)); 878*b0fc0e77Sgovinda if (ino_p && (ipil_p = ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) { 879*b0fc0e77Sgovinda if (ih_p = ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum)) { 8807c478bd9Sstevel@tonic-gate ih_p->ih_intr_state = new_intr_state; 8817c478bd9Sstevel@tonic-gate ret = DDI_SUCCESS; 8827c478bd9Sstevel@tonic-gate } 8837c478bd9Sstevel@tonic-gate } 8847c478bd9Sstevel@tonic-gate 8857c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 8867c478bd9Sstevel@tonic-gate return (ret); 8877c478bd9Sstevel@tonic-gate } 8887851eb82Sschwartz 8897851eb82Sschwartz /* 8907851eb82Sschwartz * Return the dips or number of dips associated with a given interrupt block. 8917851eb82Sschwartz * Size of dips array arg is passed in as dips_ret arg. 8927851eb82Sschwartz * Number of dips returned is returned in dips_ret arg. 8937851eb82Sschwartz * Array of dips gets returned in the dips argument. 8947851eb82Sschwartz * Function returns number of dips existing for the given interrupt block. 8957851eb82Sschwartz * 8967851eb82Sschwartz */ 8977851eb82Sschwartz uint8_t 8987851eb82Sschwartz ib_get_ino_devs( 8997851eb82Sschwartz ib_t *ib_p, uint32_t ino, uint8_t *devs_ret, pcitool_intr_dev_t *devs) 9007851eb82Sschwartz { 901*b0fc0e77Sgovinda ib_ino_info_t *ino_p; 902*b0fc0e77Sgovinda ib_ino_pil_t *ipil_p; 903*b0fc0e77Sgovinda ih_t *ih_p; 904*b0fc0e77Sgovinda uint32_t num_devs = 0; 905*b0fc0e77Sgovinda int i, j; 9067851eb82Sschwartz 9077851eb82Sschwartz mutex_enter(&ib_p->ib_ino_lst_mutex); 9087851eb82Sschwartz ino_p = ib_locate_ino(ib_p, ino); 9097851eb82Sschwartz if (ino_p != NULL) { 910*b0fc0e77Sgovinda for (j = 0, ipil_p = ino_p->ino_ipil_p; ipil_p; 911*b0fc0e77Sgovinda ipil_p = ipil_p->ipil_next_p) { 912*b0fc0e77Sgovinda num_devs += ipil_p->ipil_ih_size; 913*b0fc0e77Sgovinda 914*b0fc0e77Sgovinda for (i = 0, ih_p = ipil_p->ipil_ih_head; 915*b0fc0e77Sgovinda ((i < ipil_p->ipil_ih_size) && (i < *devs_ret)); 916*b0fc0e77Sgovinda i++, j++, ih_p = ih_p->ih_next) { 917*b0fc0e77Sgovinda (void) strncpy(devs[i].driver_name, 918*b0fc0e77Sgovinda ddi_driver_name(ih_p->ih_dip), 919*b0fc0e77Sgovinda MAXMODCONFNAME-1); 920*b0fc0e77Sgovinda devs[i].driver_name[MAXMODCONFNAME] = '\0'; 921*b0fc0e77Sgovinda (void) ddi_pathname(ih_p->ih_dip, devs[i].path); 922*b0fc0e77Sgovinda devs[i].dev_inst = 923*b0fc0e77Sgovinda ddi_get_instance(ih_p->ih_dip); 924*b0fc0e77Sgovinda } 9257851eb82Sschwartz } 926*b0fc0e77Sgovinda *devs_ret = j; 9277851eb82Sschwartz } 9287851eb82Sschwartz 9297851eb82Sschwartz mutex_exit(&ib_p->ib_ino_lst_mutex); 9307851eb82Sschwartz 9317851eb82Sschwartz return (num_devs); 9327851eb82Sschwartz } 9337851eb82Sschwartz 9347851eb82Sschwartz void ib_log_new_cpu(ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id, 9357851eb82Sschwartz uint32_t ino) 9367851eb82Sschwartz { 937*b0fc0e77Sgovinda ib_ino_info_t *ino_p; 938*b0fc0e77Sgovinda ib_ino_pil_t *ipil_p; 939*b0fc0e77Sgovinda ih_t *ih_p; 940*b0fc0e77Sgovinda int i; 9417851eb82Sschwartz 9427851eb82Sschwartz mutex_enter(&ib_p->ib_ino_lst_mutex); 9437851eb82Sschwartz 9447851eb82Sschwartz /* Log in OS data structures the new CPU. */ 9457851eb82Sschwartz ino_p = ib_locate_ino(ib_p, ino); 9467851eb82Sschwartz if (ino_p != NULL) { 9477851eb82Sschwartz 9487851eb82Sschwartz /* Log in OS data structures the new CPU. */ 9497851eb82Sschwartz ino_p->ino_cpuid = new_cpu_id; 9507851eb82Sschwartz 951*b0fc0e77Sgovinda for (ipil_p = ino_p->ino_ipil_p; ipil_p; 952*b0fc0e77Sgovinda ipil_p = ipil_p->ipil_next_p) { 953*b0fc0e77Sgovinda for (i = 0, ih_p = ipil_p->ipil_ih_head; 954*b0fc0e77Sgovinda (i < ipil_p->ipil_ih_size); 955*b0fc0e77Sgovinda i++, ih_p = ih_p->ih_next) { 956*b0fc0e77Sgovinda /* 957*b0fc0e77Sgovinda * Account for any residual time 958*b0fc0e77Sgovinda * to be logged for old cpu. 959*b0fc0e77Sgovinda */ 960*b0fc0e77Sgovinda ib_cpu_ticks_to_ih_nsec(ib_p, 961*b0fc0e77Sgovinda ipil_p->ipil_ih_head, old_cpu_id); 962*b0fc0e77Sgovinda } 963*b0fc0e77Sgovinda } 9647851eb82Sschwartz } 9657851eb82Sschwartz 9667851eb82Sschwartz mutex_exit(&ib_p->ib_ino_lst_mutex); 9677851eb82Sschwartz } 968