17c478bd9Sstevel@tonic-gate/* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate/* 23750ba224Sanbui * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate * 267c478bd9Sstevel@tonic-gate * Assembly code support for the jalapeno module 277c478bd9Sstevel@tonic-gate */ 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate#include "assym.h" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate#include <sys/asm_linkage.h> 327c478bd9Sstevel@tonic-gate#include <sys/mmu.h> 337c478bd9Sstevel@tonic-gate#include <vm/hat_sfmmu.h> 347c478bd9Sstevel@tonic-gate#include <sys/machparam.h> 357c478bd9Sstevel@tonic-gate#include <sys/machcpuvar.h> 367c478bd9Sstevel@tonic-gate#include <sys/machthread.h> 377c478bd9Sstevel@tonic-gate#include <sys/machtrap.h> 387c478bd9Sstevel@tonic-gate#include <sys/privregs.h> 397c478bd9Sstevel@tonic-gate#include <sys/asm_linkage.h> 407c478bd9Sstevel@tonic-gate#include <sys/trap.h> 417c478bd9Sstevel@tonic-gate#include <sys/cheetahregs.h> 427c478bd9Sstevel@tonic-gate#include <sys/us3_module.h> 437c478bd9Sstevel@tonic-gate#include <sys/xc_impl.h> 447c478bd9Sstevel@tonic-gate#include <sys/intreg.h> 457c478bd9Sstevel@tonic-gate#include <sys/async.h> 467c478bd9Sstevel@tonic-gate#include <sys/clock.h> 477c478bd9Sstevel@tonic-gate#include <sys/cheetahasm.h> 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate#ifdef TRAPTRACE 507c478bd9Sstevel@tonic-gate#include <sys/traptrace.h> 517c478bd9Sstevel@tonic-gate#endif /* TRAPTRACE */ 527c478bd9Sstevel@tonic-gate 537c478bd9Sstevel@tonic-gate/* BEGIN CSTYLED */ 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate#define CHK_JP_ERRATA85_ENABLED(scr, label) \ 587c478bd9Sstevel@tonic-gate ASM_LD(scr, jp_errata_85_active); \ 597c478bd9Sstevel@tonic-gate cmp scr, 1; \ 607c478bd9Sstevel@tonic-gate bne %icc, label; \ 617c478bd9Sstevel@tonic-gate nop 627c478bd9Sstevel@tonic-gate 637c478bd9Sstevel@tonic-gate#define SET_64BIT_PA(dest, scr, hi32, lo32) \ 647c478bd9Sstevel@tonic-gate set hi32, scr; \ 657c478bd9Sstevel@tonic-gate sllx scr, 32, scr; \ 667c478bd9Sstevel@tonic-gate sethi %hi(lo32), dest; \ 677c478bd9Sstevel@tonic-gate or dest, %lo(lo32), dest; \ 687c478bd9Sstevel@tonic-gate or scr, dest, dest 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate/* 71*55fea89dSDan Cross * Macro to trigger Jalapeno/Tomatillo speed change 727c478bd9Sstevel@tonic-gate * j_chng_pa - scratch register 737c478bd9Sstevel@tonic-gate * scr - scratch register 747c478bd9Sstevel@tonic-gate */ 757c478bd9Sstevel@tonic-gate#define JP_ESTAR_TRIGGER(j_chng_pa, scr) \ 767c478bd9Sstevel@tonic-gate SET_64BIT_PA(j_chng_pa, scr, TOM_HIGH_PA, M_T_J_CHNG_INIT_PA); \ 777c478bd9Sstevel@tonic-gate ldxa [j_chng_pa]ASI_IO, scr; \ 787c478bd9Sstevel@tonic-gate5: \ 797c478bd9Sstevel@tonic-gate and scr, TOM_TRIGGER_MASK, scr; \ 807c478bd9Sstevel@tonic-gate cmp scr, TOM_TRIGGER; \ 817c478bd9Sstevel@tonic-gate be,pt %icc, 5b; /* wait while 10 */ \ 827c478bd9Sstevel@tonic-gate ldxa [j_chng_pa]ASI_IO, scr; \ 837c478bd9Sstevel@tonic-gate andn scr, TOM_TRIGGER_MASK, scr; \ 847c478bd9Sstevel@tonic-gate stxa scr, [j_chng_pa]ASI_IO; /* clear j_chng[1:0] */ \ 857c478bd9Sstevel@tonic-gate or scr, TOM_TRIGGER, scr; \ 867c478bd9Sstevel@tonic-gate stxa scr, [j_chng_pa]ASI_IO; /* trigger j_chng */ \ 877c478bd9Sstevel@tonic-gate ldxa [j_chng_pa]ASI_IO, scr; \ 887c478bd9Sstevel@tonic-gate6: \ 897c478bd9Sstevel@tonic-gate and scr, TOM_TRIGGER_MASK, scr; \ 907c478bd9Sstevel@tonic-gate cmp scr, TOM_TRIGGER; \ 917c478bd9Sstevel@tonic-gate be,pt %icc, 6b; /* wait while 10 */ \ 927c478bd9Sstevel@tonic-gate ldxa [j_chng_pa]ASI_IO, scr; \ 937c478bd9Sstevel@tonic-gate andn scr, TOM_TRIGGER_MASK, scr; \ 947c478bd9Sstevel@tonic-gate stxa scr, [j_chng_pa]ASI_IO; /* deassert j_chng */ 957c478bd9Sstevel@tonic-gate 967c478bd9Sstevel@tonic-gate/* 977c478bd9Sstevel@tonic-gate * Macro to set Jalapeno CPU speed 987c478bd9Sstevel@tonic-gate * speed - new speed constant 997c478bd9Sstevel@tonic-gate * scr1 - scratch register 1007c478bd9Sstevel@tonic-gate * scr2 - scratch register 1017c478bd9Sstevel@tonic-gate */ 1027c478bd9Sstevel@tonic-gate#define SET_JP_SPEED(speed, scr1, scr2) \ 1037c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_JBUS_CONFIG, scr1; \ 1047c478bd9Sstevel@tonic-gate set JBUS_CONFIG_ECLK_MASK, scr2; \ 1057c478bd9Sstevel@tonic-gate andn scr1, scr2, scr1; \ 1067c478bd9Sstevel@tonic-gate set speed, scr2; \ 1077c478bd9Sstevel@tonic-gate or scr1, scr2, scr1; \ 1087c478bd9Sstevel@tonic-gate stxa scr1, [%g0]ASI_JBUS_CONFIG; 1097c478bd9Sstevel@tonic-gate 1107c478bd9Sstevel@tonic-gate/* 1117c478bd9Sstevel@tonic-gate * macro to set Master Tomatillo speed 1127c478bd9Sstevel@tonic-gate * speed - tomatillo speed constant 1137c478bd9Sstevel@tonic-gate * tpa - tomatillo estar control register PA 1147c478bd9Sstevel@tonic-gate * scr - scratch register 1157c478bd9Sstevel@tonic-gate */ 1167c478bd9Sstevel@tonic-gate#define SET_TOM_SPEED(speed, tpa, scr) \ 1177c478bd9Sstevel@tonic-gate ldxa [tpa]ASI_IO, scr; \ 1187c478bd9Sstevel@tonic-gate andn scr, TOM_ESTAR_ELCK_MASK, scr; \ 1197c478bd9Sstevel@tonic-gate or scr, speed, scr; \ 1207c478bd9Sstevel@tonic-gate stxa scr, [tpa]ASI_IO; 1217c478bd9Sstevel@tonic-gate 1227c478bd9Sstevel@tonic-gate/* 1237c478bd9Sstevel@tonic-gate * macro to check and set Slave Tomatillo speed 1247c478bd9Sstevel@tonic-gate * speed - tomatillo speed constant 1257c478bd9Sstevel@tonic-gate * scr1 - scratch register 1267c478bd9Sstevel@tonic-gate * scr2 - scratch register 1277c478bd9Sstevel@tonic-gate */ 1287c478bd9Sstevel@tonic-gate 1297c478bd9Sstevel@tonic-gate#define SET_SLAVE_T_SPEED(speed, scr1, scr2) \ 1307c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_JBUS_CONFIG, scr2; \ 1317c478bd9Sstevel@tonic-gate srlx scr2, JBUS_SLAVE_T_PORT_BIT, scr2; \ 1327c478bd9Sstevel@tonic-gate btst 1, scr2; \ 1337c478bd9Sstevel@tonic-gate bz,pt %icc, 4f; \ 1347c478bd9Sstevel@tonic-gate nop; \ 1357c478bd9Sstevel@tonic-gate SET_64BIT_PA(scr1, scr2, TOM_HIGH_PA, S_T_ESTAR_CTRL_PA); \ 1367c478bd9Sstevel@tonic-gate SET_TOM_SPEED(speed, scr1, scr2); \ 1377c478bd9Sstevel@tonic-gate4: 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate 1407c478bd9Sstevel@tonic-gate/* 1417c478bd9Sstevel@tonic-gate * macro to adjust ASI_MCU_CTL_REG1[26:25] fsm bits according to 1427c478bd9Sstevel@tonic-gate * new cpu speed: fsm[1:0]=11b for full speed, fsm[1:0]=0 for estar speed 1437c478bd9Sstevel@tonic-gate * value - fsm bit value constant 1447c478bd9Sstevel@tonic-gate * scr1 - scratch register 1457c478bd9Sstevel@tonic-gate * scr2 - scratch register 1467c478bd9Sstevel@tonic-gate */ 1477c478bd9Sstevel@tonic-gate#define JP_ADJUST_FSM(value, scr1, scr2) \ 1487c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_MCU_CTRL, scr1; \ 1497c478bd9Sstevel@tonic-gate set JP_MCU_FSM_MASK, scr2; \ 1507c478bd9Sstevel@tonic-gate andn scr1, scr2, scr1; \ 1517c478bd9Sstevel@tonic-gate set value, scr2; \ 1527c478bd9Sstevel@tonic-gate or scr1, scr2, scr1; \ 1537c478bd9Sstevel@tonic-gate stxa scr1, [%g0]ASI_MCU_CTRL; \ 1547c478bd9Sstevel@tonic-gate membar #Sync; 1557c478bd9Sstevel@tonic-gate 1567c478bd9Sstevel@tonic-gate/* 1577c478bd9Sstevel@tonic-gate * JP_FORCE_FULL_SPEED and its fellow macros are for Jalapeno 1587c478bd9Sstevel@tonic-gate * workstation to work around Errata 85. The front portion of 1597c478bd9Sstevel@tonic-gate * it packs JP speed(14..13) and Tomatillo speed(5..0) into one 1607c478bd9Sstevel@tonic-gate * register. 1617c478bd9Sstevel@tonic-gate * 1627c478bd9Sstevel@tonic-gate * Current code assumes that these two fields are non-overlapping. 1637c478bd9Sstevel@tonic-gate * If that assumption changes, then this code won't work. If so, we 1647c478bd9Sstevel@tonic-gate * force a compile time error by not defining the JP_FORCE_FULL_SPEED 1657c478bd9Sstevel@tonic-gate * and JP_RESTORE_SPEED macros below. 1667c478bd9Sstevel@tonic-gate */ 1677c478bd9Sstevel@tonic-gate 1687c478bd9Sstevel@tonic-gate#if !(JBUS_CONFIG_ECLK_MASK & TOM_SPEED_MASK) 1697c478bd9Sstevel@tonic-gate 1707c478bd9Sstevel@tonic-gate/* 1717c478bd9Sstevel@tonic-gate * Macro to force Jalapeno/Tomatillo to full speed 172*55fea89dSDan Cross * old_lvl - register used to save original cpu, tomatillo speed 1737c478bd9Sstevel@tonic-gate * scr2 - scratch register 1747c478bd9Sstevel@tonic-gate * scr3 - scratch register 1757c478bd9Sstevel@tonic-gate * scr4 - scratch register 1767c478bd9Sstevel@tonic-gate */ 1777c478bd9Sstevel@tonic-gate#define JP_FORCE_FULL_SPEED(old_lvl, scr2, scr3, scr4) \ 1787c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_JBUS_CONFIG, old_lvl; \ 1797c478bd9Sstevel@tonic-gate set JBUS_CONFIG_ECLK_MASK, scr4; \ 1807c478bd9Sstevel@tonic-gate and old_lvl, scr4, old_lvl; \ 1817c478bd9Sstevel@tonic-gate SET_64BIT_PA(scr2, scr3, TOM_HIGH_PA, M_T_ESTAR_CTRL_PA); \ 1827c478bd9Sstevel@tonic-gate ldxa [scr2]ASI_IO, scr3; \ 1837c478bd9Sstevel@tonic-gate set TOM_ESTAR_ELCK_MASK, scr4; \ 1847c478bd9Sstevel@tonic-gate and scr3, scr4, scr3; \ 1857c478bd9Sstevel@tonic-gate or old_lvl, scr3, old_lvl; \ 1867c478bd9Sstevel@tonic-gate /* original jp and tomatillo speed saved in old_lvl */ \ 1877c478bd9Sstevel@tonic-gate \ 1887c478bd9Sstevel@tonic-gate /* either intended or currently at full speed */ \ 1897c478bd9Sstevel@tonic-gate set JBUS_CONFIG_ECLK_MASK, scr4; \ 1907c478bd9Sstevel@tonic-gate andcc old_lvl, scr4, %g0; \ 1917c478bd9Sstevel@tonic-gate bz,pt %icc, 8f; \ 1927c478bd9Sstevel@tonic-gate nop; \ 1937c478bd9Sstevel@tonic-gate /* go through 1/2 speed. */ \ 1947c478bd9Sstevel@tonic-gate SET_JP_SPEED(JBUS_CONFIG_ECLK_2, scr3, scr4); \ 1957c478bd9Sstevel@tonic-gate SET_TOM_SPEED(TOM_HALF_SPEED, scr2, scr3); \ 1967c478bd9Sstevel@tonic-gate SET_SLAVE_T_SPEED(TOM_HALF_SPEED, scr3, scr4); \ 1977c478bd9Sstevel@tonic-gate JP_ADJUST_FSM(0, scr3, scr4); \ 1987c478bd9Sstevel@tonic-gate set jp_estar_tl0_data, scr3; \ 1997c478bd9Sstevel@tonic-gate ldx [scr3], %g0; \ 2007c478bd9Sstevel@tonic-gate membar #Sync; /* or busy wait 1us */ \ 2017c478bd9Sstevel@tonic-gate JP_ESTAR_TRIGGER(scr3, scr4); \ 2027c478bd9Sstevel@tonic-gate8: \ 2037c478bd9Sstevel@tonic-gate /* bring to 1:1 speed */ \ 2047c478bd9Sstevel@tonic-gate SET_JP_SPEED(JBUS_CONFIG_ECLK_1, scr3, scr4); \ 2057c478bd9Sstevel@tonic-gate SET_TOM_SPEED(TOM_FULL_SPEED, scr2, scr3); \ 2067c478bd9Sstevel@tonic-gate SET_SLAVE_T_SPEED(TOM_FULL_SPEED, scr3, scr4); \ 2077c478bd9Sstevel@tonic-gate JP_ADJUST_FSM(JP_MCU_FSM_MASK, scr3, scr4); \ 2087c478bd9Sstevel@tonic-gate JP_ESTAR_TRIGGER(scr3, scr4) 2097c478bd9Sstevel@tonic-gate 2107c478bd9Sstevel@tonic-gate 2117c478bd9Sstevel@tonic-gate/* 2127c478bd9Sstevel@tonic-gate * Macro to restore Jalapeno/Tomatillo to original speed 213*55fea89dSDan Cross * old_lvl - register contains saved original cpu, tomatillo speed 2147c478bd9Sstevel@tonic-gate * scr2 - scratch register 2157c478bd9Sstevel@tonic-gate * scr3 - scratch register 2167c478bd9Sstevel@tonic-gate * scr4 - scratch register 2177c478bd9Sstevel@tonic-gate * 2187c478bd9Sstevel@tonic-gate * If trap had occured in the middle of ppm cpu speed transtion, then 2197c478bd9Sstevel@tonic-gate * old_lvl[31:10] contains the intended new speed written into jbus_config. 2207c478bd9Sstevel@tonic-gate * if old_lvl[9:0] is inconsistent with old_lvl[31:10], then the trap surely 221*55fea89dSDan Cross * interrupted the ppm cpu speed transition, otherwise nothing for sure. 2227c478bd9Sstevel@tonic-gate * We'll restore the intended/then-current speed, that should cause no 2237c478bd9Sstevel@tonic-gate * trouble to subsequent ppm cpu speed change code. 2247c478bd9Sstevel@tonic-gate */ 2257c478bd9Sstevel@tonic-gate#define JP_RESTORE_SPEED(old_lvl, scr2, scr3, scr4) \ 2267c478bd9Sstevel@tonic-gate srlx old_lvl, JBUS_CONFIG_ECLK_SHIFT, scr2; \ 2277c478bd9Sstevel@tonic-gate and scr2, 3, scr2; \ 2287c478bd9Sstevel@tonic-gate add scr2, 1, scr2; \ 2297c478bd9Sstevel@tonic-gate cmp scr2, 3; \ 2307c478bd9Sstevel@tonic-gate bne,pt %icc, 7f; \ 2317c478bd9Sstevel@tonic-gate nop; \ 2327c478bd9Sstevel@tonic-gate set TOM_SLOW_SPEED, scr2; \ 2337c478bd9Sstevel@tonic-gate /* scr2 contains tom speed according to intended jp speed */ \ 2347c478bd9Sstevel@tonic-gate7: \ 2357c478bd9Sstevel@tonic-gate andn old_lvl, TOM_ESTAR_ELCK_MASK, old_lvl; \ 2367c478bd9Sstevel@tonic-gate or scr2, old_lvl, old_lvl; \ 2377c478bd9Sstevel@tonic-gate /* updated old_lvl to contain intended jp and tom speed */ \ 2387c478bd9Sstevel@tonic-gate andcc old_lvl, TOM_FULL_SPEED, %g0; \ 2397c478bd9Sstevel@tonic-gate bnz,pt %icc, 9f; /* intended full, already at full */ \ 2407c478bd9Sstevel@tonic-gate nop; \ 2417c478bd9Sstevel@tonic-gate \ 2427c478bd9Sstevel@tonic-gate /* go to half speed */ \ 2437c478bd9Sstevel@tonic-gate SET_JP_SPEED(JBUS_CONFIG_ECLK_2, scr3, scr4); \ 2447c478bd9Sstevel@tonic-gate SET_64BIT_PA(scr2, scr3, TOM_HIGH_PA, M_T_ESTAR_CTRL_PA); \ 2457c478bd9Sstevel@tonic-gate SET_TOM_SPEED(TOM_HALF_SPEED, scr2, scr3); \ 2467c478bd9Sstevel@tonic-gate SET_SLAVE_T_SPEED(TOM_HALF_SPEED, scr3, scr4); \ 2477c478bd9Sstevel@tonic-gate JP_ADJUST_FSM(0, scr3, scr4); \ 2487c478bd9Sstevel@tonic-gate set jp_estar_tl0_data, scr3; \ 2497c478bd9Sstevel@tonic-gate ldx [scr3], %g0; \ 2507c478bd9Sstevel@tonic-gate membar #Sync; \ 2517c478bd9Sstevel@tonic-gate JP_ESTAR_TRIGGER(scr3, scr4); \ 2527c478bd9Sstevel@tonic-gate andcc old_lvl, TOM_SLOW_SPEED, %g0; \ 2537c478bd9Sstevel@tonic-gate bz,pt %icc, 9f; /* intended 1:2, already at 1:2 */ \ 2547c478bd9Sstevel@tonic-gate nop; \ 2557c478bd9Sstevel@tonic-gate \ 2567c478bd9Sstevel@tonic-gate /* go to 1:32 speed */ \ 2577c478bd9Sstevel@tonic-gate SET_JP_SPEED(JBUS_CONFIG_ECLK_32, scr3, scr4); \ 2587c478bd9Sstevel@tonic-gate SET_TOM_SPEED(TOM_SLOW_SPEED, scr2, scr3); \ 2597c478bd9Sstevel@tonic-gate SET_SLAVE_T_SPEED(TOM_SLOW_SPEED, scr3, scr4); \ 2607c478bd9Sstevel@tonic-gate JP_ESTAR_TRIGGER(scr3, scr4); \ 2617c478bd9Sstevel@tonic-gate9: 2627c478bd9Sstevel@tonic-gate 2637c478bd9Sstevel@tonic-gate#endif /* !(JBUS_CONFIG_ECLK_MASK & TOM_SPEED_MASK) */ 2647c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 2657c478bd9Sstevel@tonic-gate 2667c478bd9Sstevel@tonic-gate/* 2677c478bd9Sstevel@tonic-gate * Jalapeno version to reflush an Ecache line by index. 2687c478bd9Sstevel@tonic-gate * Will flush all 4 ways (with only one scratch register). 2697c478bd9Sstevel@tonic-gate * Note that the code will be faster if we use 2 scratch registers. 2707c478bd9Sstevel@tonic-gate */ 2717c478bd9Sstevel@tonic-gate#define ECACHE_REFLUSH_LINE(ec_set_size, index, scr1) \ 2727c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR; \ 2737c478bd9Sstevel@tonic-gate ldxa [index]ASI_EC_DIAG, %g0; \ 2747c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR; \ 2757c478bd9Sstevel@tonic-gate mov 1, scr1; \ 2767c478bd9Sstevel@tonic-gate sllx scr1, JP_ECFLUSH_EC_WAY_SHIFT, scr1; \ 2777c478bd9Sstevel@tonic-gate add scr1, index, scr1; \ 2787c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR; \ 2797c478bd9Sstevel@tonic-gate ldxa [scr1]ASI_EC_DIAG, %g0; \ 2807c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR; \ 2817c478bd9Sstevel@tonic-gate mov 2, scr1; \ 2827c478bd9Sstevel@tonic-gate sllx scr1, JP_ECFLUSH_EC_WAY_SHIFT, scr1; \ 2837c478bd9Sstevel@tonic-gate add scr1, index, scr1; \ 2847c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR; \ 2857c478bd9Sstevel@tonic-gate ldxa [scr1]ASI_EC_DIAG, %g0; \ 2867c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR; \ 2877c478bd9Sstevel@tonic-gate mov 3, scr1; \ 2887c478bd9Sstevel@tonic-gate sllx scr1, JP_ECFLUSH_EC_WAY_SHIFT, scr1; \ 2897c478bd9Sstevel@tonic-gate add scr1, index, scr1; \ 2907c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR; \ 2917c478bd9Sstevel@tonic-gate ldxa [scr1]ASI_EC_DIAG, %g0; \ 2927c478bd9Sstevel@tonic-gate JP_EC_DIAG_ACCESS_MEMBAR 2937c478bd9Sstevel@tonic-gate 2947c478bd9Sstevel@tonic-gate/* 2957c478bd9Sstevel@tonic-gate * Jalapeno version of ecache_flush_line. Uses Jalapeno Ecache Displacement 2967c478bd9Sstevel@tonic-gate * Flush feature to flush all 4 sets/ways. 2977c478bd9Sstevel@tonic-gate */ 2987c478bd9Sstevel@tonic-gate#define ECACHE_FLUSH_LINE(physaddr, ec_set_size, scr1, scr2) \ 2997c478bd9Sstevel@tonic-gate CPU_INDEX(scr1, scr2); \ 3007c478bd9Sstevel@tonic-gate sllx scr1, JP_ECFLUSH_PORTID_SHIFT, scr1; \ 3017c478bd9Sstevel@tonic-gate set JP_ECACHE_IDX_DISP_FLUSH, scr2; \ 3027c478bd9Sstevel@tonic-gate or scr2, scr1, scr2; \ 3037c478bd9Sstevel@tonic-gate sub ec_set_size, 1, scr1; \ 3047c478bd9Sstevel@tonic-gate and physaddr, scr1, scr1; \ 3057c478bd9Sstevel@tonic-gate or scr2, scr1, scr1; \ 3067c478bd9Sstevel@tonic-gate ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2) 3077c478bd9Sstevel@tonic-gate 3087c478bd9Sstevel@tonic-gate/* 3097c478bd9Sstevel@tonic-gate * Macro for getting ecache size from cpunodes structure 3107c478bd9Sstevel@tonic-gate * scr1: Scratch, ecache size returned in this 3117c478bd9Sstevel@tonic-gate * scr2: Scratch 3127c478bd9Sstevel@tonic-gate */ 3137c478bd9Sstevel@tonic-gate#define GET_ECACHE_SIZE(scr1, scr2) \ 3147c478bd9Sstevel@tonic-gate CPU_INDEX(scr1, scr2); \ 3157c478bd9Sstevel@tonic-gate mulx scr1, CPU_NODE_SIZE, scr1; \ 3167c478bd9Sstevel@tonic-gate set cpunodes + ECACHE_SIZE, scr2; \ 3177c478bd9Sstevel@tonic-gate ld [scr1 + scr2], scr1 3187c478bd9Sstevel@tonic-gate 3197c478bd9Sstevel@tonic-gate/* END CSTYLED */ 3207c478bd9Sstevel@tonic-gate 3217c478bd9Sstevel@tonic-gate/* 3227c478bd9Sstevel@tonic-gate * Ship mondo to aid using implicit busy/nack pair (bn ignored) 3237c478bd9Sstevel@tonic-gate */ 3247c478bd9Sstevel@tonic-gate ENTRY_NP(shipit) 3257c478bd9Sstevel@tonic-gate sll %o0, IDCR_PID_SHIFT, %g1 ! IDCR<18:14> = agent id 3267c478bd9Sstevel@tonic-gate or %g1, IDCR_OFFSET, %g1 ! IDCR<13:0> = 0x70 3277c478bd9Sstevel@tonic-gate stxa %g0, [%g1]ASI_INTR_DISPATCH ! interrupt vector dispatch 3287c478bd9Sstevel@tonic-gate membar #Sync 3297c478bd9Sstevel@tonic-gate retl 3307c478bd9Sstevel@tonic-gate nop 3317c478bd9Sstevel@tonic-gate SET_SIZE(shipit) 3327c478bd9Sstevel@tonic-gate 3337c478bd9Sstevel@tonic-gate 3347c478bd9Sstevel@tonic-gate/* 3357c478bd9Sstevel@tonic-gate * flush_ecache: 3367c478bd9Sstevel@tonic-gate * %o0 - 64 bit physical address 3377c478bd9Sstevel@tonic-gate * %o1 - ecache size 3387c478bd9Sstevel@tonic-gate * %o2 - ecache linesize 3397c478bd9Sstevel@tonic-gate */ 3407c478bd9Sstevel@tonic-gate 3417c478bd9Sstevel@tonic-gate ENTRY(flush_ecache) 3427c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 3437c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_1); 3447c478bd9Sstevel@tonic-gate JP_FORCE_FULL_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */ 3457c478bd9Sstevel@tonic-gateflush_ecache_1: 3467c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 3477c478bd9Sstevel@tonic-gate 3487c478bd9Sstevel@tonic-gate /* 3497c478bd9Sstevel@tonic-gate * Flush the entire Ecache using displacement flush. 3507c478bd9Sstevel@tonic-gate */ 3517c478bd9Sstevel@tonic-gate ECACHE_FLUSHALL(%o1, %o2, %o0, %o4) 3527c478bd9Sstevel@tonic-gate 3537c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 3547c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_2); 3557c478bd9Sstevel@tonic-gate JP_RESTORE_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */ 3567c478bd9Sstevel@tonic-gateflush_ecache_2: 3577c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 3587c478bd9Sstevel@tonic-gate 3597c478bd9Sstevel@tonic-gate retl 3607c478bd9Sstevel@tonic-gate nop 3617c478bd9Sstevel@tonic-gate SET_SIZE(flush_ecache) 3627c478bd9Sstevel@tonic-gate 3637c478bd9Sstevel@tonic-gate 3647c478bd9Sstevel@tonic-gate .section ".text" 3657c478bd9Sstevel@tonic-gate .align 64 3667c478bd9Sstevel@tonic-gate ENTRY_NP(fast_ecc_err) 367*55fea89dSDan Cross 3687c478bd9Sstevel@tonic-gate /* 3697c478bd9Sstevel@tonic-gate * Turn off CEEN and NCEEN. 3707c478bd9Sstevel@tonic-gate */ 3717c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_ESTATE_ERR, %g3 3727c478bd9Sstevel@tonic-gate andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4 3737c478bd9Sstevel@tonic-gate stxa %g4, [%g0]ASI_ESTATE_ERR 3747c478bd9Sstevel@tonic-gate membar #Sync ! membar sync required 3757c478bd9Sstevel@tonic-gate 3767c478bd9Sstevel@tonic-gate /* 3777c478bd9Sstevel@tonic-gate * Do the CPU log out capture. 3787c478bd9Sstevel@tonic-gate * %g3 = "failed?" return value. 3797c478bd9Sstevel@tonic-gate * %g2 = Input = AFAR. Output the clo_flags info which is passed 3807c478bd9Sstevel@tonic-gate * into this macro via %g4. Output only valid if cpu_private 3817c478bd9Sstevel@tonic-gate * struct has not been initialized. 3827c478bd9Sstevel@tonic-gate * CHPR_FECCTL0_LOGOUT = cpu logout structure offset input 3837c478bd9Sstevel@tonic-gate * %g4 = Trap information stored in the cpu logout flags field 3847c478bd9Sstevel@tonic-gate * %g5 = scr1 3857c478bd9Sstevel@tonic-gate * %g6 = scr2 3867c478bd9Sstevel@tonic-gate * %g3 = scr3 3877c478bd9Sstevel@tonic-gate * %g4 = scr4 3887c478bd9Sstevel@tonic-gate */ 3897c478bd9Sstevel@tonic-gate and %g3, EN_REG_CEEN, %g4 ! store the CEEN value, TL=0 3907c478bd9Sstevel@tonic-gate set CHPR_FECCTL0_LOGOUT, %g6 3917c478bd9Sstevel@tonic-gate DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4) 3927c478bd9Sstevel@tonic-gate 3937c478bd9Sstevel@tonic-gate /* 3947c478bd9Sstevel@tonic-gate * Flush the Ecache to get the error out of the Ecache. If the UCC 3957c478bd9Sstevel@tonic-gate * or UCU is on a dirty line, then the following flush will turn 3967c478bd9Sstevel@tonic-gate * that into a WDC or WDU, respectively. 3977c478bd9Sstevel@tonic-gate */ 3987c478bd9Sstevel@tonic-gate CPU_INDEX(%g4, %g5) 3997c478bd9Sstevel@tonic-gate mulx %g4, CPU_NODE_SIZE, %g4 4007c478bd9Sstevel@tonic-gate set cpunodes, %g5 4017c478bd9Sstevel@tonic-gate add %g4, %g5, %g4 4027c478bd9Sstevel@tonic-gate ld [%g4 + ECACHE_LINESIZE], %g5 4037c478bd9Sstevel@tonic-gate ld [%g4 + ECACHE_SIZE], %g4 4047c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 4057c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_err_1); 4067c478bd9Sstevel@tonic-gate set jp_estar_tl0_data, %g6 4077c478bd9Sstevel@tonic-gate stx %g2, [%g6 + 0] 4087c478bd9Sstevel@tonic-gate stx %g3, [%g6 + 8] 4097c478bd9Sstevel@tonic-gate JP_FORCE_FULL_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */ 4107c478bd9Sstevel@tonic-gatefast_ecc_err_1: 4117c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 4127c478bd9Sstevel@tonic-gate ECACHE_FLUSHALL(%g4, %g5, %g6, %g7) 4137c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 4147c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_err_2); 4157c478bd9Sstevel@tonic-gate JP_RESTORE_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */ 4167c478bd9Sstevel@tonic-gate set jp_estar_tl0_data, %g6 4177c478bd9Sstevel@tonic-gate ldx [%g6 + 0], %g2 4187c478bd9Sstevel@tonic-gate ldx [%g6 + 8], %g3 4197c478bd9Sstevel@tonic-gatefast_ecc_err_2: 4207c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 4217c478bd9Sstevel@tonic-gate 4227c478bd9Sstevel@tonic-gate /* 4237c478bd9Sstevel@tonic-gate * Flush the Dcache. Since bad data could have been installed in 4247c478bd9Sstevel@tonic-gate * the Dcache we must flush it before re-enabling it. 4257c478bd9Sstevel@tonic-gate */ 4267c478bd9Sstevel@tonic-gate ASM_LD(%g5, dcache_size) 4277c478bd9Sstevel@tonic-gate ASM_LD(%g6, dcache_linesize) 4287c478bd9Sstevel@tonic-gate CH_DCACHE_FLUSHALL(%g5, %g6, %g7) 4297c478bd9Sstevel@tonic-gate 4307c478bd9Sstevel@tonic-gate /* 4317c478bd9Sstevel@tonic-gate * Flush the Icache. Since we turned off the Icache to capture the 4327c478bd9Sstevel@tonic-gate * Icache line it is now stale or corrupted and we must flush it 4337c478bd9Sstevel@tonic-gate * before re-enabling it. 4347c478bd9Sstevel@tonic-gate */ 4357c478bd9Sstevel@tonic-gate GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_4); 4367c478bd9Sstevel@tonic-gate ld [%g5 + CHPR_ICACHE_LINESIZE], %g6 4377c478bd9Sstevel@tonic-gate ba,pt %icc, 5f 4387c478bd9Sstevel@tonic-gate ld [%g5 + CHPR_ICACHE_SIZE], %g5 4397c478bd9Sstevel@tonic-gatefast_ecc_err_4: 4407c478bd9Sstevel@tonic-gate ASM_LD(%g5, icache_size) 4417c478bd9Sstevel@tonic-gate ASM_LD(%g6, icache_linesize) 4427c478bd9Sstevel@tonic-gate5: 4437c478bd9Sstevel@tonic-gate CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4) 4447c478bd9Sstevel@tonic-gate 4457c478bd9Sstevel@tonic-gate /* 4467c478bd9Sstevel@tonic-gate * Restore the Dcache and Icache to the previous state. 4477c478bd9Sstevel@tonic-gate */ 4487c478bd9Sstevel@tonic-gate stxa %g1, [%g0]ASI_DCU 4497c478bd9Sstevel@tonic-gate flush %g0 /* flush required after changing the IC bit */ 4507c478bd9Sstevel@tonic-gate 4517c478bd9Sstevel@tonic-gate /* 4527c478bd9Sstevel@tonic-gate * Make sure our CPU logout operation was successful. 4537c478bd9Sstevel@tonic-gate */ 4547c478bd9Sstevel@tonic-gate cmp %g3, %g0 4557c478bd9Sstevel@tonic-gate be 8f 4567c478bd9Sstevel@tonic-gate nop 4577c478bd9Sstevel@tonic-gate 4587c478bd9Sstevel@tonic-gate /* 4597c478bd9Sstevel@tonic-gate * If the logout structure had been busy, how many times have 4607c478bd9Sstevel@tonic-gate * we tried to use it and failed (nesting count)? If we have 4617c478bd9Sstevel@tonic-gate * already recursed a substantial number of times, then we can 4627c478bd9Sstevel@tonic-gate * assume things are not going to get better by themselves and 4637c478bd9Sstevel@tonic-gate * so it would be best to panic. 4647c478bd9Sstevel@tonic-gate */ 4657c478bd9Sstevel@tonic-gate cmp %g3, CLO_NESTING_MAX 4667c478bd9Sstevel@tonic-gate blt 7f 4677c478bd9Sstevel@tonic-gate nop 4687c478bd9Sstevel@tonic-gate 4697c478bd9Sstevel@tonic-gate call ptl1_panic 4707c478bd9Sstevel@tonic-gate mov PTL1_BAD_ECC, %g1 4717c478bd9Sstevel@tonic-gate 4727c478bd9Sstevel@tonic-gate7: 4737c478bd9Sstevel@tonic-gate /* 4747c478bd9Sstevel@tonic-gate * Otherwise, if the logout structure was busy but we have not 4757c478bd9Sstevel@tonic-gate * nested more times than our maximum value, then we simply 4767c478bd9Sstevel@tonic-gate * issue a retry. Our TL=0 trap handler code will check and 4777c478bd9Sstevel@tonic-gate * clear the AFSR after it is done logging what is currently 4787c478bd9Sstevel@tonic-gate * in the logout struct and handle this event at that time. 4797c478bd9Sstevel@tonic-gate */ 4807c478bd9Sstevel@tonic-gate retry 4817c478bd9Sstevel@tonic-gate8: 4827c478bd9Sstevel@tonic-gate /* 4837c478bd9Sstevel@tonic-gate * Call cpu_fast_ecc_error via systrap at PIL 14 unless we're 4847c478bd9Sstevel@tonic-gate * already at PIL 15. 4857c478bd9Sstevel@tonic-gate */ 4867c478bd9Sstevel@tonic-gate set cpu_fast_ecc_error, %g1 4877c478bd9Sstevel@tonic-gate rdpr %pil, %g4 4887c478bd9Sstevel@tonic-gate cmp %g4, PIL_14 4897c478bd9Sstevel@tonic-gate ba sys_trap 4907c478bd9Sstevel@tonic-gate movl %icc, PIL_14, %g4 4917c478bd9Sstevel@tonic-gate 4927c478bd9Sstevel@tonic-gate SET_SIZE(fast_ecc_err) 4937c478bd9Sstevel@tonic-gate 4947c478bd9Sstevel@tonic-gate 4957c478bd9Sstevel@tonic-gate/* 4967c478bd9Sstevel@tonic-gate * Fast ECC error at TL>0 handler 4977c478bd9Sstevel@tonic-gate * We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter 4987c478bd9Sstevel@tonic-gate * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate. 4997c478bd9Sstevel@tonic-gate * For a complete description of the Fast ECC at TL>0 handling see the 5007c478bd9Sstevel@tonic-gate * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in 5017c478bd9Sstevel@tonic-gate * us3_common_asm.s 5027c478bd9Sstevel@tonic-gate */ 5037c478bd9Sstevel@tonic-gate 5047c478bd9Sstevel@tonic-gate .section ".text" 5057c478bd9Sstevel@tonic-gate .align 64 5067c478bd9Sstevel@tonic-gate ENTRY_NP(fast_ecc_tl1_err) 5077c478bd9Sstevel@tonic-gate 5087c478bd9Sstevel@tonic-gate /* 5097c478bd9Sstevel@tonic-gate * This macro turns off the D$/I$ if they are on and saves their 5107c478bd9Sstevel@tonic-gate * original state in ch_err_tl1_tmp, saves all the %g registers in the 5117c478bd9Sstevel@tonic-gate * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves 5127c478bd9Sstevel@tonic-gate * the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will 5137c478bd9Sstevel@tonic-gate * point to the ch_err_tl1_data structure and the original D$/I$ state 5147c478bd9Sstevel@tonic-gate * will be saved in ch_err_tl1_tmp. All %g registers except for %g1 5157c478bd9Sstevel@tonic-gate * will be available. 5167c478bd9Sstevel@tonic-gate */ 5177c478bd9Sstevel@tonic-gate CH_ERR_TL1_FECC_ENTER; 5187c478bd9Sstevel@tonic-gate 5197c478bd9Sstevel@tonic-gate /* 5207c478bd9Sstevel@tonic-gate * Get the diagnostic logout data. %g4 must be initialized to 5217c478bd9Sstevel@tonic-gate * current CEEN state, %g5 must point to logout structure in 5227c478bd9Sstevel@tonic-gate * ch_err_tl1_data_t. %g3 will contain the nesting count upon 5237c478bd9Sstevel@tonic-gate * return. 5247c478bd9Sstevel@tonic-gate */ 5257c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_ESTATE_ERR, %g4 5267c478bd9Sstevel@tonic-gate and %g4, EN_REG_CEEN, %g4 5277c478bd9Sstevel@tonic-gate add %g1, CH_ERR_TL1_LOGOUT, %g5 5287c478bd9Sstevel@tonic-gate DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4) 5297c478bd9Sstevel@tonic-gate 5307c478bd9Sstevel@tonic-gate /* 5317c478bd9Sstevel@tonic-gate * If the logout nesting count is exceeded, we're probably 5327c478bd9Sstevel@tonic-gate * not making any progress, try to panic instead. 5337c478bd9Sstevel@tonic-gate */ 5347c478bd9Sstevel@tonic-gate cmp %g3, CLO_NESTING_MAX 5357c478bd9Sstevel@tonic-gate bge fecc_tl1_err 5367c478bd9Sstevel@tonic-gate nop 5377c478bd9Sstevel@tonic-gate 5387c478bd9Sstevel@tonic-gate /* 5397c478bd9Sstevel@tonic-gate * Save the current CEEN and NCEEN state in %g7 and turn them off 5407c478bd9Sstevel@tonic-gate * before flushing the Ecache. 5417c478bd9Sstevel@tonic-gate */ 5427c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_ESTATE_ERR, %g7 5437c478bd9Sstevel@tonic-gate andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5 5447c478bd9Sstevel@tonic-gate stxa %g5, [%g0]ASI_ESTATE_ERR 5457c478bd9Sstevel@tonic-gate membar #Sync 5467c478bd9Sstevel@tonic-gate 5477c478bd9Sstevel@tonic-gate /* 5487c478bd9Sstevel@tonic-gate * Flush the Ecache, using the largest possible cache size with the 5497c478bd9Sstevel@tonic-gate * smallest possible line size since we can't get the actual sizes 5507c478bd9Sstevel@tonic-gate * from the cpu_node due to DTLB misses. 5517c478bd9Sstevel@tonic-gate */ 5527c478bd9Sstevel@tonic-gate set JP_ECACHE_MAX_SIZE, %g4 5537c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 5547c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_tl1_err_1); 5557c478bd9Sstevel@tonic-gate set jp_estar_tl1_data, %g6 5567c478bd9Sstevel@tonic-gate stx %g2, [%g6 + 0] 5577c478bd9Sstevel@tonic-gate stx %g3, [%g6 + 8] 5587c478bd9Sstevel@tonic-gate JP_FORCE_FULL_SPEED(%g2, %g3, %g5, %g6) 5597c478bd9Sstevel@tonic-gatefast_ecc_tl1_err_1: 5607c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 5617c478bd9Sstevel@tonic-gate ECACHE_FLUSHALL(%g4, JP_ECACHE_MAX_LSIZE, %g5, %g6) 5627c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 5637c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_tl1_err_2); 5647c478bd9Sstevel@tonic-gate JP_RESTORE_SPEED(%g2, %g3, %g5, %g6) 5657c478bd9Sstevel@tonic-gate set jp_estar_tl1_data, %g6 5667c478bd9Sstevel@tonic-gate ldx [%g6 + 0], %g2 5677c478bd9Sstevel@tonic-gate ldx [%g6 + 8], %g3 5687c478bd9Sstevel@tonic-gatefast_ecc_tl1_err_2: 5697c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 5707c478bd9Sstevel@tonic-gate 5717c478bd9Sstevel@tonic-gate /* 5727c478bd9Sstevel@tonic-gate * Restore CEEN and NCEEN to the previous state. 5737c478bd9Sstevel@tonic-gate */ 5747c478bd9Sstevel@tonic-gate stxa %g7, [%g0]ASI_ESTATE_ERR 5757c478bd9Sstevel@tonic-gate membar #Sync 5767c478bd9Sstevel@tonic-gate 5777c478bd9Sstevel@tonic-gate /* 5787c478bd9Sstevel@tonic-gate * If we turned off the D$, then flush it and turn it back on. 5797c478bd9Sstevel@tonic-gate */ 5807c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3 5817c478bd9Sstevel@tonic-gate andcc %g3, CH_ERR_TSTATE_DC_ON, %g0 5827c478bd9Sstevel@tonic-gate bz %xcc, 3f 5837c478bd9Sstevel@tonic-gate nop 5847c478bd9Sstevel@tonic-gate 5857c478bd9Sstevel@tonic-gate /* 5867c478bd9Sstevel@tonic-gate * Flush the D$. 5877c478bd9Sstevel@tonic-gate */ 5887c478bd9Sstevel@tonic-gate ASM_LD(%g4, dcache_size) 5897c478bd9Sstevel@tonic-gate ASM_LD(%g5, dcache_linesize) 5907c478bd9Sstevel@tonic-gate CH_DCACHE_FLUSHALL(%g4, %g5, %g6) 5917c478bd9Sstevel@tonic-gate 5927c478bd9Sstevel@tonic-gate /* 5937c478bd9Sstevel@tonic-gate * Turn the D$ back on. 5947c478bd9Sstevel@tonic-gate */ 5957c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_DCU, %g3 5967c478bd9Sstevel@tonic-gate or %g3, DCU_DC, %g3 5977c478bd9Sstevel@tonic-gate stxa %g3, [%g0]ASI_DCU 5987c478bd9Sstevel@tonic-gate membar #Sync 5997c478bd9Sstevel@tonic-gate3: 6007c478bd9Sstevel@tonic-gate /* 6017c478bd9Sstevel@tonic-gate * If we turned off the I$, then flush it and turn it back on. 6027c478bd9Sstevel@tonic-gate */ 6037c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3 6047c478bd9Sstevel@tonic-gate andcc %g3, CH_ERR_TSTATE_IC_ON, %g0 6057c478bd9Sstevel@tonic-gate bz %xcc, 4f 6067c478bd9Sstevel@tonic-gate nop 6077c478bd9Sstevel@tonic-gate 6087c478bd9Sstevel@tonic-gate /* 6097c478bd9Sstevel@tonic-gate * Flush the I$. 6107c478bd9Sstevel@tonic-gate */ 6117c478bd9Sstevel@tonic-gate ASM_LD(%g4, icache_size) 6127c478bd9Sstevel@tonic-gate ASM_LD(%g5, icache_linesize) 6137c478bd9Sstevel@tonic-gate CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3) 6147c478bd9Sstevel@tonic-gate 6157c478bd9Sstevel@tonic-gate /* 6167c478bd9Sstevel@tonic-gate * Turn the I$ back on. Changing DCU_IC requires flush. 6177c478bd9Sstevel@tonic-gate */ 6187c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_DCU, %g3 6197c478bd9Sstevel@tonic-gate or %g3, DCU_IC, %g3 6207c478bd9Sstevel@tonic-gate stxa %g3, [%g0]ASI_DCU 6217c478bd9Sstevel@tonic-gate flush %g0 6227c478bd9Sstevel@tonic-gate4: 6237c478bd9Sstevel@tonic-gate 6247c478bd9Sstevel@tonic-gate#ifdef TRAPTRACE 6257c478bd9Sstevel@tonic-gate /* 6267c478bd9Sstevel@tonic-gate * Get current trap trace entry physical pointer. 6277c478bd9Sstevel@tonic-gate */ 6287c478bd9Sstevel@tonic-gate CPU_INDEX(%g6, %g5) 6297c478bd9Sstevel@tonic-gate sll %g6, TRAPTR_SIZE_SHIFT, %g6 6307c478bd9Sstevel@tonic-gate set trap_trace_ctl, %g5 6317c478bd9Sstevel@tonic-gate add %g6, %g5, %g6 6327c478bd9Sstevel@tonic-gate ld [%g6 + TRAPTR_LIMIT], %g5 6337c478bd9Sstevel@tonic-gate tst %g5 6347c478bd9Sstevel@tonic-gate be %icc, skip_traptrace 6357c478bd9Sstevel@tonic-gate nop 6367c478bd9Sstevel@tonic-gate ldx [%g6 + TRAPTR_PBASE], %g5 6377c478bd9Sstevel@tonic-gate ld [%g6 + TRAPTR_OFFSET], %g4 6387c478bd9Sstevel@tonic-gate add %g5, %g4, %g5 6397c478bd9Sstevel@tonic-gate 6407c478bd9Sstevel@tonic-gate /* 6417c478bd9Sstevel@tonic-gate * Create trap trace entry. 6427c478bd9Sstevel@tonic-gate */ 6437c478bd9Sstevel@tonic-gate rd %asi, %g7 6447c478bd9Sstevel@tonic-gate wr %g0, TRAPTR_ASI, %asi 6457c478bd9Sstevel@tonic-gate rd STICK, %g4 6467c478bd9Sstevel@tonic-gate stxa %g4, [%g5 + TRAP_ENT_TICK]%asi 6477c478bd9Sstevel@tonic-gate rdpr %tl, %g4 6487c478bd9Sstevel@tonic-gate stha %g4, [%g5 + TRAP_ENT_TL]%asi 6497c478bd9Sstevel@tonic-gate rdpr %tt, %g4 6507c478bd9Sstevel@tonic-gate stha %g4, [%g5 + TRAP_ENT_TT]%asi 6517c478bd9Sstevel@tonic-gate rdpr %tpc, %g4 6527c478bd9Sstevel@tonic-gate stna %g4, [%g5 + TRAP_ENT_TPC]%asi 6537c478bd9Sstevel@tonic-gate rdpr %tstate, %g4 6547c478bd9Sstevel@tonic-gate stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi 6557c478bd9Sstevel@tonic-gate stna %sp, [%g5 + TRAP_ENT_SP]%asi 6567c478bd9Sstevel@tonic-gate stna %g0, [%g5 + TRAP_ENT_TR]%asi 6577c478bd9Sstevel@tonic-gate wr %g0, %g7, %asi 6587c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_SDW_AFAR]%asi, %g3 6597c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g4 6607c478bd9Sstevel@tonic-gate wr %g0, TRAPTR_ASI, %asi 6617c478bd9Sstevel@tonic-gate stna %g3, [%g5 + TRAP_ENT_F1]%asi 6627c478bd9Sstevel@tonic-gate stna %g4, [%g5 + TRAP_ENT_F2]%asi 6637c478bd9Sstevel@tonic-gate wr %g0, %g7, %asi 6647c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_AFAR]%asi, %g3 6657c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g4 6667c478bd9Sstevel@tonic-gate wr %g0, TRAPTR_ASI, %asi 6677c478bd9Sstevel@tonic-gate stna %g3, [%g5 + TRAP_ENT_F3]%asi 6687c478bd9Sstevel@tonic-gate stna %g4, [%g5 + TRAP_ENT_F4]%asi 6697c478bd9Sstevel@tonic-gate wr %g0, %g7, %asi 6707c478bd9Sstevel@tonic-gate 6717c478bd9Sstevel@tonic-gate /* 6727c478bd9Sstevel@tonic-gate * Advance trap trace pointer. 6737c478bd9Sstevel@tonic-gate */ 6747c478bd9Sstevel@tonic-gate ld [%g6 + TRAPTR_OFFSET], %g5 6757c478bd9Sstevel@tonic-gate ld [%g6 + TRAPTR_LIMIT], %g4 6767c478bd9Sstevel@tonic-gate st %g5, [%g6 + TRAPTR_LAST_OFFSET] 6777c478bd9Sstevel@tonic-gate add %g5, TRAP_ENT_SIZE, %g5 6787c478bd9Sstevel@tonic-gate sub %g4, TRAP_ENT_SIZE, %g4 6797c478bd9Sstevel@tonic-gate cmp %g5, %g4 6807c478bd9Sstevel@tonic-gate movge %icc, 0, %g5 6817c478bd9Sstevel@tonic-gate st %g5, [%g6 + TRAPTR_OFFSET] 6827c478bd9Sstevel@tonic-gateskip_traptrace: 6837c478bd9Sstevel@tonic-gate#endif /* TRAPTRACE */ 6847c478bd9Sstevel@tonic-gate 6857c478bd9Sstevel@tonic-gate /* 6867c478bd9Sstevel@tonic-gate * If nesting count is not zero, skip all the AFSR/AFAR 6877c478bd9Sstevel@tonic-gate * handling and just do the necessary cache-flushing. 6887c478bd9Sstevel@tonic-gate */ 6897c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_NEST_CNT]%asi, %g2 6907c478bd9Sstevel@tonic-gate brnz %g2, 6f 6917c478bd9Sstevel@tonic-gate nop 6927c478bd9Sstevel@tonic-gate 6937c478bd9Sstevel@tonic-gate /* 6947c478bd9Sstevel@tonic-gate * If a UCU followed by a WDU has occurred go ahead and panic 6957c478bd9Sstevel@tonic-gate * since a UE will occur (on the retry) before the UCU and WDU 6967c478bd9Sstevel@tonic-gate * messages are enqueued. 6977c478bd9Sstevel@tonic-gate */ 6987c478bd9Sstevel@tonic-gate ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g3 6997c478bd9Sstevel@tonic-gate set 1, %g4 7007c478bd9Sstevel@tonic-gate sllx %g4, C_AFSR_UCU_SHIFT, %g4 7017c478bd9Sstevel@tonic-gate btst %g4, %g3 ! UCU in original AFSR? 7027c478bd9Sstevel@tonic-gate bz %xcc, 6f 7037c478bd9Sstevel@tonic-gate nop 7047c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_AFSR, %g4 ! current AFSR 7057c478bd9Sstevel@tonic-gate or %g3, %g4, %g3 ! %g3 = original + current AFSR 7067c478bd9Sstevel@tonic-gate set 1, %g4 7077c478bd9Sstevel@tonic-gate sllx %g4, C_AFSR_WDU_SHIFT, %g4 7087c478bd9Sstevel@tonic-gate btst %g4, %g3 ! WDU in original or current AFSR? 7097c478bd9Sstevel@tonic-gate bnz %xcc, fecc_tl1_err 7107c478bd9Sstevel@tonic-gate nop 7117c478bd9Sstevel@tonic-gate 7127c478bd9Sstevel@tonic-gate6: 7137c478bd9Sstevel@tonic-gate /* 7147c478bd9Sstevel@tonic-gate * We fall into this macro if we've successfully logged the error in 7157c478bd9Sstevel@tonic-gate * the ch_err_tl1_data structure and want the PIL15 softint to pick 7167c478bd9Sstevel@tonic-gate * it up and log it. %g1 must point to the ch_err_tl1_data structure. 7177c478bd9Sstevel@tonic-gate * Restores the %g registers and issues retry. 7187c478bd9Sstevel@tonic-gate */ 7197c478bd9Sstevel@tonic-gate CH_ERR_TL1_EXIT; 7207c478bd9Sstevel@tonic-gate /* 7217c478bd9Sstevel@tonic-gate * Establish panic exit label. 7227c478bd9Sstevel@tonic-gate */ 7237c478bd9Sstevel@tonic-gate CH_ERR_TL1_PANIC_EXIT(fecc_tl1_err); 7247c478bd9Sstevel@tonic-gate 7257c478bd9Sstevel@tonic-gate SET_SIZE(fast_ecc_tl1_err) 7267c478bd9Sstevel@tonic-gate 7277c478bd9Sstevel@tonic-gate 7287c478bd9Sstevel@tonic-gate ENTRY(get_jbus_config) 7297c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_JBUS_CONFIG, %o0 7307c478bd9Sstevel@tonic-gate retl 7317c478bd9Sstevel@tonic-gate nop 7327c478bd9Sstevel@tonic-gate SET_SIZE(get_jbus_config) 7337c478bd9Sstevel@tonic-gate 7347c478bd9Sstevel@tonic-gate ENTRY(set_jbus_config) 7357c478bd9Sstevel@tonic-gate stxa %o0, [%g0]ASI_JBUS_CONFIG 7367c478bd9Sstevel@tonic-gate membar #Sync 7377c478bd9Sstevel@tonic-gate retl 7387c478bd9Sstevel@tonic-gate nop 7397c478bd9Sstevel@tonic-gate SET_SIZE(set_jbus_config) 7407c478bd9Sstevel@tonic-gate 7417c478bd9Sstevel@tonic-gate 7427c478bd9Sstevel@tonic-gate ENTRY(get_mcu_ctl_reg1) 7437c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_MCU_CTRL, %o0 ! MCU control reg1 is at offset 0 7447c478bd9Sstevel@tonic-gate retl 7457c478bd9Sstevel@tonic-gate nop 7467c478bd9Sstevel@tonic-gate SET_SIZE(get_mcu_ctl_reg1) 7477c478bd9Sstevel@tonic-gate 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate ENTRY(set_mcu_ctl_reg1) 7507c478bd9Sstevel@tonic-gate stxa %o0, [%g0]ASI_MCU_CTRL ! MCU control reg1 is at offset 0 7517c478bd9Sstevel@tonic-gate membar #Sync 7527c478bd9Sstevel@tonic-gate retl 7537c478bd9Sstevel@tonic-gate nop 7547c478bd9Sstevel@tonic-gate SET_SIZE(set_mcu_ctl_reg1) 7557c478bd9Sstevel@tonic-gate 7567c478bd9Sstevel@tonic-gate 7577c478bd9Sstevel@tonic-gate/* 7587c478bd9Sstevel@tonic-gate * scrubphys - Pass in the aligned physical memory address 7597c478bd9Sstevel@tonic-gate * that you want to scrub, along with the ecache set size. 7607c478bd9Sstevel@tonic-gate * 7617c478bd9Sstevel@tonic-gate * 1) Displacement flush the E$ line corresponding to %addr. 7627c478bd9Sstevel@tonic-gate * The first ldxa guarantees that the %addr is no longer in 7637c478bd9Sstevel@tonic-gate * M, O, or E (goes to I or S (if instruction fetch also happens). 7647c478bd9Sstevel@tonic-gate * 2) "Write" the data using a CAS %addr,%g0,%g0. 7657c478bd9Sstevel@tonic-gate * The casxa guarantees a transition from I to M or S to M. 7667c478bd9Sstevel@tonic-gate * 3) Displacement flush the E$ line corresponding to %addr. 7677c478bd9Sstevel@tonic-gate * The second ldxa pushes the M line out of the ecache, into the 7687c478bd9Sstevel@tonic-gate * writeback buffers, on the way to memory. 7697c478bd9Sstevel@tonic-gate * 4) The "membar #Sync" pushes the cache line out of the writeback 7707c478bd9Sstevel@tonic-gate * buffers onto the bus, on the way to dram finally. 7717c478bd9Sstevel@tonic-gate * 7727c478bd9Sstevel@tonic-gate * This is a modified version of the algorithm suggested by Gary Lauterbach. 7737c478bd9Sstevel@tonic-gate * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line 7747c478bd9Sstevel@tonic-gate * as modified, but then we found out that for spitfire, if it misses in the 7757c478bd9Sstevel@tonic-gate * E$ it will probably install as an M, but if it hits in the E$, then it 7767c478bd9Sstevel@tonic-gate * will stay E, if the store doesn't happen. So the first displacement flush 7777c478bd9Sstevel@tonic-gate * should ensure that the CAS will miss in the E$. Arrgh. 7787c478bd9Sstevel@tonic-gate */ 7797c478bd9Sstevel@tonic-gate ENTRY(scrubphys) 7807c478bd9Sstevel@tonic-gate rdpr %pstate, %o4 7817c478bd9Sstevel@tonic-gate andn %o4, PSTATE_IE | PSTATE_AM, %o5 7827c478bd9Sstevel@tonic-gate wrpr %o5, %g0, %pstate ! clear IE, AM bits 7837c478bd9Sstevel@tonic-gate 7847c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 7857c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_1); 7867c478bd9Sstevel@tonic-gate JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */ 7877c478bd9Sstevel@tonic-gatescrubphys_1: 7887c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 7897c478bd9Sstevel@tonic-gate 7907c478bd9Sstevel@tonic-gate ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3) 7917c478bd9Sstevel@tonic-gate casxa [%o0]ASI_MEM, %g0, %g0 7927c478bd9Sstevel@tonic-gate ECACHE_REFLUSH_LINE(%o1, %o2, %o3) 7937c478bd9Sstevel@tonic-gate 7947c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 7957c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_2); 7967c478bd9Sstevel@tonic-gate JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */ 7977c478bd9Sstevel@tonic-gatescrubphys_2: 7987c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 7997c478bd9Sstevel@tonic-gate 8007c478bd9Sstevel@tonic-gate wrpr %g0, %o4, %pstate ! restore earlier pstate register value 8017c478bd9Sstevel@tonic-gate 8027c478bd9Sstevel@tonic-gate retl 8037c478bd9Sstevel@tonic-gate membar #Sync ! move the data out of the load buffer 8047c478bd9Sstevel@tonic-gate SET_SIZE(scrubphys) 8057c478bd9Sstevel@tonic-gate 8067c478bd9Sstevel@tonic-gate/* 807750ba224Sanbui * clearphys - Pass in the physical memory address of the checkblock 808750ba224Sanbui * that you want to push out, cleared with a recognizable pattern, 809750ba224Sanbui * from the ecache. 810750ba224Sanbui * 811750ba224Sanbui * To ensure that the ecc gets recalculated after the bad data is cleared, 812750ba224Sanbui * we must write out enough data to fill the w$ line (64 bytes). So we read 813750ba224Sanbui * in an entire ecache subblock's worth of data, and write it back out. 814750ba224Sanbui * Then we overwrite the 16 bytes of bad data with the pattern. 8157c478bd9Sstevel@tonic-gate */ 8167c478bd9Sstevel@tonic-gate ENTRY(clearphys) 8177c478bd9Sstevel@tonic-gate /* turn off IE, AM bits */ 8187c478bd9Sstevel@tonic-gate rdpr %pstate, %o4 8197c478bd9Sstevel@tonic-gate andn %o4, PSTATE_IE | PSTATE_AM, %o5 8207c478bd9Sstevel@tonic-gate wrpr %o5, %g0, %pstate 8217c478bd9Sstevel@tonic-gate 8227c478bd9Sstevel@tonic-gate /* turn off NCEEN */ 8237c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_ESTATE_ERR, %o5 8247c478bd9Sstevel@tonic-gate andn %o5, EN_REG_NCEEN, %o3 8257c478bd9Sstevel@tonic-gate stxa %o3, [%g0]ASI_ESTATE_ERR 8267c478bd9Sstevel@tonic-gate membar #Sync 8277c478bd9Sstevel@tonic-gate 828*55fea89dSDan Cross /* align address passed with 64 bytes subblock size */ 829750ba224Sanbui mov CH_ECACHE_SUBBLK_SIZE, %o2 830750ba224Sanbui andn %o0, (CH_ECACHE_SUBBLK_SIZE - 1), %g1 831*55fea89dSDan Cross 832*55fea89dSDan Cross /* move the good data into the W$ */ 8337c478bd9Sstevel@tonic-gate1: 8347c478bd9Sstevel@tonic-gate subcc %o2, 8, %o2 835750ba224Sanbui ldxa [%g1 + %o2]ASI_MEM, %g2 8367c478bd9Sstevel@tonic-gate bge 1b 837750ba224Sanbui stxa %g2, [%g1 + %o2]ASI_MEM 838750ba224Sanbui 839750ba224Sanbui /* now overwrite the bad data */ 840750ba224Sanbui setx 0xbadecc00badecc01, %g1, %g2 841750ba224Sanbui stxa %g2, [%o0]ASI_MEM 842750ba224Sanbui mov 8, %g1 843750ba224Sanbui stxa %g2, [%o0 + %g1]ASI_MEM 8447c478bd9Sstevel@tonic-gate 8457c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 8467c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, clearphys_1); 8477c478bd9Sstevel@tonic-gate JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */ 8487c478bd9Sstevel@tonic-gateclearphys_1: 8497c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 8507c478bd9Sstevel@tonic-gate 8517c478bd9Sstevel@tonic-gate ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3) 8527c478bd9Sstevel@tonic-gate casxa [%o0]ASI_MEM, %g0, %g0 8537c478bd9Sstevel@tonic-gate ECACHE_REFLUSH_LINE(%o1, %o2, %o3) 8547c478bd9Sstevel@tonic-gate 8557c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 8567c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, clearphys_2); 8577c478bd9Sstevel@tonic-gate JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */ 8587c478bd9Sstevel@tonic-gateclearphys_2: 8597c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 8607c478bd9Sstevel@tonic-gate 8617c478bd9Sstevel@tonic-gate /* clear the AFSR */ 8627c478bd9Sstevel@tonic-gate ldxa [%g0]ASI_AFSR, %o1 8637c478bd9Sstevel@tonic-gate stxa %o1, [%g0]ASI_AFSR 8647c478bd9Sstevel@tonic-gate membar #Sync 8657c478bd9Sstevel@tonic-gate 8667c478bd9Sstevel@tonic-gate /* turn NCEEN back on */ 8677c478bd9Sstevel@tonic-gate stxa %o5, [%g0]ASI_ESTATE_ERR 8687c478bd9Sstevel@tonic-gate membar #Sync 8697c478bd9Sstevel@tonic-gate 8707c478bd9Sstevel@tonic-gate /* return and re-enable IE and AM */ 8717c478bd9Sstevel@tonic-gate retl 8727c478bd9Sstevel@tonic-gate wrpr %g0, %o4, %pstate 8737c478bd9Sstevel@tonic-gate SET_SIZE(clearphys) 8747c478bd9Sstevel@tonic-gate 8757c478bd9Sstevel@tonic-gate 8767c478bd9Sstevel@tonic-gate/* 8777c478bd9Sstevel@tonic-gate * Jalapeno Ecache displacement flush the specified line from the E$ 8787c478bd9Sstevel@tonic-gate * 8797c478bd9Sstevel@tonic-gate * Register usage: 8807c478bd9Sstevel@tonic-gate * %o0 - 64 bit physical address for flushing 8817c478bd9Sstevel@tonic-gate * %o1 - Ecache set size 8827c478bd9Sstevel@tonic-gate */ 8837c478bd9Sstevel@tonic-gate ENTRY(ecache_flush_line) 8847c478bd9Sstevel@tonic-gate 8857c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 8867c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_1); 8877c478bd9Sstevel@tonic-gate JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */ 8887c478bd9Sstevel@tonic-gateecache_flush_line_1: 8897c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 8907c478bd9Sstevel@tonic-gate 8917c478bd9Sstevel@tonic-gate ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3) 8927c478bd9Sstevel@tonic-gate 8937c478bd9Sstevel@tonic-gate#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 8947c478bd9Sstevel@tonic-gate CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_2); 8957c478bd9Sstevel@tonic-gate JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */ 8967c478bd9Sstevel@tonic-gateecache_flush_line_2: 8977c478bd9Sstevel@tonic-gate#endif /* JALAPENO && JALAPENO_ERRATA_85 */ 8987c478bd9Sstevel@tonic-gate 8997c478bd9Sstevel@tonic-gate retl 9007c478bd9Sstevel@tonic-gate nop 9017c478bd9Sstevel@tonic-gate SET_SIZE(ecache_flush_line) 9027c478bd9Sstevel@tonic-gate 9037c478bd9Sstevel@tonic-gate 9047c478bd9Sstevel@tonic-gate/* 9057c478bd9Sstevel@tonic-gate * Perform necessary cpu workaround to ensure jbus ordering. 9067c478bd9Sstevel@tonic-gate * Called only from Fire systems. 9077c478bd9Sstevel@tonic-gate * CPU's internal "invalidate FIFOs" are flushed. 9087c478bd9Sstevel@tonic-gate */ 9097c478bd9Sstevel@tonic-gate 9107c478bd9Sstevel@tonic-gate#define VIS_BLOCKSIZE 64 9117c478bd9Sstevel@tonic-gate 9127c478bd9Sstevel@tonic-gate .seg ".data" 9137c478bd9Sstevel@tonic-gate .align VIS_BLOCKSIZE 9147c478bd9Sstevel@tonic-gate .type sync_buf, #object 9157c478bd9Sstevel@tonic-gatesync_buf: 9167c478bd9Sstevel@tonic-gate .skip VIS_BLOCKSIZE 9177c478bd9Sstevel@tonic-gate .size sync_buf, VIS_BLOCKSIZE 9187c478bd9Sstevel@tonic-gate 9197c478bd9Sstevel@tonic-gate ENTRY(jbus_stst_order) 9207c478bd9Sstevel@tonic-gate set sync_buf, %o1 9217c478bd9Sstevel@tonic-gate 9227c478bd9Sstevel@tonic-gate rd %fprs, %o2 ! %o2 = saved fprs 9237c478bd9Sstevel@tonic-gate or %o2, FPRS_FEF, %o3 9247c478bd9Sstevel@tonic-gate wr %g0, %o3, %fprs ! make sure fp is enabled 9257c478bd9Sstevel@tonic-gate stda %d0, [%o1]ASI_BLK_COMMIT_P 9267c478bd9Sstevel@tonic-gate wr %o2, 0, %fprs ! restore fprs 9277c478bd9Sstevel@tonic-gate 9287c478bd9Sstevel@tonic-gate retl 9297c478bd9Sstevel@tonic-gate membar #Sync 9307c478bd9Sstevel@tonic-gate SET_SIZE(jbus_stst_order) 9317c478bd9Sstevel@tonic-gate 9327c478bd9Sstevel@tonic-gate/* 9337c478bd9Sstevel@tonic-gate * This routine will not be called in Jalapeno systems. 9347c478bd9Sstevel@tonic-gate */ 9357c478bd9Sstevel@tonic-gate ENTRY(flush_ipb) 9367c478bd9Sstevel@tonic-gate retl 9377c478bd9Sstevel@tonic-gate nop 9387c478bd9Sstevel@tonic-gate SET_SIZE(flush_ipb) 9397c478bd9Sstevel@tonic-gate 940