xref: /illumos-gate/usr/src/uts/sun4/io/px/px_var.h (revision fc256490)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
57aadd8d4Skini  * Common Development and Distribution License (the "License").
67aadd8d4Skini  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22*fc256490SJason Beloro  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate #ifndef _SYS_PX_VAR_H
277c478bd9Sstevel@tonic-gate #define	_SYS_PX_VAR_H
287c478bd9Sstevel@tonic-gate 
29817a6df8Sjchu #include <sys/callb.h>
30817a6df8Sjchu 
317c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
327c478bd9Sstevel@tonic-gate extern "C" {
337c478bd9Sstevel@tonic-gate #endif
347c478bd9Sstevel@tonic-gate 
357c478bd9Sstevel@tonic-gate /*
367c478bd9Sstevel@tonic-gate  * offsets of PCI address spaces from base address:
377c478bd9Sstevel@tonic-gate  */
38f8d2de6bSjchu #define	PX_CONFIG		0x001000000ull
397c478bd9Sstevel@tonic-gate #define	PX_A_IO			0x002000000ull
407c478bd9Sstevel@tonic-gate #define	PX_B_IO			0x002010000ull
41f8d2de6bSjchu #define	PX_A_MEMORY		0x100000000ull
42f8d2de6bSjchu #define	PX_B_MEMORY		0x180000000ull
43f8d2de6bSjchu #define	PX_IO_SIZE		0x000010000ull
44f8d2de6bSjchu #define	PX_MEM_SIZE		0x080000000ull
45f8d2de6bSjchu 
46f8d2de6bSjchu /*
47f8d2de6bSjchu  * The following typedef is used to represent a
48f8d2de6bSjchu  * 1275 "reg" property of a PCI nexus.
49f8d2de6bSjchu  */
50f8d2de6bSjchu typedef struct px_nexus_regspec {
51f8d2de6bSjchu 	uint64_t phys_addr;
52f8d2de6bSjchu 	uint64_t size;
53f8d2de6bSjchu } px_nexus_regspec_t;
54f8d2de6bSjchu 
5501689544Sjchu typedef enum {
5601689544Sjchu 	PX_ATTACHED = 1,
5701689544Sjchu 	PX_DETACHED,
5801689544Sjchu 	PX_SUSPENDED
5901689544Sjchu } px_state_t;
6001689544Sjchu 
6125cf1a30Sjl enum { PX_INTR_XBC, PX_INTR_PEC, PX_INTR_HOTPLUG };
627c478bd9Sstevel@tonic-gate 
637c478bd9Sstevel@tonic-gate #define	PX_ATTACH_RETCODE(obj, op, err) \
647c478bd9Sstevel@tonic-gate 	((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS)
657c478bd9Sstevel@tonic-gate 
667c478bd9Sstevel@tonic-gate /*
677c478bd9Sstevel@tonic-gate  * px soft state structure:
687c478bd9Sstevel@tonic-gate  *
697c478bd9Sstevel@tonic-gate  * Each px node has a px soft state structure.
707c478bd9Sstevel@tonic-gate  */
717c478bd9Sstevel@tonic-gate struct px {
727c478bd9Sstevel@tonic-gate 	/*
737c478bd9Sstevel@tonic-gate 	 * State flags and mutex:
747c478bd9Sstevel@tonic-gate 	 */
757c478bd9Sstevel@tonic-gate 	px_state_t px_state;
767c478bd9Sstevel@tonic-gate 	uint_t px_soft_state;
777c478bd9Sstevel@tonic-gate 	kmutex_t px_mutex;
787c478bd9Sstevel@tonic-gate 
797c478bd9Sstevel@tonic-gate 	/*
807c478bd9Sstevel@tonic-gate 	 * Links to other state structures:
817c478bd9Sstevel@tonic-gate 	 */
827c478bd9Sstevel@tonic-gate 	dev_info_t *px_dip;		/* devinfo structure */
837c478bd9Sstevel@tonic-gate 	devhandle_t px_dev_hdl;		/* device handle */
8401689544Sjchu 	px_ib_t *px_ib_p;		/* interrupt block */
857c478bd9Sstevel@tonic-gate 	px_pec_t *px_pec_p;		/* PEC block */
867c478bd9Sstevel@tonic-gate 	px_mmu_t *px_mmu_p;		/* IOMMU block */
877c478bd9Sstevel@tonic-gate 
887c478bd9Sstevel@tonic-gate 	/*
897c478bd9Sstevel@tonic-gate 	 * px device node properties:
907c478bd9Sstevel@tonic-gate 	 */
917ea9b230Set 	pcie_req_id_t px_bdf;
9226947304SEvan Yan 	pci_bus_range_t px_bus_range;	/* "bus-range" */
9326947304SEvan Yan 	pci_ranges_t *px_ranges_p;	/* "ranges" data & length */
947c478bd9Sstevel@tonic-gate 	int px_ranges_length;
957c478bd9Sstevel@tonic-gate 	devino_t *px_inos;		/* inos from "interrupts" prop */
967c478bd9Sstevel@tonic-gate 	int px_inos_len;		/* "interrupts" length */
977c478bd9Sstevel@tonic-gate 
987c478bd9Sstevel@tonic-gate 	/* Error handling */
9901689544Sjchu 	px_fault_t	px_fault;
10001689544Sjchu 	px_fault_t	px_cb_fault;
1017c478bd9Sstevel@tonic-gate 
1027c478bd9Sstevel@tonic-gate 	/* FMA */
10301689544Sjchu 	int		px_fm_cap;
10401689544Sjchu 	kmutex_t	px_fm_mutex;
105c2a75729Sdwoods 	kthread_t	*px_fm_mutex_owner;
1067c478bd9Sstevel@tonic-gate 	ddi_iblock_cookie_t px_fm_ibc;
107eae2e508Skrishnae 	pf_data_t	px_pfd_arr[5];
108eae2e508Skrishnae 	int		px_pfd_idx;
1097c478bd9Sstevel@tonic-gate 
110b65731f1Skini 	uint32_t	px_dev_caps;
111b65731f1Skini 
1127c478bd9Sstevel@tonic-gate 	/* Platform specific information */
113eae2e508Skrishnae 	void		*px_plat_p;
1141a887b2eSjchu 
115*fc256490SJason Beloro 	/* Interrupt types supported by the fabric */
116*fc256490SJason Beloro 	int		px_supp_intr_types;
117*fc256490SJason Beloro 
1181a887b2eSjchu 	/* Power Management fields */
1191a887b2eSjchu 	kmutex_t	px_l23ready_lock; /* used in PME_To_ACK interrupt */
1201a887b2eSjchu 	kcondvar_t	px_l23ready_cv;	/* used in PME_TO_ACK timeout */
121f9721e07Sjchu 	volatile uint32_t	px_lup_pending;
1221a887b2eSjchu 	int		px_pm_flags;
1231a887b2eSjchu 	msiqid_t	px_pm_msiq_id;	/* EQ id for PCIE_PME_ACK_MSG Message */
1241a887b2eSjchu 	uint32_t	px_pmetoack_ignored; /* count of PME_To_ACKs ignored */
1251a887b2eSjchu 
126817a6df8Sjchu 	/* CPR callback id */
127817a6df8Sjchu 	callb_id_t	px_cprcb_id;
12822bbbd20Saa 	uint32_t	px_dma_sync_opt; /* DMA syncing req. of hw */
129bf8fc234Set 
130bf8fc234Set 	/* Handle for soft intr */
131bf8fc234Set 	ddi_softint_handle_t    px_dbg_hdl; /* HDL for dbg printing */
1327c478bd9Sstevel@tonic-gate };
1337c478bd9Sstevel@tonic-gate 
134b65731f1Skini /* px_dev_caps definition */
13522bbbd20Saa #define	PX_BYPASS_DMA_ALLOWED		1
13622bbbd20Saa #define	PX_DMA_SYNC_REQUIRED		4
1377c478bd9Sstevel@tonic-gate 
1383ee8f295Smg /* px_pm_flags definitions used with interrupts and FMA code */
1393ee8f295Smg #define	PX_PMETOACK_RECVD		0x01 /* With PME_To_ACK interrupt */
1403ee8f295Smg #define	PX_PME_TURNOFF_PENDING		0x02 /* With PME_To_ACK interrupt */
141f9721e07Sjchu #define	PX_LDN_EXPECTED			0x04 /* With FMA code */
1421a887b2eSjchu 
1437c478bd9Sstevel@tonic-gate #define	DIP_TO_INST(dip)	ddi_get_instance(dip)
1447c478bd9Sstevel@tonic-gate #define	INST_TO_STATE(inst)	ddi_get_soft_state(px_state_p, inst)
1457c478bd9Sstevel@tonic-gate #define	DIP_TO_STATE(dip)	INST_TO_STATE(DIP_TO_INST(dip))
1467c478bd9Sstevel@tonic-gate 
14736fe4a92Segillett #define	PX_DEV_TO_SOFTSTATE(dev)	((px_t *)ddi_get_soft_state( \
14826947304SEvan Yan 	px_state_p, PCI_MINOR_NUM_TO_INSTANCE(getminor(dev))))
1497c478bd9Sstevel@tonic-gate 
1507c478bd9Sstevel@tonic-gate extern void *px_state_p;
1517c478bd9Sstevel@tonic-gate 
1527c478bd9Sstevel@tonic-gate /*
1537c478bd9Sstevel@tonic-gate  * function prototypes for bus ops routines:
1547c478bd9Sstevel@tonic-gate  */
1557c478bd9Sstevel@tonic-gate extern int
1567c478bd9Sstevel@tonic-gate px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
1577c478bd9Sstevel@tonic-gate 	off_t offset, off_t len, caddr_t *addrp);
1587c478bd9Sstevel@tonic-gate extern int
1597c478bd9Sstevel@tonic-gate px_dma_setup(dev_info_t *dip, dev_info_t *rdip,
1607c478bd9Sstevel@tonic-gate 	ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep);
1617c478bd9Sstevel@tonic-gate extern int
1627c478bd9Sstevel@tonic-gate px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
1637c478bd9Sstevel@tonic-gate 	int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep);
1647c478bd9Sstevel@tonic-gate extern int
1657c478bd9Sstevel@tonic-gate px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
1667c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
1677c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t *cookiep, uint_t *ccountp);
1687c478bd9Sstevel@tonic-gate extern int
1697c478bd9Sstevel@tonic-gate px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip,
1707c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t handle);
1717c478bd9Sstevel@tonic-gate extern int
1727c478bd9Sstevel@tonic-gate px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
1737c478bd9Sstevel@tonic-gate 	enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
1747c478bd9Sstevel@tonic-gate 	uint_t cache_flags);
1757c478bd9Sstevel@tonic-gate extern int
1767c478bd9Sstevel@tonic-gate px_ctlops(dev_info_t *dip, dev_info_t *rdip,
1777c478bd9Sstevel@tonic-gate 	ddi_ctl_enum_t op, void *arg, void *result);
1787c478bd9Sstevel@tonic-gate extern int
1797c478bd9Sstevel@tonic-gate px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
1807c478bd9Sstevel@tonic-gate 	ddi_intr_handle_impl_t *handle, void *result);
1817c478bd9Sstevel@tonic-gate 
1827c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
1837c478bd9Sstevel@tonic-gate }
1847c478bd9Sstevel@tonic-gate #endif
1857c478bd9Sstevel@tonic-gate 
1867c478bd9Sstevel@tonic-gate #endif	/* _SYS_PX_VAR_H */
187