17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate * CDDL HEADER START
37c478bd9Sstevel@tonic-gate *
47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
51de45cd9Sgovinda * Common Development and Distribution License (the "License").
61de45cd9Sgovinda * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate *
87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate * and limitations under the License.
127c478bd9Sstevel@tonic-gate *
137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate *
197c478bd9Sstevel@tonic-gate * CDDL HEADER END
207c478bd9Sstevel@tonic-gate */
217c478bd9Sstevel@tonic-gate /*
2289b42a21Sandrew.rutz@sun.com * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23*cd21e7c5SGarrett D'Amore * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
247c478bd9Sstevel@tonic-gate */
257c478bd9Sstevel@tonic-gate
267c478bd9Sstevel@tonic-gate /*
277c478bd9Sstevel@tonic-gate * PX mmu initialization and configuration
287c478bd9Sstevel@tonic-gate */
297c478bd9Sstevel@tonic-gate #include <sys/types.h>
307c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
317c478bd9Sstevel@tonic-gate #include <sys/async.h>
327c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h>
337c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
347c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h>
357c478bd9Sstevel@tonic-gate #include <sys/vmem.h>
367c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* lddphys() */
377c478bd9Sstevel@tonic-gate #include <sys/iommutsb.h>
387c478bd9Sstevel@tonic-gate #include "px_obj.h"
397c478bd9Sstevel@tonic-gate
407c478bd9Sstevel@tonic-gate int
px_mmu_attach(px_t * px_p)417c478bd9Sstevel@tonic-gate px_mmu_attach(px_t *px_p)
427c478bd9Sstevel@tonic-gate {
437c478bd9Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip;
447c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p;
451f7be8d9Sdanice uint32_t tsb_i = 0;
467c478bd9Sstevel@tonic-gate char map_name[32];
477c478bd9Sstevel@tonic-gate px_dvma_range_prop_t *dvma_prop;
487c478bd9Sstevel@tonic-gate int dvma_prop_len;
497c478bd9Sstevel@tonic-gate uint32_t cache_size, tsb_entries;
507c478bd9Sstevel@tonic-gate
517c478bd9Sstevel@tonic-gate /*
527c478bd9Sstevel@tonic-gate * Allocate mmu state structure and link it to the
537c478bd9Sstevel@tonic-gate * px state structure.
547c478bd9Sstevel@tonic-gate */
557c478bd9Sstevel@tonic-gate mmu_p = kmem_zalloc(sizeof (px_mmu_t), KM_SLEEP);
567c478bd9Sstevel@tonic-gate if (mmu_p == NULL)
577c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
587c478bd9Sstevel@tonic-gate
597c478bd9Sstevel@tonic-gate px_p->px_mmu_p = mmu_p;
607c478bd9Sstevel@tonic-gate mmu_p->mmu_px_p = px_p;
617c478bd9Sstevel@tonic-gate mmu_p->mmu_inst = ddi_get_instance(dip);
627c478bd9Sstevel@tonic-gate
637c478bd9Sstevel@tonic-gate /*
647c478bd9Sstevel@tonic-gate * Check for "virtual-dma" property that specifies
657c478bd9Sstevel@tonic-gate * the DVMA range.
667c478bd9Sstevel@tonic-gate */
677c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
687c478bd9Sstevel@tonic-gate "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) !=
697c478bd9Sstevel@tonic-gate DDI_PROP_SUCCESS) {
707c478bd9Sstevel@tonic-gate
717c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "Getting virtual-dma failed\n");
727c478bd9Sstevel@tonic-gate
737c478bd9Sstevel@tonic-gate kmem_free(mmu_p, sizeof (px_mmu_t));
747c478bd9Sstevel@tonic-gate px_p->px_mmu_p = NULL;
757c478bd9Sstevel@tonic-gate
767c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
777c478bd9Sstevel@tonic-gate }
787c478bd9Sstevel@tonic-gate
797c478bd9Sstevel@tonic-gate mmu_p->mmu_dvma_base = dvma_prop->dvma_base;
807c478bd9Sstevel@tonic-gate mmu_p->mmu_dvma_end = dvma_prop->dvma_base +
817c478bd9Sstevel@tonic-gate (dvma_prop->dvma_len - 1);
82a2ca053eSkrishnae tsb_entries = MMU_BTOP(dvma_prop->dvma_len);
837c478bd9Sstevel@tonic-gate
847c478bd9Sstevel@tonic-gate kmem_free(dvma_prop, dvma_prop_len);
857c478bd9Sstevel@tonic-gate
867c478bd9Sstevel@tonic-gate /*
877c478bd9Sstevel@tonic-gate * Setup base and bounds for DVMA and bypass mappings.
887c478bd9Sstevel@tonic-gate */
897c478bd9Sstevel@tonic-gate mmu_p->mmu_dvma_cache_locks =
90d8d130aeSanbui kmem_zalloc(px_dvma_page_cache_entries, KM_SLEEP);
917c478bd9Sstevel@tonic-gate
927c478bd9Sstevel@tonic-gate mmu_p->dvma_base_pg = MMU_BTOP(mmu_p->mmu_dvma_base);
937c478bd9Sstevel@tonic-gate mmu_p->mmu_dvma_reserve = tsb_entries >> 1;
947c478bd9Sstevel@tonic-gate mmu_p->dvma_end_pg = MMU_BTOP(mmu_p->mmu_dvma_end);
957c478bd9Sstevel@tonic-gate
967c478bd9Sstevel@tonic-gate /*
977c478bd9Sstevel@tonic-gate * Create a virtual memory map for dvma address space.
987c478bd9Sstevel@tonic-gate * Reserve 'size' bytes of low dvma space for fast track cache.
997c478bd9Sstevel@tonic-gate */
1007c478bd9Sstevel@tonic-gate (void) snprintf(map_name, sizeof (map_name), "%s%d_dvma",
1017c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip));
1027c478bd9Sstevel@tonic-gate
1037c478bd9Sstevel@tonic-gate cache_size = MMU_PTOB(px_dvma_page_cache_entries *
104d8d130aeSanbui px_dvma_page_cache_clustsz);
1057c478bd9Sstevel@tonic-gate mmu_p->mmu_dvma_fast_end = mmu_p->mmu_dvma_base +
106d8d130aeSanbui cache_size - 1;
1077c478bd9Sstevel@tonic-gate
1087c478bd9Sstevel@tonic-gate mmu_p->mmu_dvma_map = vmem_create(map_name,
1097c478bd9Sstevel@tonic-gate (void *)(mmu_p->mmu_dvma_fast_end + 1),
110a2ca053eSkrishnae MMU_PTOB(tsb_entries) - cache_size, MMU_PAGE_SIZE,
1117c478bd9Sstevel@tonic-gate NULL, NULL, NULL, MMU_PAGE_SIZE, VM_SLEEP);
1127c478bd9Sstevel@tonic-gate
1137c478bd9Sstevel@tonic-gate mutex_init(&mmu_p->dvma_debug_lock, NULL, MUTEX_DRIVER, NULL);
1147c478bd9Sstevel@tonic-gate
1151f7be8d9Sdanice for (tsb_i = 0; tsb_i < tsb_entries; tsb_i++) {
1167c478bd9Sstevel@tonic-gate r_addr_t ra = 0;
1177c478bd9Sstevel@tonic-gate io_attributes_t attr;
1187c478bd9Sstevel@tonic-gate caddr_t va;
1197c478bd9Sstevel@tonic-gate
1201f7be8d9Sdanice if (px_lib_iommu_getmap(px_p->px_dip, PCI_TSBID(0, tsb_i),
1211f7be8d9Sdanice &attr, &ra) != DDI_SUCCESS)
1221f7be8d9Sdanice continue;
1231f7be8d9Sdanice
1241f7be8d9Sdanice va = (caddr_t)(MMU_PTOB(mmu_p->dvma_base_pg + tsb_i));
1251f7be8d9Sdanice
1261f7be8d9Sdanice if (va <= (caddr_t)mmu_p->mmu_dvma_fast_end) {
1271f7be8d9Sdanice uint32_t cache_i;
1281f7be8d9Sdanice
1291f7be8d9Sdanice /*
1301f7be8d9Sdanice * the va is within the *fast* dvma range; therefore,
1311f7be8d9Sdanice * lock its fast dvma page cache cluster in order to
1321f7be8d9Sdanice * both preserve the TTE and prevent the use of this
1331f7be8d9Sdanice * fast dvma page cache cluster by px_dvma_map_fast().
1341f7be8d9Sdanice * the lock value 0xFF comes from ldstub().
1351f7be8d9Sdanice */
1361f7be8d9Sdanice cache_i = tsb_i / px_dvma_page_cache_clustsz;
1371f7be8d9Sdanice ASSERT(cache_i < px_dvma_page_cache_entries);
1381f7be8d9Sdanice mmu_p->mmu_dvma_cache_locks[cache_i] = 0xFF;
1391f7be8d9Sdanice } else {
1407c478bd9Sstevel@tonic-gate (void) vmem_xalloc(mmu_p->mmu_dvma_map, MMU_PAGE_SIZE,
1417c478bd9Sstevel@tonic-gate MMU_PAGE_SIZE, 0, 0, va, va + MMU_PAGE_SIZE,
1427c478bd9Sstevel@tonic-gate VM_NOSLEEP | VM_BESTFIT | VM_PANIC);
1437c478bd9Sstevel@tonic-gate }
1447c478bd9Sstevel@tonic-gate }
1457c478bd9Sstevel@tonic-gate
1467c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
1477c478bd9Sstevel@tonic-gate }
1487c478bd9Sstevel@tonic-gate
1497c478bd9Sstevel@tonic-gate void
px_mmu_detach(px_t * px_p)1507c478bd9Sstevel@tonic-gate px_mmu_detach(px_t *px_p)
1517c478bd9Sstevel@tonic-gate {
1527c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p;
1537c478bd9Sstevel@tonic-gate
15489b42a21Sandrew.rutz@sun.com (void) px_lib_iommu_detach(px_p);
15589b42a21Sandrew.rutz@sun.com
1567c478bd9Sstevel@tonic-gate /*
1577c478bd9Sstevel@tonic-gate * Free the dvma resource map.
1587c478bd9Sstevel@tonic-gate */
1597c478bd9Sstevel@tonic-gate vmem_destroy(mmu_p->mmu_dvma_map);
1607c478bd9Sstevel@tonic-gate
1617c478bd9Sstevel@tonic-gate kmem_free(mmu_p->mmu_dvma_cache_locks,
1627c478bd9Sstevel@tonic-gate px_dvma_page_cache_entries);
1637c478bd9Sstevel@tonic-gate
16436fe4a92Segillett if (PX_DVMA_DBG_ON(mmu_p))
1657c478bd9Sstevel@tonic-gate px_dvma_debug_fini(mmu_p);
1667c478bd9Sstevel@tonic-gate
1677c478bd9Sstevel@tonic-gate mutex_destroy(&mmu_p->dvma_debug_lock);
1687c478bd9Sstevel@tonic-gate
1697c478bd9Sstevel@tonic-gate /*
1707c478bd9Sstevel@tonic-gate * Free the mmu state structure.
1717c478bd9Sstevel@tonic-gate */
1727c478bd9Sstevel@tonic-gate kmem_free(mmu_p, sizeof (px_mmu_t));
1737c478bd9Sstevel@tonic-gate px_p->px_mmu_p = NULL;
1747c478bd9Sstevel@tonic-gate }
1757c478bd9Sstevel@tonic-gate
176b40cec45Skrishnae int
px_mmu_map_pages(px_mmu_t * mmu_p,ddi_dma_impl_t * mp,px_dvma_addr_t dvma_pg,size_t npages,size_t pfn_index)1777c478bd9Sstevel@tonic-gate px_mmu_map_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg,
1787c478bd9Sstevel@tonic-gate size_t npages, size_t pfn_index)
1797c478bd9Sstevel@tonic-gate {
1807c478bd9Sstevel@tonic-gate dev_info_t *dip = mmu_p->mmu_px_p->px_dip;
1817c478bd9Sstevel@tonic-gate px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg);
1827c478bd9Sstevel@tonic-gate io_attributes_t attr = PX_GET_MP_TTE(mp->dmai_tte);
1837c478bd9Sstevel@tonic-gate
1847c478bd9Sstevel@tonic-gate ASSERT(npages <= mp->dmai_ndvmapages);
1851de45cd9Sgovinda DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages:%x+%x=%x "
1861de45cd9Sgovinda "npages=0x%x pfn_index=0x%x\n", (uint_t)mmu_p->dvma_base_pg,
1871de45cd9Sgovinda (uint_t)pg_index, dvma_pg, (uint_t)npages, (uint_t)pfn_index);
1887c478bd9Sstevel@tonic-gate
18944961713Sgirish if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages,
19044961713Sgirish PX_ADD_ATTR_EXTNS(attr, mp->dmai_bdf), (void *)mp, pfn_index,
19144961713Sgirish MMU_MAP_PFN) != DDI_SUCCESS) {
1921de45cd9Sgovinda DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: "
1931de45cd9Sgovinda "px_lib_iommu_map failed\n");
1947c478bd9Sstevel@tonic-gate
1951de45cd9Sgovinda return (DDI_FAILURE);
1961de45cd9Sgovinda }
1971de45cd9Sgovinda
1981de45cd9Sgovinda if (!PX_MAP_BUFZONE(mp))
1991de45cd9Sgovinda goto done;
2001de45cd9Sgovinda
2011de45cd9Sgovinda DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: redzone pg=%x\n",
2021de45cd9Sgovinda pg_index + npages);
2031de45cd9Sgovinda
2041de45cd9Sgovinda ASSERT(PX_HAS_REDZONE(mp));
2051de45cd9Sgovinda
20644961713Sgirish if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index + npages), 1,
20744961713Sgirish PX_ADD_ATTR_EXTNS(attr, mp->dmai_bdf), (void *)mp,
20844961713Sgirish pfn_index + npages - 1, MMU_MAP_PFN) != DDI_SUCCESS) {
2091de45cd9Sgovinda DBG(DBG_MAP_WIN, dip, "px_mmu_map_pages: mapping "
2101de45cd9Sgovinda "REDZONE page failed\n");
2111de45cd9Sgovinda
212d8d130aeSanbui if (px_lib_iommu_demap(dip, PCI_TSBID(0, pg_index), npages)
213d8d130aeSanbui != DDI_SUCCESS) {
214d8d130aeSanbui DBG(DBG_MAP_WIN, dip, "px_lib_iommu_demap: failed\n");
215d8d130aeSanbui }
2161de45cd9Sgovinda return (DDI_FAILURE);
2177c478bd9Sstevel@tonic-gate }
2187c478bd9Sstevel@tonic-gate
2191de45cd9Sgovinda done:
22036fe4a92Segillett if (PX_DVMA_DBG_ON(mmu_p))
2217c478bd9Sstevel@tonic-gate px_dvma_alloc_debug(mmu_p, (char *)mp->dmai_mapping,
2227c478bd9Sstevel@tonic-gate mp->dmai_size, mp);
2237c478bd9Sstevel@tonic-gate
2241de45cd9Sgovinda return (DDI_SUCCESS);
2257c478bd9Sstevel@tonic-gate }
2267c478bd9Sstevel@tonic-gate
2277c478bd9Sstevel@tonic-gate void
px_mmu_unmap_pages(px_mmu_t * mmu_p,ddi_dma_impl_t * mp,px_dvma_addr_t dvma_pg,uint_t npages)2281de45cd9Sgovinda px_mmu_unmap_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg,
2291de45cd9Sgovinda uint_t npages)
2307c478bd9Sstevel@tonic-gate {
2317c478bd9Sstevel@tonic-gate px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg);
2327c478bd9Sstevel@tonic-gate
2337c478bd9Sstevel@tonic-gate DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
2341de45cd9Sgovinda "px_mmu_unmap_pages:%x+%x=%x npages=0x%x\n",
2351de45cd9Sgovinda (uint_t)mmu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg,
2361de45cd9Sgovinda (uint_t)npages);
2377c478bd9Sstevel@tonic-gate
238d8d130aeSanbui if (px_lib_iommu_demap(mmu_p->mmu_px_p->px_dip,
239d8d130aeSanbui PCI_TSBID(0, pg_index), npages) != DDI_SUCCESS) {
240d8d130aeSanbui DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
241d8d130aeSanbui "px_lib_iommu_demap: failed\n");
242d8d130aeSanbui }
2431de45cd9Sgovinda
2441de45cd9Sgovinda if (!PX_MAP_BUFZONE(mp))
2451de45cd9Sgovinda return;
2461de45cd9Sgovinda
247d8d130aeSanbui DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip, "px_mmu_unmap_pages: "
2481de45cd9Sgovinda "redzone pg=%x\n", pg_index + npages);
2491de45cd9Sgovinda
2501de45cd9Sgovinda ASSERT(PX_HAS_REDZONE(mp));
2511de45cd9Sgovinda
252d8d130aeSanbui if (px_lib_iommu_demap(mmu_p->mmu_px_p->px_dip,
253d8d130aeSanbui PCI_TSBID(0, pg_index + npages), 1) != DDI_SUCCESS) {
254d8d130aeSanbui DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip,
255d8d130aeSanbui "px_lib_iommu_demap: failed\n");
256d8d130aeSanbui }
2577c478bd9Sstevel@tonic-gate }
2587c478bd9Sstevel@tonic-gate
2597c478bd9Sstevel@tonic-gate /*
2607c478bd9Sstevel@tonic-gate * px_mmu_map_window - map a dvma window into the mmu
261*cd21e7c5SGarrett D'Amore * used by: px_dma_win()
2627c478bd9Sstevel@tonic-gate * return value: none
2637c478bd9Sstevel@tonic-gate */
2647c478bd9Sstevel@tonic-gate /*ARGSUSED*/
2657c478bd9Sstevel@tonic-gate int
px_mmu_map_window(px_mmu_t * mmu_p,ddi_dma_impl_t * mp,px_window_t win_no)2667c478bd9Sstevel@tonic-gate px_mmu_map_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_window_t win_no)
2677c478bd9Sstevel@tonic-gate {
2687c478bd9Sstevel@tonic-gate uint32_t obj_pg0_off = mp->dmai_roffset;
2697c478bd9Sstevel@tonic-gate uint32_t win_pg0_off = win_no ? 0 : obj_pg0_off;
2707c478bd9Sstevel@tonic-gate size_t win_size = mp->dmai_winsize;
2717c478bd9Sstevel@tonic-gate size_t pfn_index = win_size * win_no; /* temp value */
2727c478bd9Sstevel@tonic-gate size_t obj_off = win_no ? pfn_index - obj_pg0_off : 0; /* xferred sz */
2737c478bd9Sstevel@tonic-gate px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping);
2747c478bd9Sstevel@tonic-gate size_t res_size = mp->dmai_object.dmao_size - obj_off + win_pg0_off;
2757c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS;
2767c478bd9Sstevel@tonic-gate
2777c478bd9Sstevel@tonic-gate ASSERT(!(win_size & MMU_PAGE_OFFSET));
2787c478bd9Sstevel@tonic-gate if (win_no >= mp->dmai_nwin)
2797c478bd9Sstevel@tonic-gate return (ret);
2807c478bd9Sstevel@tonic-gate if (res_size < win_size) /* last window */
2817c478bd9Sstevel@tonic-gate win_size = res_size; /* mp->dmai_winsize unchanged */
2827c478bd9Sstevel@tonic-gate
2837c478bd9Sstevel@tonic-gate mp->dmai_mapping = MMU_PTOB(dvma_pg) | win_pg0_off;
2847c478bd9Sstevel@tonic-gate mp->dmai_size = win_size - win_pg0_off; /* cur win xferrable size */
2857c478bd9Sstevel@tonic-gate mp->dmai_offset = obj_off; /* win offset into object */
2867c478bd9Sstevel@tonic-gate pfn_index = MMU_BTOP(pfn_index); /* index into pfnlist */
2877c478bd9Sstevel@tonic-gate ret = px_mmu_map_pages(mmu_p, mp, dvma_pg, MMU_BTOPR(win_size),
2887c478bd9Sstevel@tonic-gate pfn_index);
2897c478bd9Sstevel@tonic-gate
2907c478bd9Sstevel@tonic-gate return (ret);
2917c478bd9Sstevel@tonic-gate }
2927c478bd9Sstevel@tonic-gate
2937c478bd9Sstevel@tonic-gate /*
2947c478bd9Sstevel@tonic-gate * px_mmu_unmap_window
2957c478bd9Sstevel@tonic-gate * This routine is called to break down the mmu mappings to a dvma window.
2967c478bd9Sstevel@tonic-gate * Non partial mappings are viewed as single window mapping.
2977c478bd9Sstevel@tonic-gate * used by: px_dma_unbindhdl(), px_dma_window(),
2987c478bd9Sstevel@tonic-gate * and px_dma_ctlops() - DDI_DMA_FREE, DDI_DMA_MOVWIN, DDI_DMA_NEXTWIN
2997c478bd9Sstevel@tonic-gate * return value: none
3007c478bd9Sstevel@tonic-gate */
3017c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3027c478bd9Sstevel@tonic-gate void
px_mmu_unmap_window(px_mmu_t * mmu_p,ddi_dma_impl_t * mp)3037c478bd9Sstevel@tonic-gate px_mmu_unmap_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp)
3047c478bd9Sstevel@tonic-gate {
3057c478bd9Sstevel@tonic-gate px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping);
3067c478bd9Sstevel@tonic-gate uint_t npages = MMU_BTOP(mp->dmai_winsize);
3077c478bd9Sstevel@tonic-gate
3081de45cd9Sgovinda px_mmu_unmap_pages(mmu_p, mp, dvma_pg, npages);
3097c478bd9Sstevel@tonic-gate
31036fe4a92Segillett if (PX_DVMA_DBG_ON(mmu_p))
3117c478bd9Sstevel@tonic-gate px_dvma_free_debug(mmu_p, (char *)mp->dmai_mapping,
3127c478bd9Sstevel@tonic-gate mp->dmai_size, mp);
3137c478bd9Sstevel@tonic-gate }
3147c478bd9Sstevel@tonic-gate
3157c478bd9Sstevel@tonic-gate
3167c478bd9Sstevel@tonic-gate #if 0
3177c478bd9Sstevel@tonic-gate /*
3187c478bd9Sstevel@tonic-gate * The following table is for reference only. It denotes the
3197c478bd9Sstevel@tonic-gate * the TSB table size measured in number of 8 byte entries.
3207c478bd9Sstevel@tonic-gate * It is represented by bits 3:0 in the MMU TSB CTRL REG.
3217c478bd9Sstevel@tonic-gate */
3227c478bd9Sstevel@tonic-gate static int px_mmu_tsb_sizes[] = {
3237c478bd9Sstevel@tonic-gate 0x0, /* 1K */
3247c478bd9Sstevel@tonic-gate 0x1, /* 2K */
3257c478bd9Sstevel@tonic-gate 0x2, /* 4K */
3267c478bd9Sstevel@tonic-gate 0x3, /* 8K */
3277c478bd9Sstevel@tonic-gate 0x4, /* 16K */
3287c478bd9Sstevel@tonic-gate 0x5, /* 32K */
3297c478bd9Sstevel@tonic-gate 0x6, /* 64K */
3307c478bd9Sstevel@tonic-gate 0x7, /* 128K */
3317c478bd9Sstevel@tonic-gate 0x8 /* 256K */
3327c478bd9Sstevel@tonic-gate };
3337c478bd9Sstevel@tonic-gate #endif
3347c478bd9Sstevel@tonic-gate
3357c478bd9Sstevel@tonic-gate static char *px_mmu_errsts[] = {
3367c478bd9Sstevel@tonic-gate "Protection Error", "Invalid Error", "Timeout", "ECC Error(UE)"
3377c478bd9Sstevel@tonic-gate };
3387c478bd9Sstevel@tonic-gate
3397c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3407c478bd9Sstevel@tonic-gate static int
px_log_mmu_err(px_t * px_p)3417c478bd9Sstevel@tonic-gate px_log_mmu_err(px_t *px_p)
3427c478bd9Sstevel@tonic-gate {
3437c478bd9Sstevel@tonic-gate /*
3447c478bd9Sstevel@tonic-gate * Place holder, the correct eror bits need tobe logged.
3457c478bd9Sstevel@tonic-gate */
3467c478bd9Sstevel@tonic-gate return (0);
3477c478bd9Sstevel@tonic-gate }
348