17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5102cb92eSjohnny * Common Development and Distribution License (the "License"). 6102cb92eSjohnny * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22102cb92eSjohnny * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate /* 297c478bd9Sstevel@tonic-gate * PX nexus interrupt handling: 307c478bd9Sstevel@tonic-gate * PX device interrupt handler wrapper 317c478bd9Sstevel@tonic-gate * PIL lookup routine 327c478bd9Sstevel@tonic-gate * PX device interrupt related initchild code 337c478bd9Sstevel@tonic-gate */ 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate #include <sys/types.h> 367c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 377c478bd9Sstevel@tonic-gate #include <sys/async.h> 387c478bd9Sstevel@tonic-gate #include <sys/spl.h> 397c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 40f8d2de6bSjchu #include <sys/fm/protocol.h> 41f8d2de6bSjchu #include <sys/fm/util.h> 427c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 437c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 447c478bd9Sstevel@tonic-gate #include <sys/sdt.h> 457c478bd9Sstevel@tonic-gate #include <sys/atomic.h> 467c478bd9Sstevel@tonic-gate #include "px_obj.h" 47f8d2de6bSjchu #include <sys/ontrap.h> 48f8d2de6bSjchu #include <sys/membar.h> 496d44af1bSesolom #include <sys/clock.h> 507c478bd9Sstevel@tonic-gate 517c478bd9Sstevel@tonic-gate /* 527c478bd9Sstevel@tonic-gate * interrupt jabber: 537c478bd9Sstevel@tonic-gate * 547c478bd9Sstevel@tonic-gate * When an interrupt line is jabbering, every time the state machine for the 557c478bd9Sstevel@tonic-gate * associated ino is idled, a new mondo will be sent and the ino will go into 567c478bd9Sstevel@tonic-gate * the pending state again. The mondo will cause a new call to 577c478bd9Sstevel@tonic-gate * px_intr_wrapper() which normally idles the ino's state machine which would 587c478bd9Sstevel@tonic-gate * precipitate another trip round the loop. 597c478bd9Sstevel@tonic-gate * 607c478bd9Sstevel@tonic-gate * The loop can be broken by preventing the ino's state machine from being 617c478bd9Sstevel@tonic-gate * idled when an interrupt line is jabbering. See the comment at the 627c478bd9Sstevel@tonic-gate * beginning of px_intr_wrapper() explaining how the 'interrupt jabber 637c478bd9Sstevel@tonic-gate * protection' code does this. 647c478bd9Sstevel@tonic-gate */ 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 677c478bd9Sstevel@tonic-gate 687c478bd9Sstevel@tonic-gate /* 697c478bd9Sstevel@tonic-gate * If the unclaimed interrupt count has reached the limit set by 707c478bd9Sstevel@tonic-gate * pci_unclaimed_intr_max within the time limit, then all interrupts 717c478bd9Sstevel@tonic-gate * on this ino is blocked by not idling the interrupt state machine. 727c478bd9Sstevel@tonic-gate */ 737c478bd9Sstevel@tonic-gate static int 747c478bd9Sstevel@tonic-gate px_spurintr(px_ib_ino_info_t *ino_p) 757c478bd9Sstevel@tonic-gate { 767c478bd9Sstevel@tonic-gate px_ih_t *ih_p = ino_p->ino_ih_start; 777c478bd9Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 787c478bd9Sstevel@tonic-gate char *err_fmt_str; 797c478bd9Sstevel@tonic-gate int i; 807c478bd9Sstevel@tonic-gate 817c478bd9Sstevel@tonic-gate if (ino_p->ino_unclaimed > px_unclaimed_intr_max) 827c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 837c478bd9Sstevel@tonic-gate 847c478bd9Sstevel@tonic-gate if (!ino_p->ino_unclaimed) 857c478bd9Sstevel@tonic-gate ino_p->ino_spurintr_begin = ddi_get_lbolt(); 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed++; 887c478bd9Sstevel@tonic-gate 897c478bd9Sstevel@tonic-gate if (ino_p->ino_unclaimed <= px_unclaimed_intr_max) 907c478bd9Sstevel@tonic-gate goto clear; 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 937c478bd9Sstevel@tonic-gate > px_spurintr_duration) { 947c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 957c478bd9Sstevel@tonic-gate goto clear; 967c478bd9Sstevel@tonic-gate } 977c478bd9Sstevel@tonic-gate err_fmt_str = "%s%d: ino 0x%x blocked"; 987c478bd9Sstevel@tonic-gate goto warn; 997c478bd9Sstevel@tonic-gate clear: 1007c478bd9Sstevel@tonic-gate /* Clear the pending state */ 1017c478bd9Sstevel@tonic-gate if (px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 1027c478bd9Sstevel@tonic-gate INTR_IDLE_STATE) != DDI_SUCCESS) 1037c478bd9Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 1047c478bd9Sstevel@tonic-gate 1057c478bd9Sstevel@tonic-gate err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 1067c478bd9Sstevel@tonic-gate warn: 1077c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, err_fmt_str, NAMEINST(px_p->px_dip), ino_p->ino_ino); 1087c478bd9Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) 1097c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 1107c478bd9Sstevel@tonic-gate ih_p->ih_inum); 1117c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!\n"); 1127c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 1137c478bd9Sstevel@tonic-gate } 1147c478bd9Sstevel@tonic-gate 1157c478bd9Sstevel@tonic-gate extern uint64_t intr_get_time(void); 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate /* 118a195726fSgovinda * px_intx_intr (INTx or legacy interrupt handler) 1197c478bd9Sstevel@tonic-gate * 1207c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 1217c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 1227c478bd9Sstevel@tonic-gate * examines the return codes. 1237c478bd9Sstevel@tonic-gate * 1247c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 1257c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 1267c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 1277c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 1287c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 1297c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 1307c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 1317c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 1327c478bd9Sstevel@tonic-gate * 1337c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 1347c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 1357c478bd9Sstevel@tonic-gate */ 1367c478bd9Sstevel@tonic-gate uint_t 1377c478bd9Sstevel@tonic-gate px_intx_intr(caddr_t arg) 1387c478bd9Sstevel@tonic-gate { 1397c478bd9Sstevel@tonic-gate px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 1407c478bd9Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 1417c478bd9Sstevel@tonic-gate px_ih_t *ih_p = ino_p->ino_ih_start; 1427c478bd9Sstevel@tonic-gate uint_t result = 0, r; 1437c478bd9Sstevel@tonic-gate int i; 1447c478bd9Sstevel@tonic-gate 1457c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 1467c478bd9Sstevel@tonic-gate "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n", 1477c478bd9Sstevel@tonic-gate ino_p->ino_ino, ino_p->ino_sysino, ino_p->ino_pil, 1487c478bd9Sstevel@tonic-gate ino_p->ino_ih_size, ino_p->ino_ih_head); 1497c478bd9Sstevel@tonic-gate 1507c478bd9Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) { 1517c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 1527c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 1537c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 1547c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 1557c478bd9Sstevel@tonic-gate 1567c478bd9Sstevel@tonic-gate if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) { 1577c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, 1587c478bd9Sstevel@tonic-gate "px_intx_intr: %s%d interrupt %d is disabled\n", 1597c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 1607c478bd9Sstevel@tonic-gate ino_p->ino_ino); 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate continue; 1637c478bd9Sstevel@tonic-gate } 1647c478bd9Sstevel@tonic-gate 1657c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 1667c478bd9Sstevel@tonic-gate "ino=%x handler=%p arg1 =%p arg2 = %p\n", 1677c478bd9Sstevel@tonic-gate ino_p->ino_ino, handler, arg1, arg2); 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 1707c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 1717c478bd9Sstevel@tonic-gate 1727c478bd9Sstevel@tonic-gate r = (*handler)(arg1, arg2); 1737c478bd9Sstevel@tonic-gate 1747c478bd9Sstevel@tonic-gate /* 1757c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect against 1767c478bd9Sstevel@tonic-gate * conflicting writes to ih_ticks from ib_intr_dist_all() by 1777c478bd9Sstevel@tonic-gate * using atomic ops. 1787c478bd9Sstevel@tonic-gate */ 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate if (ino_p->ino_pil <= LOCK_LEVEL) 1817c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 1827c478bd9Sstevel@tonic-gate 1837c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 1847c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, r); 1857c478bd9Sstevel@tonic-gate 1867c478bd9Sstevel@tonic-gate result += r; 1877c478bd9Sstevel@tonic-gate 1887c478bd9Sstevel@tonic-gate if (px_check_all_handlers) 1897c478bd9Sstevel@tonic-gate continue; 1907c478bd9Sstevel@tonic-gate if (result) 1917c478bd9Sstevel@tonic-gate break; 1927c478bd9Sstevel@tonic-gate } 1937c478bd9Sstevel@tonic-gate 1947c478bd9Sstevel@tonic-gate if (!result && px_unclaimed_intr_block) 1957c478bd9Sstevel@tonic-gate return (px_spurintr(ino_p)); 1967c478bd9Sstevel@tonic-gate 1977c478bd9Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 1987c478bd9Sstevel@tonic-gate 1997c478bd9Sstevel@tonic-gate /* Clear the pending state */ 2007c478bd9Sstevel@tonic-gate if (px_lib_intr_setstate(ino_p->ino_ib_p->ib_px_p->px_dip, 2017c478bd9Sstevel@tonic-gate ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 2027c478bd9Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 2037c478bd9Sstevel@tonic-gate 2047c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 2057c478bd9Sstevel@tonic-gate } 2067c478bd9Sstevel@tonic-gate 2077c478bd9Sstevel@tonic-gate /* 208a195726fSgovinda * px_msiq_intr (MSI/X or PCIe MSG interrupt handler) 2097c478bd9Sstevel@tonic-gate * 2107c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 2117c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 2127c478bd9Sstevel@tonic-gate * examines the return codes. 2137c478bd9Sstevel@tonic-gate * 2147c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 2157c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 2167c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 2177c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 2187c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 2197c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 2207c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 2217c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 2227c478bd9Sstevel@tonic-gate * 2237c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 2247c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 2257c478bd9Sstevel@tonic-gate */ 2267c478bd9Sstevel@tonic-gate uint_t 2277c478bd9Sstevel@tonic-gate px_msiq_intr(caddr_t arg) 2287c478bd9Sstevel@tonic-gate { 2297c478bd9Sstevel@tonic-gate px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 2307c478bd9Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 2317c478bd9Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 2327c478bd9Sstevel@tonic-gate px_msiq_t *msiq_p = ino_p->ino_msiq_p; 2337c478bd9Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 2347c478bd9Sstevel@tonic-gate msiq_rec_t msiq_rec, *msiq_rec_p = &msiq_rec; 235023ccc1eSegillett msiqhead_t new_head_index = msiq_p->msiq_curr_head_idx; 236023ccc1eSegillett msiqhead_t *curr_head_p; 237023ccc1eSegillett msiqtail_t curr_tail_index; 2387c478bd9Sstevel@tonic-gate msgcode_t msg_code; 2397c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 24007f14c08Sgovinda int i, ret; 241023ccc1eSegillett ushort_t msiq_recs2process; 2427c478bd9Sstevel@tonic-gate 2437c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x " 2447c478bd9Sstevel@tonic-gate "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino, 2457c478bd9Sstevel@tonic-gate ino_p->ino_pil, ino_p->ino_ih_size, ino_p->ino_ih_head); 2467c478bd9Sstevel@tonic-gate 247023ccc1eSegillett /* Read current MSIQ tail index */ 248023ccc1eSegillett px_lib_msiq_gettail(dip, msiq_p->msiq_id, &curr_tail_index); 2497c478bd9Sstevel@tonic-gate 250023ccc1eSegillett if (curr_tail_index < new_head_index) 251023ccc1eSegillett curr_tail_index += msiq_state_p->msiq_rec_cnt; 2527c478bd9Sstevel@tonic-gate 2537c478bd9Sstevel@tonic-gate /* 254023ccc1eSegillett * Calculate the number of recs to process by taking the difference 255023ccc1eSegillett * between the head and tail pointers. For all records we always 256023ccc1eSegillett * verify that we have a valid record type before we do any processing. 257023ccc1eSegillett * If triggered, we should always have at least 1 valid record. 2587c478bd9Sstevel@tonic-gate */ 259023ccc1eSegillett msiq_recs2process = curr_tail_index - new_head_index; 260023ccc1eSegillett 261023ccc1eSegillett DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: curr_head %x " 262023ccc1eSegillett "rec2process %x\n", new_head_index, msiq_recs2process); 263023ccc1eSegillett 264023ccc1eSegillett curr_head_p = (msiqhead_t *)((caddr_t)msiq_p->msiq_base_p + 265023ccc1eSegillett new_head_index * sizeof (msiq_rec_t)); 266023ccc1eSegillett 267023ccc1eSegillett for (i = 0; i < msiq_recs2process; i++) { 268023ccc1eSegillett /* Read MSIQ record */ 269023ccc1eSegillett px_lib_get_msiq_rec(dip, curr_head_p, msiq_rec_p); 270023ccc1eSegillett 2717c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSIQ RECORD, " 2727c478bd9Sstevel@tonic-gate "msiq_rec_type 0x%llx msiq_rec_rid 0x%llx\n", 2737c478bd9Sstevel@tonic-gate msiq_rec_p->msiq_rec_type, msiq_rec_p->msiq_rec_rid); 2747c478bd9Sstevel@tonic-gate 275023ccc1eSegillett if (!msiq_rec_p->msiq_rec_type) 276023ccc1eSegillett break; 2777c478bd9Sstevel@tonic-gate 2787c478bd9Sstevel@tonic-gate /* Check MSIQ record type */ 2797c478bd9Sstevel@tonic-gate switch (msiq_rec_p->msiq_rec_type) { 2807c478bd9Sstevel@tonic-gate case MSG_REC: 2817c478bd9Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msg.msg_code; 2827c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: PCIE MSG " 2837c478bd9Sstevel@tonic-gate "record, msg type 0x%x\n", msg_code); 2847c478bd9Sstevel@tonic-gate break; 2857c478bd9Sstevel@tonic-gate case MSI32_REC: 2867c478bd9Sstevel@tonic-gate case MSI64_REC: 2877c478bd9Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msi.msi_data; 2887c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSI record, " 2897c478bd9Sstevel@tonic-gate "msi 0x%x\n", msg_code); 2907c478bd9Sstevel@tonic-gate 2917c478bd9Sstevel@tonic-gate /* Clear MSI state */ 2927c478bd9Sstevel@tonic-gate px_lib_msi_setstate(dip, (msinum_t)msg_code, 2937c478bd9Sstevel@tonic-gate PCI_MSI_STATE_IDLE); 2947c478bd9Sstevel@tonic-gate break; 2957c478bd9Sstevel@tonic-gate default: 2967c478bd9Sstevel@tonic-gate msg_code = 0; 2977c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_msiq_intr: 0x%x MSIQ " 2987c478bd9Sstevel@tonic-gate "record type is not supported", 2997c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 3007c478bd9Sstevel@tonic-gate msiq_rec_p->msiq_rec_type); 3017c478bd9Sstevel@tonic-gate goto next_rec; 3027c478bd9Sstevel@tonic-gate } 3037c478bd9Sstevel@tonic-gate 3047c478bd9Sstevel@tonic-gate /* 3057c478bd9Sstevel@tonic-gate * Scan through px_ih_t linked list, searching for the 3067c478bd9Sstevel@tonic-gate * right px_ih_t, matching MSIQ record data. 3077c478bd9Sstevel@tonic-gate */ 30807f14c08Sgovinda for (i = 0, ih_p = ino_p->ino_ih_start; 30907f14c08Sgovinda ih_p && (i < ino_p->ino_ih_size) && 31007f14c08Sgovinda ((ih_p->ih_msg_code != msg_code) || 31107f14c08Sgovinda (ih_p->ih_rec_type != msiq_rec_p->msiq_rec_type)); 31207f14c08Sgovinda ih_p = ih_p->ih_next, i++); 3137c478bd9Sstevel@tonic-gate 3147c478bd9Sstevel@tonic-gate if ((ih_p->ih_msg_code == msg_code) && 3157c478bd9Sstevel@tonic-gate (ih_p->ih_rec_type == msiq_rec_p->msiq_rec_type)) { 3167c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 3177c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 3187c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 3197c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 3207c478bd9Sstevel@tonic-gate 3217c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: ino=%x data=%x " 3227c478bd9Sstevel@tonic-gate "handler=%p arg1 =%p arg2=%p\n", ino_p->ino_ino, 3237c478bd9Sstevel@tonic-gate msg_code, handler, arg1, arg2); 3247c478bd9Sstevel@tonic-gate 3257c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 3267c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 3277c478bd9Sstevel@tonic-gate 328f8d2de6bSjchu /* 329f8d2de6bSjchu * Special case for PCIE Error Messages. 330f8d2de6bSjchu * The current frame work doesn't fit PCIE Err Msgs 331f8d2de6bSjchu * This should be fixed when PCIE MESSAGES as a whole 332f8d2de6bSjchu * is architected correctly. 333f8d2de6bSjchu */ 334f8d2de6bSjchu if ((msg_code == PCIE_MSG_CODE_ERR_COR) || 335f8d2de6bSjchu (msg_code == PCIE_MSG_CODE_ERR_NONFATAL) || 336f8d2de6bSjchu (msg_code == PCIE_MSG_CODE_ERR_FATAL)) { 337f8d2de6bSjchu ret = px_err_fabric_intr(px_p, msg_code, 338f8d2de6bSjchu msiq_rec_p->msiq_rec_rid); 339f8d2de6bSjchu } else 340f8d2de6bSjchu ret = (*handler)(arg1, arg2); 3417c478bd9Sstevel@tonic-gate 3427c478bd9Sstevel@tonic-gate /* 3437c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect 3447c478bd9Sstevel@tonic-gate * against conflicting writes to ih_ticks from 3457c478bd9Sstevel@tonic-gate * ib_intr_dist_all() by using atomic ops. 3467c478bd9Sstevel@tonic-gate */ 3477c478bd9Sstevel@tonic-gate 3487c478bd9Sstevel@tonic-gate if (ino_p->ino_pil <= LOCK_LEVEL) 3497c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 3507c478bd9Sstevel@tonic-gate 3517c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 3527c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, ret); 353023ccc1eSegillett 354023ccc1eSegillett new_head_index++; 3557c478bd9Sstevel@tonic-gate } else { 3567c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr:" 357023ccc1eSegillett "No matching MSIQ record found\n"); 3587c478bd9Sstevel@tonic-gate } 3597c478bd9Sstevel@tonic-gate next_rec: 360023ccc1eSegillett /* Get the pointer next EQ record */ 361023ccc1eSegillett curr_head_p = (msiqhead_t *) 362023ccc1eSegillett ((caddr_t)curr_head_p + sizeof (msiq_rec_t)); 363023ccc1eSegillett 364023ccc1eSegillett /* Check for overflow condition */ 365023ccc1eSegillett if (curr_head_p >= (msiqhead_t *)((caddr_t)msiq_p->msiq_base_p 366023ccc1eSegillett + msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t))) 367023ccc1eSegillett curr_head_p = (msiqhead_t *)msiq_p->msiq_base_p; 3687c478bd9Sstevel@tonic-gate 3693ee8f295Smg /* Zero out msiq_rec_type field */ 3703ee8f295Smg msiq_rec_p->msiq_rec_type = 0; 3717c478bd9Sstevel@tonic-gate } 3727c478bd9Sstevel@tonic-gate 373023ccc1eSegillett DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: # of MSIQ recs processed %x\n", 374023ccc1eSegillett (new_head_index - msiq_p->msiq_curr_head_idx)); 375023ccc1eSegillett 376023ccc1eSegillett if (new_head_index <= msiq_p->msiq_curr_head_idx) { 377023ccc1eSegillett if (px_unclaimed_intr_block) { 378023ccc1eSegillett return (px_spurintr(ino_p)); 379023ccc1eSegillett } 380023ccc1eSegillett } 3817c478bd9Sstevel@tonic-gate 3827c478bd9Sstevel@tonic-gate /* Update MSIQ head index with no of MSIQ records processed */ 383023ccc1eSegillett if (new_head_index >= msiq_state_p->msiq_rec_cnt) 384023ccc1eSegillett new_head_index -= msiq_state_p->msiq_rec_cnt; 3857c478bd9Sstevel@tonic-gate 386023ccc1eSegillett msiq_p->msiq_curr_head_idx = new_head_index; 387023ccc1eSegillett px_lib_msiq_sethead(dip, msiq_p->msiq_id, new_head_index); 3887c478bd9Sstevel@tonic-gate 3897c478bd9Sstevel@tonic-gate /* Clear the pending state */ 3907c478bd9Sstevel@tonic-gate if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 3917c478bd9Sstevel@tonic-gate INTR_IDLE_STATE) != DDI_SUCCESS) 3927c478bd9Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 3937c478bd9Sstevel@tonic-gate 3947c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3957c478bd9Sstevel@tonic-gate } 3967c478bd9Sstevel@tonic-gate 3977c478bd9Sstevel@tonic-gate dev_info_t * 3987c478bd9Sstevel@tonic-gate px_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 3997c478bd9Sstevel@tonic-gate { 4007c478bd9Sstevel@tonic-gate dev_info_t *cdip = rdip; 4017c478bd9Sstevel@tonic-gate 4027c478bd9Sstevel@tonic-gate for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 4037c478bd9Sstevel@tonic-gate ; 4047c478bd9Sstevel@tonic-gate 4057c478bd9Sstevel@tonic-gate return (cdip); 4067c478bd9Sstevel@tonic-gate } 4077c478bd9Sstevel@tonic-gate 4087c478bd9Sstevel@tonic-gate /* Default class to pil value mapping */ 4097c478bd9Sstevel@tonic-gate px_class_val_t px_default_pil [] = { 4107c478bd9Sstevel@tonic-gate {0x000000, 0xff0000, 0x1}, /* Class code for pre-2.0 devices */ 4117c478bd9Sstevel@tonic-gate {0x010000, 0xff0000, 0x4}, /* Mass Storage Controller */ 4127c478bd9Sstevel@tonic-gate {0x020000, 0xff0000, 0x6}, /* Network Controller */ 4137c478bd9Sstevel@tonic-gate {0x030000, 0xff0000, 0x9}, /* Display Controller */ 4147c478bd9Sstevel@tonic-gate {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ 41544bb982bSgovinda {0x050000, 0xff0000, 0x9}, /* Memory Controller */ 41644bb982bSgovinda {0x060000, 0xff0000, 0x9}, /* Bridge Controller */ 4177c478bd9Sstevel@tonic-gate {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ 4187c478bd9Sstevel@tonic-gate {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ 4197c478bd9Sstevel@tonic-gate {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ 4207c478bd9Sstevel@tonic-gate {0x0c0300, 0xffff00, 0x9}, /* Serial Bus Universal Serial Bus */ 4217c478bd9Sstevel@tonic-gate {0x0c0400, 0xffff00, 0x6}, /* Serial Bus, Fibre Channel */ 4227c478bd9Sstevel@tonic-gate {0x0c0600, 0xffff00, 0x6} /* Serial Bus, Infiniband */ 4237c478bd9Sstevel@tonic-gate }; 4247c478bd9Sstevel@tonic-gate 4257c478bd9Sstevel@tonic-gate /* 4267c478bd9Sstevel@tonic-gate * Default class to intr_weight value mapping (% of CPU). A driver.conf 4277c478bd9Sstevel@tonic-gate * entry on or above the pci node like 4287c478bd9Sstevel@tonic-gate * 4297c478bd9Sstevel@tonic-gate * pci-class-intr-weights= 0x020000, 0xff0000, 30; 4307c478bd9Sstevel@tonic-gate * 4317c478bd9Sstevel@tonic-gate * can be used to augment or override entries in the default table below. 4327c478bd9Sstevel@tonic-gate * 4337c478bd9Sstevel@tonic-gate * NB: The values below give NICs preference on redistribution, and provide 4347c478bd9Sstevel@tonic-gate * NICs some isolation from other interrupt sources. We need better interfaces 4357c478bd9Sstevel@tonic-gate * that allow the NIC driver to identify a specific NIC instance as high 4367c478bd9Sstevel@tonic-gate * bandwidth, and thus deserving of separation from other low bandwidth 4377c478bd9Sstevel@tonic-gate * NICs additional isolation from other interrupt sources. 4387c478bd9Sstevel@tonic-gate * 4397c478bd9Sstevel@tonic-gate * NB: We treat Infiniband like a NIC. 4407c478bd9Sstevel@tonic-gate */ 4417c478bd9Sstevel@tonic-gate px_class_val_t px_default_intr_weight [] = { 4427c478bd9Sstevel@tonic-gate {0x020000, 0xff0000, 35}, /* Network Controller */ 4437c478bd9Sstevel@tonic-gate {0x010000, 0xff0000, 10}, /* Mass Storage Controller */ 4447c478bd9Sstevel@tonic-gate {0x0c0400, 0xffff00, 10}, /* Serial Bus, Fibre Channel */ 4457c478bd9Sstevel@tonic-gate {0x0c0600, 0xffff00, 50} /* Serial Bus, Infiniband */ 4467c478bd9Sstevel@tonic-gate }; 4477c478bd9Sstevel@tonic-gate 4487c478bd9Sstevel@tonic-gate static uint32_t 4497c478bd9Sstevel@tonic-gate px_match_class_val(uint32_t key, px_class_val_t *rec_p, int nrec, 4507c478bd9Sstevel@tonic-gate uint32_t default_val) 4517c478bd9Sstevel@tonic-gate { 4527c478bd9Sstevel@tonic-gate int i; 4537c478bd9Sstevel@tonic-gate 4547c478bd9Sstevel@tonic-gate for (i = 0; i < nrec; rec_p++, i++) { 4557c478bd9Sstevel@tonic-gate if ((rec_p->class_code & rec_p->class_mask) == 4567c478bd9Sstevel@tonic-gate (key & rec_p->class_mask)) 4577c478bd9Sstevel@tonic-gate return (rec_p->class_val); 4587c478bd9Sstevel@tonic-gate } 4597c478bd9Sstevel@tonic-gate 4607c478bd9Sstevel@tonic-gate return (default_val); 4617c478bd9Sstevel@tonic-gate } 4627c478bd9Sstevel@tonic-gate 4637c478bd9Sstevel@tonic-gate /* 4647c478bd9Sstevel@tonic-gate * px_class_to_val 4657c478bd9Sstevel@tonic-gate * 4667c478bd9Sstevel@tonic-gate * Return the configuration value, based on class code and sub class code, 4677c478bd9Sstevel@tonic-gate * from the specified property based or default px_class_val_t table. 4687c478bd9Sstevel@tonic-gate */ 4697c478bd9Sstevel@tonic-gate uint32_t 4707c478bd9Sstevel@tonic-gate px_class_to_val(dev_info_t *rdip, char *property_name, px_class_val_t *rec_p, 4717c478bd9Sstevel@tonic-gate int nrec, uint32_t default_val) 4727c478bd9Sstevel@tonic-gate { 4737c478bd9Sstevel@tonic-gate int property_len; 4747c478bd9Sstevel@tonic-gate uint32_t class_code; 4757c478bd9Sstevel@tonic-gate px_class_val_t *conf; 4767c478bd9Sstevel@tonic-gate uint32_t val = default_val; 4777c478bd9Sstevel@tonic-gate 4787c478bd9Sstevel@tonic-gate /* 4797c478bd9Sstevel@tonic-gate * Use the "class-code" property to get the base and sub class 4807c478bd9Sstevel@tonic-gate * codes for the requesting device. 4817c478bd9Sstevel@tonic-gate */ 4827c478bd9Sstevel@tonic-gate class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 4837c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "class-code", -1); 4847c478bd9Sstevel@tonic-gate 4857c478bd9Sstevel@tonic-gate if (class_code == -1) 4867c478bd9Sstevel@tonic-gate return (val); 4877c478bd9Sstevel@tonic-gate 4887c478bd9Sstevel@tonic-gate /* look up the val from the default table */ 4897c478bd9Sstevel@tonic-gate val = px_match_class_val(class_code, rec_p, nrec, val); 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate /* see if there is a more specific property specified value */ 4927c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM, 4937c478bd9Sstevel@tonic-gate property_name, (caddr_t)&conf, &property_len)) 4947c478bd9Sstevel@tonic-gate return (val); 4957c478bd9Sstevel@tonic-gate 4967c478bd9Sstevel@tonic-gate if ((property_len % sizeof (px_class_val_t)) == 0) 4977c478bd9Sstevel@tonic-gate val = px_match_class_val(class_code, conf, 4987c478bd9Sstevel@tonic-gate property_len / sizeof (px_class_val_t), val); 4997c478bd9Sstevel@tonic-gate kmem_free(conf, property_len); 5007c478bd9Sstevel@tonic-gate return (val); 5017c478bd9Sstevel@tonic-gate } 5027c478bd9Sstevel@tonic-gate 5037c478bd9Sstevel@tonic-gate /* px_class_to_pil: return the pil for a given device. */ 5047c478bd9Sstevel@tonic-gate uint32_t 5057c478bd9Sstevel@tonic-gate px_class_to_pil(dev_info_t *rdip) 5067c478bd9Sstevel@tonic-gate { 5077c478bd9Sstevel@tonic-gate uint32_t pil; 5087c478bd9Sstevel@tonic-gate 5097c478bd9Sstevel@tonic-gate /* default pil is 0 (uninitialized) */ 5107c478bd9Sstevel@tonic-gate pil = px_class_to_val(rdip, 5117c478bd9Sstevel@tonic-gate "pci-class-priorities", px_default_pil, 5127c478bd9Sstevel@tonic-gate sizeof (px_default_pil) / sizeof (px_class_val_t), 0); 5137c478bd9Sstevel@tonic-gate 5147c478bd9Sstevel@tonic-gate /* range check the result */ 5157c478bd9Sstevel@tonic-gate if (pil >= 0xf) 5167c478bd9Sstevel@tonic-gate pil = 0; 5177c478bd9Sstevel@tonic-gate 5187c478bd9Sstevel@tonic-gate return (pil); 5197c478bd9Sstevel@tonic-gate } 5207c478bd9Sstevel@tonic-gate 5217c478bd9Sstevel@tonic-gate /* px_class_to_intr_weight: return the intr_weight for a given device. */ 5227c478bd9Sstevel@tonic-gate static int32_t 5237c478bd9Sstevel@tonic-gate px_class_to_intr_weight(dev_info_t *rdip) 5247c478bd9Sstevel@tonic-gate { 5257c478bd9Sstevel@tonic-gate int32_t intr_weight; 5267c478bd9Sstevel@tonic-gate 5277c478bd9Sstevel@tonic-gate /* default weight is 0% */ 5287c478bd9Sstevel@tonic-gate intr_weight = px_class_to_val(rdip, 5297c478bd9Sstevel@tonic-gate "pci-class-intr-weights", px_default_intr_weight, 5307c478bd9Sstevel@tonic-gate sizeof (px_default_intr_weight) / sizeof (px_class_val_t), 0); 5317c478bd9Sstevel@tonic-gate 5327c478bd9Sstevel@tonic-gate /* range check the result */ 5337c478bd9Sstevel@tonic-gate if (intr_weight < 0) 5347c478bd9Sstevel@tonic-gate intr_weight = 0; 5357c478bd9Sstevel@tonic-gate if (intr_weight > 1000) 5367c478bd9Sstevel@tonic-gate intr_weight = 1000; 5377c478bd9Sstevel@tonic-gate 5387c478bd9Sstevel@tonic-gate return (intr_weight); 5397c478bd9Sstevel@tonic-gate } 5407c478bd9Sstevel@tonic-gate 5417c478bd9Sstevel@tonic-gate /* ARGSUSED */ 5427c478bd9Sstevel@tonic-gate int 5437c478bd9Sstevel@tonic-gate px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 5447c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 5457c478bd9Sstevel@tonic-gate { 546a195726fSgovinda px_t *px_p = DIP_TO_STATE(dip); 547a195726fSgovinda int ret = DDI_SUCCESS; 5487c478bd9Sstevel@tonic-gate 5497c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x " 5507c478bd9Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 5517c478bd9Sstevel@tonic-gate 5527c478bd9Sstevel@tonic-gate switch (intr_op) { 5537c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 5547c478bd9Sstevel@tonic-gate ret = pci_intx_get_cap(rdip, (int *)result); 5557c478bd9Sstevel@tonic-gate break; 5567c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 5577c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n"); 5587c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 5597c478bd9Sstevel@tonic-gate break; 5607c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 5617c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_scratch1; 5627c478bd9Sstevel@tonic-gate break; 5637c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 5647c478bd9Sstevel@tonic-gate break; 5657c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 566a195726fSgovinda *(int *)result = hdlp->ih_pri ? 567a195726fSgovinda hdlp->ih_pri : px_class_to_pil(rdip); 5687c478bd9Sstevel@tonic-gate break; 5697c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 5707c478bd9Sstevel@tonic-gate break; 5717c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 5727c478bd9Sstevel@tonic-gate ret = px_add_intx_intr(dip, rdip, hdlp); 5737c478bd9Sstevel@tonic-gate break; 5747c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 5757c478bd9Sstevel@tonic-gate ret = px_rem_intx_intr(dip, rdip, hdlp); 5767c478bd9Sstevel@tonic-gate break; 5777c478bd9Sstevel@tonic-gate case DDI_INTROP_ENABLE: 5787c478bd9Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 57936fe4a92Segillett hdlp->ih_vector, PX_INTR_STATE_ENABLE, 0, 0); 5807c478bd9Sstevel@tonic-gate break; 5817c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 5827c478bd9Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 58336fe4a92Segillett hdlp->ih_vector, PX_INTR_STATE_DISABLE, 0, 0); 5847c478bd9Sstevel@tonic-gate break; 5857c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 5867c478bd9Sstevel@tonic-gate ret = pci_intx_set_mask(rdip); 5877c478bd9Sstevel@tonic-gate break; 5887c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 5897c478bd9Sstevel@tonic-gate ret = pci_intx_clr_mask(rdip); 5907c478bd9Sstevel@tonic-gate break; 5917c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 5927c478bd9Sstevel@tonic-gate ret = pci_intx_get_pending(rdip, (int *)result); 5937c478bd9Sstevel@tonic-gate break; 5947c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 5957c478bd9Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 596a54f81fbSanish *(int *)result = i_ddi_get_intx_nintrs(rdip); 5977c478bd9Sstevel@tonic-gate break; 5987c478bd9Sstevel@tonic-gate default: 5997c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 6007c478bd9Sstevel@tonic-gate break; 6017c478bd9Sstevel@tonic-gate } 6027c478bd9Sstevel@tonic-gate 6037c478bd9Sstevel@tonic-gate return (ret); 6047c478bd9Sstevel@tonic-gate } 6057c478bd9Sstevel@tonic-gate 6067c478bd9Sstevel@tonic-gate /* ARGSUSED */ 6077c478bd9Sstevel@tonic-gate int 6087c478bd9Sstevel@tonic-gate px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 6097c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 6107c478bd9Sstevel@tonic-gate { 6117c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 6127c478bd9Sstevel@tonic-gate px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 6139c75c6bfSgovinda msiq_rec_type_t msiq_rec_type; 6149c75c6bfSgovinda msi_type_t msi_type; 6159c75c6bfSgovinda uint64_t msi_addr; 6167c478bd9Sstevel@tonic-gate msinum_t msi_num; 6177c478bd9Sstevel@tonic-gate msiqid_t msiq_id; 6187c478bd9Sstevel@tonic-gate uint_t nintrs; 6197c478bd9Sstevel@tonic-gate int i, ret = DDI_SUCCESS; 6207c478bd9Sstevel@tonic-gate 6217c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x " 6227c478bd9Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 6237c478bd9Sstevel@tonic-gate 6249c75c6bfSgovinda /* Check for MSI64 support */ 62507f14c08Sgovinda if ((hdlp->ih_cap & DDI_INTR_FLAG_MSI64) && msi_state_p->msi_addr64) { 6269c75c6bfSgovinda msiq_rec_type = MSI64_REC; 6279c75c6bfSgovinda msi_type = MSI64_TYPE; 62807f14c08Sgovinda msi_addr = msi_state_p->msi_addr64; 6299c75c6bfSgovinda } else { 6309c75c6bfSgovinda msiq_rec_type = MSI32_REC; 6319c75c6bfSgovinda msi_type = MSI32_TYPE; 6329c75c6bfSgovinda msi_addr = msi_state_p->msi_addr32; 6339c75c6bfSgovinda } 6349c75c6bfSgovinda 6357c478bd9Sstevel@tonic-gate switch (intr_op) { 6367c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 6377c478bd9Sstevel@tonic-gate ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result); 6387c478bd9Sstevel@tonic-gate break; 6397c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 6407c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: SetCap is not supported\n"); 6417c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 6427c478bd9Sstevel@tonic-gate break; 6437c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 6447c478bd9Sstevel@tonic-gate /* 6457c478bd9Sstevel@tonic-gate * We need to restrict this allocation in future 6467c478bd9Sstevel@tonic-gate * based on Resource Management policies. 6477c478bd9Sstevel@tonic-gate */ 6487c478bd9Sstevel@tonic-gate if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_inum, 64920036fe5Segillett hdlp->ih_scratch1, (uintptr_t)hdlp->ih_scratch2, &msi_num, 65020036fe5Segillett (int *)result)) != DDI_SUCCESS) { 65120036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: allocation " 65220036fe5Segillett "failed, rdip 0x%p type 0x%d inum 0x%x " 65320036fe5Segillett "count 0x%x\n", rdip, hdlp->ih_type, hdlp->ih_inum, 65420036fe5Segillett hdlp->ih_scratch1); 6557c478bd9Sstevel@tonic-gate 6567c478bd9Sstevel@tonic-gate return (ret); 6577c478bd9Sstevel@tonic-gate } 6587c478bd9Sstevel@tonic-gate 65920036fe5Segillett if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && 66020036fe5Segillett (i_ddi_get_msix(rdip) == NULL)) { 66120036fe5Segillett ddi_intr_msix_t *msix_p; 66220036fe5Segillett 66320036fe5Segillett if (msix_p = pci_msix_init(rdip)) { 66420036fe5Segillett i_ddi_set_msix(rdip, msix_p); 66520036fe5Segillett break; 66620036fe5Segillett } 66720036fe5Segillett 66820036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: MSI-X allocation " 66920036fe5Segillett "failed, rdip 0x%p inum 0x%x\n", rdip, 67020036fe5Segillett hdlp->ih_inum); 67120036fe5Segillett 67220036fe5Segillett (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 67320036fe5Segillett hdlp->ih_scratch1); 67420036fe5Segillett 67520036fe5Segillett return (DDI_FAILURE); 67620036fe5Segillett } 67720036fe5Segillett 6787c478bd9Sstevel@tonic-gate break; 6797c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 680*95003185Segillett (void) pci_msi_disable_mode(rdip, hdlp->ih_type, NULL); 6817c478bd9Sstevel@tonic-gate (void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum); 68220036fe5Segillett 68320036fe5Segillett if (hdlp->ih_type == DDI_INTR_TYPE_MSI) 68420036fe5Segillett goto msi_free; 68520036fe5Segillett 68620036fe5Segillett if (hdlp->ih_flags & DDI_INTR_MSIX_DUP) 68720036fe5Segillett break; 68820036fe5Segillett 68920036fe5Segillett if (((i_ddi_intr_get_current_nintrs(hdlp->ih_dip) - 1) == 0) && 69020036fe5Segillett (i_ddi_get_msix(rdip))) { 69120036fe5Segillett pci_msix_fini(i_ddi_get_msix(rdip)); 69220036fe5Segillett i_ddi_set_msix(rdip, NULL); 69320036fe5Segillett } 69420036fe5Segillett msi_free: 6957c478bd9Sstevel@tonic-gate (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 6967c478bd9Sstevel@tonic-gate hdlp->ih_scratch1); 6977c478bd9Sstevel@tonic-gate break; 6987c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 6997c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_pri ? 7007c478bd9Sstevel@tonic-gate hdlp->ih_pri : px_class_to_pil(rdip); 7017c478bd9Sstevel@tonic-gate break; 7027c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 7037c478bd9Sstevel@tonic-gate break; 7047c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 7057c478bd9Sstevel@tonic-gate if ((ret = px_msi_get_msinum(px_p, hdlp->ih_dip, 7067c478bd9Sstevel@tonic-gate hdlp->ih_inum, &msi_num)) != DDI_SUCCESS) 7077c478bd9Sstevel@tonic-gate return (ret); 7087c478bd9Sstevel@tonic-gate 7097c478bd9Sstevel@tonic-gate if ((ret = px_add_msiq_intr(dip, rdip, hdlp, 7109c75c6bfSgovinda msiq_rec_type, msi_num, &msiq_id)) != DDI_SUCCESS) { 7117c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler " 7127c478bd9Sstevel@tonic-gate "failed, rdip 0x%p msi 0x%x\n", rdip, msi_num); 7137c478bd9Sstevel@tonic-gate return (ret); 7147c478bd9Sstevel@tonic-gate } 7157c478bd9Sstevel@tonic-gate 7167c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id); 7177c478bd9Sstevel@tonic-gate 7187c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setmsiq(dip, msi_num, 7199c75c6bfSgovinda msiq_id, msi_type)) != DDI_SUCCESS) { 7207c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 7219c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 7227c478bd9Sstevel@tonic-gate return (ret); 7237c478bd9Sstevel@tonic-gate } 7247c478bd9Sstevel@tonic-gate 7257c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 7267c478bd9Sstevel@tonic-gate PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) { 7277c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 7289c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 7297c478bd9Sstevel@tonic-gate return (ret); 7307c478bd9Sstevel@tonic-gate } 7317c478bd9Sstevel@tonic-gate 7327c478bd9Sstevel@tonic-gate hdlp->ih_vector = msi_num; 7337c478bd9Sstevel@tonic-gate break; 7347c478bd9Sstevel@tonic-gate case DDI_INTROP_DUPVEC: 73520036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: dupisr - inum: %x, " 73620036fe5Segillett "new_vector: %x\n", hdlp->ih_inum, hdlp->ih_scratch1); 73720036fe5Segillett 73820036fe5Segillett ret = pci_msix_dup(hdlp->ih_dip, hdlp->ih_inum, 73920036fe5Segillett hdlp->ih_scratch1); 7407c478bd9Sstevel@tonic-gate break; 7417c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 7427c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 7437c478bd9Sstevel@tonic-gate 7447c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_getmsiq(dip, msi_num, 7457c478bd9Sstevel@tonic-gate &msiq_id)) != DDI_SUCCESS) 7467c478bd9Sstevel@tonic-gate return (ret); 7477c478bd9Sstevel@tonic-gate 7487c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 7499c75c6bfSgovinda PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) 7507c478bd9Sstevel@tonic-gate return (ret); 7517c478bd9Sstevel@tonic-gate 7527c478bd9Sstevel@tonic-gate ret = px_rem_msiq_intr(dip, rdip, 7539c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 7547c478bd9Sstevel@tonic-gate 7557c478bd9Sstevel@tonic-gate hdlp->ih_vector = 0; 7567c478bd9Sstevel@tonic-gate break; 7577c478bd9Sstevel@tonic-gate case DDI_INTROP_ENABLE: 7587c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 7597c478bd9Sstevel@tonic-gate 7607c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 7617c478bd9Sstevel@tonic-gate PCI_MSI_VALID)) != DDI_SUCCESS) 7627c478bd9Sstevel@tonic-gate return (ret); 7637c478bd9Sstevel@tonic-gate 764*95003185Segillett if ((pci_is_msi_enabled(rdip, hdlp->ih_type) != DDI_SUCCESS) || 765*95003185Segillett (hdlp->ih_type == DDI_INTR_TYPE_MSIX)) { 7667c478bd9Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 7677c478bd9Sstevel@tonic-gate 7687c478bd9Sstevel@tonic-gate if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 7699c75c6bfSgovinda nintrs, hdlp->ih_inum, msi_addr, 770*95003185Segillett hdlp->ih_type == DDI_INTR_TYPE_MSIX ? 771*95003185Segillett msi_num : msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 7727c478bd9Sstevel@tonic-gate return (ret); 7737c478bd9Sstevel@tonic-gate 774*95003185Segillett if ((ret = pci_msi_enable_mode(rdip, hdlp->ih_type)) 775*95003185Segillett != DDI_SUCCESS) 7767c478bd9Sstevel@tonic-gate return (ret); 7777c478bd9Sstevel@tonic-gate } 7787c478bd9Sstevel@tonic-gate 77936fe4a92Segillett if ((ret = pci_msi_clr_mask(rdip, hdlp->ih_type, 78036fe4a92Segillett hdlp->ih_inum)) != DDI_SUCCESS) 78136fe4a92Segillett return (ret); 78236fe4a92Segillett 78320036fe5Segillett if (hdlp->ih_flags & DDI_INTR_MSIX_DUP) 78420036fe5Segillett break; 78520036fe5Segillett 78636fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 78736fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 78836fe4a92Segillett return (ret); 78936fe4a92Segillett 79036fe4a92Segillett ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 79136fe4a92Segillett px_msiqid_to_devino(px_p, msiq_id), PX_INTR_STATE_ENABLE, 7929c75c6bfSgovinda msiq_rec_type, msi_num); 7937c478bd9Sstevel@tonic-gate 7947c478bd9Sstevel@tonic-gate break; 7957c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 7967c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 7977c478bd9Sstevel@tonic-gate 7987c478bd9Sstevel@tonic-gate if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type, 7997c478bd9Sstevel@tonic-gate hdlp->ih_inum)) != DDI_SUCCESS) 8007c478bd9Sstevel@tonic-gate return (ret); 8017c478bd9Sstevel@tonic-gate 80236fe4a92Segillett if ((ret = px_lib_msi_setvalid(dip, msi_num, 80336fe4a92Segillett PCI_MSI_INVALID)) != DDI_SUCCESS) 80436fe4a92Segillett return (ret); 80536fe4a92Segillett 80620036fe5Segillett if (hdlp->ih_flags & DDI_INTR_MSIX_DUP) 80720036fe5Segillett break; 80820036fe5Segillett 80936fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 81036fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 81136fe4a92Segillett return (ret); 81236fe4a92Segillett 81336fe4a92Segillett ret = px_ib_update_intr_state(px_p, rdip, 81436fe4a92Segillett hdlp->ih_inum, px_msiqid_to_devino(px_p, msiq_id), 8159c75c6bfSgovinda PX_INTR_STATE_DISABLE, msiq_rec_type, msi_num); 81636fe4a92Segillett 8177c478bd9Sstevel@tonic-gate break; 8187c478bd9Sstevel@tonic-gate case DDI_INTROP_BLOCKENABLE: 8197c478bd9Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 8207c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 8217c478bd9Sstevel@tonic-gate 8227c478bd9Sstevel@tonic-gate if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 8239c75c6bfSgovinda nintrs, hdlp->ih_inum, msi_addr, 8247c478bd9Sstevel@tonic-gate msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 8257c478bd9Sstevel@tonic-gate return (ret); 8267c478bd9Sstevel@tonic-gate 8277c478bd9Sstevel@tonic-gate for (i = 0; i < nintrs; i++, msi_num++) { 8287c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 8297c478bd9Sstevel@tonic-gate PCI_MSI_VALID)) != DDI_SUCCESS) 8307c478bd9Sstevel@tonic-gate return (ret); 83136fe4a92Segillett 83236fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 83336fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 83436fe4a92Segillett return (ret); 83536fe4a92Segillett 83636fe4a92Segillett if ((ret = px_ib_update_intr_state(px_p, rdip, 83736fe4a92Segillett hdlp->ih_inum + i, px_msiqid_to_devino(px_p, 8389c75c6bfSgovinda msiq_id), PX_INTR_STATE_ENABLE, msiq_rec_type, 8399c75c6bfSgovinda msi_num)) != DDI_SUCCESS) 84036fe4a92Segillett return (ret); 8417c478bd9Sstevel@tonic-gate } 8427c478bd9Sstevel@tonic-gate 843*95003185Segillett ret = pci_msi_enable_mode(rdip, hdlp->ih_type); 8447c478bd9Sstevel@tonic-gate break; 8457c478bd9Sstevel@tonic-gate case DDI_INTROP_BLOCKDISABLE: 8467c478bd9Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 8477c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 8487c478bd9Sstevel@tonic-gate 8497c478bd9Sstevel@tonic-gate if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type, 850*95003185Segillett hdlp->ih_cap & DDI_INTR_FLAG_BLOCK)) != DDI_SUCCESS) 8517c478bd9Sstevel@tonic-gate return (ret); 8527c478bd9Sstevel@tonic-gate 8537c478bd9Sstevel@tonic-gate for (i = 0; i < nintrs; i++, msi_num++) { 8547c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 8557c478bd9Sstevel@tonic-gate PCI_MSI_INVALID)) != DDI_SUCCESS) 8567c478bd9Sstevel@tonic-gate return (ret); 85736fe4a92Segillett 85836fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 85936fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 86036fe4a92Segillett return (ret); 86136fe4a92Segillett 86236fe4a92Segillett if ((ret = px_ib_update_intr_state(px_p, rdip, 86336fe4a92Segillett hdlp->ih_inum + i, px_msiqid_to_devino(px_p, 8649c75c6bfSgovinda msiq_id), PX_INTR_STATE_DISABLE, msiq_rec_type, 86536fe4a92Segillett msi_num)) != DDI_SUCCESS) 86636fe4a92Segillett return (ret); 8677c478bd9Sstevel@tonic-gate } 8687c478bd9Sstevel@tonic-gate 8697c478bd9Sstevel@tonic-gate break; 8707c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 8717c478bd9Sstevel@tonic-gate ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 8727c478bd9Sstevel@tonic-gate break; 8737c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 8747c478bd9Sstevel@tonic-gate ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 8757c478bd9Sstevel@tonic-gate break; 8767c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 8777c478bd9Sstevel@tonic-gate ret = pci_msi_get_pending(rdip, hdlp->ih_type, 8787c478bd9Sstevel@tonic-gate hdlp->ih_inum, (int *)result); 8797c478bd9Sstevel@tonic-gate break; 8807c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 8817c478bd9Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 8827c478bd9Sstevel@tonic-gate break; 8837c478bd9Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 8847c478bd9Sstevel@tonic-gate /* XXX - a new interface may be needed */ 8857c478bd9Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 8867c478bd9Sstevel@tonic-gate break; 8877c478bd9Sstevel@tonic-gate default: 8887c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 8897c478bd9Sstevel@tonic-gate break; 8907c478bd9Sstevel@tonic-gate } 8917c478bd9Sstevel@tonic-gate 8927c478bd9Sstevel@tonic-gate return (ret); 8937c478bd9Sstevel@tonic-gate } 8947c478bd9Sstevel@tonic-gate 8956d44af1bSesolom static struct { 8966d44af1bSesolom kstat_named_t pxintr_ks_name; 8976d44af1bSesolom kstat_named_t pxintr_ks_type; 8986d44af1bSesolom kstat_named_t pxintr_ks_cpu; 8996d44af1bSesolom kstat_named_t pxintr_ks_pil; 9006d44af1bSesolom kstat_named_t pxintr_ks_time; 9016d44af1bSesolom kstat_named_t pxintr_ks_ino; 9026d44af1bSesolom kstat_named_t pxintr_ks_cookie; 9036d44af1bSesolom kstat_named_t pxintr_ks_devpath; 9046d44af1bSesolom kstat_named_t pxintr_ks_buspath; 9056d44af1bSesolom } pxintr_ks_template = { 9066d44af1bSesolom { "name", KSTAT_DATA_CHAR }, 9076d44af1bSesolom { "type", KSTAT_DATA_CHAR }, 9086d44af1bSesolom { "cpu", KSTAT_DATA_UINT64 }, 9096d44af1bSesolom { "pil", KSTAT_DATA_UINT64 }, 9106d44af1bSesolom { "time", KSTAT_DATA_UINT64 }, 9116d44af1bSesolom { "ino", KSTAT_DATA_UINT64 }, 9126d44af1bSesolom { "cookie", KSTAT_DATA_UINT64 }, 9136d44af1bSesolom { "devpath", KSTAT_DATA_STRING }, 9146d44af1bSesolom { "buspath", KSTAT_DATA_STRING }, 9156d44af1bSesolom }; 9166d44af1bSesolom 9176d44af1bSesolom static uint32_t pxintr_ks_instance; 918d48713b8Sesolom static char ih_devpath[MAXPATHLEN]; 919d48713b8Sesolom static char ih_buspath[MAXPATHLEN]; 9206d44af1bSesolom kmutex_t pxintr_ks_template_lock; 9216d44af1bSesolom 9226d44af1bSesolom int 9236d44af1bSesolom px_ks_update(kstat_t *ksp, int rw) 9246d44af1bSesolom { 9256d44af1bSesolom px_ih_t *ih_p = ksp->ks_private; 9266d44af1bSesolom int maxlen = sizeof (pxintr_ks_template.pxintr_ks_name.value.c); 9276d44af1bSesolom px_ib_t *ib_p = ih_p->ih_ino_p->ino_ib_p; 9286d44af1bSesolom px_t *px_p = ib_p->ib_px_p; 9296d44af1bSesolom devino_t ino; 9306d44af1bSesolom sysino_t sysino; 9316d44af1bSesolom 9326d44af1bSesolom ino = ih_p->ih_ino_p->ino_ino; 9336d44af1bSesolom (void) px_lib_intr_devino_to_sysino(px_p->px_dip, ino, &sysino); 9346d44af1bSesolom 9356d44af1bSesolom (void) snprintf(pxintr_ks_template.pxintr_ks_name.value.c, maxlen, 9366d44af1bSesolom "%s%d", ddi_driver_name(ih_p->ih_dip), 9376d44af1bSesolom ddi_get_instance(ih_p->ih_dip)); 9386d44af1bSesolom 9396d44af1bSesolom (void) ddi_pathname(ih_p->ih_dip, ih_devpath); 9406d44af1bSesolom (void) ddi_pathname(px_p->px_dip, ih_buspath); 9416d44af1bSesolom kstat_named_setstr(&pxintr_ks_template.pxintr_ks_devpath, ih_devpath); 9426d44af1bSesolom kstat_named_setstr(&pxintr_ks_template.pxintr_ks_buspath, ih_buspath); 9436d44af1bSesolom 944e1d9f4e6Sschwartz if (ih_p->ih_intr_state == PX_INTR_STATE_ENABLE) { 945e1d9f4e6Sschwartz 946e1d9f4e6Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 947e1d9f4e6Sschwartz (ih_p->ih_rec_type == 0) ? "fixed" : "msi"); 948e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cpu.value.ui64 = 949e1d9f4e6Sschwartz ih_p->ih_ino_p->ino_cpuid; 950e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_pil.value.ui64 = 951e1d9f4e6Sschwartz ih_p->ih_ino_p->ino_pil; 952e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_time.value.ui64 = ih_p->ih_nsec + 953e1d9f4e6Sschwartz (uint64_t)tick2ns((hrtime_t)ih_p->ih_ticks, 954e1d9f4e6Sschwartz ih_p->ih_ino_p->ino_cpuid); 955e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_ino.value.ui64 = ino; 956e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cookie.value.ui64 = sysino; 957e1d9f4e6Sschwartz } else { 958e1d9f4e6Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 959e1d9f4e6Sschwartz "disabled"); 960e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cpu.value.ui64 = 0; 961e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_pil.value.ui64 = 0; 962e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_time.value.ui64 = 0; 963e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_ino.value.ui64 = 0; 964e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cookie.value.ui64 = 0; 965e1d9f4e6Sschwartz } 9666d44af1bSesolom return (0); 9676d44af1bSesolom } 9686d44af1bSesolom 9696d44af1bSesolom void 9706d44af1bSesolom px_create_intr_kstats(px_ih_t *ih_p) 9716d44af1bSesolom { 9726d44af1bSesolom msiq_rec_type_t rec_type = ih_p->ih_rec_type; 9736d44af1bSesolom 9746d44af1bSesolom ASSERT(ih_p->ih_ksp == NULL); 9756d44af1bSesolom 9766d44af1bSesolom /* 9776d44af1bSesolom * Create pci_intrs::: kstats for all ih types except messages, 9786d44af1bSesolom * which represent unusual conditions and don't need to be tracked. 9796d44af1bSesolom */ 9806d44af1bSesolom if (rec_type == 0 || rec_type == MSI32_REC || rec_type == MSI64_REC) { 9816d44af1bSesolom ih_p->ih_ksp = kstat_create("pci_intrs", 9826d44af1bSesolom atomic_inc_32_nv(&pxintr_ks_instance), "config", 9836d44af1bSesolom "interrupts", KSTAT_TYPE_NAMED, 9846d44af1bSesolom sizeof (pxintr_ks_template) / sizeof (kstat_named_t), 9856d44af1bSesolom KSTAT_FLAG_VIRTUAL); 9866d44af1bSesolom } 9876d44af1bSesolom if (ih_p->ih_ksp != NULL) { 9886d44af1bSesolom ih_p->ih_ksp->ks_data_size += MAXPATHLEN * 2; 9896d44af1bSesolom ih_p->ih_ksp->ks_lock = &pxintr_ks_template_lock; 9906d44af1bSesolom ih_p->ih_ksp->ks_data = &pxintr_ks_template; 9916d44af1bSesolom ih_p->ih_ksp->ks_private = ih_p; 9926d44af1bSesolom ih_p->ih_ksp->ks_update = px_ks_update; 9936d44af1bSesolom } 9946d44af1bSesolom } 9956d44af1bSesolom 996a195726fSgovinda /* 997a195726fSgovinda * px_add_intx_intr: 998a195726fSgovinda * 999a195726fSgovinda * This function is called to register INTx and legacy hardware 1000a195726fSgovinda * interrupt pins interrupts. 1001a195726fSgovinda */ 10027c478bd9Sstevel@tonic-gate int 10037c478bd9Sstevel@tonic-gate px_add_intx_intr(dev_info_t *dip, dev_info_t *rdip, 10047c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 10057c478bd9Sstevel@tonic-gate { 10067c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 10077c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 10087c478bd9Sstevel@tonic-gate devino_t ino; 10097c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 10107c478bd9Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 10117c478bd9Sstevel@tonic-gate int32_t weight; 10127c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 10137c478bd9Sstevel@tonic-gate 10147c478bd9Sstevel@tonic-gate ino = hdlp->ih_vector; 10157c478bd9Sstevel@tonic-gate 10167c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: rdip=%s%d ino=%x " 10177c478bd9Sstevel@tonic-gate "handler=%x arg1=%x arg2=%x\n", ddi_driver_name(rdip), 10187c478bd9Sstevel@tonic-gate ddi_get_instance(rdip), ino, hdlp->ih_cb_func, 10197c478bd9Sstevel@tonic-gate hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 10207c478bd9Sstevel@tonic-gate 10217c478bd9Sstevel@tonic-gate ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, 10227c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0); 10237c478bd9Sstevel@tonic-gate 10247c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 10257c478bd9Sstevel@tonic-gate 10267c478bd9Sstevel@tonic-gate if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 10277c478bd9Sstevel@tonic-gate uint32_t intr_index = hdlp->ih_inum; 10287c478bd9Sstevel@tonic-gate if (px_ib_ino_locate_intr(ino_p, rdip, intr_index, 0, 0)) { 10297c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: " 10307c478bd9Sstevel@tonic-gate "dup intr #%d\n", intr_index); 10317c478bd9Sstevel@tonic-gate 10327c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 10337c478bd9Sstevel@tonic-gate goto fail1; 10347c478bd9Sstevel@tonic-gate } 10357c478bd9Sstevel@tonic-gate 10367c478bd9Sstevel@tonic-gate /* Save mondo value in hdlp */ 10377c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 10387c478bd9Sstevel@tonic-gate 10397c478bd9Sstevel@tonic-gate if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 10407c478bd9Sstevel@tonic-gate != DDI_SUCCESS) 10417c478bd9Sstevel@tonic-gate goto fail1; 10427c478bd9Sstevel@tonic-gate } else { 10437c478bd9Sstevel@tonic-gate ino_p = px_ib_new_ino(ib_p, ino, ih_p); 10447c478bd9Sstevel@tonic-gate 10457c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 10467c478bd9Sstevel@tonic-gate hdlp->ih_pri = px_class_to_pil(rdip); 10477c478bd9Sstevel@tonic-gate 10487c478bd9Sstevel@tonic-gate /* Save mondo value in hdlp */ 10497c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 10507c478bd9Sstevel@tonic-gate 10517c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: pil=0x%x mondo=0x%x\n", 10527c478bd9Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 10537c478bd9Sstevel@tonic-gate 10547c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 10557c478bd9Sstevel@tonic-gate (ddi_intr_handler_t *)px_intx_intr, (caddr_t)ino_p, NULL); 10567c478bd9Sstevel@tonic-gate 10577c478bd9Sstevel@tonic-gate ret = i_ddi_add_ivintr(hdlp); 10587c478bd9Sstevel@tonic-gate 10597c478bd9Sstevel@tonic-gate /* 10607c478bd9Sstevel@tonic-gate * Restore original interrupt handler 10617c478bd9Sstevel@tonic-gate * and arguments in interrupt handle. 10627c478bd9Sstevel@tonic-gate */ 10637c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 10647c478bd9Sstevel@tonic-gate ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 10657c478bd9Sstevel@tonic-gate 10667c478bd9Sstevel@tonic-gate if (ret != DDI_SUCCESS) 10677c478bd9Sstevel@tonic-gate goto fail2; 10687c478bd9Sstevel@tonic-gate 10697c478bd9Sstevel@tonic-gate /* Save the pil for this ino */ 10707c478bd9Sstevel@tonic-gate ino_p->ino_pil = hdlp->ih_pri; 10717c478bd9Sstevel@tonic-gate 10727c478bd9Sstevel@tonic-gate /* select cpu, saving it for sharing and removal */ 10737c478bd9Sstevel@tonic-gate ino_p->ino_cpuid = intr_dist_cpuid(); 10747c478bd9Sstevel@tonic-gate 10757c478bd9Sstevel@tonic-gate /* Enable interrupt */ 10767c478bd9Sstevel@tonic-gate px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 10777c478bd9Sstevel@tonic-gate } 10787c478bd9Sstevel@tonic-gate 10797c478bd9Sstevel@tonic-gate /* add weight to the cpu that we are already targeting */ 10807c478bd9Sstevel@tonic-gate weight = px_class_to_intr_weight(rdip); 10817c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 10827c478bd9Sstevel@tonic-gate 10837c478bd9Sstevel@tonic-gate ih_p->ih_ino_p = ino_p; 10846d44af1bSesolom px_create_intr_kstats(ih_p); 10857c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp) 10867c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 10877c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 10887c478bd9Sstevel@tonic-gate 10897c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: done! Interrupt 0x%x pil=%x\n", 10907c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 10917c478bd9Sstevel@tonic-gate 10927c478bd9Sstevel@tonic-gate return (ret); 10937c478bd9Sstevel@tonic-gate fail2: 10947c478bd9Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 10957c478bd9Sstevel@tonic-gate fail1: 10967c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 10977c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 10987c478bd9Sstevel@tonic-gate 10997c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 11007c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 11017c478bd9Sstevel@tonic-gate 11027c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: Failed! Interrupt 0x%x " 11037c478bd9Sstevel@tonic-gate "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri); 11047c478bd9Sstevel@tonic-gate 11057c478bd9Sstevel@tonic-gate return (ret); 11067c478bd9Sstevel@tonic-gate } 11077c478bd9Sstevel@tonic-gate 1108a195726fSgovinda /* 1109a195726fSgovinda * px_rem_intx_intr: 1110a195726fSgovinda * 1111a195726fSgovinda * This function is called to unregister INTx and legacy hardware 1112a195726fSgovinda * interrupt pins interrupts. 1113a195726fSgovinda */ 11147c478bd9Sstevel@tonic-gate int 11157c478bd9Sstevel@tonic-gate px_rem_intx_intr(dev_info_t *dip, dev_info_t *rdip, 11167c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 11177c478bd9Sstevel@tonic-gate { 11187c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 11197c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 11207c478bd9Sstevel@tonic-gate devino_t ino; 11217c478bd9Sstevel@tonic-gate cpuid_t curr_cpu; 11227c478bd9Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 11237c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 11247c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 11257c478bd9Sstevel@tonic-gate 11267c478bd9Sstevel@tonic-gate ino = hdlp->ih_vector; 11277c478bd9Sstevel@tonic-gate 11287c478bd9Sstevel@tonic-gate DBG(DBG_R_INTX, dip, "px_rem_intx_intr: rdip=%s%d ino=%x\n", 11297c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 11307c478bd9Sstevel@tonic-gate 11317c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 11327c478bd9Sstevel@tonic-gate 11337c478bd9Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 11347c478bd9Sstevel@tonic-gate ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 0, 0); 11357c478bd9Sstevel@tonic-gate 11367c478bd9Sstevel@tonic-gate /* Get the current cpu */ 11377c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 11387c478bd9Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 11397c478bd9Sstevel@tonic-gate goto fail; 11407c478bd9Sstevel@tonic-gate 11417c478bd9Sstevel@tonic-gate if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 11427c478bd9Sstevel@tonic-gate goto fail; 11437c478bd9Sstevel@tonic-gate 11447c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 11457c478bd9Sstevel@tonic-gate 11467c478bd9Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) { 11477c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 11487c478bd9Sstevel@tonic-gate INTR_DELIVERED_STATE)) != DDI_SUCCESS) 11497c478bd9Sstevel@tonic-gate goto fail; 11507c478bd9Sstevel@tonic-gate 11517c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 11527c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 11537c478bd9Sstevel@tonic-gate 11547c478bd9Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 11557c478bd9Sstevel@tonic-gate kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 11567c478bd9Sstevel@tonic-gate } else { 11577c478bd9Sstevel@tonic-gate /* Re-enable interrupt only if mapping regsiter still shared */ 1158a195726fSgovinda PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 11597c478bd9Sstevel@tonic-gate } 11607c478bd9Sstevel@tonic-gate 11617c478bd9Sstevel@tonic-gate fail: 11627c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 11637c478bd9Sstevel@tonic-gate return (ret); 11647c478bd9Sstevel@tonic-gate } 11657c478bd9Sstevel@tonic-gate 1166a195726fSgovinda /* 1167a195726fSgovinda * px_add_msiq_intr: 1168a195726fSgovinda * 1169a195726fSgovinda * This function is called to register MSI/Xs and PCIe message interrupts. 1170a195726fSgovinda */ 11717c478bd9Sstevel@tonic-gate int 11727c478bd9Sstevel@tonic-gate px_add_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 11737c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 11747c478bd9Sstevel@tonic-gate msgcode_t msg_code, msiqid_t *msiq_id_p) 11757c478bd9Sstevel@tonic-gate { 11767c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 11777c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 11787c478bd9Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &ib_p->ib_msiq_state; 11797c478bd9Sstevel@tonic-gate devino_t ino; 11807c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 11817c478bd9Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 11827c478bd9Sstevel@tonic-gate int32_t weight; 11837c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 11847c478bd9Sstevel@tonic-gate 11857c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=%x " 11867c478bd9Sstevel@tonic-gate "arg1=%x arg2=%x\n", ddi_driver_name(rdip), ddi_get_instance(rdip), 11877c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 11887c478bd9Sstevel@tonic-gate 11897c478bd9Sstevel@tonic-gate if ((ret = px_msiq_alloc(px_p, rec_type, msiq_id_p)) != DDI_SUCCESS) { 11907c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 11917c478bd9Sstevel@tonic-gate "msiq allocation failed\n"); 11927c478bd9Sstevel@tonic-gate return (ret); 11937c478bd9Sstevel@tonic-gate } 11947c478bd9Sstevel@tonic-gate 11957c478bd9Sstevel@tonic-gate ino = px_msiqid_to_devino(px_p, *msiq_id_p); 11967c478bd9Sstevel@tonic-gate 11977c478bd9Sstevel@tonic-gate ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func, 11987c478bd9Sstevel@tonic-gate hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code); 11997c478bd9Sstevel@tonic-gate 12007c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 12017c478bd9Sstevel@tonic-gate 12027c478bd9Sstevel@tonic-gate if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 12037c478bd9Sstevel@tonic-gate uint32_t intr_index = hdlp->ih_inum; 12047c478bd9Sstevel@tonic-gate if (px_ib_ino_locate_intr(ino_p, rdip, 12057c478bd9Sstevel@tonic-gate intr_index, rec_type, msg_code)) { 12067c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 12077c478bd9Sstevel@tonic-gate "dup intr #%d\n", intr_index); 12087c478bd9Sstevel@tonic-gate 12097c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 12107c478bd9Sstevel@tonic-gate goto fail1; 12117c478bd9Sstevel@tonic-gate } 12127c478bd9Sstevel@tonic-gate 12137c478bd9Sstevel@tonic-gate if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 12147c478bd9Sstevel@tonic-gate != DDI_SUCCESS) 12157c478bd9Sstevel@tonic-gate goto fail1; 12167c478bd9Sstevel@tonic-gate } else { 12177c478bd9Sstevel@tonic-gate ino_p = px_ib_new_ino(ib_p, ino, ih_p); 12187c478bd9Sstevel@tonic-gate 12197c478bd9Sstevel@tonic-gate ino_p->ino_msiq_p = msiq_state_p->msiq_p + 12207c478bd9Sstevel@tonic-gate (*msiq_id_p - msiq_state_p->msiq_1st_msiq_id); 12217c478bd9Sstevel@tonic-gate 12227c478bd9Sstevel@tonic-gate if (hdlp->ih_pri == 0) 12237c478bd9Sstevel@tonic-gate hdlp->ih_pri = px_class_to_pil(rdip); 12247c478bd9Sstevel@tonic-gate 12257c478bd9Sstevel@tonic-gate /* Save mondo value in hdlp */ 12267c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 12277c478bd9Sstevel@tonic-gate 12287c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n", 12297c478bd9Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 12307c478bd9Sstevel@tonic-gate 12317c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 12327c478bd9Sstevel@tonic-gate (ddi_intr_handler_t *)px_msiq_intr, (caddr_t)ino_p, NULL); 12337c478bd9Sstevel@tonic-gate 12347c478bd9Sstevel@tonic-gate ret = i_ddi_add_ivintr(hdlp); 12357c478bd9Sstevel@tonic-gate 12367c478bd9Sstevel@tonic-gate /* 12377c478bd9Sstevel@tonic-gate * Restore original interrupt handler 12387c478bd9Sstevel@tonic-gate * and arguments in interrupt handle. 12397c478bd9Sstevel@tonic-gate */ 12407c478bd9Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 12417c478bd9Sstevel@tonic-gate ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 12427c478bd9Sstevel@tonic-gate 12437c478bd9Sstevel@tonic-gate if (ret != DDI_SUCCESS) 12447c478bd9Sstevel@tonic-gate goto fail2; 12457c478bd9Sstevel@tonic-gate 12467c478bd9Sstevel@tonic-gate /* Save the pil for this ino */ 12477c478bd9Sstevel@tonic-gate ino_p->ino_pil = hdlp->ih_pri; 12487c478bd9Sstevel@tonic-gate 12497c478bd9Sstevel@tonic-gate /* Enable MSIQ */ 12507c478bd9Sstevel@tonic-gate px_lib_msiq_setstate(dip, *msiq_id_p, PCI_MSIQ_STATE_IDLE); 12517c478bd9Sstevel@tonic-gate px_lib_msiq_setvalid(dip, *msiq_id_p, PCI_MSIQ_VALID); 12527c478bd9Sstevel@tonic-gate 12537c478bd9Sstevel@tonic-gate /* select cpu, saving it for sharing and removal */ 12547c478bd9Sstevel@tonic-gate ino_p->ino_cpuid = intr_dist_cpuid(); 12557c478bd9Sstevel@tonic-gate 12567c478bd9Sstevel@tonic-gate /* Enable interrupt */ 12577c478bd9Sstevel@tonic-gate px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino_p->ino_ino); 12587c478bd9Sstevel@tonic-gate } 12597c478bd9Sstevel@tonic-gate 12607c478bd9Sstevel@tonic-gate /* add weight to the cpu that we are already targeting */ 12617c478bd9Sstevel@tonic-gate weight = px_class_to_intr_weight(rdip); 12627c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 12637c478bd9Sstevel@tonic-gate 12647c478bd9Sstevel@tonic-gate ih_p->ih_ino_p = ino_p; 12656d44af1bSesolom px_create_intr_kstats(ih_p); 12667c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp) 12677c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 12687c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 12697c478bd9Sstevel@tonic-gate 12707c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n", 12717c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 12727c478bd9Sstevel@tonic-gate 12737c478bd9Sstevel@tonic-gate return (ret); 12747c478bd9Sstevel@tonic-gate fail2: 12757c478bd9Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 12767c478bd9Sstevel@tonic-gate fail1: 12777c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 12787c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 12797c478bd9Sstevel@tonic-gate 12807c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 12817c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 12827c478bd9Sstevel@tonic-gate 12837c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n", 12847c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 12857c478bd9Sstevel@tonic-gate 12867c478bd9Sstevel@tonic-gate return (ret); 12877c478bd9Sstevel@tonic-gate } 12887c478bd9Sstevel@tonic-gate 1289a195726fSgovinda /* 1290a195726fSgovinda * px_rem_msiq_intr: 1291a195726fSgovinda * 1292a195726fSgovinda * This function is called to unregister MSI/Xs and PCIe message interrupts. 1293a195726fSgovinda */ 12947c478bd9Sstevel@tonic-gate int 12957c478bd9Sstevel@tonic-gate px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 12967c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 12977c478bd9Sstevel@tonic-gate msgcode_t msg_code, msiqid_t msiq_id) 12987c478bd9Sstevel@tonic-gate { 12997c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 13007c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 13017c478bd9Sstevel@tonic-gate devino_t ino = px_msiqid_to_devino(px_p, msiq_id); 13027c478bd9Sstevel@tonic-gate cpuid_t curr_cpu; 13037c478bd9Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 13047c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 13057c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 13067c478bd9Sstevel@tonic-gate 13077c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n", 13087c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), msiq_id, ino); 13097c478bd9Sstevel@tonic-gate 13107c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 13117c478bd9Sstevel@tonic-gate 13127c478bd9Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 13137c478bd9Sstevel@tonic-gate ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 13147c478bd9Sstevel@tonic-gate rec_type, msg_code); 13157c478bd9Sstevel@tonic-gate 13167c478bd9Sstevel@tonic-gate /* Get the current cpu */ 13177c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 13187c478bd9Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 13197c478bd9Sstevel@tonic-gate goto fail; 13207c478bd9Sstevel@tonic-gate 13217c478bd9Sstevel@tonic-gate if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 13227c478bd9Sstevel@tonic-gate goto fail; 13237c478bd9Sstevel@tonic-gate 13247c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 13257c478bd9Sstevel@tonic-gate 13267c478bd9Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) { 13277c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 13287c478bd9Sstevel@tonic-gate INTR_DELIVERED_STATE)) != DDI_SUCCESS) 13297c478bd9Sstevel@tonic-gate goto fail; 13307c478bd9Sstevel@tonic-gate 13317c478bd9Sstevel@tonic-gate px_lib_msiq_setvalid(dip, px_devino_to_msiqid(px_p, ino), 13327c478bd9Sstevel@tonic-gate PCI_MSIQ_INVALID); 13337c478bd9Sstevel@tonic-gate 13347c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 13357c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 13367c478bd9Sstevel@tonic-gate 13377c478bd9Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 13387c478bd9Sstevel@tonic-gate 13397c478bd9Sstevel@tonic-gate (void) px_msiq_free(px_p, msiq_id); 13407c478bd9Sstevel@tonic-gate kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 13417c478bd9Sstevel@tonic-gate } else { 13427c478bd9Sstevel@tonic-gate /* Re-enable interrupt only if mapping regsiter still shared */ 1343a195726fSgovinda PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 13447c478bd9Sstevel@tonic-gate } 13457c478bd9Sstevel@tonic-gate 13467c478bd9Sstevel@tonic-gate fail: 13477c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 13487c478bd9Sstevel@tonic-gate return (ret); 13497c478bd9Sstevel@tonic-gate } 1350