xref: /illumos-gate/usr/src/uts/sun4/io/px/px_intr.c (revision 7c478bd9)
1*7c478bd9Sstevel@tonic-gate /*
2*7c478bd9Sstevel@tonic-gate  * CDDL HEADER START
3*7c478bd9Sstevel@tonic-gate  *
4*7c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*7c478bd9Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
6*7c478bd9Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
7*7c478bd9Sstevel@tonic-gate  * with the License.
8*7c478bd9Sstevel@tonic-gate  *
9*7c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*7c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
11*7c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
12*7c478bd9Sstevel@tonic-gate  * and limitations under the License.
13*7c478bd9Sstevel@tonic-gate  *
14*7c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
15*7c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*7c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
17*7c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
18*7c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
19*7c478bd9Sstevel@tonic-gate  *
20*7c478bd9Sstevel@tonic-gate  * CDDL HEADER END
21*7c478bd9Sstevel@tonic-gate  */
22*7c478bd9Sstevel@tonic-gate /*
23*7c478bd9Sstevel@tonic-gate  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24*7c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
25*7c478bd9Sstevel@tonic-gate  */
26*7c478bd9Sstevel@tonic-gate 
27*7c478bd9Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
28*7c478bd9Sstevel@tonic-gate 
29*7c478bd9Sstevel@tonic-gate /*
30*7c478bd9Sstevel@tonic-gate  * PX nexus interrupt handling:
31*7c478bd9Sstevel@tonic-gate  *	PX device interrupt handler wrapper
32*7c478bd9Sstevel@tonic-gate  *	PIL lookup routine
33*7c478bd9Sstevel@tonic-gate  *	PX device interrupt related initchild code
34*7c478bd9Sstevel@tonic-gate  */
35*7c478bd9Sstevel@tonic-gate 
36*7c478bd9Sstevel@tonic-gate #include <sys/types.h>
37*7c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
38*7c478bd9Sstevel@tonic-gate #include <sys/async.h>
39*7c478bd9Sstevel@tonic-gate #include <sys/spl.h>
40*7c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
41*7c478bd9Sstevel@tonic-gate #include <sys/machsystm.h>	/* e_ddi_nodeid_to_dip() */
42*7c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h>
43*7c478bd9Sstevel@tonic-gate #include <sys/sdt.h>
44*7c478bd9Sstevel@tonic-gate #include <sys/atomic.h>
45*7c478bd9Sstevel@tonic-gate #include "px_obj.h"
46*7c478bd9Sstevel@tonic-gate 
47*7c478bd9Sstevel@tonic-gate /*
48*7c478bd9Sstevel@tonic-gate  * interrupt jabber:
49*7c478bd9Sstevel@tonic-gate  *
50*7c478bd9Sstevel@tonic-gate  * When an interrupt line is jabbering, every time the state machine for the
51*7c478bd9Sstevel@tonic-gate  * associated ino is idled, a new mondo will be sent and the ino will go into
52*7c478bd9Sstevel@tonic-gate  * the pending state again. The mondo will cause a new call to
53*7c478bd9Sstevel@tonic-gate  * px_intr_wrapper() which normally idles the ino's state machine which would
54*7c478bd9Sstevel@tonic-gate  * precipitate another trip round the loop.
55*7c478bd9Sstevel@tonic-gate  *
56*7c478bd9Sstevel@tonic-gate  * The loop can be broken by preventing the ino's state machine from being
57*7c478bd9Sstevel@tonic-gate  * idled when an interrupt line is jabbering. See the comment at the
58*7c478bd9Sstevel@tonic-gate  * beginning of px_intr_wrapper() explaining how the 'interrupt jabber
59*7c478bd9Sstevel@tonic-gate  * protection' code does this.
60*7c478bd9Sstevel@tonic-gate  */
61*7c478bd9Sstevel@tonic-gate 
62*7c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/
63*7c478bd9Sstevel@tonic-gate 
64*7c478bd9Sstevel@tonic-gate 
65*7c478bd9Sstevel@tonic-gate /*
66*7c478bd9Sstevel@tonic-gate  * If the unclaimed interrupt count has reached the limit set by
67*7c478bd9Sstevel@tonic-gate  * pci_unclaimed_intr_max within the time limit, then all interrupts
68*7c478bd9Sstevel@tonic-gate  * on this ino is blocked by not idling the interrupt state machine.
69*7c478bd9Sstevel@tonic-gate  */
70*7c478bd9Sstevel@tonic-gate static int
71*7c478bd9Sstevel@tonic-gate px_spurintr(px_ib_ino_info_t *ino_p)
72*7c478bd9Sstevel@tonic-gate {
73*7c478bd9Sstevel@tonic-gate 	px_ih_t	*ih_p = ino_p->ino_ih_start;
74*7c478bd9Sstevel@tonic-gate 	px_t	*px_p = ino_p->ino_ib_p->ib_px_p;
75*7c478bd9Sstevel@tonic-gate 	char	*err_fmt_str;
76*7c478bd9Sstevel@tonic-gate 	int	i;
77*7c478bd9Sstevel@tonic-gate 
78*7c478bd9Sstevel@tonic-gate 	if (ino_p->ino_unclaimed > px_unclaimed_intr_max)
79*7c478bd9Sstevel@tonic-gate 		return (DDI_INTR_CLAIMED);
80*7c478bd9Sstevel@tonic-gate 
81*7c478bd9Sstevel@tonic-gate 	if (!ino_p->ino_unclaimed)
82*7c478bd9Sstevel@tonic-gate 		ino_p->ino_spurintr_begin = ddi_get_lbolt();
83*7c478bd9Sstevel@tonic-gate 
84*7c478bd9Sstevel@tonic-gate 	ino_p->ino_unclaimed++;
85*7c478bd9Sstevel@tonic-gate 
86*7c478bd9Sstevel@tonic-gate 	if (ino_p->ino_unclaimed <= px_unclaimed_intr_max)
87*7c478bd9Sstevel@tonic-gate 		goto clear;
88*7c478bd9Sstevel@tonic-gate 
89*7c478bd9Sstevel@tonic-gate 	if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin)
90*7c478bd9Sstevel@tonic-gate 	    > px_spurintr_duration) {
91*7c478bd9Sstevel@tonic-gate 		ino_p->ino_unclaimed = 0;
92*7c478bd9Sstevel@tonic-gate 		goto clear;
93*7c478bd9Sstevel@tonic-gate 	}
94*7c478bd9Sstevel@tonic-gate 	err_fmt_str = "%s%d: ino 0x%x blocked";
95*7c478bd9Sstevel@tonic-gate 	goto warn;
96*7c478bd9Sstevel@tonic-gate clear:
97*7c478bd9Sstevel@tonic-gate 	/* Clear the pending state */
98*7c478bd9Sstevel@tonic-gate 	if (px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino,
99*7c478bd9Sstevel@tonic-gate 	    INTR_IDLE_STATE) != DDI_SUCCESS)
100*7c478bd9Sstevel@tonic-gate 		return (DDI_INTR_UNCLAIMED);
101*7c478bd9Sstevel@tonic-gate 
102*7c478bd9Sstevel@tonic-gate 	err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x";
103*7c478bd9Sstevel@tonic-gate warn:
104*7c478bd9Sstevel@tonic-gate 	cmn_err(CE_WARN, err_fmt_str, NAMEINST(px_p->px_dip), ino_p->ino_ino);
105*7c478bd9Sstevel@tonic-gate 	for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next)
106*7c478bd9Sstevel@tonic-gate 		cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip),
107*7c478bd9Sstevel@tonic-gate 		    ih_p->ih_inum);
108*7c478bd9Sstevel@tonic-gate 	cmn_err(CE_CONT, "!\n");
109*7c478bd9Sstevel@tonic-gate 	return (DDI_INTR_CLAIMED);
110*7c478bd9Sstevel@tonic-gate }
111*7c478bd9Sstevel@tonic-gate 
112*7c478bd9Sstevel@tonic-gate 
113*7c478bd9Sstevel@tonic-gate extern uint64_t intr_get_time(void);
114*7c478bd9Sstevel@tonic-gate 
115*7c478bd9Sstevel@tonic-gate /*
116*7c478bd9Sstevel@tonic-gate  * px_intx_intr (legacy or intx interrupt handler)
117*7c478bd9Sstevel@tonic-gate  *
118*7c478bd9Sstevel@tonic-gate  * This routine is used as wrapper around interrupt handlers installed by child
119*7c478bd9Sstevel@tonic-gate  * device drivers.  This routine invokes the driver interrupt handlers and
120*7c478bd9Sstevel@tonic-gate  * examines the return codes.
121*7c478bd9Sstevel@tonic-gate  *
122*7c478bd9Sstevel@tonic-gate  * There is a count of unclaimed interrupts kept on a per-ino basis. If at
123*7c478bd9Sstevel@tonic-gate  * least one handler claims the interrupt then the counter is halved and the
124*7c478bd9Sstevel@tonic-gate  * interrupt state machine is idled. If no handler claims the interrupt then
125*7c478bd9Sstevel@tonic-gate  * the counter is incremented by one and the state machine is idled.
126*7c478bd9Sstevel@tonic-gate  * If the count ever reaches the limit value set by pci_unclaimed_intr_max
127*7c478bd9Sstevel@tonic-gate  * then the interrupt state machine is not idled thus preventing any further
128*7c478bd9Sstevel@tonic-gate  * interrupts on that ino. The state machine will only be idled again if a
129*7c478bd9Sstevel@tonic-gate  * handler is subsequently added or removed.
130*7c478bd9Sstevel@tonic-gate  *
131*7c478bd9Sstevel@tonic-gate  * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt,
132*7c478bd9Sstevel@tonic-gate  * DDI_INTR_UNCLAIMED otherwise.
133*7c478bd9Sstevel@tonic-gate  */
134*7c478bd9Sstevel@tonic-gate uint_t
135*7c478bd9Sstevel@tonic-gate px_intx_intr(caddr_t arg)
136*7c478bd9Sstevel@tonic-gate {
137*7c478bd9Sstevel@tonic-gate 	px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg;
138*7c478bd9Sstevel@tonic-gate 	px_t		*px_p = ino_p->ino_ib_p->ib_px_p;
139*7c478bd9Sstevel@tonic-gate 	px_ih_t		*ih_p = ino_p->ino_ih_start;
140*7c478bd9Sstevel@tonic-gate 	uint_t		result = 0, r;
141*7c478bd9Sstevel@tonic-gate 	int		i;
142*7c478bd9Sstevel@tonic-gate 
143*7c478bd9Sstevel@tonic-gate 	DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:"
144*7c478bd9Sstevel@tonic-gate 	    "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n",
145*7c478bd9Sstevel@tonic-gate 	    ino_p->ino_ino, ino_p->ino_sysino, ino_p->ino_pil,
146*7c478bd9Sstevel@tonic-gate 	    ino_p->ino_ih_size, ino_p->ino_ih_head);
147*7c478bd9Sstevel@tonic-gate 
148*7c478bd9Sstevel@tonic-gate 	for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) {
149*7c478bd9Sstevel@tonic-gate 		dev_info_t *dip = ih_p->ih_dip;
150*7c478bd9Sstevel@tonic-gate 		uint_t (*handler)() = ih_p->ih_handler;
151*7c478bd9Sstevel@tonic-gate 		caddr_t arg1 = ih_p->ih_handler_arg1;
152*7c478bd9Sstevel@tonic-gate 		caddr_t arg2 = ih_p->ih_handler_arg2;
153*7c478bd9Sstevel@tonic-gate 
154*7c478bd9Sstevel@tonic-gate 		if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) {
155*7c478bd9Sstevel@tonic-gate 			DBG(DBG_INTX_INTR, px_p->px_dip,
156*7c478bd9Sstevel@tonic-gate 			    "px_intx_intr: %s%d interrupt %d is disabled\n",
157*7c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
158*7c478bd9Sstevel@tonic-gate 			    ino_p->ino_ino);
159*7c478bd9Sstevel@tonic-gate 
160*7c478bd9Sstevel@tonic-gate 			continue;
161*7c478bd9Sstevel@tonic-gate 		}
162*7c478bd9Sstevel@tonic-gate 
163*7c478bd9Sstevel@tonic-gate 		DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:"
164*7c478bd9Sstevel@tonic-gate 		    "ino=%x handler=%p arg1 =%p arg2 = %p\n",
165*7c478bd9Sstevel@tonic-gate 		    ino_p->ino_ino, handler, arg1, arg2);
166*7c478bd9Sstevel@tonic-gate 
167*7c478bd9Sstevel@tonic-gate 		DTRACE_PROBE4(interrupt__start, dev_info_t, dip,
168*7c478bd9Sstevel@tonic-gate 		    void *, handler, caddr_t, arg1, caddr_t, arg2);
169*7c478bd9Sstevel@tonic-gate 
170*7c478bd9Sstevel@tonic-gate 		r = (*handler)(arg1, arg2);
171*7c478bd9Sstevel@tonic-gate 
172*7c478bd9Sstevel@tonic-gate 		/*
173*7c478bd9Sstevel@tonic-gate 		 * Account for time used by this interrupt. Protect against
174*7c478bd9Sstevel@tonic-gate 		 * conflicting writes to ih_ticks from ib_intr_dist_all() by
175*7c478bd9Sstevel@tonic-gate 		 * using atomic ops.
176*7c478bd9Sstevel@tonic-gate 		 */
177*7c478bd9Sstevel@tonic-gate 
178*7c478bd9Sstevel@tonic-gate 		if (ino_p->ino_pil <= LOCK_LEVEL)
179*7c478bd9Sstevel@tonic-gate 			atomic_add_64(&ih_p->ih_ticks, intr_get_time());
180*7c478bd9Sstevel@tonic-gate 
181*7c478bd9Sstevel@tonic-gate 		DTRACE_PROBE4(interrupt__complete, dev_info_t, dip,
182*7c478bd9Sstevel@tonic-gate 		    void *, handler, caddr_t, arg1, int, r);
183*7c478bd9Sstevel@tonic-gate 
184*7c478bd9Sstevel@tonic-gate 		result += r;
185*7c478bd9Sstevel@tonic-gate 
186*7c478bd9Sstevel@tonic-gate 		if (px_check_all_handlers)
187*7c478bd9Sstevel@tonic-gate 			continue;
188*7c478bd9Sstevel@tonic-gate 		if (result)
189*7c478bd9Sstevel@tonic-gate 			break;
190*7c478bd9Sstevel@tonic-gate 	}
191*7c478bd9Sstevel@tonic-gate 
192*7c478bd9Sstevel@tonic-gate 	if (!result && px_unclaimed_intr_block)
193*7c478bd9Sstevel@tonic-gate 		return (px_spurintr(ino_p));
194*7c478bd9Sstevel@tonic-gate 
195*7c478bd9Sstevel@tonic-gate 	ino_p->ino_unclaimed = 0;
196*7c478bd9Sstevel@tonic-gate 
197*7c478bd9Sstevel@tonic-gate 	/* Clear the pending state */
198*7c478bd9Sstevel@tonic-gate 	if (px_lib_intr_setstate(ino_p->ino_ib_p->ib_px_p->px_dip,
199*7c478bd9Sstevel@tonic-gate 	    ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS)
200*7c478bd9Sstevel@tonic-gate 		return (DDI_INTR_UNCLAIMED);
201*7c478bd9Sstevel@tonic-gate 
202*7c478bd9Sstevel@tonic-gate 	return (DDI_INTR_CLAIMED);
203*7c478bd9Sstevel@tonic-gate }
204*7c478bd9Sstevel@tonic-gate 
205*7c478bd9Sstevel@tonic-gate /*
206*7c478bd9Sstevel@tonic-gate  * px_msiq_intr (MSI/MSIX/MSG interrupt handler)
207*7c478bd9Sstevel@tonic-gate  *
208*7c478bd9Sstevel@tonic-gate  * This routine is used as wrapper around interrupt handlers installed by child
209*7c478bd9Sstevel@tonic-gate  * device drivers.  This routine invokes the driver interrupt handlers and
210*7c478bd9Sstevel@tonic-gate  * examines the return codes.
211*7c478bd9Sstevel@tonic-gate  *
212*7c478bd9Sstevel@tonic-gate  * There is a count of unclaimed interrupts kept on a per-ino basis. If at
213*7c478bd9Sstevel@tonic-gate  * least one handler claims the interrupt then the counter is halved and the
214*7c478bd9Sstevel@tonic-gate  * interrupt state machine is idled. If no handler claims the interrupt then
215*7c478bd9Sstevel@tonic-gate  * the counter is incremented by one and the state machine is idled.
216*7c478bd9Sstevel@tonic-gate  * If the count ever reaches the limit value set by pci_unclaimed_intr_max
217*7c478bd9Sstevel@tonic-gate  * then the interrupt state machine is not idled thus preventing any further
218*7c478bd9Sstevel@tonic-gate  * interrupts on that ino. The state machine will only be idled again if a
219*7c478bd9Sstevel@tonic-gate  * handler is subsequently added or removed.
220*7c478bd9Sstevel@tonic-gate  *
221*7c478bd9Sstevel@tonic-gate  * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt,
222*7c478bd9Sstevel@tonic-gate  * DDI_INTR_UNCLAIMED otherwise.
223*7c478bd9Sstevel@tonic-gate  */
224*7c478bd9Sstevel@tonic-gate uint_t
225*7c478bd9Sstevel@tonic-gate px_msiq_intr(caddr_t arg)
226*7c478bd9Sstevel@tonic-gate {
227*7c478bd9Sstevel@tonic-gate 	px_ib_ino_info_t	*ino_p = (px_ib_ino_info_t *)arg;
228*7c478bd9Sstevel@tonic-gate 	px_t		*px_p = ino_p->ino_ib_p->ib_px_p;
229*7c478bd9Sstevel@tonic-gate 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
230*7c478bd9Sstevel@tonic-gate 	px_msiq_t	*msiq_p = ino_p->ino_msiq_p;
231*7c478bd9Sstevel@tonic-gate 	dev_info_t	*dip = px_p->px_dip;
232*7c478bd9Sstevel@tonic-gate 	msiq_rec_t	msiq_rec, *msiq_rec_p = &msiq_rec;
233*7c478bd9Sstevel@tonic-gate 	msiqhead_t	curr_msiq_rec_cnt, new_msiq_rec_cnt;
234*7c478bd9Sstevel@tonic-gate 	msgcode_t	msg_code;
235*7c478bd9Sstevel@tonic-gate 	px_ih_t		*ih_p;
236*7c478bd9Sstevel@tonic-gate 	int		ret;
237*7c478bd9Sstevel@tonic-gate 
238*7c478bd9Sstevel@tonic-gate 	DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x "
239*7c478bd9Sstevel@tonic-gate 	    "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino,
240*7c478bd9Sstevel@tonic-gate 	    ino_p->ino_pil, ino_p->ino_ih_size, ino_p->ino_ih_head);
241*7c478bd9Sstevel@tonic-gate 
242*7c478bd9Sstevel@tonic-gate 	/* Read current MSIQ head index */
243*7c478bd9Sstevel@tonic-gate 	px_lib_msiq_gethead(dip, msiq_p->msiq_id, &curr_msiq_rec_cnt);
244*7c478bd9Sstevel@tonic-gate 	msiq_p->msiq_curr = (uint64_t)((caddr_t)msiq_p->msiq_base +
245*7c478bd9Sstevel@tonic-gate 	    curr_msiq_rec_cnt * sizeof (msiq_rec_t));
246*7c478bd9Sstevel@tonic-gate 	new_msiq_rec_cnt = curr_msiq_rec_cnt;
247*7c478bd9Sstevel@tonic-gate 
248*7c478bd9Sstevel@tonic-gate 	/* Read next MSIQ record */
249*7c478bd9Sstevel@tonic-gate 	px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p);
250*7c478bd9Sstevel@tonic-gate 
251*7c478bd9Sstevel@tonic-gate 	/*
252*7c478bd9Sstevel@tonic-gate 	 * Process current MSIQ record as long as request id
253*7c478bd9Sstevel@tonic-gate 	 * field is non-zero.
254*7c478bd9Sstevel@tonic-gate 	 */
255*7c478bd9Sstevel@tonic-gate 	while (msiq_rec_p->msiq_rec_rid) {
256*7c478bd9Sstevel@tonic-gate 		DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSIQ RECORD, "
257*7c478bd9Sstevel@tonic-gate 		    "msiq_rec_type 0x%llx msiq_rec_rid 0x%llx\n",
258*7c478bd9Sstevel@tonic-gate 		    msiq_rec_p->msiq_rec_type, msiq_rec_p->msiq_rec_rid);
259*7c478bd9Sstevel@tonic-gate 
260*7c478bd9Sstevel@tonic-gate 		/* Get the pointer next EQ record */
261*7c478bd9Sstevel@tonic-gate 		msiq_p->msiq_curr = (uint64_t)
262*7c478bd9Sstevel@tonic-gate 		    ((caddr_t)msiq_p->msiq_curr + sizeof (msiq_rec_t));
263*7c478bd9Sstevel@tonic-gate 
264*7c478bd9Sstevel@tonic-gate 		/* Check for overflow condition */
265*7c478bd9Sstevel@tonic-gate 		if (msiq_p->msiq_curr >= (uint64_t)((caddr_t)msiq_p->msiq_base +
266*7c478bd9Sstevel@tonic-gate 		    msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t)))
267*7c478bd9Sstevel@tonic-gate 			msiq_p->msiq_curr = msiq_p->msiq_base;
268*7c478bd9Sstevel@tonic-gate 
269*7c478bd9Sstevel@tonic-gate 		/* Check MSIQ record type */
270*7c478bd9Sstevel@tonic-gate 		switch (msiq_rec_p->msiq_rec_type) {
271*7c478bd9Sstevel@tonic-gate 		case MSG_REC:
272*7c478bd9Sstevel@tonic-gate 			msg_code = msiq_rec_p->msiq_rec_data.msg.msg_code;
273*7c478bd9Sstevel@tonic-gate 			DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: PCIE MSG "
274*7c478bd9Sstevel@tonic-gate 			    "record, msg type 0x%x\n", msg_code);
275*7c478bd9Sstevel@tonic-gate 			break;
276*7c478bd9Sstevel@tonic-gate 		case MSI32_REC:
277*7c478bd9Sstevel@tonic-gate 		case MSI64_REC:
278*7c478bd9Sstevel@tonic-gate 			msg_code = msiq_rec_p->msiq_rec_data.msi.msi_data;
279*7c478bd9Sstevel@tonic-gate 			DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSI record, "
280*7c478bd9Sstevel@tonic-gate 			    "msi 0x%x\n", msg_code);
281*7c478bd9Sstevel@tonic-gate 
282*7c478bd9Sstevel@tonic-gate 			/* Clear MSI state */
283*7c478bd9Sstevel@tonic-gate 			px_lib_msi_setstate(dip, (msinum_t)msg_code,
284*7c478bd9Sstevel@tonic-gate 			    PCI_MSI_STATE_IDLE);
285*7c478bd9Sstevel@tonic-gate 			break;
286*7c478bd9Sstevel@tonic-gate 		default:
287*7c478bd9Sstevel@tonic-gate 			msg_code = 0;
288*7c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, "%s%d: px_msiq_intr: 0x%x MSIQ "
289*7c478bd9Sstevel@tonic-gate 			    "record type is not supported",
290*7c478bd9Sstevel@tonic-gate 			    ddi_driver_name(dip), ddi_get_instance(dip),
291*7c478bd9Sstevel@tonic-gate 			    msiq_rec_p->msiq_rec_type);
292*7c478bd9Sstevel@tonic-gate 			goto next_rec;
293*7c478bd9Sstevel@tonic-gate 		}
294*7c478bd9Sstevel@tonic-gate 
295*7c478bd9Sstevel@tonic-gate 		ih_p = ino_p->ino_ih_start;
296*7c478bd9Sstevel@tonic-gate 
297*7c478bd9Sstevel@tonic-gate 		/*
298*7c478bd9Sstevel@tonic-gate 		 * Scan through px_ih_t linked list, searching for the
299*7c478bd9Sstevel@tonic-gate 		 * right px_ih_t, matching MSIQ record data.
300*7c478bd9Sstevel@tonic-gate 		 */
301*7c478bd9Sstevel@tonic-gate 		while ((ih_p) && (ih_p->ih_msg_code != msg_code) &&
302*7c478bd9Sstevel@tonic-gate 		    (ih_p->ih_rec_type != msiq_rec_p->msiq_rec_type))
303*7c478bd9Sstevel@tonic-gate 			ih_p = ih_p->ih_next;
304*7c478bd9Sstevel@tonic-gate 
305*7c478bd9Sstevel@tonic-gate 		if ((ih_p->ih_msg_code == msg_code) &&
306*7c478bd9Sstevel@tonic-gate 		    (ih_p->ih_rec_type == msiq_rec_p->msiq_rec_type)) {
307*7c478bd9Sstevel@tonic-gate 			dev_info_t *dip = ih_p->ih_dip;
308*7c478bd9Sstevel@tonic-gate 			uint_t (*handler)() = ih_p->ih_handler;
309*7c478bd9Sstevel@tonic-gate 			caddr_t arg1 = ih_p->ih_handler_arg1;
310*7c478bd9Sstevel@tonic-gate 			caddr_t arg2 = ih_p->ih_handler_arg2;
311*7c478bd9Sstevel@tonic-gate 
312*7c478bd9Sstevel@tonic-gate 			DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: ino=%x data=%x "
313*7c478bd9Sstevel@tonic-gate 			    "handler=%p arg1 =%p arg2=%p\n", ino_p->ino_ino,
314*7c478bd9Sstevel@tonic-gate 			    msg_code, handler, arg1, arg2);
315*7c478bd9Sstevel@tonic-gate 
316*7c478bd9Sstevel@tonic-gate 			DTRACE_PROBE4(interrupt__start, dev_info_t, dip,
317*7c478bd9Sstevel@tonic-gate 			    void *, handler, caddr_t, arg1, caddr_t, arg2);
318*7c478bd9Sstevel@tonic-gate 
319*7c478bd9Sstevel@tonic-gate 			if (msiq_rec_p->msiq_rec_type == MSG_REC)
320*7c478bd9Sstevel@tonic-gate 				px_p->px_pec_p->pec_msiq_rec_p = msiq_rec_p;
321*7c478bd9Sstevel@tonic-gate 
322*7c478bd9Sstevel@tonic-gate 			ret = (*handler)(arg1, arg2);
323*7c478bd9Sstevel@tonic-gate 
324*7c478bd9Sstevel@tonic-gate 			/*
325*7c478bd9Sstevel@tonic-gate 			 * Account for time used by this interrupt. Protect
326*7c478bd9Sstevel@tonic-gate 			 * against conflicting writes to ih_ticks from
327*7c478bd9Sstevel@tonic-gate 			 * ib_intr_dist_all() by using atomic ops.
328*7c478bd9Sstevel@tonic-gate 			 */
329*7c478bd9Sstevel@tonic-gate 
330*7c478bd9Sstevel@tonic-gate 			if (ino_p->ino_pil <= LOCK_LEVEL)
331*7c478bd9Sstevel@tonic-gate 				atomic_add_64(&ih_p->ih_ticks, intr_get_time());
332*7c478bd9Sstevel@tonic-gate 
333*7c478bd9Sstevel@tonic-gate 			DTRACE_PROBE4(interrupt__complete, dev_info_t, dip,
334*7c478bd9Sstevel@tonic-gate 			    void *, handler, caddr_t, arg1, int, ret);
335*7c478bd9Sstevel@tonic-gate 		} else {
336*7c478bd9Sstevel@tonic-gate 			DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr:"
337*7c478bd9Sstevel@tonic-gate 			    "Not found matching MSIQ record\n");
338*7c478bd9Sstevel@tonic-gate 
339*7c478bd9Sstevel@tonic-gate 			/* px_spurintr(ino_p); */
340*7c478bd9Sstevel@tonic-gate 			ino_p->ino_unclaimed++;
341*7c478bd9Sstevel@tonic-gate 		}
342*7c478bd9Sstevel@tonic-gate 
343*7c478bd9Sstevel@tonic-gate next_rec:
344*7c478bd9Sstevel@tonic-gate 		new_msiq_rec_cnt++;
345*7c478bd9Sstevel@tonic-gate 
346*7c478bd9Sstevel@tonic-gate 		/* Zero out msiq_rec_rid field */
347*7c478bd9Sstevel@tonic-gate 		msiq_rec_p->msiq_rec_rid = 0;
348*7c478bd9Sstevel@tonic-gate 
349*7c478bd9Sstevel@tonic-gate 		/* Read next MSIQ record */
350*7c478bd9Sstevel@tonic-gate 		px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p);
351*7c478bd9Sstevel@tonic-gate 	}
352*7c478bd9Sstevel@tonic-gate 
353*7c478bd9Sstevel@tonic-gate 	DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: No of MSIQ recs processed %x\n",
354*7c478bd9Sstevel@tonic-gate 	    (new_msiq_rec_cnt - curr_msiq_rec_cnt));
355*7c478bd9Sstevel@tonic-gate 
356*7c478bd9Sstevel@tonic-gate 	/*  Update MSIQ head index with no of MSIQ records processed */
357*7c478bd9Sstevel@tonic-gate 	if (new_msiq_rec_cnt > curr_msiq_rec_cnt)  {
358*7c478bd9Sstevel@tonic-gate 		if (new_msiq_rec_cnt >= msiq_state_p->msiq_rec_cnt)
359*7c478bd9Sstevel@tonic-gate 			new_msiq_rec_cnt -= msiq_state_p->msiq_rec_cnt;
360*7c478bd9Sstevel@tonic-gate 
361*7c478bd9Sstevel@tonic-gate 		px_lib_msiq_sethead(dip, msiq_p->msiq_id, new_msiq_rec_cnt);
362*7c478bd9Sstevel@tonic-gate 	}
363*7c478bd9Sstevel@tonic-gate 
364*7c478bd9Sstevel@tonic-gate 	/* Clear the pending state */
365*7c478bd9Sstevel@tonic-gate 	if (px_lib_intr_setstate(dip, ino_p->ino_sysino,
366*7c478bd9Sstevel@tonic-gate 	    INTR_IDLE_STATE) != DDI_SUCCESS)
367*7c478bd9Sstevel@tonic-gate 		return (DDI_INTR_UNCLAIMED);
368*7c478bd9Sstevel@tonic-gate 
369*7c478bd9Sstevel@tonic-gate 	return (DDI_INTR_CLAIMED);
370*7c478bd9Sstevel@tonic-gate }
371*7c478bd9Sstevel@tonic-gate 
372*7c478bd9Sstevel@tonic-gate dev_info_t *
373*7c478bd9Sstevel@tonic-gate px_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip)
374*7c478bd9Sstevel@tonic-gate {
375*7c478bd9Sstevel@tonic-gate 	dev_info_t	*cdip = rdip;
376*7c478bd9Sstevel@tonic-gate 
377*7c478bd9Sstevel@tonic-gate 	for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip))
378*7c478bd9Sstevel@tonic-gate 		;
379*7c478bd9Sstevel@tonic-gate 
380*7c478bd9Sstevel@tonic-gate 	return (cdip);
381*7c478bd9Sstevel@tonic-gate }
382*7c478bd9Sstevel@tonic-gate 
383*7c478bd9Sstevel@tonic-gate /* Default class to pil value mapping */
384*7c478bd9Sstevel@tonic-gate px_class_val_t px_default_pil [] = {
385*7c478bd9Sstevel@tonic-gate 	{0x000000, 0xff0000, 0x1},	/* Class code for pre-2.0 devices */
386*7c478bd9Sstevel@tonic-gate 	{0x010000, 0xff0000, 0x4},	/* Mass Storage Controller */
387*7c478bd9Sstevel@tonic-gate 	{0x020000, 0xff0000, 0x6},	/* Network Controller */
388*7c478bd9Sstevel@tonic-gate 	{0x030000, 0xff0000, 0x9},	/* Display Controller */
389*7c478bd9Sstevel@tonic-gate 	{0x040000, 0xff0000, 0x9},	/* Multimedia Controller */
390*7c478bd9Sstevel@tonic-gate 	{0x050000, 0xff0000, 0xb},	/* Memory Controller */
391*7c478bd9Sstevel@tonic-gate 	{0x060000, 0xff0000, 0xb},	/* Bridge Controller */
392*7c478bd9Sstevel@tonic-gate 	{0x0c0000, 0xffff00, 0x9},	/* Serial Bus, FireWire (IEEE 1394) */
393*7c478bd9Sstevel@tonic-gate 	{0x0c0100, 0xffff00, 0x4},	/* Serial Bus, ACCESS.bus */
394*7c478bd9Sstevel@tonic-gate 	{0x0c0200, 0xffff00, 0x4},	/* Serial Bus, SSA */
395*7c478bd9Sstevel@tonic-gate 	{0x0c0300, 0xffff00, 0x9},	/* Serial Bus Universal Serial Bus */
396*7c478bd9Sstevel@tonic-gate 	{0x0c0400, 0xffff00, 0x6},	/* Serial Bus, Fibre Channel */
397*7c478bd9Sstevel@tonic-gate 	{0x0c0600, 0xffff00, 0x6}	/* Serial Bus, Infiniband */
398*7c478bd9Sstevel@tonic-gate };
399*7c478bd9Sstevel@tonic-gate 
400*7c478bd9Sstevel@tonic-gate /*
401*7c478bd9Sstevel@tonic-gate  * Default class to intr_weight value mapping (% of CPU).  A driver.conf
402*7c478bd9Sstevel@tonic-gate  * entry on or above the pci node like
403*7c478bd9Sstevel@tonic-gate  *
404*7c478bd9Sstevel@tonic-gate  *	pci-class-intr-weights= 0x020000, 0xff0000, 30;
405*7c478bd9Sstevel@tonic-gate  *
406*7c478bd9Sstevel@tonic-gate  * can be used to augment or override entries in the default table below.
407*7c478bd9Sstevel@tonic-gate  *
408*7c478bd9Sstevel@tonic-gate  * NB: The values below give NICs preference on redistribution, and provide
409*7c478bd9Sstevel@tonic-gate  * NICs some isolation from other interrupt sources. We need better interfaces
410*7c478bd9Sstevel@tonic-gate  * that allow the NIC driver to identify a specific NIC instance as high
411*7c478bd9Sstevel@tonic-gate  * bandwidth, and thus deserving of separation from other low bandwidth
412*7c478bd9Sstevel@tonic-gate  * NICs additional isolation from other interrupt sources.
413*7c478bd9Sstevel@tonic-gate  *
414*7c478bd9Sstevel@tonic-gate  * NB: We treat Infiniband like a NIC.
415*7c478bd9Sstevel@tonic-gate  */
416*7c478bd9Sstevel@tonic-gate px_class_val_t px_default_intr_weight [] = {
417*7c478bd9Sstevel@tonic-gate 	{0x020000, 0xff0000, 35},	/* Network Controller */
418*7c478bd9Sstevel@tonic-gate 	{0x010000, 0xff0000, 10},	/* Mass Storage Controller */
419*7c478bd9Sstevel@tonic-gate 	{0x0c0400, 0xffff00, 10},	/* Serial Bus, Fibre Channel */
420*7c478bd9Sstevel@tonic-gate 	{0x0c0600, 0xffff00, 50}	/* Serial Bus, Infiniband */
421*7c478bd9Sstevel@tonic-gate };
422*7c478bd9Sstevel@tonic-gate 
423*7c478bd9Sstevel@tonic-gate static uint32_t
424*7c478bd9Sstevel@tonic-gate px_match_class_val(uint32_t key, px_class_val_t *rec_p, int nrec,
425*7c478bd9Sstevel@tonic-gate     uint32_t default_val)
426*7c478bd9Sstevel@tonic-gate {
427*7c478bd9Sstevel@tonic-gate 	int	i;
428*7c478bd9Sstevel@tonic-gate 
429*7c478bd9Sstevel@tonic-gate 	for (i = 0; i < nrec; rec_p++, i++) {
430*7c478bd9Sstevel@tonic-gate 		if ((rec_p->class_code & rec_p->class_mask) ==
431*7c478bd9Sstevel@tonic-gate 		    (key & rec_p->class_mask))
432*7c478bd9Sstevel@tonic-gate 			return (rec_p->class_val);
433*7c478bd9Sstevel@tonic-gate 	}
434*7c478bd9Sstevel@tonic-gate 
435*7c478bd9Sstevel@tonic-gate 	return (default_val);
436*7c478bd9Sstevel@tonic-gate }
437*7c478bd9Sstevel@tonic-gate 
438*7c478bd9Sstevel@tonic-gate /*
439*7c478bd9Sstevel@tonic-gate  * px_class_to_val
440*7c478bd9Sstevel@tonic-gate  *
441*7c478bd9Sstevel@tonic-gate  * Return the configuration value, based on class code and sub class code,
442*7c478bd9Sstevel@tonic-gate  * from the specified property based or default px_class_val_t table.
443*7c478bd9Sstevel@tonic-gate  */
444*7c478bd9Sstevel@tonic-gate uint32_t
445*7c478bd9Sstevel@tonic-gate px_class_to_val(dev_info_t *rdip, char *property_name, px_class_val_t *rec_p,
446*7c478bd9Sstevel@tonic-gate     int nrec, uint32_t default_val)
447*7c478bd9Sstevel@tonic-gate {
448*7c478bd9Sstevel@tonic-gate 	int property_len;
449*7c478bd9Sstevel@tonic-gate 	uint32_t class_code;
450*7c478bd9Sstevel@tonic-gate 	px_class_val_t *conf;
451*7c478bd9Sstevel@tonic-gate 	uint32_t val = default_val;
452*7c478bd9Sstevel@tonic-gate 
453*7c478bd9Sstevel@tonic-gate 	/*
454*7c478bd9Sstevel@tonic-gate 	 * Use the "class-code" property to get the base and sub class
455*7c478bd9Sstevel@tonic-gate 	 * codes for the requesting device.
456*7c478bd9Sstevel@tonic-gate 	 */
457*7c478bd9Sstevel@tonic-gate 	class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip,
458*7c478bd9Sstevel@tonic-gate 	    DDI_PROP_DONTPASS, "class-code", -1);
459*7c478bd9Sstevel@tonic-gate 
460*7c478bd9Sstevel@tonic-gate 	if (class_code == -1)
461*7c478bd9Sstevel@tonic-gate 		return (val);
462*7c478bd9Sstevel@tonic-gate 
463*7c478bd9Sstevel@tonic-gate 	/* look up the val from the default table */
464*7c478bd9Sstevel@tonic-gate 	val = px_match_class_val(class_code, rec_p, nrec, val);
465*7c478bd9Sstevel@tonic-gate 
466*7c478bd9Sstevel@tonic-gate 	/* see if there is a more specific property specified value */
467*7c478bd9Sstevel@tonic-gate 	if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM,
468*7c478bd9Sstevel@tonic-gate 	    property_name, (caddr_t)&conf, &property_len))
469*7c478bd9Sstevel@tonic-gate 		return (val);
470*7c478bd9Sstevel@tonic-gate 
471*7c478bd9Sstevel@tonic-gate 	if ((property_len % sizeof (px_class_val_t)) == 0)
472*7c478bd9Sstevel@tonic-gate 		val = px_match_class_val(class_code, conf,
473*7c478bd9Sstevel@tonic-gate 		    property_len / sizeof (px_class_val_t), val);
474*7c478bd9Sstevel@tonic-gate 	kmem_free(conf, property_len);
475*7c478bd9Sstevel@tonic-gate 	return (val);
476*7c478bd9Sstevel@tonic-gate }
477*7c478bd9Sstevel@tonic-gate 
478*7c478bd9Sstevel@tonic-gate 
479*7c478bd9Sstevel@tonic-gate /* px_class_to_pil: return the pil for a given device. */
480*7c478bd9Sstevel@tonic-gate uint32_t
481*7c478bd9Sstevel@tonic-gate px_class_to_pil(dev_info_t *rdip)
482*7c478bd9Sstevel@tonic-gate {
483*7c478bd9Sstevel@tonic-gate 	uint32_t pil;
484*7c478bd9Sstevel@tonic-gate 
485*7c478bd9Sstevel@tonic-gate 	/* default pil is 0 (uninitialized) */
486*7c478bd9Sstevel@tonic-gate 	pil = px_class_to_val(rdip,
487*7c478bd9Sstevel@tonic-gate 	    "pci-class-priorities", px_default_pil,
488*7c478bd9Sstevel@tonic-gate 	    sizeof (px_default_pil) / sizeof (px_class_val_t), 0);
489*7c478bd9Sstevel@tonic-gate 
490*7c478bd9Sstevel@tonic-gate 	/* range check the result */
491*7c478bd9Sstevel@tonic-gate 	if (pil >= 0xf)
492*7c478bd9Sstevel@tonic-gate 		pil = 0;
493*7c478bd9Sstevel@tonic-gate 
494*7c478bd9Sstevel@tonic-gate 	return (pil);
495*7c478bd9Sstevel@tonic-gate }
496*7c478bd9Sstevel@tonic-gate 
497*7c478bd9Sstevel@tonic-gate 
498*7c478bd9Sstevel@tonic-gate /* px_class_to_intr_weight: return the intr_weight for a given device. */
499*7c478bd9Sstevel@tonic-gate static int32_t
500*7c478bd9Sstevel@tonic-gate px_class_to_intr_weight(dev_info_t *rdip)
501*7c478bd9Sstevel@tonic-gate {
502*7c478bd9Sstevel@tonic-gate 	int32_t intr_weight;
503*7c478bd9Sstevel@tonic-gate 
504*7c478bd9Sstevel@tonic-gate 	/* default weight is 0% */
505*7c478bd9Sstevel@tonic-gate 	intr_weight = px_class_to_val(rdip,
506*7c478bd9Sstevel@tonic-gate 	    "pci-class-intr-weights", px_default_intr_weight,
507*7c478bd9Sstevel@tonic-gate 	    sizeof (px_default_intr_weight) / sizeof (px_class_val_t), 0);
508*7c478bd9Sstevel@tonic-gate 
509*7c478bd9Sstevel@tonic-gate 	/* range check the result */
510*7c478bd9Sstevel@tonic-gate 	if (intr_weight < 0)
511*7c478bd9Sstevel@tonic-gate 		intr_weight = 0;
512*7c478bd9Sstevel@tonic-gate 	if (intr_weight > 1000)
513*7c478bd9Sstevel@tonic-gate 		intr_weight = 1000;
514*7c478bd9Sstevel@tonic-gate 
515*7c478bd9Sstevel@tonic-gate 	return (intr_weight);
516*7c478bd9Sstevel@tonic-gate }
517*7c478bd9Sstevel@tonic-gate 
518*7c478bd9Sstevel@tonic-gate 
519*7c478bd9Sstevel@tonic-gate /* ARGSUSED */
520*7c478bd9Sstevel@tonic-gate int
521*7c478bd9Sstevel@tonic-gate px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
522*7c478bd9Sstevel@tonic-gate     ddi_intr_handle_impl_t *hdlp, void *result)
523*7c478bd9Sstevel@tonic-gate {
524*7c478bd9Sstevel@tonic-gate 	px_t		*px_p = DIP_TO_STATE(dip);
525*7c478bd9Sstevel@tonic-gate 	ddi_ispec_t	*ip = (ddi_ispec_t *)hdlp->ih_private;
526*7c478bd9Sstevel@tonic-gate 	int		ret = DDI_SUCCESS;
527*7c478bd9Sstevel@tonic-gate 
528*7c478bd9Sstevel@tonic-gate 	DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x "
529*7c478bd9Sstevel@tonic-gate 	    "handle=%p\n", dip, rdip, intr_op, hdlp);
530*7c478bd9Sstevel@tonic-gate 
531*7c478bd9Sstevel@tonic-gate 	switch (intr_op) {
532*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETCAP:
533*7c478bd9Sstevel@tonic-gate 		ret = pci_intx_get_cap(rdip, (int *)result);
534*7c478bd9Sstevel@tonic-gate 		break;
535*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETCAP:
536*7c478bd9Sstevel@tonic-gate 		DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n");
537*7c478bd9Sstevel@tonic-gate 		ret = DDI_ENOTSUP;
538*7c478bd9Sstevel@tonic-gate 		break;
539*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ALLOC:
540*7c478bd9Sstevel@tonic-gate 		*(int *)result = hdlp->ih_scratch1;
541*7c478bd9Sstevel@tonic-gate 		break;
542*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_FREE:
543*7c478bd9Sstevel@tonic-gate 		break;
544*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETPRI:
545*7c478bd9Sstevel@tonic-gate 		*(int *)result = ip->is_pil ?
546*7c478bd9Sstevel@tonic-gate 		    ip->is_pil : px_class_to_pil(rdip);
547*7c478bd9Sstevel@tonic-gate 		break;
548*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETPRI:
549*7c478bd9Sstevel@tonic-gate 		ip->is_pil = (*(int *)result);
550*7c478bd9Sstevel@tonic-gate 		break;
551*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ADDISR:
552*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = *ip->is_intr;
553*7c478bd9Sstevel@tonic-gate 
554*7c478bd9Sstevel@tonic-gate 		ret = px_add_intx_intr(dip, rdip, hdlp);
555*7c478bd9Sstevel@tonic-gate 		break;
556*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_REMISR:
557*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = *ip->is_intr;
558*7c478bd9Sstevel@tonic-gate 
559*7c478bd9Sstevel@tonic-gate 		ret = px_rem_intx_intr(dip, rdip, hdlp);
560*7c478bd9Sstevel@tonic-gate 		break;
561*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ENABLE:
562*7c478bd9Sstevel@tonic-gate 		ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,
563*7c478bd9Sstevel@tonic-gate 		    *ip->is_intr, PX_INTR_STATE_ENABLE);
564*7c478bd9Sstevel@tonic-gate 		break;
565*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_DISABLE:
566*7c478bd9Sstevel@tonic-gate 		ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,
567*7c478bd9Sstevel@tonic-gate 		    *ip->is_intr, PX_INTR_STATE_DISABLE);
568*7c478bd9Sstevel@tonic-gate 		break;
569*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETMASK:
570*7c478bd9Sstevel@tonic-gate 		ret = pci_intx_set_mask(rdip);
571*7c478bd9Sstevel@tonic-gate 		break;
572*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_CLRMASK:
573*7c478bd9Sstevel@tonic-gate 		ret = pci_intx_clr_mask(rdip);
574*7c478bd9Sstevel@tonic-gate 		break;
575*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETPENDING:
576*7c478bd9Sstevel@tonic-gate 		ret = pci_intx_get_pending(rdip, (int *)result);
577*7c478bd9Sstevel@tonic-gate 		break;
578*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_NINTRS:
579*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_NAVAIL:
580*7c478bd9Sstevel@tonic-gate 		*(int *)result = i_ddi_get_nintrs(rdip);
581*7c478bd9Sstevel@tonic-gate 		break;
582*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SUPPORTED_TYPES:
583*7c478bd9Sstevel@tonic-gate 		*(int *)result = DDI_INTR_TYPE_FIXED;
584*7c478bd9Sstevel@tonic-gate 		break;
585*7c478bd9Sstevel@tonic-gate 	default:
586*7c478bd9Sstevel@tonic-gate 		ret = DDI_ENOTSUP;
587*7c478bd9Sstevel@tonic-gate 		break;
588*7c478bd9Sstevel@tonic-gate 	}
589*7c478bd9Sstevel@tonic-gate 
590*7c478bd9Sstevel@tonic-gate 	return (ret);
591*7c478bd9Sstevel@tonic-gate }
592*7c478bd9Sstevel@tonic-gate 
593*7c478bd9Sstevel@tonic-gate /* ARGSUSED */
594*7c478bd9Sstevel@tonic-gate int
595*7c478bd9Sstevel@tonic-gate px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
596*7c478bd9Sstevel@tonic-gate     ddi_intr_handle_impl_t *hdlp, void *result)
597*7c478bd9Sstevel@tonic-gate {
598*7c478bd9Sstevel@tonic-gate 	px_t			*px_p = DIP_TO_STATE(dip);
599*7c478bd9Sstevel@tonic-gate 	px_msi_state_t		*msi_state_p = &px_p->px_ib_p->ib_msi_state;
600*7c478bd9Sstevel@tonic-gate 	msinum_t		msi_num;
601*7c478bd9Sstevel@tonic-gate 	msiqid_t		msiq_id;
602*7c478bd9Sstevel@tonic-gate 	uint_t			nintrs;
603*7c478bd9Sstevel@tonic-gate 	int			i, ret = DDI_SUCCESS;
604*7c478bd9Sstevel@tonic-gate 
605*7c478bd9Sstevel@tonic-gate 	DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x "
606*7c478bd9Sstevel@tonic-gate 	    "handle=%p\n", dip, rdip, intr_op, hdlp);
607*7c478bd9Sstevel@tonic-gate 
608*7c478bd9Sstevel@tonic-gate 	switch (intr_op) {
609*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETCAP:
610*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result);
611*7c478bd9Sstevel@tonic-gate 		break;
612*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETCAP:
613*7c478bd9Sstevel@tonic-gate 		DBG(DBG_INTROPS, dip, "px_msix_ops: SetCap is not supported\n");
614*7c478bd9Sstevel@tonic-gate 		ret = DDI_ENOTSUP;
615*7c478bd9Sstevel@tonic-gate 		break;
616*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ALLOC:
617*7c478bd9Sstevel@tonic-gate 		/*
618*7c478bd9Sstevel@tonic-gate 		 * We need to restrict this allocation in future
619*7c478bd9Sstevel@tonic-gate 		 * based on Resource Management policies.
620*7c478bd9Sstevel@tonic-gate 		 */
621*7c478bd9Sstevel@tonic-gate 		if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_inum,
622*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_scratch1, hdlp->ih_scratch2, &msi_num,
623*7c478bd9Sstevel@tonic-gate 		    (int *)result)) != DDI_SUCCESS) {
624*7c478bd9Sstevel@tonic-gate 			DBG(DBG_INTROPS, dip, "px_msix_ops: MSI allocation "
625*7c478bd9Sstevel@tonic-gate 			    "failed, rdip 0x%p inum 0x%x count 0x%x\n",
626*7c478bd9Sstevel@tonic-gate 			    rdip, hdlp->ih_inum, hdlp->ih_scratch1);
627*7c478bd9Sstevel@tonic-gate 
628*7c478bd9Sstevel@tonic-gate 			return (ret);
629*7c478bd9Sstevel@tonic-gate 		}
630*7c478bd9Sstevel@tonic-gate 
631*7c478bd9Sstevel@tonic-gate 		break;
632*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_FREE:
633*7c478bd9Sstevel@tonic-gate 		(void) pci_msi_disable_mode(rdip, hdlp->ih_type, hdlp->ih_inum);
634*7c478bd9Sstevel@tonic-gate 		(void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum);
635*7c478bd9Sstevel@tonic-gate 		(void) px_msi_free(px_p, rdip, hdlp->ih_inum,
636*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_scratch1);
637*7c478bd9Sstevel@tonic-gate 		break;
638*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETPRI:
639*7c478bd9Sstevel@tonic-gate 		*(int *)result = hdlp->ih_pri ?
640*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_pri : px_class_to_pil(rdip);
641*7c478bd9Sstevel@tonic-gate 		break;
642*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETPRI:
643*7c478bd9Sstevel@tonic-gate 		break;
644*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ADDISR:
645*7c478bd9Sstevel@tonic-gate 		if ((ret = px_msi_get_msinum(px_p, hdlp->ih_dip,
646*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_inum, &msi_num)) != DDI_SUCCESS)
647*7c478bd9Sstevel@tonic-gate 			return (ret);
648*7c478bd9Sstevel@tonic-gate 
649*7c478bd9Sstevel@tonic-gate 		if ((ret = px_add_msiq_intr(dip, rdip, hdlp,
650*7c478bd9Sstevel@tonic-gate 		    MSI32_REC, msi_num, &msiq_id)) != DDI_SUCCESS) {
651*7c478bd9Sstevel@tonic-gate 			DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler "
652*7c478bd9Sstevel@tonic-gate 			    "failed, rdip 0x%p msi 0x%x\n", rdip, msi_num);
653*7c478bd9Sstevel@tonic-gate 			return (ret);
654*7c478bd9Sstevel@tonic-gate 		}
655*7c478bd9Sstevel@tonic-gate 
656*7c478bd9Sstevel@tonic-gate 		DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id);
657*7c478bd9Sstevel@tonic-gate 
658*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_msi_setmsiq(dip, msi_num,
659*7c478bd9Sstevel@tonic-gate 		    msiq_id, MSI32_TYPE)) != DDI_SUCCESS) {
660*7c478bd9Sstevel@tonic-gate 			(void) px_rem_msiq_intr(dip, rdip,
661*7c478bd9Sstevel@tonic-gate 			    hdlp, MSI32_REC, msi_num, msiq_id);
662*7c478bd9Sstevel@tonic-gate 			return (ret);
663*7c478bd9Sstevel@tonic-gate 		}
664*7c478bd9Sstevel@tonic-gate 
665*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_msi_setstate(dip, msi_num,
666*7c478bd9Sstevel@tonic-gate 		    PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) {
667*7c478bd9Sstevel@tonic-gate 			(void) px_rem_msiq_intr(dip, rdip,
668*7c478bd9Sstevel@tonic-gate 			    hdlp, MSI32_REC, msi_num, msiq_id);
669*7c478bd9Sstevel@tonic-gate 			return (ret);
670*7c478bd9Sstevel@tonic-gate 		}
671*7c478bd9Sstevel@tonic-gate 
672*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = msi_num;
673*7c478bd9Sstevel@tonic-gate 		break;
674*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_DUPVEC:
675*7c478bd9Sstevel@tonic-gate 		DBG(DBG_INTROPS, dip, "px_msix_ops: DupIsr is not supported\n");
676*7c478bd9Sstevel@tonic-gate 		ret = DDI_ENOTSUP;
677*7c478bd9Sstevel@tonic-gate 		break;
678*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_REMISR:
679*7c478bd9Sstevel@tonic-gate 		msi_num = hdlp->ih_vector;
680*7c478bd9Sstevel@tonic-gate 
681*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_msi_getmsiq(dip, msi_num,
682*7c478bd9Sstevel@tonic-gate 		    &msiq_id)) != DDI_SUCCESS)
683*7c478bd9Sstevel@tonic-gate 			return (ret);
684*7c478bd9Sstevel@tonic-gate 
685*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_msi_setstate(dip, msi_num,
686*7c478bd9Sstevel@tonic-gate 		    PCI_MSI_STATE_DELIVERED)) != DDI_SUCCESS)
687*7c478bd9Sstevel@tonic-gate 			return (ret);
688*7c478bd9Sstevel@tonic-gate 
689*7c478bd9Sstevel@tonic-gate 		ret = px_rem_msiq_intr(dip, rdip,
690*7c478bd9Sstevel@tonic-gate 		    hdlp, MSI32_REC, msi_num, msiq_id);
691*7c478bd9Sstevel@tonic-gate 
692*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = 0;
693*7c478bd9Sstevel@tonic-gate 		break;
694*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ENABLE:
695*7c478bd9Sstevel@tonic-gate 		msi_num = hdlp->ih_vector;
696*7c478bd9Sstevel@tonic-gate 
697*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_msi_setvalid(dip, msi_num,
698*7c478bd9Sstevel@tonic-gate 		    PCI_MSI_VALID)) != DDI_SUCCESS)
699*7c478bd9Sstevel@tonic-gate 			return (ret);
700*7c478bd9Sstevel@tonic-gate 
701*7c478bd9Sstevel@tonic-gate 		if (pci_is_msi_enabled(rdip, hdlp->ih_type) != DDI_SUCCESS) {
702*7c478bd9Sstevel@tonic-gate 			nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip);
703*7c478bd9Sstevel@tonic-gate 
704*7c478bd9Sstevel@tonic-gate 			if ((ret = pci_msi_configure(rdip, hdlp->ih_type,
705*7c478bd9Sstevel@tonic-gate 			    nintrs, hdlp->ih_inum, msi_state_p->msi_addr32,
706*7c478bd9Sstevel@tonic-gate 			    msi_num & ~(nintrs - 1))) != DDI_SUCCESS)
707*7c478bd9Sstevel@tonic-gate 				return (ret);
708*7c478bd9Sstevel@tonic-gate 
709*7c478bd9Sstevel@tonic-gate 			if ((ret = pci_msi_enable_mode(rdip, hdlp->ih_type,
710*7c478bd9Sstevel@tonic-gate 			    hdlp->ih_inum)) != DDI_SUCCESS)
711*7c478bd9Sstevel@tonic-gate 				return (ret);
712*7c478bd9Sstevel@tonic-gate 		}
713*7c478bd9Sstevel@tonic-gate 
714*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum);
715*7c478bd9Sstevel@tonic-gate 
716*7c478bd9Sstevel@tonic-gate 		break;
717*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_DISABLE:
718*7c478bd9Sstevel@tonic-gate 		msi_num = hdlp->ih_vector;
719*7c478bd9Sstevel@tonic-gate 
720*7c478bd9Sstevel@tonic-gate 		if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type,
721*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_inum)) != DDI_SUCCESS)
722*7c478bd9Sstevel@tonic-gate 			return (ret);
723*7c478bd9Sstevel@tonic-gate 
724*7c478bd9Sstevel@tonic-gate 		ret = px_lib_msi_setvalid(dip, msi_num, PCI_MSI_INVALID);
725*7c478bd9Sstevel@tonic-gate 		break;
726*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_BLOCKENABLE:
727*7c478bd9Sstevel@tonic-gate 		nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip);
728*7c478bd9Sstevel@tonic-gate 		msi_num = hdlp->ih_vector;
729*7c478bd9Sstevel@tonic-gate 
730*7c478bd9Sstevel@tonic-gate 		if ((ret = pci_msi_configure(rdip, hdlp->ih_type,
731*7c478bd9Sstevel@tonic-gate 		    nintrs, hdlp->ih_inum, msi_state_p->msi_addr32,
732*7c478bd9Sstevel@tonic-gate 		    msi_num & ~(nintrs - 1))) != DDI_SUCCESS)
733*7c478bd9Sstevel@tonic-gate 			return (ret);
734*7c478bd9Sstevel@tonic-gate 
735*7c478bd9Sstevel@tonic-gate 		for (i = 0; i < nintrs; i++, msi_num++) {
736*7c478bd9Sstevel@tonic-gate 			if ((ret = px_lib_msi_setvalid(dip, msi_num,
737*7c478bd9Sstevel@tonic-gate 			    PCI_MSI_VALID)) != DDI_SUCCESS)
738*7c478bd9Sstevel@tonic-gate 				return (ret);
739*7c478bd9Sstevel@tonic-gate 		}
740*7c478bd9Sstevel@tonic-gate 
741*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_enable_mode(rdip, hdlp->ih_type, hdlp->ih_inum);
742*7c478bd9Sstevel@tonic-gate 		break;
743*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_BLOCKDISABLE:
744*7c478bd9Sstevel@tonic-gate 		nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip);
745*7c478bd9Sstevel@tonic-gate 		msi_num = hdlp->ih_vector;
746*7c478bd9Sstevel@tonic-gate 
747*7c478bd9Sstevel@tonic-gate 		if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type,
748*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_inum)) != DDI_SUCCESS)
749*7c478bd9Sstevel@tonic-gate 			return (ret);
750*7c478bd9Sstevel@tonic-gate 
751*7c478bd9Sstevel@tonic-gate 		for (i = 0; i < nintrs; i++, msi_num++) {
752*7c478bd9Sstevel@tonic-gate 			if ((ret = px_lib_msi_setvalid(dip, msi_num,
753*7c478bd9Sstevel@tonic-gate 			    PCI_MSI_INVALID)) != DDI_SUCCESS)
754*7c478bd9Sstevel@tonic-gate 				return (ret);
755*7c478bd9Sstevel@tonic-gate 		}
756*7c478bd9Sstevel@tonic-gate 
757*7c478bd9Sstevel@tonic-gate 		break;
758*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETMASK:
759*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum);
760*7c478bd9Sstevel@tonic-gate 		break;
761*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_CLRMASK:
762*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum);
763*7c478bd9Sstevel@tonic-gate 		break;
764*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETPENDING:
765*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_get_pending(rdip, hdlp->ih_type,
766*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_inum, (int *)result);
767*7c478bd9Sstevel@tonic-gate 		break;
768*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_NINTRS:
769*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result);
770*7c478bd9Sstevel@tonic-gate 		break;
771*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_NAVAIL:
772*7c478bd9Sstevel@tonic-gate 		/* XXX - a new interface may be needed */
773*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result);
774*7c478bd9Sstevel@tonic-gate 		break;
775*7c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SUPPORTED_TYPES:
776*7c478bd9Sstevel@tonic-gate 		ret = pci_msi_get_supported_type(rdip, (int *)result);
777*7c478bd9Sstevel@tonic-gate 		break;
778*7c478bd9Sstevel@tonic-gate 	default:
779*7c478bd9Sstevel@tonic-gate 		ret = DDI_ENOTSUP;
780*7c478bd9Sstevel@tonic-gate 		break;
781*7c478bd9Sstevel@tonic-gate 	}
782*7c478bd9Sstevel@tonic-gate 
783*7c478bd9Sstevel@tonic-gate 	return (ret);
784*7c478bd9Sstevel@tonic-gate }
785*7c478bd9Sstevel@tonic-gate 
786*7c478bd9Sstevel@tonic-gate int
787*7c478bd9Sstevel@tonic-gate px_add_intx_intr(dev_info_t *dip, dev_info_t *rdip,
788*7c478bd9Sstevel@tonic-gate     ddi_intr_handle_impl_t *hdlp)
789*7c478bd9Sstevel@tonic-gate {
790*7c478bd9Sstevel@tonic-gate 	px_t		*px_p = INST_TO_STATE(ddi_get_instance(dip));
791*7c478bd9Sstevel@tonic-gate 	px_ib_t		*ib_p = px_p->px_ib_p;
792*7c478bd9Sstevel@tonic-gate 	devino_t	ino;
793*7c478bd9Sstevel@tonic-gate 	px_ih_t		*ih_p;
794*7c478bd9Sstevel@tonic-gate 	px_ib_ino_info_t *ino_p;
795*7c478bd9Sstevel@tonic-gate 	int32_t		weight;
796*7c478bd9Sstevel@tonic-gate 	int		ret = DDI_SUCCESS;
797*7c478bd9Sstevel@tonic-gate 
798*7c478bd9Sstevel@tonic-gate 	ino = hdlp->ih_vector;
799*7c478bd9Sstevel@tonic-gate 
800*7c478bd9Sstevel@tonic-gate 	DBG(DBG_A_INTX, dip, "px_add_intx_intr: rdip=%s%d ino=%x "
801*7c478bd9Sstevel@tonic-gate 	    "handler=%x arg1=%x arg2=%x\n", ddi_driver_name(rdip),
802*7c478bd9Sstevel@tonic-gate 	    ddi_get_instance(rdip), ino, hdlp->ih_cb_func,
803*7c478bd9Sstevel@tonic-gate 	    hdlp->ih_cb_arg1, hdlp->ih_cb_arg2);
804*7c478bd9Sstevel@tonic-gate 
805*7c478bd9Sstevel@tonic-gate 	ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum,
806*7c478bd9Sstevel@tonic-gate 	    hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0);
807*7c478bd9Sstevel@tonic-gate 
808*7c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
809*7c478bd9Sstevel@tonic-gate 
810*7c478bd9Sstevel@tonic-gate 	if (ino_p = px_ib_locate_ino(ib_p, ino)) {	/* sharing ino */
811*7c478bd9Sstevel@tonic-gate 		uint32_t intr_index = hdlp->ih_inum;
812*7c478bd9Sstevel@tonic-gate 		if (px_ib_ino_locate_intr(ino_p, rdip, intr_index, 0, 0)) {
813*7c478bd9Sstevel@tonic-gate 			DBG(DBG_A_INTX, dip, "px_add_intx_intr: "
814*7c478bd9Sstevel@tonic-gate 			    "dup intr #%d\n", intr_index);
815*7c478bd9Sstevel@tonic-gate 
816*7c478bd9Sstevel@tonic-gate 			ret = DDI_FAILURE;
817*7c478bd9Sstevel@tonic-gate 			goto fail1;
818*7c478bd9Sstevel@tonic-gate 		}
819*7c478bd9Sstevel@tonic-gate 
820*7c478bd9Sstevel@tonic-gate 		/* Save mondo value in hdlp */
821*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = ino_p->ino_sysino;
822*7c478bd9Sstevel@tonic-gate 
823*7c478bd9Sstevel@tonic-gate 		if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p))
824*7c478bd9Sstevel@tonic-gate 		    != DDI_SUCCESS)
825*7c478bd9Sstevel@tonic-gate 			goto fail1;
826*7c478bd9Sstevel@tonic-gate 	} else {
827*7c478bd9Sstevel@tonic-gate 		ino_p = px_ib_new_ino(ib_p, ino, ih_p);
828*7c478bd9Sstevel@tonic-gate 
829*7c478bd9Sstevel@tonic-gate 		if (hdlp->ih_pri == 0)
830*7c478bd9Sstevel@tonic-gate 			hdlp->ih_pri = px_class_to_pil(rdip);
831*7c478bd9Sstevel@tonic-gate 
832*7c478bd9Sstevel@tonic-gate 		/* Save mondo value in hdlp */
833*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = ino_p->ino_sysino;
834*7c478bd9Sstevel@tonic-gate 
835*7c478bd9Sstevel@tonic-gate 		DBG(DBG_A_INTX, dip, "px_add_intx_intr: pil=0x%x mondo=0x%x\n",
836*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_pri, hdlp->ih_vector);
837*7c478bd9Sstevel@tonic-gate 
838*7c478bd9Sstevel@tonic-gate 		DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp,
839*7c478bd9Sstevel@tonic-gate 		    (ddi_intr_handler_t *)px_intx_intr, (caddr_t)ino_p, NULL);
840*7c478bd9Sstevel@tonic-gate 
841*7c478bd9Sstevel@tonic-gate 		ret = i_ddi_add_ivintr(hdlp);
842*7c478bd9Sstevel@tonic-gate 
843*7c478bd9Sstevel@tonic-gate 		/*
844*7c478bd9Sstevel@tonic-gate 		 * Restore original interrupt handler
845*7c478bd9Sstevel@tonic-gate 		 * and arguments in interrupt handle.
846*7c478bd9Sstevel@tonic-gate 		 */
847*7c478bd9Sstevel@tonic-gate 		DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler,
848*7c478bd9Sstevel@tonic-gate 		    ih_p->ih_handler_arg1, ih_p->ih_handler_arg2);
849*7c478bd9Sstevel@tonic-gate 
850*7c478bd9Sstevel@tonic-gate 		if (ret != DDI_SUCCESS)
851*7c478bd9Sstevel@tonic-gate 			goto fail2;
852*7c478bd9Sstevel@tonic-gate 
853*7c478bd9Sstevel@tonic-gate 		/* Save the pil for this ino */
854*7c478bd9Sstevel@tonic-gate 		ino_p->ino_pil = hdlp->ih_pri;
855*7c478bd9Sstevel@tonic-gate 
856*7c478bd9Sstevel@tonic-gate 		/* select cpu, saving it for sharing and removal */
857*7c478bd9Sstevel@tonic-gate 		ino_p->ino_cpuid = intr_dist_cpuid();
858*7c478bd9Sstevel@tonic-gate 
859*7c478bd9Sstevel@tonic-gate 		/* Enable interrupt */
860*7c478bd9Sstevel@tonic-gate 		px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino);
861*7c478bd9Sstevel@tonic-gate 	}
862*7c478bd9Sstevel@tonic-gate 
863*7c478bd9Sstevel@tonic-gate 	/* add weight to the cpu that we are already targeting */
864*7c478bd9Sstevel@tonic-gate 	weight = px_class_to_intr_weight(rdip);
865*7c478bd9Sstevel@tonic-gate 	intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight);
866*7c478bd9Sstevel@tonic-gate 
867*7c478bd9Sstevel@tonic-gate 	ih_p->ih_ino_p = ino_p;
868*7c478bd9Sstevel@tonic-gate 	if (ih_p->ih_ksp)
869*7c478bd9Sstevel@tonic-gate 		kstat_install(ih_p->ih_ksp);
870*7c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
871*7c478bd9Sstevel@tonic-gate 
872*7c478bd9Sstevel@tonic-gate 	DBG(DBG_A_INTX, dip, "px_add_intx_intr: done! Interrupt 0x%x pil=%x\n",
873*7c478bd9Sstevel@tonic-gate 	    ino_p->ino_sysino, hdlp->ih_pri);
874*7c478bd9Sstevel@tonic-gate 
875*7c478bd9Sstevel@tonic-gate 	return (ret);
876*7c478bd9Sstevel@tonic-gate fail2:
877*7c478bd9Sstevel@tonic-gate 	px_ib_delete_ino(ib_p, ino_p);
878*7c478bd9Sstevel@tonic-gate fail1:
879*7c478bd9Sstevel@tonic-gate 	if (ih_p->ih_config_handle)
880*7c478bd9Sstevel@tonic-gate 		pci_config_teardown(&ih_p->ih_config_handle);
881*7c478bd9Sstevel@tonic-gate 
882*7c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
883*7c478bd9Sstevel@tonic-gate 	kmem_free(ih_p, sizeof (px_ih_t));
884*7c478bd9Sstevel@tonic-gate 
885*7c478bd9Sstevel@tonic-gate 	DBG(DBG_A_INTX, dip, "px_add_intx_intr: Failed! Interrupt 0x%x "
886*7c478bd9Sstevel@tonic-gate 	    "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri);
887*7c478bd9Sstevel@tonic-gate 
888*7c478bd9Sstevel@tonic-gate 	return (ret);
889*7c478bd9Sstevel@tonic-gate }
890*7c478bd9Sstevel@tonic-gate 
891*7c478bd9Sstevel@tonic-gate int
892*7c478bd9Sstevel@tonic-gate px_rem_intx_intr(dev_info_t *dip, dev_info_t *rdip,
893*7c478bd9Sstevel@tonic-gate     ddi_intr_handle_impl_t *hdlp)
894*7c478bd9Sstevel@tonic-gate {
895*7c478bd9Sstevel@tonic-gate 	px_t		*px_p = INST_TO_STATE(ddi_get_instance(dip));
896*7c478bd9Sstevel@tonic-gate 	px_ib_t		*ib_p = px_p->px_ib_p;
897*7c478bd9Sstevel@tonic-gate 	devino_t	ino;
898*7c478bd9Sstevel@tonic-gate 	cpuid_t		curr_cpu;
899*7c478bd9Sstevel@tonic-gate 	px_ib_ino_info_t	*ino_p;
900*7c478bd9Sstevel@tonic-gate 	px_ih_t		*ih_p;
901*7c478bd9Sstevel@tonic-gate 	int		ret = DDI_SUCCESS;
902*7c478bd9Sstevel@tonic-gate 
903*7c478bd9Sstevel@tonic-gate 	ino = hdlp->ih_vector;
904*7c478bd9Sstevel@tonic-gate 
905*7c478bd9Sstevel@tonic-gate 	DBG(DBG_R_INTX, dip, "px_rem_intx_intr: rdip=%s%d ino=%x\n",
906*7c478bd9Sstevel@tonic-gate 	    ddi_driver_name(rdip), ddi_get_instance(rdip), ino);
907*7c478bd9Sstevel@tonic-gate 
908*7c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
909*7c478bd9Sstevel@tonic-gate 
910*7c478bd9Sstevel@tonic-gate 	ino_p = px_ib_locate_ino(ib_p, ino);
911*7c478bd9Sstevel@tonic-gate 	ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 0, 0);
912*7c478bd9Sstevel@tonic-gate 
913*7c478bd9Sstevel@tonic-gate 	/* Get the current cpu */
914*7c478bd9Sstevel@tonic-gate 	if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino,
915*7c478bd9Sstevel@tonic-gate 	    &curr_cpu)) != DDI_SUCCESS)
916*7c478bd9Sstevel@tonic-gate 		goto fail;
917*7c478bd9Sstevel@tonic-gate 
918*7c478bd9Sstevel@tonic-gate 	if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS)
919*7c478bd9Sstevel@tonic-gate 		goto fail;
920*7c478bd9Sstevel@tonic-gate 
921*7c478bd9Sstevel@tonic-gate 	intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip);
922*7c478bd9Sstevel@tonic-gate 
923*7c478bd9Sstevel@tonic-gate 	if (ino_p->ino_ih_size == 0) {
924*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino,
925*7c478bd9Sstevel@tonic-gate 		    INTR_DELIVERED_STATE)) != DDI_SUCCESS)
926*7c478bd9Sstevel@tonic-gate 			goto fail;
927*7c478bd9Sstevel@tonic-gate 
928*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = ino_p->ino_sysino;
929*7c478bd9Sstevel@tonic-gate 		i_ddi_rem_ivintr(hdlp);
930*7c478bd9Sstevel@tonic-gate 
931*7c478bd9Sstevel@tonic-gate 		px_ib_delete_ino(ib_p, ino_p);
932*7c478bd9Sstevel@tonic-gate 		kmem_free(ino_p, sizeof (px_ib_ino_info_t));
933*7c478bd9Sstevel@tonic-gate 	} else {
934*7c478bd9Sstevel@tonic-gate 		/* Re-enable interrupt only if mapping regsiter still shared */
935*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_intr_settarget(px_p->px_dip,
936*7c478bd9Sstevel@tonic-gate 			    ino_p->ino_sysino, curr_cpu)) != DDI_SUCCESS)
937*7c478bd9Sstevel@tonic-gate 			goto fail;
938*7c478bd9Sstevel@tonic-gate 
939*7c478bd9Sstevel@tonic-gate 		ret = px_lib_intr_setvalid(px_p->px_dip, ino_p->ino_sysino,
940*7c478bd9Sstevel@tonic-gate 		    INTR_VALID);
941*7c478bd9Sstevel@tonic-gate 	}
942*7c478bd9Sstevel@tonic-gate 
943*7c478bd9Sstevel@tonic-gate fail:
944*7c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
945*7c478bd9Sstevel@tonic-gate 	return (ret);
946*7c478bd9Sstevel@tonic-gate }
947*7c478bd9Sstevel@tonic-gate 
948*7c478bd9Sstevel@tonic-gate int
949*7c478bd9Sstevel@tonic-gate px_add_msiq_intr(dev_info_t *dip, dev_info_t *rdip,
950*7c478bd9Sstevel@tonic-gate     ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type,
951*7c478bd9Sstevel@tonic-gate     msgcode_t msg_code, msiqid_t *msiq_id_p)
952*7c478bd9Sstevel@tonic-gate {
953*7c478bd9Sstevel@tonic-gate 	px_t		*px_p = INST_TO_STATE(ddi_get_instance(dip));
954*7c478bd9Sstevel@tonic-gate 	px_ib_t		*ib_p = px_p->px_ib_p;
955*7c478bd9Sstevel@tonic-gate 	px_msiq_state_t	*msiq_state_p = &ib_p->ib_msiq_state;
956*7c478bd9Sstevel@tonic-gate 	devino_t	ino;
957*7c478bd9Sstevel@tonic-gate 	px_ih_t		*ih_p;
958*7c478bd9Sstevel@tonic-gate 	px_ib_ino_info_t	*ino_p;
959*7c478bd9Sstevel@tonic-gate 	int32_t		weight;
960*7c478bd9Sstevel@tonic-gate 	int		ret = DDI_SUCCESS;
961*7c478bd9Sstevel@tonic-gate 
962*7c478bd9Sstevel@tonic-gate 	DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=%x "
963*7c478bd9Sstevel@tonic-gate 	    "arg1=%x arg2=%x\n", ddi_driver_name(rdip), ddi_get_instance(rdip),
964*7c478bd9Sstevel@tonic-gate 	    hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2);
965*7c478bd9Sstevel@tonic-gate 
966*7c478bd9Sstevel@tonic-gate 	if ((ret = px_msiq_alloc(px_p, rec_type, msiq_id_p)) != DDI_SUCCESS) {
967*7c478bd9Sstevel@tonic-gate 		DBG(DBG_MSIQ, dip, "px_add_msiq_intr: "
968*7c478bd9Sstevel@tonic-gate 		    "msiq allocation failed\n");
969*7c478bd9Sstevel@tonic-gate 		return (ret);
970*7c478bd9Sstevel@tonic-gate 	}
971*7c478bd9Sstevel@tonic-gate 
972*7c478bd9Sstevel@tonic-gate 	ino = px_msiqid_to_devino(px_p, *msiq_id_p);
973*7c478bd9Sstevel@tonic-gate 
974*7c478bd9Sstevel@tonic-gate 	ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func,
975*7c478bd9Sstevel@tonic-gate 	    hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code);
976*7c478bd9Sstevel@tonic-gate 
977*7c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
978*7c478bd9Sstevel@tonic-gate 
979*7c478bd9Sstevel@tonic-gate 	if (ino_p = px_ib_locate_ino(ib_p, ino)) {	/* sharing ino */
980*7c478bd9Sstevel@tonic-gate 		uint32_t intr_index = hdlp->ih_inum;
981*7c478bd9Sstevel@tonic-gate 		if (px_ib_ino_locate_intr(ino_p, rdip,
982*7c478bd9Sstevel@tonic-gate 		    intr_index, rec_type, msg_code)) {
983*7c478bd9Sstevel@tonic-gate 			DBG(DBG_MSIQ, dip, "px_add_msiq_intr: "
984*7c478bd9Sstevel@tonic-gate 			    "dup intr #%d\n", intr_index);
985*7c478bd9Sstevel@tonic-gate 
986*7c478bd9Sstevel@tonic-gate 			ret = DDI_FAILURE;
987*7c478bd9Sstevel@tonic-gate 			goto fail1;
988*7c478bd9Sstevel@tonic-gate 		}
989*7c478bd9Sstevel@tonic-gate 
990*7c478bd9Sstevel@tonic-gate 		if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p))
991*7c478bd9Sstevel@tonic-gate 		    != DDI_SUCCESS)
992*7c478bd9Sstevel@tonic-gate 			goto fail1;
993*7c478bd9Sstevel@tonic-gate 	} else {
994*7c478bd9Sstevel@tonic-gate 		ino_p = px_ib_new_ino(ib_p, ino, ih_p);
995*7c478bd9Sstevel@tonic-gate 
996*7c478bd9Sstevel@tonic-gate 		ino_p->ino_msiq_p = msiq_state_p->msiq_p +
997*7c478bd9Sstevel@tonic-gate 		    (*msiq_id_p - msiq_state_p->msiq_1st_msiq_id);
998*7c478bd9Sstevel@tonic-gate 
999*7c478bd9Sstevel@tonic-gate 		if (hdlp->ih_pri == 0)
1000*7c478bd9Sstevel@tonic-gate 			hdlp->ih_pri = px_class_to_pil(rdip);
1001*7c478bd9Sstevel@tonic-gate 
1002*7c478bd9Sstevel@tonic-gate 		/* Save mondo value in hdlp */
1003*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = ino_p->ino_sysino;
1004*7c478bd9Sstevel@tonic-gate 
1005*7c478bd9Sstevel@tonic-gate 		DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n",
1006*7c478bd9Sstevel@tonic-gate 		    hdlp->ih_pri, hdlp->ih_vector);
1007*7c478bd9Sstevel@tonic-gate 
1008*7c478bd9Sstevel@tonic-gate 		DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp,
1009*7c478bd9Sstevel@tonic-gate 		    (ddi_intr_handler_t *)px_msiq_intr, (caddr_t)ino_p, NULL);
1010*7c478bd9Sstevel@tonic-gate 
1011*7c478bd9Sstevel@tonic-gate 		ret = i_ddi_add_ivintr(hdlp);
1012*7c478bd9Sstevel@tonic-gate 
1013*7c478bd9Sstevel@tonic-gate 		/*
1014*7c478bd9Sstevel@tonic-gate 		 * Restore original interrupt handler
1015*7c478bd9Sstevel@tonic-gate 		 * and arguments in interrupt handle.
1016*7c478bd9Sstevel@tonic-gate 		 */
1017*7c478bd9Sstevel@tonic-gate 		DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler,
1018*7c478bd9Sstevel@tonic-gate 		    ih_p->ih_handler_arg1, ih_p->ih_handler_arg2);
1019*7c478bd9Sstevel@tonic-gate 
1020*7c478bd9Sstevel@tonic-gate 		if (ret != DDI_SUCCESS)
1021*7c478bd9Sstevel@tonic-gate 			goto fail2;
1022*7c478bd9Sstevel@tonic-gate 
1023*7c478bd9Sstevel@tonic-gate 		/* Save the pil for this ino */
1024*7c478bd9Sstevel@tonic-gate 		ino_p->ino_pil = hdlp->ih_pri;
1025*7c478bd9Sstevel@tonic-gate 
1026*7c478bd9Sstevel@tonic-gate 		/* Enable MSIQ */
1027*7c478bd9Sstevel@tonic-gate 		px_lib_msiq_setstate(dip, *msiq_id_p, PCI_MSIQ_STATE_IDLE);
1028*7c478bd9Sstevel@tonic-gate 		px_lib_msiq_setvalid(dip, *msiq_id_p, PCI_MSIQ_VALID);
1029*7c478bd9Sstevel@tonic-gate 
1030*7c478bd9Sstevel@tonic-gate 		/* select cpu, saving it for sharing and removal */
1031*7c478bd9Sstevel@tonic-gate 		ino_p->ino_cpuid = intr_dist_cpuid();
1032*7c478bd9Sstevel@tonic-gate 
1033*7c478bd9Sstevel@tonic-gate 		/* Enable interrupt */
1034*7c478bd9Sstevel@tonic-gate 		px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino_p->ino_ino);
1035*7c478bd9Sstevel@tonic-gate 	}
1036*7c478bd9Sstevel@tonic-gate 
1037*7c478bd9Sstevel@tonic-gate 	/* add weight to the cpu that we are already targeting */
1038*7c478bd9Sstevel@tonic-gate 	weight = px_class_to_intr_weight(rdip);
1039*7c478bd9Sstevel@tonic-gate 	intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight);
1040*7c478bd9Sstevel@tonic-gate 
1041*7c478bd9Sstevel@tonic-gate 	ih_p->ih_ino_p = ino_p;
1042*7c478bd9Sstevel@tonic-gate 	if (ih_p->ih_ksp)
1043*7c478bd9Sstevel@tonic-gate 		kstat_install(ih_p->ih_ksp);
1044*7c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
1045*7c478bd9Sstevel@tonic-gate 
1046*7c478bd9Sstevel@tonic-gate 	DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n",
1047*7c478bd9Sstevel@tonic-gate 	    ino_p->ino_sysino, hdlp->ih_pri);
1048*7c478bd9Sstevel@tonic-gate 
1049*7c478bd9Sstevel@tonic-gate 	return (ret);
1050*7c478bd9Sstevel@tonic-gate fail2:
1051*7c478bd9Sstevel@tonic-gate 	px_ib_delete_ino(ib_p, ino_p);
1052*7c478bd9Sstevel@tonic-gate fail1:
1053*7c478bd9Sstevel@tonic-gate 	if (ih_p->ih_config_handle)
1054*7c478bd9Sstevel@tonic-gate 		pci_config_teardown(&ih_p->ih_config_handle);
1055*7c478bd9Sstevel@tonic-gate 
1056*7c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
1057*7c478bd9Sstevel@tonic-gate 	kmem_free(ih_p, sizeof (px_ih_t));
1058*7c478bd9Sstevel@tonic-gate 
1059*7c478bd9Sstevel@tonic-gate 	DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n",
1060*7c478bd9Sstevel@tonic-gate 	    ino_p->ino_sysino, hdlp->ih_pri);
1061*7c478bd9Sstevel@tonic-gate 
1062*7c478bd9Sstevel@tonic-gate 	return (ret);
1063*7c478bd9Sstevel@tonic-gate }
1064*7c478bd9Sstevel@tonic-gate 
1065*7c478bd9Sstevel@tonic-gate int
1066*7c478bd9Sstevel@tonic-gate px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip,
1067*7c478bd9Sstevel@tonic-gate     ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type,
1068*7c478bd9Sstevel@tonic-gate     msgcode_t msg_code, msiqid_t msiq_id)
1069*7c478bd9Sstevel@tonic-gate {
1070*7c478bd9Sstevel@tonic-gate 	px_t		*px_p = INST_TO_STATE(ddi_get_instance(dip));
1071*7c478bd9Sstevel@tonic-gate 	px_ib_t		*ib_p = px_p->px_ib_p;
1072*7c478bd9Sstevel@tonic-gate 	devino_t	ino = px_msiqid_to_devino(px_p, msiq_id);
1073*7c478bd9Sstevel@tonic-gate 	cpuid_t		curr_cpu;
1074*7c478bd9Sstevel@tonic-gate 	px_ib_ino_info_t *ino_p;
1075*7c478bd9Sstevel@tonic-gate 	px_ih_t		*ih_p;
1076*7c478bd9Sstevel@tonic-gate 	int		ret = DDI_SUCCESS;
1077*7c478bd9Sstevel@tonic-gate 
1078*7c478bd9Sstevel@tonic-gate 	DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n",
1079*7c478bd9Sstevel@tonic-gate 	    ddi_driver_name(rdip), ddi_get_instance(rdip), msiq_id, ino);
1080*7c478bd9Sstevel@tonic-gate 
1081*7c478bd9Sstevel@tonic-gate 	mutex_enter(&ib_p->ib_ino_lst_mutex);
1082*7c478bd9Sstevel@tonic-gate 
1083*7c478bd9Sstevel@tonic-gate 	ino_p = px_ib_locate_ino(ib_p, ino);
1084*7c478bd9Sstevel@tonic-gate 	ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum,
1085*7c478bd9Sstevel@tonic-gate 	    rec_type, msg_code);
1086*7c478bd9Sstevel@tonic-gate 
1087*7c478bd9Sstevel@tonic-gate 	/* Get the current cpu */
1088*7c478bd9Sstevel@tonic-gate 	if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino,
1089*7c478bd9Sstevel@tonic-gate 	    &curr_cpu)) != DDI_SUCCESS)
1090*7c478bd9Sstevel@tonic-gate 		goto fail;
1091*7c478bd9Sstevel@tonic-gate 
1092*7c478bd9Sstevel@tonic-gate 	if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS)
1093*7c478bd9Sstevel@tonic-gate 		goto fail;
1094*7c478bd9Sstevel@tonic-gate 
1095*7c478bd9Sstevel@tonic-gate 	intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip);
1096*7c478bd9Sstevel@tonic-gate 
1097*7c478bd9Sstevel@tonic-gate 	if (ino_p->ino_ih_size == 0) {
1098*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino,
1099*7c478bd9Sstevel@tonic-gate 		    INTR_DELIVERED_STATE)) != DDI_SUCCESS)
1100*7c478bd9Sstevel@tonic-gate 			goto fail;
1101*7c478bd9Sstevel@tonic-gate 
1102*7c478bd9Sstevel@tonic-gate 		px_lib_msiq_setvalid(dip, px_devino_to_msiqid(px_p, ino),
1103*7c478bd9Sstevel@tonic-gate 		    PCI_MSIQ_INVALID);
1104*7c478bd9Sstevel@tonic-gate 
1105*7c478bd9Sstevel@tonic-gate 		hdlp->ih_vector = ino_p->ino_sysino;
1106*7c478bd9Sstevel@tonic-gate 		i_ddi_rem_ivintr(hdlp);
1107*7c478bd9Sstevel@tonic-gate 
1108*7c478bd9Sstevel@tonic-gate 		px_ib_delete_ino(ib_p, ino_p);
1109*7c478bd9Sstevel@tonic-gate 
1110*7c478bd9Sstevel@tonic-gate 		(void) px_msiq_free(px_p, msiq_id);
1111*7c478bd9Sstevel@tonic-gate 		kmem_free(ino_p, sizeof (px_ib_ino_info_t));
1112*7c478bd9Sstevel@tonic-gate 	} else {
1113*7c478bd9Sstevel@tonic-gate 		/* Re-enable interrupt only if mapping regsiter still shared */
1114*7c478bd9Sstevel@tonic-gate 		if ((ret = px_lib_intr_settarget(px_p->px_dip,
1115*7c478bd9Sstevel@tonic-gate 			    ino_p->ino_sysino, curr_cpu)) != DDI_SUCCESS)
1116*7c478bd9Sstevel@tonic-gate 			goto fail;
1117*7c478bd9Sstevel@tonic-gate 
1118*7c478bd9Sstevel@tonic-gate 		ret = px_lib_intr_setvalid(px_p->px_dip, ino_p->ino_sysino,
1119*7c478bd9Sstevel@tonic-gate 		    INTR_VALID);
1120*7c478bd9Sstevel@tonic-gate 	}
1121*7c478bd9Sstevel@tonic-gate 
1122*7c478bd9Sstevel@tonic-gate fail:
1123*7c478bd9Sstevel@tonic-gate 	mutex_exit(&ib_p->ib_ino_lst_mutex);
1124*7c478bd9Sstevel@tonic-gate 	return (ret);
1125*7c478bd9Sstevel@tonic-gate }
1126