17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5102cb92eSjohnny * Common Development and Distribution License (the "License"). 6102cb92eSjohnny * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22614edcaeSEvan Yan * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate /* 277c478bd9Sstevel@tonic-gate * PX nexus interrupt handling: 287c478bd9Sstevel@tonic-gate * PX device interrupt handler wrapper 297c478bd9Sstevel@tonic-gate * PIL lookup routine 307c478bd9Sstevel@tonic-gate * PX device interrupt related initchild code 317c478bd9Sstevel@tonic-gate */ 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #include <sys/types.h> 347c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 357c478bd9Sstevel@tonic-gate #include <sys/async.h> 367c478bd9Sstevel@tonic-gate #include <sys/spl.h> 377c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 38f8d2de6bSjchu #include <sys/fm/protocol.h> 39f8d2de6bSjchu #include <sys/fm/util.h> 407c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 417c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 427c478bd9Sstevel@tonic-gate #include <sys/sdt.h> 437c478bd9Sstevel@tonic-gate #include <sys/atomic.h> 447c478bd9Sstevel@tonic-gate #include "px_obj.h" 45f8d2de6bSjchu #include <sys/ontrap.h> 46f8d2de6bSjchu #include <sys/membar.h> 476d44af1bSesolom #include <sys/clock.h> 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate /* 507c478bd9Sstevel@tonic-gate * interrupt jabber: 517c478bd9Sstevel@tonic-gate * 527c478bd9Sstevel@tonic-gate * When an interrupt line is jabbering, every time the state machine for the 537c478bd9Sstevel@tonic-gate * associated ino is idled, a new mondo will be sent and the ino will go into 547c478bd9Sstevel@tonic-gate * the pending state again. The mondo will cause a new call to 557c478bd9Sstevel@tonic-gate * px_intr_wrapper() which normally idles the ino's state machine which would 567c478bd9Sstevel@tonic-gate * precipitate another trip round the loop. 577c478bd9Sstevel@tonic-gate * 587c478bd9Sstevel@tonic-gate * The loop can be broken by preventing the ino's state machine from being 597c478bd9Sstevel@tonic-gate * idled when an interrupt line is jabbering. See the comment at the 607c478bd9Sstevel@tonic-gate * beginning of px_intr_wrapper() explaining how the 'interrupt jabber 617c478bd9Sstevel@tonic-gate * protection' code does this. 627c478bd9Sstevel@tonic-gate */ 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate /* 677c478bd9Sstevel@tonic-gate * If the unclaimed interrupt count has reached the limit set by 687c478bd9Sstevel@tonic-gate * pci_unclaimed_intr_max within the time limit, then all interrupts 697c478bd9Sstevel@tonic-gate * on this ino is blocked by not idling the interrupt state machine. 707c478bd9Sstevel@tonic-gate */ 717c478bd9Sstevel@tonic-gate static int 72b0fc0e77Sgovinda px_spurintr(px_ino_pil_t *ipil_p) 737c478bd9Sstevel@tonic-gate { 74b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 75b0fc0e77Sgovinda px_ih_t *ih_p = ipil_p->ipil_ih_start; 76b0fc0e77Sgovinda px_t *px_p = ino_p->ino_ib_p->ib_px_p; 77b0fc0e77Sgovinda char *err_fmt_str; 78b0fc0e77Sgovinda boolean_t blocked = B_FALSE; 79b0fc0e77Sgovinda int i; 807c478bd9Sstevel@tonic-gate 81b0fc0e77Sgovinda if (ino_p->ino_unclaimed_intrs > px_unclaimed_intr_max) 827c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 837c478bd9Sstevel@tonic-gate 84b0fc0e77Sgovinda if (!ino_p->ino_unclaimed_intrs) 857c478bd9Sstevel@tonic-gate ino_p->ino_spurintr_begin = ddi_get_lbolt(); 867c478bd9Sstevel@tonic-gate 87b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs++; 887c478bd9Sstevel@tonic-gate 89b0fc0e77Sgovinda if (ino_p->ino_unclaimed_intrs <= px_unclaimed_intr_max) 907c478bd9Sstevel@tonic-gate goto clear; 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 937c478bd9Sstevel@tonic-gate > px_spurintr_duration) { 94b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs = 0; 957c478bd9Sstevel@tonic-gate goto clear; 967c478bd9Sstevel@tonic-gate } 977c478bd9Sstevel@tonic-gate err_fmt_str = "%s%d: ino 0x%x blocked"; 98b0fc0e77Sgovinda blocked = B_TRUE; 997c478bd9Sstevel@tonic-gate goto warn; 1007c478bd9Sstevel@tonic-gate clear: 1017c478bd9Sstevel@tonic-gate err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 1027c478bd9Sstevel@tonic-gate warn: 1037c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, err_fmt_str, NAMEINST(px_p->px_dip), ino_p->ino_ino); 104b0fc0e77Sgovinda for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) 1057c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 1067c478bd9Sstevel@tonic-gate ih_p->ih_inum); 1077c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!\n"); 108b0fc0e77Sgovinda 109b0fc0e77Sgovinda /* Clear the pending state */ 110b0fc0e77Sgovinda if (blocked == B_FALSE) { 111b0fc0e77Sgovinda if (px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 112b0fc0e77Sgovinda INTR_IDLE_STATE) != DDI_SUCCESS) 113b0fc0e77Sgovinda return (DDI_INTR_UNCLAIMED); 114b0fc0e77Sgovinda } 115b0fc0e77Sgovinda 1167c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 1177c478bd9Sstevel@tonic-gate } 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate extern uint64_t intr_get_time(void); 1207c478bd9Sstevel@tonic-gate 1217c478bd9Sstevel@tonic-gate /* 122a195726fSgovinda * px_intx_intr (INTx or legacy interrupt handler) 1237c478bd9Sstevel@tonic-gate * 1247c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 1257c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 1267c478bd9Sstevel@tonic-gate * examines the return codes. 1277c478bd9Sstevel@tonic-gate * 1287c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 1297c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 1307c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 1317c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 1327c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 1337c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 1347c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 1357c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 1367c478bd9Sstevel@tonic-gate * 1377c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 1387c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 1397c478bd9Sstevel@tonic-gate */ 1407c478bd9Sstevel@tonic-gate uint_t 1417c478bd9Sstevel@tonic-gate px_intx_intr(caddr_t arg) 1427c478bd9Sstevel@tonic-gate { 143b0fc0e77Sgovinda px_ino_pil_t *ipil_p = (px_ino_pil_t *)arg; 144b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 1457c478bd9Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 146b0fc0e77Sgovinda px_ih_t *ih_p = ipil_p->ipil_ih_start; 147b0fc0e77Sgovinda ushort_t pil = ipil_p->ipil_pil; 148b0fc0e77Sgovinda uint_t result = 0, r = DDI_INTR_UNCLAIMED; 1497c478bd9Sstevel@tonic-gate int i; 1507c478bd9Sstevel@tonic-gate 1517c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 1527c478bd9Sstevel@tonic-gate "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n", 153b0fc0e77Sgovinda ino_p->ino_ino, ino_p->ino_sysino, ipil_p->ipil_pil, 154b0fc0e77Sgovinda ipil_p->ipil_ih_size, ipil_p->ipil_ih_head); 1557c478bd9Sstevel@tonic-gate 156b0fc0e77Sgovinda for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) { 1577c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 1587c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 1597c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 1607c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) { 1637c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, 1647c478bd9Sstevel@tonic-gate "px_intx_intr: %s%d interrupt %d is disabled\n", 1657c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 1667c478bd9Sstevel@tonic-gate ino_p->ino_ino); 1677c478bd9Sstevel@tonic-gate 1687c478bd9Sstevel@tonic-gate continue; 1697c478bd9Sstevel@tonic-gate } 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 1727c478bd9Sstevel@tonic-gate "ino=%x handler=%p arg1 =%p arg2 = %p\n", 1737c478bd9Sstevel@tonic-gate ino_p->ino_ino, handler, arg1, arg2); 1747c478bd9Sstevel@tonic-gate 1757c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 1767c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 1777c478bd9Sstevel@tonic-gate 1787c478bd9Sstevel@tonic-gate r = (*handler)(arg1, arg2); 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate /* 1817c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect against 1827c478bd9Sstevel@tonic-gate * conflicting writes to ih_ticks from ib_intr_dist_all() by 1837c478bd9Sstevel@tonic-gate * using atomic ops. 1847c478bd9Sstevel@tonic-gate */ 1857c478bd9Sstevel@tonic-gate 186b0fc0e77Sgovinda if (pil <= LOCK_LEVEL) 1877c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 1887c478bd9Sstevel@tonic-gate 1897c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 1907c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, r); 1917c478bd9Sstevel@tonic-gate 1927c478bd9Sstevel@tonic-gate result += r; 1937c478bd9Sstevel@tonic-gate 1947c478bd9Sstevel@tonic-gate if (px_check_all_handlers) 1957c478bd9Sstevel@tonic-gate continue; 1967c478bd9Sstevel@tonic-gate if (result) 1977c478bd9Sstevel@tonic-gate break; 1987c478bd9Sstevel@tonic-gate } 1997c478bd9Sstevel@tonic-gate 200b0fc0e77Sgovinda if (result) 201b0fc0e77Sgovinda ino_p->ino_claimed |= (1 << pil); 202b0fc0e77Sgovinda 203b0fc0e77Sgovinda /* Interrupt can only be cleared after all pil levels are handled */ 204b0fc0e77Sgovinda if (pil != ino_p->ino_lopil) 205b0fc0e77Sgovinda return (DDI_INTR_CLAIMED); 206b0fc0e77Sgovinda 207b0fc0e77Sgovinda if (!ino_p->ino_claimed) { 208b0fc0e77Sgovinda if (px_unclaimed_intr_block) 209b0fc0e77Sgovinda return (px_spurintr(ipil_p)); 210b0fc0e77Sgovinda } 2117c478bd9Sstevel@tonic-gate 212b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs = 0; 213b0fc0e77Sgovinda ino_p->ino_claimed = 0; 2147c478bd9Sstevel@tonic-gate 2157c478bd9Sstevel@tonic-gate /* Clear the pending state */ 216b0fc0e77Sgovinda if (px_lib_intr_setstate(px_p->px_dip, 2177c478bd9Sstevel@tonic-gate ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 2187c478bd9Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 2217c478bd9Sstevel@tonic-gate } 2227c478bd9Sstevel@tonic-gate 2237c478bd9Sstevel@tonic-gate /* 224a195726fSgovinda * px_msiq_intr (MSI/X or PCIe MSG interrupt handler) 2257c478bd9Sstevel@tonic-gate * 2267c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 2277c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 2287c478bd9Sstevel@tonic-gate * examines the return codes. 2297c478bd9Sstevel@tonic-gate * 2307c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 2317c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 2327c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 2337c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 2347c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 2357c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 2367c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 2377c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 2387c478bd9Sstevel@tonic-gate * 2397c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 2407c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 2417c478bd9Sstevel@tonic-gate */ 2427c478bd9Sstevel@tonic-gate uint_t 2437c478bd9Sstevel@tonic-gate px_msiq_intr(caddr_t arg) 2447c478bd9Sstevel@tonic-gate { 245b0fc0e77Sgovinda px_ino_pil_t *ipil_p = (px_ino_pil_t *)arg; 246b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 2477c478bd9Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 2487c478bd9Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 2497c478bd9Sstevel@tonic-gate px_msiq_t *msiq_p = ino_p->ino_msiq_p; 2507c478bd9Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 251b0fc0e77Sgovinda ushort_t pil = ipil_p->ipil_pil; 2527c478bd9Sstevel@tonic-gate msiq_rec_t msiq_rec, *msiq_rec_p = &msiq_rec; 253023ccc1eSegillett msiqhead_t *curr_head_p; 254023ccc1eSegillett msiqtail_t curr_tail_index; 2557c478bd9Sstevel@tonic-gate msgcode_t msg_code; 2567c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 257b0fc0e77Sgovinda uint_t ret = DDI_INTR_UNCLAIMED; 258b0fc0e77Sgovinda int i, j; 2597c478bd9Sstevel@tonic-gate 2607c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x " 2617c478bd9Sstevel@tonic-gate "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino, 262b0fc0e77Sgovinda ipil_p->ipil_pil, ipil_p->ipil_ih_size, ipil_p->ipil_ih_head); 263b0fc0e77Sgovinda 264b0fc0e77Sgovinda /* 265b0fc0e77Sgovinda * The px_msiq_intr() handles multiple interrupt priorities and it 266b0fc0e77Sgovinda * will set msiq->msiq_rec2process to the number of MSIQ records to 267b0fc0e77Sgovinda * process while handling the highest priority interrupt. Subsequent 268b0fc0e77Sgovinda * lower priority interrupts will just process any unprocessed MSIQ 269b0fc0e77Sgovinda * records or will just return immediately. 270b0fc0e77Sgovinda */ 271b0fc0e77Sgovinda if (msiq_p->msiq_recs2process == 0) { 272b0fc0e77Sgovinda /* Read current MSIQ tail index */ 273b0fc0e77Sgovinda px_lib_msiq_gettail(dip, msiq_p->msiq_id, &curr_tail_index); 274b0fc0e77Sgovinda msiq_p->msiq_new_head_index = msiq_p->msiq_curr_head_index; 275b0fc0e77Sgovinda 276b0fc0e77Sgovinda if (curr_tail_index < msiq_p->msiq_curr_head_index) 277b0fc0e77Sgovinda curr_tail_index += msiq_state_p->msiq_rec_cnt; 2787c478bd9Sstevel@tonic-gate 279b0fc0e77Sgovinda msiq_p->msiq_recs2process = curr_tail_index - 280b0fc0e77Sgovinda msiq_p->msiq_curr_head_index; 281b0fc0e77Sgovinda } 282b0fc0e77Sgovinda 283b0fc0e77Sgovinda DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: curr_head %x new_head %x " 284b0fc0e77Sgovinda "rec2process %x\n", msiq_p->msiq_curr_head_index, 285b0fc0e77Sgovinda msiq_p->msiq_new_head_index, msiq_p->msiq_recs2process); 2867c478bd9Sstevel@tonic-gate 287b0fc0e77Sgovinda /* If all MSIQ records are already processed, just return immediately */ 288b0fc0e77Sgovinda if ((msiq_p->msiq_new_head_index - msiq_p->msiq_curr_head_index) 289b0fc0e77Sgovinda == msiq_p->msiq_recs2process) 290b0fc0e77Sgovinda goto intr_done; 291b0fc0e77Sgovinda 292b0fc0e77Sgovinda curr_head_p = (msiqhead_t *)((caddr_t)msiq_p->msiq_base_p + 293b0fc0e77Sgovinda (msiq_p->msiq_curr_head_index * sizeof (msiq_rec_t))); 2947c478bd9Sstevel@tonic-gate 2957c478bd9Sstevel@tonic-gate /* 296023ccc1eSegillett * Calculate the number of recs to process by taking the difference 297023ccc1eSegillett * between the head and tail pointers. For all records we always 298023ccc1eSegillett * verify that we have a valid record type before we do any processing. 299b0fc0e77Sgovinda * If triggered, we should always have at least one valid record. 3007c478bd9Sstevel@tonic-gate */ 301b0fc0e77Sgovinda for (i = 0; i < msiq_p->msiq_recs2process; i++) { 302*2324ee65SAlan Adamson, SD OSSD msiq_rec_type_t rec_type; 303*2324ee65SAlan Adamson, SD OSSD 304b0fc0e77Sgovinda /* Read next MSIQ record */ 305023ccc1eSegillett px_lib_get_msiq_rec(dip, curr_head_p, msiq_rec_p); 306023ccc1eSegillett 307*2324ee65SAlan Adamson, SD OSSD rec_type = msiq_rec_p->msiq_rec_type; 308*2324ee65SAlan Adamson, SD OSSD 3097c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSIQ RECORD, " 3107c478bd9Sstevel@tonic-gate "msiq_rec_type 0x%llx msiq_rec_rid 0x%llx\n", 311*2324ee65SAlan Adamson, SD OSSD rec_type, msiq_rec_p->msiq_rec_rid); 3127c478bd9Sstevel@tonic-gate 313*2324ee65SAlan Adamson, SD OSSD if (!rec_type) 314b0fc0e77Sgovinda goto next_rec; 3157c478bd9Sstevel@tonic-gate 3167c478bd9Sstevel@tonic-gate /* Check MSIQ record type */ 317*2324ee65SAlan Adamson, SD OSSD switch (rec_type) { 3187c478bd9Sstevel@tonic-gate case MSG_REC: 3197c478bd9Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msg.msg_code; 3207c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: PCIE MSG " 3217c478bd9Sstevel@tonic-gate "record, msg type 0x%x\n", msg_code); 3227c478bd9Sstevel@tonic-gate break; 3237c478bd9Sstevel@tonic-gate case MSI32_REC: 3247c478bd9Sstevel@tonic-gate case MSI64_REC: 3257c478bd9Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msi.msi_data; 3267c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSI record, " 3277c478bd9Sstevel@tonic-gate "msi 0x%x\n", msg_code); 3287c478bd9Sstevel@tonic-gate 3297c478bd9Sstevel@tonic-gate /* Clear MSI state */ 3307c478bd9Sstevel@tonic-gate px_lib_msi_setstate(dip, (msinum_t)msg_code, 3317c478bd9Sstevel@tonic-gate PCI_MSI_STATE_IDLE); 3327c478bd9Sstevel@tonic-gate break; 3337c478bd9Sstevel@tonic-gate default: 3347c478bd9Sstevel@tonic-gate msg_code = 0; 3357c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_msiq_intr: 0x%x MSIQ " 3367c478bd9Sstevel@tonic-gate "record type is not supported", 3377c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 338*2324ee65SAlan Adamson, SD OSSD rec_type); 339b0fc0e77Sgovinda 3407c478bd9Sstevel@tonic-gate goto next_rec; 3417c478bd9Sstevel@tonic-gate } 3427c478bd9Sstevel@tonic-gate 3437c478bd9Sstevel@tonic-gate /* 3447c478bd9Sstevel@tonic-gate * Scan through px_ih_t linked list, searching for the 3457c478bd9Sstevel@tonic-gate * right px_ih_t, matching MSIQ record data. 3467c478bd9Sstevel@tonic-gate */ 347b0fc0e77Sgovinda for (j = 0, ih_p = ipil_p->ipil_ih_start; 348b0fc0e77Sgovinda ih_p && (j < ipil_p->ipil_ih_size) && 34907f14c08Sgovinda ((ih_p->ih_msg_code != msg_code) || 350*2324ee65SAlan Adamson, SD OSSD (ih_p->ih_rec_type != rec_type)); 3512917a9c9Sschwartz ih_p = ih_p->ih_next, j++) 3522917a9c9Sschwartz ; 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate if ((ih_p->ih_msg_code == msg_code) && 355*2324ee65SAlan Adamson, SD OSSD (ih_p->ih_rec_type == rec_type)) { 3567c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 3577c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 3587c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 3597c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 3607c478bd9Sstevel@tonic-gate 3617c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: ino=%x data=%x " 3627c478bd9Sstevel@tonic-gate "handler=%p arg1 =%p arg2=%p\n", ino_p->ino_ino, 3637c478bd9Sstevel@tonic-gate msg_code, handler, arg1, arg2); 3647c478bd9Sstevel@tonic-gate 3657c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 3667c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 3677c478bd9Sstevel@tonic-gate 368f8d2de6bSjchu /* 369f8d2de6bSjchu * Special case for PCIE Error Messages. 370f8d2de6bSjchu * The current frame work doesn't fit PCIE Err Msgs 371f8d2de6bSjchu * This should be fixed when PCIE MESSAGES as a whole 372f8d2de6bSjchu * is architected correctly. 373f8d2de6bSjchu */ 374*2324ee65SAlan Adamson, SD OSSD if ((rec_type == MSG_REC) && 375*2324ee65SAlan Adamson, SD OSSD ((msg_code == PCIE_MSG_CODE_ERR_COR) || 376f8d2de6bSjchu (msg_code == PCIE_MSG_CODE_ERR_NONFATAL) || 377*2324ee65SAlan Adamson, SD OSSD (msg_code == PCIE_MSG_CODE_ERR_FATAL))) { 378f8d2de6bSjchu ret = px_err_fabric_intr(px_p, msg_code, 379f8d2de6bSjchu msiq_rec_p->msiq_rec_rid); 380f8d2de6bSjchu } else 381f8d2de6bSjchu ret = (*handler)(arg1, arg2); 3827c478bd9Sstevel@tonic-gate 3837c478bd9Sstevel@tonic-gate /* 3847c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect 3857c478bd9Sstevel@tonic-gate * against conflicting writes to ih_ticks from 3867c478bd9Sstevel@tonic-gate * ib_intr_dist_all() by using atomic ops. 3877c478bd9Sstevel@tonic-gate */ 3887c478bd9Sstevel@tonic-gate 389b0fc0e77Sgovinda if (pil <= LOCK_LEVEL) 3907c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 3917c478bd9Sstevel@tonic-gate 3927c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 3937c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, ret); 394023ccc1eSegillett 395b0fc0e77Sgovinda msiq_p->msiq_new_head_index++; 396b0fc0e77Sgovinda px_lib_clr_msiq_rec(dip, curr_head_p); 3977c478bd9Sstevel@tonic-gate } else { 3987c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr:" 399023ccc1eSegillett "No matching MSIQ record found\n"); 4007c478bd9Sstevel@tonic-gate } 4017c478bd9Sstevel@tonic-gate next_rec: 402023ccc1eSegillett /* Get the pointer next EQ record */ 403023ccc1eSegillett curr_head_p = (msiqhead_t *) 404023ccc1eSegillett ((caddr_t)curr_head_p + sizeof (msiq_rec_t)); 405023ccc1eSegillett 406023ccc1eSegillett /* Check for overflow condition */ 407023ccc1eSegillett if (curr_head_p >= (msiqhead_t *)((caddr_t)msiq_p->msiq_base_p 408b0fc0e77Sgovinda + (msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t)))) 409023ccc1eSegillett curr_head_p = (msiqhead_t *)msiq_p->msiq_base_p; 4107c478bd9Sstevel@tonic-gate } 4117c478bd9Sstevel@tonic-gate 412b0fc0e77Sgovinda DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: No of MSIQ recs processed %x\n", 413b0fc0e77Sgovinda (msiq_p->msiq_new_head_index - msiq_p->msiq_curr_head_index)); 414023ccc1eSegillett 415b0fc0e77Sgovinda DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: curr_head %x new_head %x " 416b0fc0e77Sgovinda "rec2process %x\n", msiq_p->msiq_curr_head_index, 417b0fc0e77Sgovinda msiq_p->msiq_new_head_index, msiq_p->msiq_recs2process); 418b0fc0e77Sgovinda 419b0fc0e77Sgovinda /* ino_claimed used just for debugging purpose */ 420b0fc0e77Sgovinda if (ret) 421b0fc0e77Sgovinda ino_p->ino_claimed |= (1 << pil); 422b0fc0e77Sgovinda 423b0fc0e77Sgovinda intr_done: 424b0fc0e77Sgovinda /* Interrupt can only be cleared after all pil levels are handled */ 425b0fc0e77Sgovinda if (pil != ino_p->ino_lopil) 426b0fc0e77Sgovinda return (DDI_INTR_CLAIMED); 427b0fc0e77Sgovinda 428b0fc0e77Sgovinda if (msiq_p->msiq_new_head_index <= msiq_p->msiq_curr_head_index) { 429b0fc0e77Sgovinda if (px_unclaimed_intr_block) 430b0fc0e77Sgovinda return (px_spurintr(ipil_p)); 431023ccc1eSegillett } 4327c478bd9Sstevel@tonic-gate 4337c478bd9Sstevel@tonic-gate /* Update MSIQ head index with no of MSIQ records processed */ 434b0fc0e77Sgovinda if (msiq_p->msiq_new_head_index >= msiq_state_p->msiq_rec_cnt) 435b0fc0e77Sgovinda msiq_p->msiq_new_head_index -= msiq_state_p->msiq_rec_cnt; 4367c478bd9Sstevel@tonic-gate 437b0fc0e77Sgovinda msiq_p->msiq_curr_head_index = msiq_p->msiq_new_head_index; 438b0fc0e77Sgovinda px_lib_msiq_sethead(dip, msiq_p->msiq_id, msiq_p->msiq_new_head_index); 439b0fc0e77Sgovinda 440b0fc0e77Sgovinda msiq_p->msiq_new_head_index = 0; 441b0fc0e77Sgovinda msiq_p->msiq_recs2process = 0; 442b0fc0e77Sgovinda ino_p->ino_claimed = 0; 4437c478bd9Sstevel@tonic-gate 4447c478bd9Sstevel@tonic-gate /* Clear the pending state */ 4457c478bd9Sstevel@tonic-gate if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 4467c478bd9Sstevel@tonic-gate INTR_IDLE_STATE) != DDI_SUCCESS) 4477c478bd9Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 4487c478bd9Sstevel@tonic-gate 4497c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 4507c478bd9Sstevel@tonic-gate } 4517c478bd9Sstevel@tonic-gate 4527c478bd9Sstevel@tonic-gate dev_info_t * 4537c478bd9Sstevel@tonic-gate px_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 4547c478bd9Sstevel@tonic-gate { 4557c478bd9Sstevel@tonic-gate dev_info_t *cdip = rdip; 4567c478bd9Sstevel@tonic-gate 4577c478bd9Sstevel@tonic-gate for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 4587c478bd9Sstevel@tonic-gate ; 4597c478bd9Sstevel@tonic-gate 4607c478bd9Sstevel@tonic-gate return (cdip); 4617c478bd9Sstevel@tonic-gate } 4627c478bd9Sstevel@tonic-gate 4637c478bd9Sstevel@tonic-gate /* ARGSUSED */ 4647c478bd9Sstevel@tonic-gate int 4657c478bd9Sstevel@tonic-gate px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 4667c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 4677c478bd9Sstevel@tonic-gate { 468a195726fSgovinda px_t *px_p = DIP_TO_STATE(dip); 469a195726fSgovinda int ret = DDI_SUCCESS; 4707c478bd9Sstevel@tonic-gate 4717c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x " 4727c478bd9Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 4737c478bd9Sstevel@tonic-gate 4747c478bd9Sstevel@tonic-gate switch (intr_op) { 4757c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 4767c478bd9Sstevel@tonic-gate ret = pci_intx_get_cap(rdip, (int *)result); 4777c478bd9Sstevel@tonic-gate break; 4787c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 4797c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n"); 4807c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 4817c478bd9Sstevel@tonic-gate break; 4827c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 4837c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_scratch1; 4847c478bd9Sstevel@tonic-gate break; 4857c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 4867c478bd9Sstevel@tonic-gate break; 4877c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 488a195726fSgovinda *(int *)result = hdlp->ih_pri ? 489614edcaeSEvan Yan hdlp->ih_pri : pci_class_to_pil(rdip); 4907c478bd9Sstevel@tonic-gate break; 4917c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 4927c478bd9Sstevel@tonic-gate break; 4937c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 4947c478bd9Sstevel@tonic-gate ret = px_add_intx_intr(dip, rdip, hdlp); 4957c478bd9Sstevel@tonic-gate break; 4967c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 4977c478bd9Sstevel@tonic-gate ret = px_rem_intx_intr(dip, rdip, hdlp); 4987c478bd9Sstevel@tonic-gate break; 4997c478bd9Sstevel@tonic-gate case DDI_INTROP_ENABLE: 5007c478bd9Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 501b0fc0e77Sgovinda hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_ENABLE, 0, 0); 5027c478bd9Sstevel@tonic-gate break; 5037c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 5047c478bd9Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 505b0fc0e77Sgovinda hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_DISABLE, 0, 0); 5067c478bd9Sstevel@tonic-gate break; 5077c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 5087c478bd9Sstevel@tonic-gate ret = pci_intx_set_mask(rdip); 5097c478bd9Sstevel@tonic-gate break; 5107c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 5117c478bd9Sstevel@tonic-gate ret = pci_intx_clr_mask(rdip); 5127c478bd9Sstevel@tonic-gate break; 5137c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 5147c478bd9Sstevel@tonic-gate ret = pci_intx_get_pending(rdip, (int *)result); 5157c478bd9Sstevel@tonic-gate break; 5167c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 5177c478bd9Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 518a54f81fbSanish *(int *)result = i_ddi_get_intx_nintrs(rdip); 5197c478bd9Sstevel@tonic-gate break; 5207c478bd9Sstevel@tonic-gate default: 5217c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 5227c478bd9Sstevel@tonic-gate break; 5237c478bd9Sstevel@tonic-gate } 5247c478bd9Sstevel@tonic-gate 5257c478bd9Sstevel@tonic-gate return (ret); 5267c478bd9Sstevel@tonic-gate } 5277c478bd9Sstevel@tonic-gate 5287c478bd9Sstevel@tonic-gate /* ARGSUSED */ 5297c478bd9Sstevel@tonic-gate int 5307c478bd9Sstevel@tonic-gate px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 5317c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 5327c478bd9Sstevel@tonic-gate { 5337c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 5347c478bd9Sstevel@tonic-gate px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 5359c75c6bfSgovinda msiq_rec_type_t msiq_rec_type; 5369c75c6bfSgovinda msi_type_t msi_type; 5379c75c6bfSgovinda uint64_t msi_addr; 5387c478bd9Sstevel@tonic-gate msinum_t msi_num; 5397c478bd9Sstevel@tonic-gate msiqid_t msiq_id; 5407c478bd9Sstevel@tonic-gate uint_t nintrs; 5417c478bd9Sstevel@tonic-gate int i, ret = DDI_SUCCESS; 5427c478bd9Sstevel@tonic-gate 5437c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x " 5447c478bd9Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 5457c478bd9Sstevel@tonic-gate 5469c75c6bfSgovinda /* Check for MSI64 support */ 54707f14c08Sgovinda if ((hdlp->ih_cap & DDI_INTR_FLAG_MSI64) && msi_state_p->msi_addr64) { 5489c75c6bfSgovinda msiq_rec_type = MSI64_REC; 5499c75c6bfSgovinda msi_type = MSI64_TYPE; 55007f14c08Sgovinda msi_addr = msi_state_p->msi_addr64; 5519c75c6bfSgovinda } else { 5529c75c6bfSgovinda msiq_rec_type = MSI32_REC; 5539c75c6bfSgovinda msi_type = MSI32_TYPE; 5549c75c6bfSgovinda msi_addr = msi_state_p->msi_addr32; 5559c75c6bfSgovinda } 5569c75c6bfSgovinda 5577c478bd9Sstevel@tonic-gate switch (intr_op) { 5587c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 5597c478bd9Sstevel@tonic-gate ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result); 5607c478bd9Sstevel@tonic-gate break; 5617c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 5627c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: SetCap is not supported\n"); 5637c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 5647c478bd9Sstevel@tonic-gate break; 5657c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 5667c478bd9Sstevel@tonic-gate /* 5677c478bd9Sstevel@tonic-gate * We need to restrict this allocation in future 5687c478bd9Sstevel@tonic-gate * based on Resource Management policies. 5697c478bd9Sstevel@tonic-gate */ 5705febcb4aSScott Carter, SD IOSW if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_type, 5715febcb4aSScott Carter, SD IOSW hdlp->ih_inum, hdlp->ih_scratch1, 5725febcb4aSScott Carter, SD IOSW (uintptr_t)hdlp->ih_scratch2, 57320036fe5Segillett (int *)result)) != DDI_SUCCESS) { 57420036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: allocation " 57520036fe5Segillett "failed, rdip 0x%p type 0x%d inum 0x%x " 57620036fe5Segillett "count 0x%x\n", rdip, hdlp->ih_type, hdlp->ih_inum, 57720036fe5Segillett hdlp->ih_scratch1); 5787c478bd9Sstevel@tonic-gate 5797c478bd9Sstevel@tonic-gate return (ret); 5807c478bd9Sstevel@tonic-gate } 5817c478bd9Sstevel@tonic-gate 58220036fe5Segillett if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && 58320036fe5Segillett (i_ddi_get_msix(rdip) == NULL)) { 58420036fe5Segillett ddi_intr_msix_t *msix_p; 58520036fe5Segillett 58620036fe5Segillett if (msix_p = pci_msix_init(rdip)) { 58720036fe5Segillett i_ddi_set_msix(rdip, msix_p); 58820036fe5Segillett break; 58920036fe5Segillett } 59020036fe5Segillett 59120036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: MSI-X allocation " 59220036fe5Segillett "failed, rdip 0x%p inum 0x%x\n", rdip, 59320036fe5Segillett hdlp->ih_inum); 59420036fe5Segillett 59520036fe5Segillett (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 59620036fe5Segillett hdlp->ih_scratch1); 59720036fe5Segillett 59820036fe5Segillett return (DDI_FAILURE); 59920036fe5Segillett } 60020036fe5Segillett 6017c478bd9Sstevel@tonic-gate break; 6027c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 6037c478bd9Sstevel@tonic-gate (void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum); 60420036fe5Segillett 60520036fe5Segillett if (hdlp->ih_type == DDI_INTR_TYPE_MSI) 60620036fe5Segillett goto msi_free; 60720036fe5Segillett 60820036fe5Segillett if (hdlp->ih_flags & DDI_INTR_MSIX_DUP) 60920036fe5Segillett break; 61020036fe5Segillett 61120036fe5Segillett if (((i_ddi_intr_get_current_nintrs(hdlp->ih_dip) - 1) == 0) && 61220036fe5Segillett (i_ddi_get_msix(rdip))) { 61320036fe5Segillett pci_msix_fini(i_ddi_get_msix(rdip)); 61420036fe5Segillett i_ddi_set_msix(rdip, NULL); 61520036fe5Segillett } 61620036fe5Segillett msi_free: 6177c478bd9Sstevel@tonic-gate (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 6187c478bd9Sstevel@tonic-gate hdlp->ih_scratch1); 6197c478bd9Sstevel@tonic-gate break; 6207c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 6217c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_pri ? 622614edcaeSEvan Yan hdlp->ih_pri : pci_class_to_pil(rdip); 6237c478bd9Sstevel@tonic-gate break; 6247c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 6257c478bd9Sstevel@tonic-gate break; 6267c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 6277c478bd9Sstevel@tonic-gate if ((ret = px_msi_get_msinum(px_p, hdlp->ih_dip, 6287c478bd9Sstevel@tonic-gate hdlp->ih_inum, &msi_num)) != DDI_SUCCESS) 6297c478bd9Sstevel@tonic-gate return (ret); 6307c478bd9Sstevel@tonic-gate 6317c478bd9Sstevel@tonic-gate if ((ret = px_add_msiq_intr(dip, rdip, hdlp, 6329c75c6bfSgovinda msiq_rec_type, msi_num, &msiq_id)) != DDI_SUCCESS) { 6337c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler " 6347c478bd9Sstevel@tonic-gate "failed, rdip 0x%p msi 0x%x\n", rdip, msi_num); 6357c478bd9Sstevel@tonic-gate return (ret); 6367c478bd9Sstevel@tonic-gate } 6377c478bd9Sstevel@tonic-gate 6387c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id); 6397c478bd9Sstevel@tonic-gate 6407c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setmsiq(dip, msi_num, 6419c75c6bfSgovinda msiq_id, msi_type)) != DDI_SUCCESS) { 6427c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 6439c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 6447c478bd9Sstevel@tonic-gate return (ret); 6457c478bd9Sstevel@tonic-gate } 6467c478bd9Sstevel@tonic-gate 6477c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 6487c478bd9Sstevel@tonic-gate PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) { 6497c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 6509c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 6517c478bd9Sstevel@tonic-gate return (ret); 6527c478bd9Sstevel@tonic-gate } 6537c478bd9Sstevel@tonic-gate 6547c478bd9Sstevel@tonic-gate hdlp->ih_vector = msi_num; 6557c478bd9Sstevel@tonic-gate break; 6567c478bd9Sstevel@tonic-gate case DDI_INTROP_DUPVEC: 65720036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: dupisr - inum: %x, " 65820036fe5Segillett "new_vector: %x\n", hdlp->ih_inum, hdlp->ih_scratch1); 65920036fe5Segillett 66020036fe5Segillett ret = pci_msix_dup(hdlp->ih_dip, hdlp->ih_inum, 66120036fe5Segillett hdlp->ih_scratch1); 6627c478bd9Sstevel@tonic-gate break; 6637c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 6647c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 6657c478bd9Sstevel@tonic-gate 6667c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_getmsiq(dip, msi_num, 6677c478bd9Sstevel@tonic-gate &msiq_id)) != DDI_SUCCESS) 6687c478bd9Sstevel@tonic-gate return (ret); 6697c478bd9Sstevel@tonic-gate 6707c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 6719c75c6bfSgovinda PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) 6727c478bd9Sstevel@tonic-gate return (ret); 6737c478bd9Sstevel@tonic-gate 6747c478bd9Sstevel@tonic-gate ret = px_rem_msiq_intr(dip, rdip, 6759c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 6767c478bd9Sstevel@tonic-gate 6777c478bd9Sstevel@tonic-gate hdlp->ih_vector = 0; 6787c478bd9Sstevel@tonic-gate break; 6797c478bd9Sstevel@tonic-gate case DDI_INTROP_ENABLE: 6807c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 6817c478bd9Sstevel@tonic-gate 6827c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 6837c478bd9Sstevel@tonic-gate PCI_MSI_VALID)) != DDI_SUCCESS) 6847c478bd9Sstevel@tonic-gate return (ret); 6857c478bd9Sstevel@tonic-gate 68695003185Segillett if ((pci_is_msi_enabled(rdip, hdlp->ih_type) != DDI_SUCCESS) || 68795003185Segillett (hdlp->ih_type == DDI_INTR_TYPE_MSIX)) { 6887c478bd9Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 6897c478bd9Sstevel@tonic-gate 6907c478bd9Sstevel@tonic-gate if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 6919c75c6bfSgovinda nintrs, hdlp->ih_inum, msi_addr, 69295003185Segillett hdlp->ih_type == DDI_INTR_TYPE_MSIX ? 69395003185Segillett msi_num : msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 6947c478bd9Sstevel@tonic-gate return (ret); 6957c478bd9Sstevel@tonic-gate 69695003185Segillett if ((ret = pci_msi_enable_mode(rdip, hdlp->ih_type)) 69795003185Segillett != DDI_SUCCESS) 6987c478bd9Sstevel@tonic-gate return (ret); 6997c478bd9Sstevel@tonic-gate } 7007c478bd9Sstevel@tonic-gate 70136fe4a92Segillett if ((ret = pci_msi_clr_mask(rdip, hdlp->ih_type, 70236fe4a92Segillett hdlp->ih_inum)) != DDI_SUCCESS) 70336fe4a92Segillett return (ret); 70436fe4a92Segillett 70520036fe5Segillett if (hdlp->ih_flags & DDI_INTR_MSIX_DUP) 70620036fe5Segillett break; 70720036fe5Segillett 70836fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 70936fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 71036fe4a92Segillett return (ret); 71136fe4a92Segillett 71236fe4a92Segillett ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 713b0fc0e77Sgovinda px_msiqid_to_devino(px_p, msiq_id), hdlp->ih_pri, 714b0fc0e77Sgovinda PX_INTR_STATE_ENABLE, msiq_rec_type, msi_num); 7157c478bd9Sstevel@tonic-gate 7167c478bd9Sstevel@tonic-gate break; 7177c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 7187c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 7197c478bd9Sstevel@tonic-gate 7202145b8d4SGuoli Shu if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type, 7212145b8d4SGuoli Shu hdlp->ih_cap & DDI_INTR_FLAG_BLOCK)) != DDI_SUCCESS) 7222145b8d4SGuoli Shu return (ret); 7232145b8d4SGuoli Shu 7247c478bd9Sstevel@tonic-gate if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type, 7257c478bd9Sstevel@tonic-gate hdlp->ih_inum)) != DDI_SUCCESS) 7267c478bd9Sstevel@tonic-gate return (ret); 7277c478bd9Sstevel@tonic-gate 72836fe4a92Segillett if ((ret = px_lib_msi_setvalid(dip, msi_num, 72936fe4a92Segillett PCI_MSI_INVALID)) != DDI_SUCCESS) 73036fe4a92Segillett return (ret); 73136fe4a92Segillett 73220036fe5Segillett if (hdlp->ih_flags & DDI_INTR_MSIX_DUP) 73320036fe5Segillett break; 73420036fe5Segillett 73536fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 73636fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 73736fe4a92Segillett return (ret); 73836fe4a92Segillett 73936fe4a92Segillett ret = px_ib_update_intr_state(px_p, rdip, 74036fe4a92Segillett hdlp->ih_inum, px_msiqid_to_devino(px_p, msiq_id), 741b0fc0e77Sgovinda hdlp->ih_pri, PX_INTR_STATE_DISABLE, msiq_rec_type, 742b0fc0e77Sgovinda msi_num); 74336fe4a92Segillett 7447c478bd9Sstevel@tonic-gate break; 7457c478bd9Sstevel@tonic-gate case DDI_INTROP_BLOCKENABLE: 7467c478bd9Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 7477c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 7509c75c6bfSgovinda nintrs, hdlp->ih_inum, msi_addr, 7517c478bd9Sstevel@tonic-gate msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 7527c478bd9Sstevel@tonic-gate return (ret); 7537c478bd9Sstevel@tonic-gate 7547c478bd9Sstevel@tonic-gate for (i = 0; i < nintrs; i++, msi_num++) { 7557c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 7567c478bd9Sstevel@tonic-gate PCI_MSI_VALID)) != DDI_SUCCESS) 7577c478bd9Sstevel@tonic-gate return (ret); 75836fe4a92Segillett 75936fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 76036fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 76136fe4a92Segillett return (ret); 76236fe4a92Segillett 76336fe4a92Segillett if ((ret = px_ib_update_intr_state(px_p, rdip, 76436fe4a92Segillett hdlp->ih_inum + i, px_msiqid_to_devino(px_p, 765b0fc0e77Sgovinda msiq_id), hdlp->ih_pri, PX_INTR_STATE_ENABLE, 766b0fc0e77Sgovinda msiq_rec_type, msi_num)) != DDI_SUCCESS) 76736fe4a92Segillett return (ret); 7687c478bd9Sstevel@tonic-gate } 7697c478bd9Sstevel@tonic-gate 77095003185Segillett ret = pci_msi_enable_mode(rdip, hdlp->ih_type); 7717c478bd9Sstevel@tonic-gate break; 7727c478bd9Sstevel@tonic-gate case DDI_INTROP_BLOCKDISABLE: 7737c478bd9Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 7747c478bd9Sstevel@tonic-gate msi_num = hdlp->ih_vector; 7757c478bd9Sstevel@tonic-gate 7767c478bd9Sstevel@tonic-gate if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type, 77795003185Segillett hdlp->ih_cap & DDI_INTR_FLAG_BLOCK)) != DDI_SUCCESS) 7787c478bd9Sstevel@tonic-gate return (ret); 7797c478bd9Sstevel@tonic-gate 7807c478bd9Sstevel@tonic-gate for (i = 0; i < nintrs; i++, msi_num++) { 7817c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 7827c478bd9Sstevel@tonic-gate PCI_MSI_INVALID)) != DDI_SUCCESS) 7837c478bd9Sstevel@tonic-gate return (ret); 78436fe4a92Segillett 78536fe4a92Segillett if ((ret = px_lib_msi_getmsiq(dip, msi_num, 78636fe4a92Segillett &msiq_id)) != DDI_SUCCESS) 78736fe4a92Segillett return (ret); 78836fe4a92Segillett 78936fe4a92Segillett if ((ret = px_ib_update_intr_state(px_p, rdip, 79036fe4a92Segillett hdlp->ih_inum + i, px_msiqid_to_devino(px_p, 791b0fc0e77Sgovinda msiq_id), hdlp->ih_pri, PX_INTR_STATE_DISABLE, 792b0fc0e77Sgovinda msiq_rec_type, msi_num)) != DDI_SUCCESS) 79336fe4a92Segillett return (ret); 7947c478bd9Sstevel@tonic-gate } 7957c478bd9Sstevel@tonic-gate 7967c478bd9Sstevel@tonic-gate break; 7977c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 7987c478bd9Sstevel@tonic-gate ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 7997c478bd9Sstevel@tonic-gate break; 8007c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 8017c478bd9Sstevel@tonic-gate ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 8027c478bd9Sstevel@tonic-gate break; 8037c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 8047c478bd9Sstevel@tonic-gate ret = pci_msi_get_pending(rdip, hdlp->ih_type, 8057c478bd9Sstevel@tonic-gate hdlp->ih_inum, (int *)result); 8067c478bd9Sstevel@tonic-gate break; 8077c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 8087c478bd9Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 8097c478bd9Sstevel@tonic-gate break; 8107c478bd9Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 8117c478bd9Sstevel@tonic-gate /* XXX - a new interface may be needed */ 8127c478bd9Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 8137c478bd9Sstevel@tonic-gate break; 8145febcb4aSScott Carter, SD IOSW case DDI_INTROP_GETPOOL: 8155febcb4aSScott Carter, SD IOSW if (msi_state_p->msi_pool_p == NULL) { 8165febcb4aSScott Carter, SD IOSW *(ddi_irm_pool_t **)result = NULL; 8175febcb4aSScott Carter, SD IOSW return (DDI_ENOTSUP); 8185febcb4aSScott Carter, SD IOSW } 8195febcb4aSScott Carter, SD IOSW *(ddi_irm_pool_t **)result = msi_state_p->msi_pool_p; 8205febcb4aSScott Carter, SD IOSW ret = DDI_SUCCESS; 8215febcb4aSScott Carter, SD IOSW break; 8227c478bd9Sstevel@tonic-gate default: 8237c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 8247c478bd9Sstevel@tonic-gate break; 8257c478bd9Sstevel@tonic-gate } 8267c478bd9Sstevel@tonic-gate 8277c478bd9Sstevel@tonic-gate return (ret); 8287c478bd9Sstevel@tonic-gate } 8297c478bd9Sstevel@tonic-gate 8306d44af1bSesolom static struct { 8316d44af1bSesolom kstat_named_t pxintr_ks_name; 8326d44af1bSesolom kstat_named_t pxintr_ks_type; 8336d44af1bSesolom kstat_named_t pxintr_ks_cpu; 8346d44af1bSesolom kstat_named_t pxintr_ks_pil; 8356d44af1bSesolom kstat_named_t pxintr_ks_time; 8366d44af1bSesolom kstat_named_t pxintr_ks_ino; 8376d44af1bSesolom kstat_named_t pxintr_ks_cookie; 8386d44af1bSesolom kstat_named_t pxintr_ks_devpath; 8396d44af1bSesolom kstat_named_t pxintr_ks_buspath; 8406d44af1bSesolom } pxintr_ks_template = { 8416d44af1bSesolom { "name", KSTAT_DATA_CHAR }, 8426d44af1bSesolom { "type", KSTAT_DATA_CHAR }, 8436d44af1bSesolom { "cpu", KSTAT_DATA_UINT64 }, 8446d44af1bSesolom { "pil", KSTAT_DATA_UINT64 }, 8456d44af1bSesolom { "time", KSTAT_DATA_UINT64 }, 8466d44af1bSesolom { "ino", KSTAT_DATA_UINT64 }, 8476d44af1bSesolom { "cookie", KSTAT_DATA_UINT64 }, 8486d44af1bSesolom { "devpath", KSTAT_DATA_STRING }, 8496d44af1bSesolom { "buspath", KSTAT_DATA_STRING }, 8506d44af1bSesolom }; 8516d44af1bSesolom 8526d44af1bSesolom static uint32_t pxintr_ks_instance; 853d48713b8Sesolom static char ih_devpath[MAXPATHLEN]; 854d48713b8Sesolom static char ih_buspath[MAXPATHLEN]; 8556d44af1bSesolom kmutex_t pxintr_ks_template_lock; 8566d44af1bSesolom 8576d44af1bSesolom int 8586d44af1bSesolom px_ks_update(kstat_t *ksp, int rw) 8596d44af1bSesolom { 8606d44af1bSesolom px_ih_t *ih_p = ksp->ks_private; 8616d44af1bSesolom int maxlen = sizeof (pxintr_ks_template.pxintr_ks_name.value.c); 862b0fc0e77Sgovinda px_ino_pil_t *ipil_p = ih_p->ih_ipil_p; 863b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 864b0fc0e77Sgovinda px_t *px_p = ino_p->ino_ib_p->ib_px_p; 8656d44af1bSesolom devino_t ino; 8666d44af1bSesolom sysino_t sysino; 8676d44af1bSesolom 868b0fc0e77Sgovinda ino = ino_p->ino_ino; 869d8d130aeSanbui if (px_lib_intr_devino_to_sysino(px_p->px_dip, ino, &sysino) != 870d8d130aeSanbui DDI_SUCCESS) { 871d8d130aeSanbui cmn_err(CE_WARN, "px_ks_update: px_lib_intr_devino_to_sysino " 872d8d130aeSanbui "failed"); 873d8d130aeSanbui } 8746d44af1bSesolom 8756d44af1bSesolom (void) snprintf(pxintr_ks_template.pxintr_ks_name.value.c, maxlen, 8766d44af1bSesolom "%s%d", ddi_driver_name(ih_p->ih_dip), 8776d44af1bSesolom ddi_get_instance(ih_p->ih_dip)); 8786d44af1bSesolom 8796d44af1bSesolom (void) ddi_pathname(ih_p->ih_dip, ih_devpath); 8806d44af1bSesolom (void) ddi_pathname(px_p->px_dip, ih_buspath); 8816d44af1bSesolom kstat_named_setstr(&pxintr_ks_template.pxintr_ks_devpath, ih_devpath); 8826d44af1bSesolom kstat_named_setstr(&pxintr_ks_template.pxintr_ks_buspath, ih_buspath); 8836d44af1bSesolom 884e1d9f4e6Sschwartz if (ih_p->ih_intr_state == PX_INTR_STATE_ENABLE) { 885e1d9f4e6Sschwartz 8862917a9c9Sschwartz switch (i_ddi_intr_get_current_type(ih_p->ih_dip)) { 8872917a9c9Sschwartz case DDI_INTR_TYPE_MSI: 8882917a9c9Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 8892917a9c9Sschwartz "msi"); 8902917a9c9Sschwartz break; 8912917a9c9Sschwartz case DDI_INTR_TYPE_MSIX: 8922917a9c9Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 8932917a9c9Sschwartz "msix"); 8942917a9c9Sschwartz break; 8952917a9c9Sschwartz default: 8962917a9c9Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 8972917a9c9Sschwartz "fixed"); 8982917a9c9Sschwartz break; 8992917a9c9Sschwartz } 9002917a9c9Sschwartz 901b0fc0e77Sgovinda pxintr_ks_template.pxintr_ks_cpu.value.ui64 = ino_p->ino_cpuid; 902b0fc0e77Sgovinda pxintr_ks_template.pxintr_ks_pil.value.ui64 = ipil_p->ipil_pil; 903e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_time.value.ui64 = ih_p->ih_nsec + 904e1d9f4e6Sschwartz (uint64_t)tick2ns((hrtime_t)ih_p->ih_ticks, 905b0fc0e77Sgovinda ino_p->ino_cpuid); 906e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_ino.value.ui64 = ino; 907e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cookie.value.ui64 = sysino; 908e1d9f4e6Sschwartz } else { 909e1d9f4e6Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 910e1d9f4e6Sschwartz "disabled"); 911e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cpu.value.ui64 = 0; 912e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_pil.value.ui64 = 0; 913e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_time.value.ui64 = 0; 914e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_ino.value.ui64 = 0; 915e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cookie.value.ui64 = 0; 916e1d9f4e6Sschwartz } 9176d44af1bSesolom return (0); 9186d44af1bSesolom } 9196d44af1bSesolom 9206d44af1bSesolom void 9216d44af1bSesolom px_create_intr_kstats(px_ih_t *ih_p) 9226d44af1bSesolom { 9236d44af1bSesolom msiq_rec_type_t rec_type = ih_p->ih_rec_type; 9246d44af1bSesolom 9256d44af1bSesolom ASSERT(ih_p->ih_ksp == NULL); 9266d44af1bSesolom 9276d44af1bSesolom /* 9286d44af1bSesolom * Create pci_intrs::: kstats for all ih types except messages, 9296d44af1bSesolom * which represent unusual conditions and don't need to be tracked. 9306d44af1bSesolom */ 9316d44af1bSesolom if (rec_type == 0 || rec_type == MSI32_REC || rec_type == MSI64_REC) { 9326d44af1bSesolom ih_p->ih_ksp = kstat_create("pci_intrs", 9336d44af1bSesolom atomic_inc_32_nv(&pxintr_ks_instance), "config", 9346d44af1bSesolom "interrupts", KSTAT_TYPE_NAMED, 9356d44af1bSesolom sizeof (pxintr_ks_template) / sizeof (kstat_named_t), 9366d44af1bSesolom KSTAT_FLAG_VIRTUAL); 9376d44af1bSesolom } 9386d44af1bSesolom if (ih_p->ih_ksp != NULL) { 9396d44af1bSesolom ih_p->ih_ksp->ks_data_size += MAXPATHLEN * 2; 9406d44af1bSesolom ih_p->ih_ksp->ks_lock = &pxintr_ks_template_lock; 9416d44af1bSesolom ih_p->ih_ksp->ks_data = &pxintr_ks_template; 9426d44af1bSesolom ih_p->ih_ksp->ks_private = ih_p; 9436d44af1bSesolom ih_p->ih_ksp->ks_update = px_ks_update; 9446d44af1bSesolom } 9456d44af1bSesolom } 9466d44af1bSesolom 947a195726fSgovinda /* 948a195726fSgovinda * px_add_intx_intr: 949a195726fSgovinda * 950a195726fSgovinda * This function is called to register INTx and legacy hardware 951a195726fSgovinda * interrupt pins interrupts. 952a195726fSgovinda */ 9537c478bd9Sstevel@tonic-gate int 9547c478bd9Sstevel@tonic-gate px_add_intx_intr(dev_info_t *dip, dev_info_t *rdip, 9557c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 9567c478bd9Sstevel@tonic-gate { 9577c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 9587c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 9597c478bd9Sstevel@tonic-gate devino_t ino; 9607c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 961b0fc0e77Sgovinda px_ino_t *ino_p; 962b0fc0e77Sgovinda px_ino_pil_t *ipil_p, *ipil_list; 9637c478bd9Sstevel@tonic-gate int32_t weight; 9647c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 9657c478bd9Sstevel@tonic-gate 9667c478bd9Sstevel@tonic-gate ino = hdlp->ih_vector; 9677c478bd9Sstevel@tonic-gate 9687c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: rdip=%s%d ino=%x " 9697c478bd9Sstevel@tonic-gate "handler=%x arg1=%x arg2=%x\n", ddi_driver_name(rdip), 9707c478bd9Sstevel@tonic-gate ddi_get_instance(rdip), ino, hdlp->ih_cb_func, 9717c478bd9Sstevel@tonic-gate hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 9727c478bd9Sstevel@tonic-gate 9737c478bd9Sstevel@tonic-gate ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, 9747c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0); 9757c478bd9Sstevel@tonic-gate 9767c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 9777c478bd9Sstevel@tonic-gate 978b0fc0e77Sgovinda ino_p = px_ib_locate_ino(ib_p, ino); 979b0fc0e77Sgovinda ipil_list = ino_p ? ino_p->ino_ipil_p : NULL; 980b0fc0e77Sgovinda 981b0fc0e77Sgovinda /* Sharing ino */ 982b0fc0e77Sgovinda if (ino_p && (ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) { 983b0fc0e77Sgovinda if (px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, 0, 0)) { 9847c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: " 985b0fc0e77Sgovinda "dup intr #%d\n", hdlp->ih_inum); 9867c478bd9Sstevel@tonic-gate 9877c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 9887c478bd9Sstevel@tonic-gate goto fail1; 9897c478bd9Sstevel@tonic-gate } 9907c478bd9Sstevel@tonic-gate 9917c478bd9Sstevel@tonic-gate /* Save mondo value in hdlp */ 9927c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 9937c478bd9Sstevel@tonic-gate 994b0fc0e77Sgovinda if ((ret = px_ib_ino_add_intr(px_p, ipil_p, 995b0fc0e77Sgovinda ih_p)) != DDI_SUCCESS) 9967c478bd9Sstevel@tonic-gate goto fail1; 9977c478bd9Sstevel@tonic-gate 998b0fc0e77Sgovinda goto ino_done; 999b0fc0e77Sgovinda } 10007c478bd9Sstevel@tonic-gate 1001b0fc0e77Sgovinda if (hdlp->ih_pri == 0) 1002614edcaeSEvan Yan hdlp->ih_pri = pci_class_to_pil(rdip); 10037c478bd9Sstevel@tonic-gate 1004b0fc0e77Sgovinda ipil_p = px_ib_new_ino_pil(ib_p, ino, hdlp->ih_pri, ih_p); 1005b0fc0e77Sgovinda ino_p = ipil_p->ipil_ino_p; 10067c478bd9Sstevel@tonic-gate 1007b0fc0e77Sgovinda /* Save mondo value in hdlp */ 1008b0fc0e77Sgovinda hdlp->ih_vector = ino_p->ino_sysino; 10097c478bd9Sstevel@tonic-gate 1010b0fc0e77Sgovinda DBG(DBG_A_INTX, dip, "px_add_intx_intr: pil=0x%x mondo=0x%x\n", 1011b0fc0e77Sgovinda hdlp->ih_pri, hdlp->ih_vector); 10127c478bd9Sstevel@tonic-gate 1013b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 1014b0fc0e77Sgovinda (ddi_intr_handler_t *)px_intx_intr, (caddr_t)ipil_p, NULL); 1015b0fc0e77Sgovinda 1016b0fc0e77Sgovinda ret = i_ddi_add_ivintr(hdlp); 10177c478bd9Sstevel@tonic-gate 1018b0fc0e77Sgovinda /* 1019b0fc0e77Sgovinda * Restore original interrupt handler 1020b0fc0e77Sgovinda * and arguments in interrupt handle. 1021b0fc0e77Sgovinda */ 1022b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1023b0fc0e77Sgovinda ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 10247c478bd9Sstevel@tonic-gate 1025b0fc0e77Sgovinda if (ret != DDI_SUCCESS) 1026b0fc0e77Sgovinda goto fail2; 10277c478bd9Sstevel@tonic-gate 1028b0fc0e77Sgovinda /* Save the pil for this ino */ 1029b0fc0e77Sgovinda ipil_p->ipil_pil = hdlp->ih_pri; 1030b0fc0e77Sgovinda 1031b0fc0e77Sgovinda /* Select cpu, saving it for sharing and removal */ 1032b0fc0e77Sgovinda if (ipil_list == NULL) { 10337c478bd9Sstevel@tonic-gate ino_p->ino_cpuid = intr_dist_cpuid(); 10347c478bd9Sstevel@tonic-gate 10357c478bd9Sstevel@tonic-gate /* Enable interrupt */ 10367c478bd9Sstevel@tonic-gate px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 10377c478bd9Sstevel@tonic-gate } 10387c478bd9Sstevel@tonic-gate 1039b0fc0e77Sgovinda ino_done: 1040b0fc0e77Sgovinda /* Add weight to the cpu that we are already targeting */ 1041614edcaeSEvan Yan weight = pci_class_to_intr_weight(rdip); 10427c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 10437c478bd9Sstevel@tonic-gate 1044b0fc0e77Sgovinda ih_p->ih_ipil_p = ipil_p; 10456d44af1bSesolom px_create_intr_kstats(ih_p); 10467c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp) 10477c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 10487c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 10497c478bd9Sstevel@tonic-gate 10507c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: done! Interrupt 0x%x pil=%x\n", 10517c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 10527c478bd9Sstevel@tonic-gate 10537c478bd9Sstevel@tonic-gate return (ret); 10547c478bd9Sstevel@tonic-gate fail2: 1055b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 10567c478bd9Sstevel@tonic-gate fail1: 10577c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 10587c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 10597c478bd9Sstevel@tonic-gate 10607c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 10617c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 10627c478bd9Sstevel@tonic-gate 10637c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: Failed! Interrupt 0x%x " 10647c478bd9Sstevel@tonic-gate "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri); 10657c478bd9Sstevel@tonic-gate 10667c478bd9Sstevel@tonic-gate return (ret); 10677c478bd9Sstevel@tonic-gate } 10687c478bd9Sstevel@tonic-gate 1069a195726fSgovinda /* 1070a195726fSgovinda * px_rem_intx_intr: 1071a195726fSgovinda * 1072a195726fSgovinda * This function is called to unregister INTx and legacy hardware 1073a195726fSgovinda * interrupt pins interrupts. 1074a195726fSgovinda */ 10757c478bd9Sstevel@tonic-gate int 10767c478bd9Sstevel@tonic-gate px_rem_intx_intr(dev_info_t *dip, dev_info_t *rdip, 10777c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 10787c478bd9Sstevel@tonic-gate { 10797c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 10807c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 10817c478bd9Sstevel@tonic-gate devino_t ino; 10827c478bd9Sstevel@tonic-gate cpuid_t curr_cpu; 1083b0fc0e77Sgovinda px_ino_t *ino_p; 1084b0fc0e77Sgovinda px_ino_pil_t *ipil_p; 10857c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 10867c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 10877c478bd9Sstevel@tonic-gate 10887c478bd9Sstevel@tonic-gate ino = hdlp->ih_vector; 10897c478bd9Sstevel@tonic-gate 10907c478bd9Sstevel@tonic-gate DBG(DBG_R_INTX, dip, "px_rem_intx_intr: rdip=%s%d ino=%x\n", 10917c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 10927c478bd9Sstevel@tonic-gate 10937c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 10947c478bd9Sstevel@tonic-gate 10957c478bd9Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 1096b0fc0e77Sgovinda ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri); 1097b0fc0e77Sgovinda ih_p = px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, 0, 0); 10987c478bd9Sstevel@tonic-gate 10997c478bd9Sstevel@tonic-gate /* Get the current cpu */ 11007c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 11017c478bd9Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 11027c478bd9Sstevel@tonic-gate goto fail; 11037c478bd9Sstevel@tonic-gate 1104b0fc0e77Sgovinda if ((ret = px_ib_ino_rem_intr(px_p, ipil_p, ih_p)) != DDI_SUCCESS) 11057c478bd9Sstevel@tonic-gate goto fail; 11067c478bd9Sstevel@tonic-gate 11077c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 11087c478bd9Sstevel@tonic-gate 1109b0fc0e77Sgovinda if (ipil_p->ipil_ih_size == 0) { 11107c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 11117c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 11127c478bd9Sstevel@tonic-gate 1113b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 1114b0fc0e77Sgovinda } 1115b0fc0e77Sgovinda 1116b0fc0e77Sgovinda if (ino_p->ino_ipil_size == 0) { 1117b0fc0e77Sgovinda kmem_free(ino_p, sizeof (px_ino_t)); 11187c478bd9Sstevel@tonic-gate } else { 11190d2a6fcfSegillett /* Re-enable interrupt only if mapping register still shared */ 11200d2a6fcfSegillett PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 11217c478bd9Sstevel@tonic-gate } 11227c478bd9Sstevel@tonic-gate 11237c478bd9Sstevel@tonic-gate fail: 11247c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 11257c478bd9Sstevel@tonic-gate return (ret); 11267c478bd9Sstevel@tonic-gate } 11277c478bd9Sstevel@tonic-gate 1128a195726fSgovinda /* 1129a195726fSgovinda * px_add_msiq_intr: 1130a195726fSgovinda * 1131a195726fSgovinda * This function is called to register MSI/Xs and PCIe message interrupts. 1132a195726fSgovinda */ 11337c478bd9Sstevel@tonic-gate int 11347c478bd9Sstevel@tonic-gate px_add_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 11357c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 11367c478bd9Sstevel@tonic-gate msgcode_t msg_code, msiqid_t *msiq_id_p) 11377c478bd9Sstevel@tonic-gate { 11387c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 11397c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 11407c478bd9Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &ib_p->ib_msiq_state; 11417c478bd9Sstevel@tonic-gate devino_t ino; 11427c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 1143b0fc0e77Sgovinda px_ino_t *ino_p; 1144b0fc0e77Sgovinda px_ino_pil_t *ipil_p, *ipil_list; 11457c478bd9Sstevel@tonic-gate int32_t weight; 11467c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 11477c478bd9Sstevel@tonic-gate 11487c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=%x " 11497c478bd9Sstevel@tonic-gate "arg1=%x arg2=%x\n", ddi_driver_name(rdip), ddi_get_instance(rdip), 11507c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 11517c478bd9Sstevel@tonic-gate 11527c478bd9Sstevel@tonic-gate if ((ret = px_msiq_alloc(px_p, rec_type, msiq_id_p)) != DDI_SUCCESS) { 11537c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 11547c478bd9Sstevel@tonic-gate "msiq allocation failed\n"); 11557c478bd9Sstevel@tonic-gate return (ret); 11567c478bd9Sstevel@tonic-gate } 11577c478bd9Sstevel@tonic-gate 11587c478bd9Sstevel@tonic-gate ino = px_msiqid_to_devino(px_p, *msiq_id_p); 11597c478bd9Sstevel@tonic-gate 11607c478bd9Sstevel@tonic-gate ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func, 11617c478bd9Sstevel@tonic-gate hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code); 11627c478bd9Sstevel@tonic-gate 11637c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 11647c478bd9Sstevel@tonic-gate 1165b0fc0e77Sgovinda ino_p = px_ib_locate_ino(ib_p, ino); 1166b0fc0e77Sgovinda ipil_list = ino_p ? ino_p->ino_ipil_p : NULL; 1167b0fc0e77Sgovinda 1168b0fc0e77Sgovinda /* Sharing ino */ 1169b0fc0e77Sgovinda if (ino_p && (ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) { 1170b0fc0e77Sgovinda if (px_ib_intr_locate_ih(ipil_p, rdip, 1171b0fc0e77Sgovinda hdlp->ih_inum, rec_type, msg_code)) { 11727c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 1173b0fc0e77Sgovinda "dup intr #%d\n", hdlp->ih_inum); 11747c478bd9Sstevel@tonic-gate 11757c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 11767c478bd9Sstevel@tonic-gate goto fail1; 11777c478bd9Sstevel@tonic-gate } 11787c478bd9Sstevel@tonic-gate 1179b0fc0e77Sgovinda /* Save mondo value in hdlp */ 1180b0fc0e77Sgovinda hdlp->ih_vector = ino_p->ino_sysino; 1181b0fc0e77Sgovinda 1182b0fc0e77Sgovinda if ((ret = px_ib_ino_add_intr(px_p, ipil_p, 1183b0fc0e77Sgovinda ih_p)) != DDI_SUCCESS) 11847c478bd9Sstevel@tonic-gate goto fail1; 11857c478bd9Sstevel@tonic-gate 1186b0fc0e77Sgovinda goto ino_done; 1187b0fc0e77Sgovinda } 11887c478bd9Sstevel@tonic-gate 1189b0fc0e77Sgovinda if (hdlp->ih_pri == 0) 1190614edcaeSEvan Yan hdlp->ih_pri = pci_class_to_pil(rdip); 11917c478bd9Sstevel@tonic-gate 1192b0fc0e77Sgovinda ipil_p = px_ib_new_ino_pil(ib_p, ino, hdlp->ih_pri, ih_p); 1193b0fc0e77Sgovinda ino_p = ipil_p->ipil_ino_p; 11947c478bd9Sstevel@tonic-gate 1195b0fc0e77Sgovinda ino_p->ino_msiq_p = msiq_state_p->msiq_p + 1196b0fc0e77Sgovinda (*msiq_id_p - msiq_state_p->msiq_1st_msiq_id); 11977c478bd9Sstevel@tonic-gate 1198b0fc0e77Sgovinda /* Save mondo value in hdlp */ 1199b0fc0e77Sgovinda hdlp->ih_vector = ino_p->ino_sysino; 12007c478bd9Sstevel@tonic-gate 1201b0fc0e77Sgovinda DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n", 1202b0fc0e77Sgovinda hdlp->ih_pri, hdlp->ih_vector); 12037c478bd9Sstevel@tonic-gate 1204b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 1205b0fc0e77Sgovinda (ddi_intr_handler_t *)px_msiq_intr, (caddr_t)ipil_p, NULL); 1206b0fc0e77Sgovinda 1207b0fc0e77Sgovinda ret = i_ddi_add_ivintr(hdlp); 1208b0fc0e77Sgovinda 1209b0fc0e77Sgovinda /* 1210b0fc0e77Sgovinda * Restore original interrupt handler 1211b0fc0e77Sgovinda * and arguments in interrupt handle. 1212b0fc0e77Sgovinda */ 1213b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1214b0fc0e77Sgovinda ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 12157c478bd9Sstevel@tonic-gate 1216b0fc0e77Sgovinda if (ret != DDI_SUCCESS) 1217b0fc0e77Sgovinda goto fail2; 12187c478bd9Sstevel@tonic-gate 1219b0fc0e77Sgovinda /* Save the pil for this ino */ 1220b0fc0e77Sgovinda ipil_p->ipil_pil = hdlp->ih_pri; 1221b0fc0e77Sgovinda 1222b0fc0e77Sgovinda /* Select cpu, saving it for sharing and removal */ 1223b0fc0e77Sgovinda if (ipil_list == NULL) { 1224b0fc0e77Sgovinda ino_p->ino_cpuid = intr_dist_cpuid(); 12257c478bd9Sstevel@tonic-gate 12267c478bd9Sstevel@tonic-gate /* Enable MSIQ */ 12277c478bd9Sstevel@tonic-gate px_lib_msiq_setstate(dip, *msiq_id_p, PCI_MSIQ_STATE_IDLE); 12287c478bd9Sstevel@tonic-gate px_lib_msiq_setvalid(dip, *msiq_id_p, PCI_MSIQ_VALID); 12297c478bd9Sstevel@tonic-gate 12307c478bd9Sstevel@tonic-gate /* Enable interrupt */ 1231b0fc0e77Sgovinda px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 12327c478bd9Sstevel@tonic-gate } 12337c478bd9Sstevel@tonic-gate 1234b0fc0e77Sgovinda ino_done: 1235b0fc0e77Sgovinda /* Add weight to the cpu that we are already targeting */ 1236614edcaeSEvan Yan weight = pci_class_to_intr_weight(rdip); 12377c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 12387c478bd9Sstevel@tonic-gate 1239b0fc0e77Sgovinda ih_p->ih_ipil_p = ipil_p; 12406d44af1bSesolom px_create_intr_kstats(ih_p); 12417c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp) 12427c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 12437c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 12447c478bd9Sstevel@tonic-gate 12457c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n", 12467c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 12477c478bd9Sstevel@tonic-gate 12487c478bd9Sstevel@tonic-gate return (ret); 12497c478bd9Sstevel@tonic-gate fail2: 1250b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 12517c478bd9Sstevel@tonic-gate fail1: 12527c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 12537c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 12547c478bd9Sstevel@tonic-gate 12557c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 12567c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 12577c478bd9Sstevel@tonic-gate 12587c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n", 12597c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 12607c478bd9Sstevel@tonic-gate 12617c478bd9Sstevel@tonic-gate return (ret); 12627c478bd9Sstevel@tonic-gate } 12637c478bd9Sstevel@tonic-gate 1264a195726fSgovinda /* 1265a195726fSgovinda * px_rem_msiq_intr: 1266a195726fSgovinda * 1267a195726fSgovinda * This function is called to unregister MSI/Xs and PCIe message interrupts. 1268a195726fSgovinda */ 12697c478bd9Sstevel@tonic-gate int 12707c478bd9Sstevel@tonic-gate px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 12717c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 12727c478bd9Sstevel@tonic-gate msgcode_t msg_code, msiqid_t msiq_id) 12737c478bd9Sstevel@tonic-gate { 12747c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 12757c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 12767c478bd9Sstevel@tonic-gate devino_t ino = px_msiqid_to_devino(px_p, msiq_id); 12777c478bd9Sstevel@tonic-gate cpuid_t curr_cpu; 1278b0fc0e77Sgovinda px_ino_t *ino_p; 1279b0fc0e77Sgovinda px_ino_pil_t *ipil_p; 12807c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 12817c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 12827c478bd9Sstevel@tonic-gate 12837c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n", 12847c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), msiq_id, ino); 12857c478bd9Sstevel@tonic-gate 12867c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 12877c478bd9Sstevel@tonic-gate 12887c478bd9Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 1289b0fc0e77Sgovinda ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri); 1290b0fc0e77Sgovinda ih_p = px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, rec_type, 1291b0fc0e77Sgovinda msg_code); 12927c478bd9Sstevel@tonic-gate 12937c478bd9Sstevel@tonic-gate /* Get the current cpu */ 12947c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 12957c478bd9Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 12967c478bd9Sstevel@tonic-gate goto fail; 12977c478bd9Sstevel@tonic-gate 1298b0fc0e77Sgovinda if ((ret = px_ib_ino_rem_intr(px_p, ipil_p, ih_p)) != DDI_SUCCESS) 12997c478bd9Sstevel@tonic-gate goto fail; 13007c478bd9Sstevel@tonic-gate 13017c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 13027c478bd9Sstevel@tonic-gate 1303b0fc0e77Sgovinda if (ipil_p->ipil_ih_size == 0) { 13047c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 13057c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 13067c478bd9Sstevel@tonic-gate 1307b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 1308b0fc0e77Sgovinda 1309b0fc0e77Sgovinda if (ino_p->ino_ipil_size == 0) 1310b0fc0e77Sgovinda px_lib_msiq_setvalid(dip, 1311b0fc0e77Sgovinda px_devino_to_msiqid(px_p, ino), PCI_MSIQ_INVALID); 13127c478bd9Sstevel@tonic-gate 13137c478bd9Sstevel@tonic-gate (void) px_msiq_free(px_p, msiq_id); 1314b0fc0e77Sgovinda } 1315b0fc0e77Sgovinda 1316b0fc0e77Sgovinda if (ino_p->ino_ipil_size == 0) { 1317b0fc0e77Sgovinda kmem_free(ino_p, sizeof (px_ino_t)); 13187c478bd9Sstevel@tonic-gate } else { 13190d2a6fcfSegillett /* Re-enable interrupt only if mapping register still shared */ 13200d2a6fcfSegillett PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 13217c478bd9Sstevel@tonic-gate } 13227c478bd9Sstevel@tonic-gate 13237c478bd9Sstevel@tonic-gate fail: 13247c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 13257c478bd9Sstevel@tonic-gate return (ret); 13267c478bd9Sstevel@tonic-gate } 1327