17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5102cb92eSjohnny * Common Development and Distribution License (the "License"). 6102cb92eSjohnny * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22614edcaeSEvan Yan * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate /* 277c478bd9Sstevel@tonic-gate * PX nexus interrupt handling: 287c478bd9Sstevel@tonic-gate * PX device interrupt handler wrapper 297c478bd9Sstevel@tonic-gate * PIL lookup routine 307c478bd9Sstevel@tonic-gate * PX device interrupt related initchild code 317c478bd9Sstevel@tonic-gate */ 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #include <sys/types.h> 347c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 357c478bd9Sstevel@tonic-gate #include <sys/async.h> 367c478bd9Sstevel@tonic-gate #include <sys/spl.h> 377c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 38f8d2de6bSjchu #include <sys/fm/protocol.h> 39f8d2de6bSjchu #include <sys/fm/util.h> 407c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 417c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 427c478bd9Sstevel@tonic-gate #include <sys/sdt.h> 437c478bd9Sstevel@tonic-gate #include <sys/atomic.h> 447c478bd9Sstevel@tonic-gate #include "px_obj.h" 45f8d2de6bSjchu #include <sys/ontrap.h> 46f8d2de6bSjchu #include <sys/membar.h> 476d44af1bSesolom #include <sys/clock.h> 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate /* 507c478bd9Sstevel@tonic-gate * interrupt jabber: 517c478bd9Sstevel@tonic-gate * 527c478bd9Sstevel@tonic-gate * When an interrupt line is jabbering, every time the state machine for the 537c478bd9Sstevel@tonic-gate * associated ino is idled, a new mondo will be sent and the ino will go into 547c478bd9Sstevel@tonic-gate * the pending state again. The mondo will cause a new call to 557c478bd9Sstevel@tonic-gate * px_intr_wrapper() which normally idles the ino's state machine which would 567c478bd9Sstevel@tonic-gate * precipitate another trip round the loop. 577c478bd9Sstevel@tonic-gate * 587c478bd9Sstevel@tonic-gate * The loop can be broken by preventing the ino's state machine from being 597c478bd9Sstevel@tonic-gate * idled when an interrupt line is jabbering. See the comment at the 607c478bd9Sstevel@tonic-gate * beginning of px_intr_wrapper() explaining how the 'interrupt jabber 617c478bd9Sstevel@tonic-gate * protection' code does this. 627c478bd9Sstevel@tonic-gate */ 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate /* 677c478bd9Sstevel@tonic-gate * If the unclaimed interrupt count has reached the limit set by 687c478bd9Sstevel@tonic-gate * pci_unclaimed_intr_max within the time limit, then all interrupts 697c478bd9Sstevel@tonic-gate * on this ino is blocked by not idling the interrupt state machine. 707c478bd9Sstevel@tonic-gate */ 717c478bd9Sstevel@tonic-gate static int 72b0fc0e77Sgovinda px_spurintr(px_ino_pil_t *ipil_p) 737c478bd9Sstevel@tonic-gate { 74b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 75b0fc0e77Sgovinda px_ih_t *ih_p = ipil_p->ipil_ih_start; 76b0fc0e77Sgovinda px_t *px_p = ino_p->ino_ib_p->ib_px_p; 77b0fc0e77Sgovinda char *err_fmt_str; 78b0fc0e77Sgovinda boolean_t blocked = B_FALSE; 79b0fc0e77Sgovinda int i; 807c478bd9Sstevel@tonic-gate 81b0fc0e77Sgovinda if (ino_p->ino_unclaimed_intrs > px_unclaimed_intr_max) 827c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 837c478bd9Sstevel@tonic-gate 84b0fc0e77Sgovinda if (!ino_p->ino_unclaimed_intrs) 857c478bd9Sstevel@tonic-gate ino_p->ino_spurintr_begin = ddi_get_lbolt(); 867c478bd9Sstevel@tonic-gate 87b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs++; 887c478bd9Sstevel@tonic-gate 89b0fc0e77Sgovinda if (ino_p->ino_unclaimed_intrs <= px_unclaimed_intr_max) 907c478bd9Sstevel@tonic-gate goto clear; 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 937c478bd9Sstevel@tonic-gate > px_spurintr_duration) { 94b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs = 0; 957c478bd9Sstevel@tonic-gate goto clear; 967c478bd9Sstevel@tonic-gate } 977c478bd9Sstevel@tonic-gate err_fmt_str = "%s%d: ino 0x%x blocked"; 98b0fc0e77Sgovinda blocked = B_TRUE; 997c478bd9Sstevel@tonic-gate goto warn; 1007c478bd9Sstevel@tonic-gate clear: 1017c478bd9Sstevel@tonic-gate err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 1027c478bd9Sstevel@tonic-gate warn: 1037c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, err_fmt_str, NAMEINST(px_p->px_dip), ino_p->ino_ino); 104b0fc0e77Sgovinda for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) 1057c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 1067c478bd9Sstevel@tonic-gate ih_p->ih_inum); 1077c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!\n"); 108b0fc0e77Sgovinda 109b0fc0e77Sgovinda /* Clear the pending state */ 110b0fc0e77Sgovinda if (blocked == B_FALSE) { 111b0fc0e77Sgovinda if (px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 112b0fc0e77Sgovinda INTR_IDLE_STATE) != DDI_SUCCESS) 113b0fc0e77Sgovinda return (DDI_INTR_UNCLAIMED); 114b0fc0e77Sgovinda } 115b0fc0e77Sgovinda 1167c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 1177c478bd9Sstevel@tonic-gate } 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate extern uint64_t intr_get_time(void); 1207c478bd9Sstevel@tonic-gate 1217c478bd9Sstevel@tonic-gate /* 122a195726fSgovinda * px_intx_intr (INTx or legacy interrupt handler) 1237c478bd9Sstevel@tonic-gate * 1247c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 1257c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 1267c478bd9Sstevel@tonic-gate * examines the return codes. 1277c478bd9Sstevel@tonic-gate * 1287c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 1297c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 1307c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 1317c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 1327c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 1337c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 1347c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 1357c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 1367c478bd9Sstevel@tonic-gate * 1377c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 1387c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 1397c478bd9Sstevel@tonic-gate */ 1407c478bd9Sstevel@tonic-gate uint_t 1417c478bd9Sstevel@tonic-gate px_intx_intr(caddr_t arg) 1427c478bd9Sstevel@tonic-gate { 143b0fc0e77Sgovinda px_ino_pil_t *ipil_p = (px_ino_pil_t *)arg; 144b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 1457c478bd9Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 146b0fc0e77Sgovinda px_ih_t *ih_p = ipil_p->ipil_ih_start; 147b0fc0e77Sgovinda ushort_t pil = ipil_p->ipil_pil; 148b0fc0e77Sgovinda uint_t result = 0, r = DDI_INTR_UNCLAIMED; 1497c478bd9Sstevel@tonic-gate int i; 1507c478bd9Sstevel@tonic-gate 1517c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 1527c478bd9Sstevel@tonic-gate "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n", 153b0fc0e77Sgovinda ino_p->ino_ino, ino_p->ino_sysino, ipil_p->ipil_pil, 154b0fc0e77Sgovinda ipil_p->ipil_ih_size, ipil_p->ipil_ih_head); 1557c478bd9Sstevel@tonic-gate 156b0fc0e77Sgovinda for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) { 1577c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 1587c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 1597c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 1607c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) { 1637c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, 1647c478bd9Sstevel@tonic-gate "px_intx_intr: %s%d interrupt %d is disabled\n", 1657c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 1667c478bd9Sstevel@tonic-gate ino_p->ino_ino); 1677c478bd9Sstevel@tonic-gate 1687c478bd9Sstevel@tonic-gate continue; 1697c478bd9Sstevel@tonic-gate } 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 1727c478bd9Sstevel@tonic-gate "ino=%x handler=%p arg1 =%p arg2 = %p\n", 1737c478bd9Sstevel@tonic-gate ino_p->ino_ino, handler, arg1, arg2); 1747c478bd9Sstevel@tonic-gate 1757c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 1767c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 1777c478bd9Sstevel@tonic-gate 1787c478bd9Sstevel@tonic-gate r = (*handler)(arg1, arg2); 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate /* 1817c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect against 1827c478bd9Sstevel@tonic-gate * conflicting writes to ih_ticks from ib_intr_dist_all() by 1837c478bd9Sstevel@tonic-gate * using atomic ops. 1847c478bd9Sstevel@tonic-gate */ 1857c478bd9Sstevel@tonic-gate 186b0fc0e77Sgovinda if (pil <= LOCK_LEVEL) 1877c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 1887c478bd9Sstevel@tonic-gate 1897c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 1907c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, r); 1917c478bd9Sstevel@tonic-gate 1927c478bd9Sstevel@tonic-gate result += r; 1937c478bd9Sstevel@tonic-gate 1947c478bd9Sstevel@tonic-gate if (px_check_all_handlers) 1957c478bd9Sstevel@tonic-gate continue; 1967c478bd9Sstevel@tonic-gate if (result) 1977c478bd9Sstevel@tonic-gate break; 1987c478bd9Sstevel@tonic-gate } 1997c478bd9Sstevel@tonic-gate 200b0fc0e77Sgovinda if (result) 201b0fc0e77Sgovinda ino_p->ino_claimed |= (1 << pil); 202b0fc0e77Sgovinda 203b0fc0e77Sgovinda /* Interrupt can only be cleared after all pil levels are handled */ 204b0fc0e77Sgovinda if (pil != ino_p->ino_lopil) 205b0fc0e77Sgovinda return (DDI_INTR_CLAIMED); 206b0fc0e77Sgovinda 207b0fc0e77Sgovinda if (!ino_p->ino_claimed) { 208b0fc0e77Sgovinda if (px_unclaimed_intr_block) 209b0fc0e77Sgovinda return (px_spurintr(ipil_p)); 210b0fc0e77Sgovinda } 2117c478bd9Sstevel@tonic-gate 212b0fc0e77Sgovinda ino_p->ino_unclaimed_intrs = 0; 213b0fc0e77Sgovinda ino_p->ino_claimed = 0; 2147c478bd9Sstevel@tonic-gate 2157c478bd9Sstevel@tonic-gate /* Clear the pending state */ 216b0fc0e77Sgovinda if (px_lib_intr_setstate(px_p->px_dip, 2177c478bd9Sstevel@tonic-gate ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 2187c478bd9Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 2217c478bd9Sstevel@tonic-gate } 2227c478bd9Sstevel@tonic-gate 2237c478bd9Sstevel@tonic-gate /* 224a195726fSgovinda * px_msiq_intr (MSI/X or PCIe MSG interrupt handler) 2257c478bd9Sstevel@tonic-gate * 2267c478bd9Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 2277c478bd9Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 2287c478bd9Sstevel@tonic-gate * examines the return codes. 2297c478bd9Sstevel@tonic-gate * 2307c478bd9Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 2317c478bd9Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 2327c478bd9Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 2337c478bd9Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 2347c478bd9Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 2357c478bd9Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 2367c478bd9Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 2377c478bd9Sstevel@tonic-gate * handler is subsequently added or removed. 2387c478bd9Sstevel@tonic-gate * 2397c478bd9Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 2407c478bd9Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 2417c478bd9Sstevel@tonic-gate */ 2427c478bd9Sstevel@tonic-gate uint_t 2437c478bd9Sstevel@tonic-gate px_msiq_intr(caddr_t arg) 2447c478bd9Sstevel@tonic-gate { 245b0fc0e77Sgovinda px_ino_pil_t *ipil_p = (px_ino_pil_t *)arg; 246b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 2477c478bd9Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 2487c478bd9Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 2497c478bd9Sstevel@tonic-gate px_msiq_t *msiq_p = ino_p->ino_msiq_p; 2507c478bd9Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 251b0fc0e77Sgovinda ushort_t pil = ipil_p->ipil_pil; 2527c478bd9Sstevel@tonic-gate msiq_rec_t msiq_rec, *msiq_rec_p = &msiq_rec; 253023ccc1eSegillett msiqhead_t *curr_head_p; 254023ccc1eSegillett msiqtail_t curr_tail_index; 2557c478bd9Sstevel@tonic-gate msgcode_t msg_code; 2567c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 257b0fc0e77Sgovinda uint_t ret = DDI_INTR_UNCLAIMED; 258b0fc0e77Sgovinda int i, j; 2597c478bd9Sstevel@tonic-gate 2607c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x " 2617c478bd9Sstevel@tonic-gate "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino, 262b0fc0e77Sgovinda ipil_p->ipil_pil, ipil_p->ipil_ih_size, ipil_p->ipil_ih_head); 263b0fc0e77Sgovinda 264b0fc0e77Sgovinda /* 265b0fc0e77Sgovinda * The px_msiq_intr() handles multiple interrupt priorities and it 266b0fc0e77Sgovinda * will set msiq->msiq_rec2process to the number of MSIQ records to 267b0fc0e77Sgovinda * process while handling the highest priority interrupt. Subsequent 268b0fc0e77Sgovinda * lower priority interrupts will just process any unprocessed MSIQ 269b0fc0e77Sgovinda * records or will just return immediately. 270b0fc0e77Sgovinda */ 271b0fc0e77Sgovinda if (msiq_p->msiq_recs2process == 0) { 272b0fc0e77Sgovinda /* Read current MSIQ tail index */ 273b0fc0e77Sgovinda px_lib_msiq_gettail(dip, msiq_p->msiq_id, &curr_tail_index); 274b0fc0e77Sgovinda msiq_p->msiq_new_head_index = msiq_p->msiq_curr_head_index; 275b0fc0e77Sgovinda 276b0fc0e77Sgovinda if (curr_tail_index < msiq_p->msiq_curr_head_index) 277b0fc0e77Sgovinda curr_tail_index += msiq_state_p->msiq_rec_cnt; 2787c478bd9Sstevel@tonic-gate 279b0fc0e77Sgovinda msiq_p->msiq_recs2process = curr_tail_index - 280b0fc0e77Sgovinda msiq_p->msiq_curr_head_index; 281b0fc0e77Sgovinda } 282b0fc0e77Sgovinda 283b0fc0e77Sgovinda DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: curr_head %x new_head %x " 284b0fc0e77Sgovinda "rec2process %x\n", msiq_p->msiq_curr_head_index, 285b0fc0e77Sgovinda msiq_p->msiq_new_head_index, msiq_p->msiq_recs2process); 2867c478bd9Sstevel@tonic-gate 287b0fc0e77Sgovinda /* If all MSIQ records are already processed, just return immediately */ 288b0fc0e77Sgovinda if ((msiq_p->msiq_new_head_index - msiq_p->msiq_curr_head_index) 289b0fc0e77Sgovinda == msiq_p->msiq_recs2process) 290b0fc0e77Sgovinda goto intr_done; 291b0fc0e77Sgovinda 292b0fc0e77Sgovinda curr_head_p = (msiqhead_t *)((caddr_t)msiq_p->msiq_base_p + 293b0fc0e77Sgovinda (msiq_p->msiq_curr_head_index * sizeof (msiq_rec_t))); 2947c478bd9Sstevel@tonic-gate 2957c478bd9Sstevel@tonic-gate /* 296023ccc1eSegillett * Calculate the number of recs to process by taking the difference 297023ccc1eSegillett * between the head and tail pointers. For all records we always 298023ccc1eSegillett * verify that we have a valid record type before we do any processing. 299b0fc0e77Sgovinda * If triggered, we should always have at least one valid record. 3007c478bd9Sstevel@tonic-gate */ 301b0fc0e77Sgovinda for (i = 0; i < msiq_p->msiq_recs2process; i++) { 3022324ee65SAlan Adamson, SD OSSD msiq_rec_type_t rec_type; 3032324ee65SAlan Adamson, SD OSSD 304b0fc0e77Sgovinda /* Read next MSIQ record */ 305023ccc1eSegillett px_lib_get_msiq_rec(dip, curr_head_p, msiq_rec_p); 306023ccc1eSegillett 3072324ee65SAlan Adamson, SD OSSD rec_type = msiq_rec_p->msiq_rec_type; 3082324ee65SAlan Adamson, SD OSSD 3097c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSIQ RECORD, " 3107c478bd9Sstevel@tonic-gate "msiq_rec_type 0x%llx msiq_rec_rid 0x%llx\n", 3112324ee65SAlan Adamson, SD OSSD rec_type, msiq_rec_p->msiq_rec_rid); 3127c478bd9Sstevel@tonic-gate 3132324ee65SAlan Adamson, SD OSSD if (!rec_type) 314b0fc0e77Sgovinda goto next_rec; 3157c478bd9Sstevel@tonic-gate 3167c478bd9Sstevel@tonic-gate /* Check MSIQ record type */ 3172324ee65SAlan Adamson, SD OSSD switch (rec_type) { 3187c478bd9Sstevel@tonic-gate case MSG_REC: 3197c478bd9Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msg.msg_code; 3207c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: PCIE MSG " 3217c478bd9Sstevel@tonic-gate "record, msg type 0x%x\n", msg_code); 3227c478bd9Sstevel@tonic-gate break; 3237c478bd9Sstevel@tonic-gate case MSI32_REC: 3247c478bd9Sstevel@tonic-gate case MSI64_REC: 3257c478bd9Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msi.msi_data; 3267c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSI record, " 3277c478bd9Sstevel@tonic-gate "msi 0x%x\n", msg_code); 3287c478bd9Sstevel@tonic-gate 3297c478bd9Sstevel@tonic-gate /* Clear MSI state */ 3307c478bd9Sstevel@tonic-gate px_lib_msi_setstate(dip, (msinum_t)msg_code, 3317c478bd9Sstevel@tonic-gate PCI_MSI_STATE_IDLE); 3327c478bd9Sstevel@tonic-gate break; 3337c478bd9Sstevel@tonic-gate default: 3347c478bd9Sstevel@tonic-gate msg_code = 0; 3357c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_msiq_intr: 0x%x MSIQ " 3367c478bd9Sstevel@tonic-gate "record type is not supported", 3377c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 3382324ee65SAlan Adamson, SD OSSD rec_type); 339b0fc0e77Sgovinda 3407c478bd9Sstevel@tonic-gate goto next_rec; 3417c478bd9Sstevel@tonic-gate } 3427c478bd9Sstevel@tonic-gate 3437c478bd9Sstevel@tonic-gate /* 3447c478bd9Sstevel@tonic-gate * Scan through px_ih_t linked list, searching for the 3457c478bd9Sstevel@tonic-gate * right px_ih_t, matching MSIQ record data. 3467c478bd9Sstevel@tonic-gate */ 347b0fc0e77Sgovinda for (j = 0, ih_p = ipil_p->ipil_ih_start; 348b0fc0e77Sgovinda ih_p && (j < ipil_p->ipil_ih_size) && 34907f14c08Sgovinda ((ih_p->ih_msg_code != msg_code) || 3502324ee65SAlan Adamson, SD OSSD (ih_p->ih_rec_type != rec_type)); 3512917a9c9Sschwartz ih_p = ih_p->ih_next, j++) 3522917a9c9Sschwartz ; 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate if ((ih_p->ih_msg_code == msg_code) && 3552324ee65SAlan Adamson, SD OSSD (ih_p->ih_rec_type == rec_type)) { 3567c478bd9Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 3577c478bd9Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 3587c478bd9Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 3597c478bd9Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 3607c478bd9Sstevel@tonic-gate 3617c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: ino=%x data=%x " 3627c478bd9Sstevel@tonic-gate "handler=%p arg1 =%p arg2=%p\n", ino_p->ino_ino, 3637c478bd9Sstevel@tonic-gate msg_code, handler, arg1, arg2); 3647c478bd9Sstevel@tonic-gate 3657c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 3667c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 3677c478bd9Sstevel@tonic-gate 368*09b1eac2SEvan Yan ih_p->ih_retarget_flag = B_FALSE; 369*09b1eac2SEvan Yan 370f8d2de6bSjchu /* 371f8d2de6bSjchu * Special case for PCIE Error Messages. 372f8d2de6bSjchu * The current frame work doesn't fit PCIE Err Msgs 373f8d2de6bSjchu * This should be fixed when PCIE MESSAGES as a whole 374f8d2de6bSjchu * is architected correctly. 375f8d2de6bSjchu */ 3762324ee65SAlan Adamson, SD OSSD if ((rec_type == MSG_REC) && 3772324ee65SAlan Adamson, SD OSSD ((msg_code == PCIE_MSG_CODE_ERR_COR) || 378f8d2de6bSjchu (msg_code == PCIE_MSG_CODE_ERR_NONFATAL) || 3792324ee65SAlan Adamson, SD OSSD (msg_code == PCIE_MSG_CODE_ERR_FATAL))) { 380f8d2de6bSjchu ret = px_err_fabric_intr(px_p, msg_code, 381f8d2de6bSjchu msiq_rec_p->msiq_rec_rid); 382f8d2de6bSjchu } else 383f8d2de6bSjchu ret = (*handler)(arg1, arg2); 3847c478bd9Sstevel@tonic-gate 3857c478bd9Sstevel@tonic-gate /* 3867c478bd9Sstevel@tonic-gate * Account for time used by this interrupt. Protect 3877c478bd9Sstevel@tonic-gate * against conflicting writes to ih_ticks from 3887c478bd9Sstevel@tonic-gate * ib_intr_dist_all() by using atomic ops. 3897c478bd9Sstevel@tonic-gate */ 3907c478bd9Sstevel@tonic-gate 391b0fc0e77Sgovinda if (pil <= LOCK_LEVEL) 3927c478bd9Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 3937c478bd9Sstevel@tonic-gate 3947c478bd9Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 3957c478bd9Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, ret); 396023ccc1eSegillett 397b0fc0e77Sgovinda msiq_p->msiq_new_head_index++; 398b0fc0e77Sgovinda px_lib_clr_msiq_rec(dip, curr_head_p); 3997c478bd9Sstevel@tonic-gate } else { 4007c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr:" 401023ccc1eSegillett "No matching MSIQ record found\n"); 4027c478bd9Sstevel@tonic-gate } 4037c478bd9Sstevel@tonic-gate next_rec: 404023ccc1eSegillett /* Get the pointer next EQ record */ 405023ccc1eSegillett curr_head_p = (msiqhead_t *) 406023ccc1eSegillett ((caddr_t)curr_head_p + sizeof (msiq_rec_t)); 407023ccc1eSegillett 408023ccc1eSegillett /* Check for overflow condition */ 409023ccc1eSegillett if (curr_head_p >= (msiqhead_t *)((caddr_t)msiq_p->msiq_base_p 410b0fc0e77Sgovinda + (msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t)))) 411023ccc1eSegillett curr_head_p = (msiqhead_t *)msiq_p->msiq_base_p; 4127c478bd9Sstevel@tonic-gate } 4137c478bd9Sstevel@tonic-gate 414b0fc0e77Sgovinda DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: No of MSIQ recs processed %x\n", 415b0fc0e77Sgovinda (msiq_p->msiq_new_head_index - msiq_p->msiq_curr_head_index)); 416023ccc1eSegillett 417b0fc0e77Sgovinda DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: curr_head %x new_head %x " 418b0fc0e77Sgovinda "rec2process %x\n", msiq_p->msiq_curr_head_index, 419b0fc0e77Sgovinda msiq_p->msiq_new_head_index, msiq_p->msiq_recs2process); 420b0fc0e77Sgovinda 421b0fc0e77Sgovinda /* ino_claimed used just for debugging purpose */ 422b0fc0e77Sgovinda if (ret) 423b0fc0e77Sgovinda ino_p->ino_claimed |= (1 << pil); 424b0fc0e77Sgovinda 425b0fc0e77Sgovinda intr_done: 426b0fc0e77Sgovinda /* Interrupt can only be cleared after all pil levels are handled */ 427b0fc0e77Sgovinda if (pil != ino_p->ino_lopil) 428b0fc0e77Sgovinda return (DDI_INTR_CLAIMED); 429b0fc0e77Sgovinda 430b0fc0e77Sgovinda if (msiq_p->msiq_new_head_index <= msiq_p->msiq_curr_head_index) { 431b0fc0e77Sgovinda if (px_unclaimed_intr_block) 432b0fc0e77Sgovinda return (px_spurintr(ipil_p)); 433023ccc1eSegillett } 4347c478bd9Sstevel@tonic-gate 4357c478bd9Sstevel@tonic-gate /* Update MSIQ head index with no of MSIQ records processed */ 436b0fc0e77Sgovinda if (msiq_p->msiq_new_head_index >= msiq_state_p->msiq_rec_cnt) 437b0fc0e77Sgovinda msiq_p->msiq_new_head_index -= msiq_state_p->msiq_rec_cnt; 4387c478bd9Sstevel@tonic-gate 439b0fc0e77Sgovinda msiq_p->msiq_curr_head_index = msiq_p->msiq_new_head_index; 440b0fc0e77Sgovinda px_lib_msiq_sethead(dip, msiq_p->msiq_id, msiq_p->msiq_new_head_index); 441b0fc0e77Sgovinda 442b0fc0e77Sgovinda msiq_p->msiq_new_head_index = 0; 443b0fc0e77Sgovinda msiq_p->msiq_recs2process = 0; 444b0fc0e77Sgovinda ino_p->ino_claimed = 0; 4457c478bd9Sstevel@tonic-gate 4467c478bd9Sstevel@tonic-gate /* Clear the pending state */ 4477c478bd9Sstevel@tonic-gate if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 4487c478bd9Sstevel@tonic-gate INTR_IDLE_STATE) != DDI_SUCCESS) 4497c478bd9Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 4507c478bd9Sstevel@tonic-gate 4517c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 4527c478bd9Sstevel@tonic-gate } 4537c478bd9Sstevel@tonic-gate 4547c478bd9Sstevel@tonic-gate dev_info_t * 4557c478bd9Sstevel@tonic-gate px_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 4567c478bd9Sstevel@tonic-gate { 4577c478bd9Sstevel@tonic-gate dev_info_t *cdip = rdip; 4587c478bd9Sstevel@tonic-gate 4597c478bd9Sstevel@tonic-gate for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 4607c478bd9Sstevel@tonic-gate ; 4617c478bd9Sstevel@tonic-gate 4627c478bd9Sstevel@tonic-gate return (cdip); 4637c478bd9Sstevel@tonic-gate } 4647c478bd9Sstevel@tonic-gate 4657c478bd9Sstevel@tonic-gate /* ARGSUSED */ 4667c478bd9Sstevel@tonic-gate int 4677c478bd9Sstevel@tonic-gate px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 4687c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 4697c478bd9Sstevel@tonic-gate { 470a195726fSgovinda px_t *px_p = DIP_TO_STATE(dip); 471a195726fSgovinda int ret = DDI_SUCCESS; 4727c478bd9Sstevel@tonic-gate 4737c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x " 4747c478bd9Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 4757c478bd9Sstevel@tonic-gate 4767c478bd9Sstevel@tonic-gate switch (intr_op) { 4777c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 4787c478bd9Sstevel@tonic-gate ret = pci_intx_get_cap(rdip, (int *)result); 4797c478bd9Sstevel@tonic-gate break; 4807c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 4817c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n"); 4827c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 4837c478bd9Sstevel@tonic-gate break; 4847c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 4857c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_scratch1; 4867c478bd9Sstevel@tonic-gate break; 4877c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 4887c478bd9Sstevel@tonic-gate break; 4897c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 490a195726fSgovinda *(int *)result = hdlp->ih_pri ? 491614edcaeSEvan Yan hdlp->ih_pri : pci_class_to_pil(rdip); 4927c478bd9Sstevel@tonic-gate break; 4937c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 4947c478bd9Sstevel@tonic-gate break; 4957c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 4967c478bd9Sstevel@tonic-gate ret = px_add_intx_intr(dip, rdip, hdlp); 4977c478bd9Sstevel@tonic-gate break; 4987c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 4997c478bd9Sstevel@tonic-gate ret = px_rem_intx_intr(dip, rdip, hdlp); 5007c478bd9Sstevel@tonic-gate break; 501*09b1eac2SEvan Yan case DDI_INTROP_GETTARGET: 502*09b1eac2SEvan Yan ret = px_ib_get_intr_target(px_p, hdlp->ih_vector, 503*09b1eac2SEvan Yan (cpuid_t *)result); 504*09b1eac2SEvan Yan break; 505*09b1eac2SEvan Yan case DDI_INTROP_SETTARGET: 506*09b1eac2SEvan Yan ret = DDI_ENOTSUP; 507*09b1eac2SEvan Yan break; 5087c478bd9Sstevel@tonic-gate case DDI_INTROP_ENABLE: 5097c478bd9Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 510b0fc0e77Sgovinda hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_ENABLE, 0, 0); 5117c478bd9Sstevel@tonic-gate break; 5127c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 5137c478bd9Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 514b0fc0e77Sgovinda hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_DISABLE, 0, 0); 5157c478bd9Sstevel@tonic-gate break; 5167c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 5177c478bd9Sstevel@tonic-gate ret = pci_intx_set_mask(rdip); 5187c478bd9Sstevel@tonic-gate break; 5197c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 5207c478bd9Sstevel@tonic-gate ret = pci_intx_clr_mask(rdip); 5217c478bd9Sstevel@tonic-gate break; 5227c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 5237c478bd9Sstevel@tonic-gate ret = pci_intx_get_pending(rdip, (int *)result); 5247c478bd9Sstevel@tonic-gate break; 5257c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 5267c478bd9Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 527a54f81fbSanish *(int *)result = i_ddi_get_intx_nintrs(rdip); 5287c478bd9Sstevel@tonic-gate break; 5297c478bd9Sstevel@tonic-gate default: 5307c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 5317c478bd9Sstevel@tonic-gate break; 5327c478bd9Sstevel@tonic-gate } 5337c478bd9Sstevel@tonic-gate 5347c478bd9Sstevel@tonic-gate return (ret); 5357c478bd9Sstevel@tonic-gate } 5367c478bd9Sstevel@tonic-gate 5377c478bd9Sstevel@tonic-gate /* ARGSUSED */ 5387c478bd9Sstevel@tonic-gate int 5397c478bd9Sstevel@tonic-gate px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 5407c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 5417c478bd9Sstevel@tonic-gate { 5427c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 5437c478bd9Sstevel@tonic-gate px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 5449c75c6bfSgovinda msiq_rec_type_t msiq_rec_type; 5459c75c6bfSgovinda msi_type_t msi_type; 5469c75c6bfSgovinda uint64_t msi_addr; 5477c478bd9Sstevel@tonic-gate msinum_t msi_num; 5487c478bd9Sstevel@tonic-gate msiqid_t msiq_id; 5497c478bd9Sstevel@tonic-gate uint_t nintrs; 550*09b1eac2SEvan Yan int ret = DDI_SUCCESS; 5517c478bd9Sstevel@tonic-gate 5527c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x " 5537c478bd9Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 5547c478bd9Sstevel@tonic-gate 5559c75c6bfSgovinda /* Check for MSI64 support */ 55607f14c08Sgovinda if ((hdlp->ih_cap & DDI_INTR_FLAG_MSI64) && msi_state_p->msi_addr64) { 5579c75c6bfSgovinda msiq_rec_type = MSI64_REC; 5589c75c6bfSgovinda msi_type = MSI64_TYPE; 55907f14c08Sgovinda msi_addr = msi_state_p->msi_addr64; 5609c75c6bfSgovinda } else { 5619c75c6bfSgovinda msiq_rec_type = MSI32_REC; 5629c75c6bfSgovinda msi_type = MSI32_TYPE; 5639c75c6bfSgovinda msi_addr = msi_state_p->msi_addr32; 5649c75c6bfSgovinda } 5659c75c6bfSgovinda 566*09b1eac2SEvan Yan (void) px_msi_get_msinum(px_p, hdlp->ih_dip, 567*09b1eac2SEvan Yan (hdlp->ih_flags & DDI_INTR_MSIX_DUP) ? hdlp->ih_main->ih_inum : 568*09b1eac2SEvan Yan hdlp->ih_inum, &msi_num); 569*09b1eac2SEvan Yan 5707c478bd9Sstevel@tonic-gate switch (intr_op) { 5717c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 5727c478bd9Sstevel@tonic-gate ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result); 573*09b1eac2SEvan Yan if (ret == DDI_SUCCESS) 574*09b1eac2SEvan Yan *(int *)result |= DDI_INTR_FLAG_RETARGETABLE; 5757c478bd9Sstevel@tonic-gate break; 5767c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 5777c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: SetCap is not supported\n"); 5787c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 5797c478bd9Sstevel@tonic-gate break; 5807c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 5817c478bd9Sstevel@tonic-gate /* 5827c478bd9Sstevel@tonic-gate * We need to restrict this allocation in future 5837c478bd9Sstevel@tonic-gate * based on Resource Management policies. 5847c478bd9Sstevel@tonic-gate */ 5855febcb4aSScott Carter, SD IOSW if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_type, 5865febcb4aSScott Carter, SD IOSW hdlp->ih_inum, hdlp->ih_scratch1, 5875febcb4aSScott Carter, SD IOSW (uintptr_t)hdlp->ih_scratch2, 58820036fe5Segillett (int *)result)) != DDI_SUCCESS) { 58920036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: allocation " 59020036fe5Segillett "failed, rdip 0x%p type 0x%d inum 0x%x " 59120036fe5Segillett "count 0x%x\n", rdip, hdlp->ih_type, hdlp->ih_inum, 59220036fe5Segillett hdlp->ih_scratch1); 5937c478bd9Sstevel@tonic-gate 5947c478bd9Sstevel@tonic-gate return (ret); 5957c478bd9Sstevel@tonic-gate } 5967c478bd9Sstevel@tonic-gate 59720036fe5Segillett if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && 59820036fe5Segillett (i_ddi_get_msix(rdip) == NULL)) { 59920036fe5Segillett ddi_intr_msix_t *msix_p; 60020036fe5Segillett 60120036fe5Segillett if (msix_p = pci_msix_init(rdip)) { 60220036fe5Segillett i_ddi_set_msix(rdip, msix_p); 60320036fe5Segillett break; 60420036fe5Segillett } 60520036fe5Segillett 60620036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: MSI-X allocation " 60720036fe5Segillett "failed, rdip 0x%p inum 0x%x\n", rdip, 60820036fe5Segillett hdlp->ih_inum); 60920036fe5Segillett 61020036fe5Segillett (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 61120036fe5Segillett hdlp->ih_scratch1); 61220036fe5Segillett 61320036fe5Segillett return (DDI_FAILURE); 61420036fe5Segillett } 61520036fe5Segillett 6167c478bd9Sstevel@tonic-gate break; 6177c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 6187c478bd9Sstevel@tonic-gate (void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum); 61920036fe5Segillett 62020036fe5Segillett if (hdlp->ih_type == DDI_INTR_TYPE_MSI) 62120036fe5Segillett goto msi_free; 62220036fe5Segillett 62320036fe5Segillett if (hdlp->ih_flags & DDI_INTR_MSIX_DUP) 62420036fe5Segillett break; 62520036fe5Segillett 62620036fe5Segillett if (((i_ddi_intr_get_current_nintrs(hdlp->ih_dip) - 1) == 0) && 62720036fe5Segillett (i_ddi_get_msix(rdip))) { 62820036fe5Segillett pci_msix_fini(i_ddi_get_msix(rdip)); 62920036fe5Segillett i_ddi_set_msix(rdip, NULL); 63020036fe5Segillett } 63120036fe5Segillett msi_free: 6327c478bd9Sstevel@tonic-gate (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 6337c478bd9Sstevel@tonic-gate hdlp->ih_scratch1); 6347c478bd9Sstevel@tonic-gate break; 6357c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 6367c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_pri ? 637614edcaeSEvan Yan hdlp->ih_pri : pci_class_to_pil(rdip); 6387c478bd9Sstevel@tonic-gate break; 6397c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 6407c478bd9Sstevel@tonic-gate break; 6417c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 6427c478bd9Sstevel@tonic-gate if ((ret = px_add_msiq_intr(dip, rdip, hdlp, 643*09b1eac2SEvan Yan msiq_rec_type, msi_num, -1, &msiq_id)) != DDI_SUCCESS) { 6447c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler " 6457c478bd9Sstevel@tonic-gate "failed, rdip 0x%p msi 0x%x\n", rdip, msi_num); 6467c478bd9Sstevel@tonic-gate return (ret); 6477c478bd9Sstevel@tonic-gate } 6487c478bd9Sstevel@tonic-gate 6497c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id); 6507c478bd9Sstevel@tonic-gate 6517c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setmsiq(dip, msi_num, 6529c75c6bfSgovinda msiq_id, msi_type)) != DDI_SUCCESS) { 6537c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 6549c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 6557c478bd9Sstevel@tonic-gate return (ret); 6567c478bd9Sstevel@tonic-gate } 6577c478bd9Sstevel@tonic-gate 6587c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 6597c478bd9Sstevel@tonic-gate PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) { 6607c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 6619c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 6627c478bd9Sstevel@tonic-gate return (ret); 6637c478bd9Sstevel@tonic-gate } 6647c478bd9Sstevel@tonic-gate 665*09b1eac2SEvan Yan if ((ret = px_lib_msi_setvalid(dip, msi_num, 666*09b1eac2SEvan Yan PCI_MSI_VALID)) != DDI_SUCCESS) 667*09b1eac2SEvan Yan return (ret); 668*09b1eac2SEvan Yan 669*09b1eac2SEvan Yan ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 670*09b1eac2SEvan Yan px_msiqid_to_devino(px_p, msiq_id), hdlp->ih_pri, 671*09b1eac2SEvan Yan PX_INTR_STATE_ENABLE, msiq_rec_type, msi_num); 672*09b1eac2SEvan Yan 6737c478bd9Sstevel@tonic-gate break; 6747c478bd9Sstevel@tonic-gate case DDI_INTROP_DUPVEC: 67520036fe5Segillett DBG(DBG_INTROPS, dip, "px_msix_ops: dupisr - inum: %x, " 67620036fe5Segillett "new_vector: %x\n", hdlp->ih_inum, hdlp->ih_scratch1); 67720036fe5Segillett 67820036fe5Segillett ret = pci_msix_dup(hdlp->ih_dip, hdlp->ih_inum, 67920036fe5Segillett hdlp->ih_scratch1); 6807c478bd9Sstevel@tonic-gate break; 6817c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 6827c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_getmsiq(dip, msi_num, 6837c478bd9Sstevel@tonic-gate &msiq_id)) != DDI_SUCCESS) 6847c478bd9Sstevel@tonic-gate return (ret); 6857c478bd9Sstevel@tonic-gate 686*09b1eac2SEvan Yan if ((ret = px_ib_update_intr_state(px_p, rdip, 687*09b1eac2SEvan Yan hdlp->ih_inum, px_msiqid_to_devino(px_p, msiq_id), 688*09b1eac2SEvan Yan hdlp->ih_pri, PX_INTR_STATE_DISABLE, msiq_rec_type, 689*09b1eac2SEvan Yan msi_num)) != DDI_SUCCESS) 690*09b1eac2SEvan Yan return (ret); 691*09b1eac2SEvan Yan 692*09b1eac2SEvan Yan if ((ret = px_lib_msi_setvalid(dip, msi_num, 693*09b1eac2SEvan Yan PCI_MSI_INVALID)) != DDI_SUCCESS) 694*09b1eac2SEvan Yan return (ret); 695*09b1eac2SEvan Yan 6967c478bd9Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 6979c75c6bfSgovinda PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) 6987c478bd9Sstevel@tonic-gate return (ret); 6997c478bd9Sstevel@tonic-gate 7007c478bd9Sstevel@tonic-gate ret = px_rem_msiq_intr(dip, rdip, 7019c75c6bfSgovinda hdlp, msiq_rec_type, msi_num, msiq_id); 7027c478bd9Sstevel@tonic-gate 7037c478bd9Sstevel@tonic-gate break; 704*09b1eac2SEvan Yan case DDI_INTROP_GETTARGET: 705*09b1eac2SEvan Yan if ((ret = px_lib_msi_getmsiq(dip, msi_num, 706*09b1eac2SEvan Yan &msiq_id)) != DDI_SUCCESS) 7077c478bd9Sstevel@tonic-gate return (ret); 7087c478bd9Sstevel@tonic-gate 709*09b1eac2SEvan Yan ret = px_ib_get_intr_target(px_p, 710*09b1eac2SEvan Yan px_msiqid_to_devino(px_p, msiq_id), (cpuid_t *)result); 711*09b1eac2SEvan Yan break; 712*09b1eac2SEvan Yan case DDI_INTROP_SETTARGET: 713*09b1eac2SEvan Yan ret = px_ib_set_msix_target(px_p, hdlp, msi_num, 714*09b1eac2SEvan Yan *(cpuid_t *)result); 715*09b1eac2SEvan Yan break; 716*09b1eac2SEvan Yan case DDI_INTROP_ENABLE: 717*09b1eac2SEvan Yan /* 718*09b1eac2SEvan Yan * curr_nenables will be greater than 0 if rdip is using 719*09b1eac2SEvan Yan * MSI-X and also, if it is using DUP interface. If this 720*09b1eac2SEvan Yan * curr_enables is > 1, return after clearing the mask bit. 721*09b1eac2SEvan Yan */ 722*09b1eac2SEvan Yan if ((pci_is_msi_enabled(rdip, hdlp->ih_type) == DDI_SUCCESS) && 723*09b1eac2SEvan Yan (i_ddi_intr_get_current_nenables(rdip) > 0)) { 724*09b1eac2SEvan Yan return (pci_msi_clr_mask(rdip, hdlp->ih_type, 725*09b1eac2SEvan Yan hdlp->ih_inum)); 7267c478bd9Sstevel@tonic-gate } 7277c478bd9Sstevel@tonic-gate 728*09b1eac2SEvan Yan nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 72936fe4a92Segillett 730*09b1eac2SEvan Yan if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 731*09b1eac2SEvan Yan nintrs, hdlp->ih_inum, msi_addr, 732*09b1eac2SEvan Yan hdlp->ih_type == DDI_INTR_TYPE_MSIX ? msi_num : 733*09b1eac2SEvan Yan msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 734*09b1eac2SEvan Yan return (ret); 73520036fe5Segillett 736*09b1eac2SEvan Yan if ((ret = pci_msi_enable_mode(rdip, 737*09b1eac2SEvan Yan hdlp->ih_type)) != DDI_SUCCESS) 73836fe4a92Segillett return (ret); 73936fe4a92Segillett 740*09b1eac2SEvan Yan if ((ret = pci_msi_clr_mask(rdip, hdlp->ih_type, 741*09b1eac2SEvan Yan hdlp->ih_inum)) != DDI_SUCCESS) 742*09b1eac2SEvan Yan return (ret); 7437c478bd9Sstevel@tonic-gate 7447c478bd9Sstevel@tonic-gate break; 7457c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 7467c478bd9Sstevel@tonic-gate if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type, 7477c478bd9Sstevel@tonic-gate hdlp->ih_inum)) != DDI_SUCCESS) 7487c478bd9Sstevel@tonic-gate return (ret); 7497c478bd9Sstevel@tonic-gate 750*09b1eac2SEvan Yan /* 751*09b1eac2SEvan Yan * curr_nenables will be greater than 1 if rdip is using 752*09b1eac2SEvan Yan * MSI-X and also, if it is using DUP interface. If this 753*09b1eac2SEvan Yan * curr_enables is > 1, return after setting the mask bit. 754*09b1eac2SEvan Yan */ 755*09b1eac2SEvan Yan if (i_ddi_intr_get_current_nenables(rdip) > 1) 756*09b1eac2SEvan Yan return (DDI_SUCCESS); 75720036fe5Segillett 758*09b1eac2SEvan Yan if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type)) 759*09b1eac2SEvan Yan != DDI_SUCCESS) 76036fe4a92Segillett return (ret); 76136fe4a92Segillett 7627c478bd9Sstevel@tonic-gate break; 7637c478bd9Sstevel@tonic-gate case DDI_INTROP_BLOCKENABLE: 7647c478bd9Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 7657c478bd9Sstevel@tonic-gate 7667c478bd9Sstevel@tonic-gate if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 7679c75c6bfSgovinda nintrs, hdlp->ih_inum, msi_addr, 7687c478bd9Sstevel@tonic-gate msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 7697c478bd9Sstevel@tonic-gate return (ret); 7707c478bd9Sstevel@tonic-gate 77195003185Segillett ret = pci_msi_enable_mode(rdip, hdlp->ih_type); 7727c478bd9Sstevel@tonic-gate break; 7737c478bd9Sstevel@tonic-gate case DDI_INTROP_BLOCKDISABLE: 774*09b1eac2SEvan Yan ret = pci_msi_disable_mode(rdip, hdlp->ih_type); 7757c478bd9Sstevel@tonic-gate break; 7767c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 7777c478bd9Sstevel@tonic-gate ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 7787c478bd9Sstevel@tonic-gate break; 7797c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 7807c478bd9Sstevel@tonic-gate ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 7817c478bd9Sstevel@tonic-gate break; 7827c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 7837c478bd9Sstevel@tonic-gate ret = pci_msi_get_pending(rdip, hdlp->ih_type, 7847c478bd9Sstevel@tonic-gate hdlp->ih_inum, (int *)result); 7857c478bd9Sstevel@tonic-gate break; 7867c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 7877c478bd9Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 7887c478bd9Sstevel@tonic-gate break; 7897c478bd9Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 7907c478bd9Sstevel@tonic-gate /* XXX - a new interface may be needed */ 7917c478bd9Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 7927c478bd9Sstevel@tonic-gate break; 7935febcb4aSScott Carter, SD IOSW case DDI_INTROP_GETPOOL: 7945febcb4aSScott Carter, SD IOSW if (msi_state_p->msi_pool_p == NULL) { 7955febcb4aSScott Carter, SD IOSW *(ddi_irm_pool_t **)result = NULL; 7965febcb4aSScott Carter, SD IOSW return (DDI_ENOTSUP); 7975febcb4aSScott Carter, SD IOSW } 7985febcb4aSScott Carter, SD IOSW *(ddi_irm_pool_t **)result = msi_state_p->msi_pool_p; 7995febcb4aSScott Carter, SD IOSW ret = DDI_SUCCESS; 8005febcb4aSScott Carter, SD IOSW break; 8017c478bd9Sstevel@tonic-gate default: 8027c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 8037c478bd9Sstevel@tonic-gate break; 8047c478bd9Sstevel@tonic-gate } 8057c478bd9Sstevel@tonic-gate 8067c478bd9Sstevel@tonic-gate return (ret); 8077c478bd9Sstevel@tonic-gate } 8087c478bd9Sstevel@tonic-gate 8096d44af1bSesolom static struct { 8106d44af1bSesolom kstat_named_t pxintr_ks_name; 8116d44af1bSesolom kstat_named_t pxintr_ks_type; 8126d44af1bSesolom kstat_named_t pxintr_ks_cpu; 8136d44af1bSesolom kstat_named_t pxintr_ks_pil; 8146d44af1bSesolom kstat_named_t pxintr_ks_time; 8156d44af1bSesolom kstat_named_t pxintr_ks_ino; 8166d44af1bSesolom kstat_named_t pxintr_ks_cookie; 8176d44af1bSesolom kstat_named_t pxintr_ks_devpath; 8186d44af1bSesolom kstat_named_t pxintr_ks_buspath; 8196d44af1bSesolom } pxintr_ks_template = { 8206d44af1bSesolom { "name", KSTAT_DATA_CHAR }, 8216d44af1bSesolom { "type", KSTAT_DATA_CHAR }, 8226d44af1bSesolom { "cpu", KSTAT_DATA_UINT64 }, 8236d44af1bSesolom { "pil", KSTAT_DATA_UINT64 }, 8246d44af1bSesolom { "time", KSTAT_DATA_UINT64 }, 8256d44af1bSesolom { "ino", KSTAT_DATA_UINT64 }, 8266d44af1bSesolom { "cookie", KSTAT_DATA_UINT64 }, 8276d44af1bSesolom { "devpath", KSTAT_DATA_STRING }, 8286d44af1bSesolom { "buspath", KSTAT_DATA_STRING }, 8296d44af1bSesolom }; 8306d44af1bSesolom 8316d44af1bSesolom static uint32_t pxintr_ks_instance; 832d48713b8Sesolom static char ih_devpath[MAXPATHLEN]; 833d48713b8Sesolom static char ih_buspath[MAXPATHLEN]; 8346d44af1bSesolom kmutex_t pxintr_ks_template_lock; 8356d44af1bSesolom 8366d44af1bSesolom int 8376d44af1bSesolom px_ks_update(kstat_t *ksp, int rw) 8386d44af1bSesolom { 8396d44af1bSesolom px_ih_t *ih_p = ksp->ks_private; 8406d44af1bSesolom int maxlen = sizeof (pxintr_ks_template.pxintr_ks_name.value.c); 841b0fc0e77Sgovinda px_ino_pil_t *ipil_p = ih_p->ih_ipil_p; 842b0fc0e77Sgovinda px_ino_t *ino_p = ipil_p->ipil_ino_p; 843b0fc0e77Sgovinda px_t *px_p = ino_p->ino_ib_p->ib_px_p; 8446d44af1bSesolom devino_t ino; 8456d44af1bSesolom sysino_t sysino; 8466d44af1bSesolom 847b0fc0e77Sgovinda ino = ino_p->ino_ino; 848d8d130aeSanbui if (px_lib_intr_devino_to_sysino(px_p->px_dip, ino, &sysino) != 849d8d130aeSanbui DDI_SUCCESS) { 850d8d130aeSanbui cmn_err(CE_WARN, "px_ks_update: px_lib_intr_devino_to_sysino " 851d8d130aeSanbui "failed"); 852d8d130aeSanbui } 8536d44af1bSesolom 8546d44af1bSesolom (void) snprintf(pxintr_ks_template.pxintr_ks_name.value.c, maxlen, 8556d44af1bSesolom "%s%d", ddi_driver_name(ih_p->ih_dip), 8566d44af1bSesolom ddi_get_instance(ih_p->ih_dip)); 8576d44af1bSesolom 8586d44af1bSesolom (void) ddi_pathname(ih_p->ih_dip, ih_devpath); 8596d44af1bSesolom (void) ddi_pathname(px_p->px_dip, ih_buspath); 8606d44af1bSesolom kstat_named_setstr(&pxintr_ks_template.pxintr_ks_devpath, ih_devpath); 8616d44af1bSesolom kstat_named_setstr(&pxintr_ks_template.pxintr_ks_buspath, ih_buspath); 8626d44af1bSesolom 863e1d9f4e6Sschwartz if (ih_p->ih_intr_state == PX_INTR_STATE_ENABLE) { 864e1d9f4e6Sschwartz 8652917a9c9Sschwartz switch (i_ddi_intr_get_current_type(ih_p->ih_dip)) { 8662917a9c9Sschwartz case DDI_INTR_TYPE_MSI: 8672917a9c9Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 8682917a9c9Sschwartz "msi"); 8692917a9c9Sschwartz break; 8702917a9c9Sschwartz case DDI_INTR_TYPE_MSIX: 8712917a9c9Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 8722917a9c9Sschwartz "msix"); 8732917a9c9Sschwartz break; 8742917a9c9Sschwartz default: 8752917a9c9Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 8762917a9c9Sschwartz "fixed"); 8772917a9c9Sschwartz break; 8782917a9c9Sschwartz } 8792917a9c9Sschwartz 880b0fc0e77Sgovinda pxintr_ks_template.pxintr_ks_cpu.value.ui64 = ino_p->ino_cpuid; 881b0fc0e77Sgovinda pxintr_ks_template.pxintr_ks_pil.value.ui64 = ipil_p->ipil_pil; 882e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_time.value.ui64 = ih_p->ih_nsec + 883e1d9f4e6Sschwartz (uint64_t)tick2ns((hrtime_t)ih_p->ih_ticks, 884b0fc0e77Sgovinda ino_p->ino_cpuid); 885e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_ino.value.ui64 = ino; 886e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cookie.value.ui64 = sysino; 887e1d9f4e6Sschwartz } else { 888e1d9f4e6Sschwartz (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 889e1d9f4e6Sschwartz "disabled"); 890e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cpu.value.ui64 = 0; 891e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_pil.value.ui64 = 0; 892e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_time.value.ui64 = 0; 893e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_ino.value.ui64 = 0; 894e1d9f4e6Sschwartz pxintr_ks_template.pxintr_ks_cookie.value.ui64 = 0; 895e1d9f4e6Sschwartz } 8966d44af1bSesolom return (0); 8976d44af1bSesolom } 8986d44af1bSesolom 8996d44af1bSesolom void 9006d44af1bSesolom px_create_intr_kstats(px_ih_t *ih_p) 9016d44af1bSesolom { 9026d44af1bSesolom msiq_rec_type_t rec_type = ih_p->ih_rec_type; 9036d44af1bSesolom 9046d44af1bSesolom ASSERT(ih_p->ih_ksp == NULL); 9056d44af1bSesolom 9066d44af1bSesolom /* 9076d44af1bSesolom * Create pci_intrs::: kstats for all ih types except messages, 9086d44af1bSesolom * which represent unusual conditions and don't need to be tracked. 9096d44af1bSesolom */ 9106d44af1bSesolom if (rec_type == 0 || rec_type == MSI32_REC || rec_type == MSI64_REC) { 9116d44af1bSesolom ih_p->ih_ksp = kstat_create("pci_intrs", 9126d44af1bSesolom atomic_inc_32_nv(&pxintr_ks_instance), "config", 9136d44af1bSesolom "interrupts", KSTAT_TYPE_NAMED, 9146d44af1bSesolom sizeof (pxintr_ks_template) / sizeof (kstat_named_t), 9156d44af1bSesolom KSTAT_FLAG_VIRTUAL); 9166d44af1bSesolom } 9176d44af1bSesolom if (ih_p->ih_ksp != NULL) { 9186d44af1bSesolom ih_p->ih_ksp->ks_data_size += MAXPATHLEN * 2; 9196d44af1bSesolom ih_p->ih_ksp->ks_lock = &pxintr_ks_template_lock; 9206d44af1bSesolom ih_p->ih_ksp->ks_data = &pxintr_ks_template; 9216d44af1bSesolom ih_p->ih_ksp->ks_private = ih_p; 9226d44af1bSesolom ih_p->ih_ksp->ks_update = px_ks_update; 9236d44af1bSesolom } 9246d44af1bSesolom } 9256d44af1bSesolom 926a195726fSgovinda /* 927a195726fSgovinda * px_add_intx_intr: 928a195726fSgovinda * 929a195726fSgovinda * This function is called to register INTx and legacy hardware 930a195726fSgovinda * interrupt pins interrupts. 931a195726fSgovinda */ 9327c478bd9Sstevel@tonic-gate int 9337c478bd9Sstevel@tonic-gate px_add_intx_intr(dev_info_t *dip, dev_info_t *rdip, 9347c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 9357c478bd9Sstevel@tonic-gate { 9367c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 9377c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 9387c478bd9Sstevel@tonic-gate devino_t ino; 9397c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 940b0fc0e77Sgovinda px_ino_t *ino_p; 941b0fc0e77Sgovinda px_ino_pil_t *ipil_p, *ipil_list; 9427c478bd9Sstevel@tonic-gate int32_t weight; 9437c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 9447c478bd9Sstevel@tonic-gate 9457c478bd9Sstevel@tonic-gate ino = hdlp->ih_vector; 9467c478bd9Sstevel@tonic-gate 9477c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: rdip=%s%d ino=%x " 9487c478bd9Sstevel@tonic-gate "handler=%x arg1=%x arg2=%x\n", ddi_driver_name(rdip), 9497c478bd9Sstevel@tonic-gate ddi_get_instance(rdip), ino, hdlp->ih_cb_func, 9507c478bd9Sstevel@tonic-gate hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 9517c478bd9Sstevel@tonic-gate 9527c478bd9Sstevel@tonic-gate ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, 9537c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0); 9547c478bd9Sstevel@tonic-gate 9557c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 9567c478bd9Sstevel@tonic-gate 957b0fc0e77Sgovinda ino_p = px_ib_locate_ino(ib_p, ino); 958b0fc0e77Sgovinda ipil_list = ino_p ? ino_p->ino_ipil_p : NULL; 959b0fc0e77Sgovinda 960b0fc0e77Sgovinda /* Sharing ino */ 961b0fc0e77Sgovinda if (ino_p && (ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) { 962b0fc0e77Sgovinda if (px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, 0, 0)) { 9637c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: " 964b0fc0e77Sgovinda "dup intr #%d\n", hdlp->ih_inum); 9657c478bd9Sstevel@tonic-gate 9667c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 9677c478bd9Sstevel@tonic-gate goto fail1; 9687c478bd9Sstevel@tonic-gate } 9697c478bd9Sstevel@tonic-gate 9707c478bd9Sstevel@tonic-gate /* Save mondo value in hdlp */ 9717c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 9727c478bd9Sstevel@tonic-gate 973b0fc0e77Sgovinda if ((ret = px_ib_ino_add_intr(px_p, ipil_p, 974b0fc0e77Sgovinda ih_p)) != DDI_SUCCESS) 9757c478bd9Sstevel@tonic-gate goto fail1; 9767c478bd9Sstevel@tonic-gate 977b0fc0e77Sgovinda goto ino_done; 978b0fc0e77Sgovinda } 9797c478bd9Sstevel@tonic-gate 980b0fc0e77Sgovinda if (hdlp->ih_pri == 0) 981614edcaeSEvan Yan hdlp->ih_pri = pci_class_to_pil(rdip); 9827c478bd9Sstevel@tonic-gate 983b0fc0e77Sgovinda ipil_p = px_ib_new_ino_pil(ib_p, ino, hdlp->ih_pri, ih_p); 984b0fc0e77Sgovinda ino_p = ipil_p->ipil_ino_p; 9857c478bd9Sstevel@tonic-gate 986b0fc0e77Sgovinda /* Save mondo value in hdlp */ 987b0fc0e77Sgovinda hdlp->ih_vector = ino_p->ino_sysino; 9887c478bd9Sstevel@tonic-gate 989b0fc0e77Sgovinda DBG(DBG_A_INTX, dip, "px_add_intx_intr: pil=0x%x mondo=0x%x\n", 990b0fc0e77Sgovinda hdlp->ih_pri, hdlp->ih_vector); 9917c478bd9Sstevel@tonic-gate 992b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 993b0fc0e77Sgovinda (ddi_intr_handler_t *)px_intx_intr, (caddr_t)ipil_p, NULL); 994b0fc0e77Sgovinda 995b0fc0e77Sgovinda ret = i_ddi_add_ivintr(hdlp); 9967c478bd9Sstevel@tonic-gate 997b0fc0e77Sgovinda /* 998b0fc0e77Sgovinda * Restore original interrupt handler 999b0fc0e77Sgovinda * and arguments in interrupt handle. 1000b0fc0e77Sgovinda */ 1001b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1002b0fc0e77Sgovinda ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 10037c478bd9Sstevel@tonic-gate 1004b0fc0e77Sgovinda if (ret != DDI_SUCCESS) 1005b0fc0e77Sgovinda goto fail2; 10067c478bd9Sstevel@tonic-gate 1007b0fc0e77Sgovinda /* Save the pil for this ino */ 1008b0fc0e77Sgovinda ipil_p->ipil_pil = hdlp->ih_pri; 1009b0fc0e77Sgovinda 1010b0fc0e77Sgovinda /* Select cpu, saving it for sharing and removal */ 1011b0fc0e77Sgovinda if (ipil_list == NULL) { 1012*09b1eac2SEvan Yan if (ino_p->ino_cpuid == -1) 1013*09b1eac2SEvan Yan ino_p->ino_cpuid = intr_dist_cpuid(); 10147c478bd9Sstevel@tonic-gate 10157c478bd9Sstevel@tonic-gate /* Enable interrupt */ 10167c478bd9Sstevel@tonic-gate px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 10177c478bd9Sstevel@tonic-gate } 10187c478bd9Sstevel@tonic-gate 1019b0fc0e77Sgovinda ino_done: 1020*09b1eac2SEvan Yan hdlp->ih_target = ino_p->ino_cpuid; 1021*09b1eac2SEvan Yan 1022b0fc0e77Sgovinda /* Add weight to the cpu that we are already targeting */ 1023614edcaeSEvan Yan weight = pci_class_to_intr_weight(rdip); 10247c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 10257c478bd9Sstevel@tonic-gate 1026b0fc0e77Sgovinda ih_p->ih_ipil_p = ipil_p; 10276d44af1bSesolom px_create_intr_kstats(ih_p); 10287c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp) 10297c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 10307c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 10317c478bd9Sstevel@tonic-gate 10327c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: done! Interrupt 0x%x pil=%x\n", 10337c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 10347c478bd9Sstevel@tonic-gate 10357c478bd9Sstevel@tonic-gate return (ret); 10367c478bd9Sstevel@tonic-gate fail2: 1037b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 10387c478bd9Sstevel@tonic-gate fail1: 10397c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 10407c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 10417c478bd9Sstevel@tonic-gate 10427c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 10437c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 10447c478bd9Sstevel@tonic-gate 10457c478bd9Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: Failed! Interrupt 0x%x " 10467c478bd9Sstevel@tonic-gate "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri); 10477c478bd9Sstevel@tonic-gate 10487c478bd9Sstevel@tonic-gate return (ret); 10497c478bd9Sstevel@tonic-gate } 10507c478bd9Sstevel@tonic-gate 1051a195726fSgovinda /* 1052a195726fSgovinda * px_rem_intx_intr: 1053a195726fSgovinda * 1054a195726fSgovinda * This function is called to unregister INTx and legacy hardware 1055a195726fSgovinda * interrupt pins interrupts. 1056a195726fSgovinda */ 10577c478bd9Sstevel@tonic-gate int 10587c478bd9Sstevel@tonic-gate px_rem_intx_intr(dev_info_t *dip, dev_info_t *rdip, 10597c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 10607c478bd9Sstevel@tonic-gate { 10617c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 10627c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 10637c478bd9Sstevel@tonic-gate devino_t ino; 10647c478bd9Sstevel@tonic-gate cpuid_t curr_cpu; 1065b0fc0e77Sgovinda px_ino_t *ino_p; 1066b0fc0e77Sgovinda px_ino_pil_t *ipil_p; 10677c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 10687c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 10697c478bd9Sstevel@tonic-gate 10707c478bd9Sstevel@tonic-gate ino = hdlp->ih_vector; 10717c478bd9Sstevel@tonic-gate 10727c478bd9Sstevel@tonic-gate DBG(DBG_R_INTX, dip, "px_rem_intx_intr: rdip=%s%d ino=%x\n", 10737c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 10747c478bd9Sstevel@tonic-gate 10757c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 10767c478bd9Sstevel@tonic-gate 10777c478bd9Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 1078b0fc0e77Sgovinda ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri); 1079b0fc0e77Sgovinda ih_p = px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, 0, 0); 10807c478bd9Sstevel@tonic-gate 10817c478bd9Sstevel@tonic-gate /* Get the current cpu */ 10827c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 10837c478bd9Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 10847c478bd9Sstevel@tonic-gate goto fail; 10857c478bd9Sstevel@tonic-gate 1086b0fc0e77Sgovinda if ((ret = px_ib_ino_rem_intr(px_p, ipil_p, ih_p)) != DDI_SUCCESS) 10877c478bd9Sstevel@tonic-gate goto fail; 10887c478bd9Sstevel@tonic-gate 10897c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 10907c478bd9Sstevel@tonic-gate 1091b0fc0e77Sgovinda if (ipil_p->ipil_ih_size == 0) { 10927c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 10937c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 10947c478bd9Sstevel@tonic-gate 1095b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 1096b0fc0e77Sgovinda } 1097b0fc0e77Sgovinda 1098b0fc0e77Sgovinda if (ino_p->ino_ipil_size == 0) { 1099b0fc0e77Sgovinda kmem_free(ino_p, sizeof (px_ino_t)); 11007c478bd9Sstevel@tonic-gate } else { 11010d2a6fcfSegillett /* Re-enable interrupt only if mapping register still shared */ 11020d2a6fcfSegillett PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 11037c478bd9Sstevel@tonic-gate } 11047c478bd9Sstevel@tonic-gate 11057c478bd9Sstevel@tonic-gate fail: 11067c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 11077c478bd9Sstevel@tonic-gate return (ret); 11087c478bd9Sstevel@tonic-gate } 11097c478bd9Sstevel@tonic-gate 1110a195726fSgovinda /* 1111a195726fSgovinda * px_add_msiq_intr: 1112a195726fSgovinda * 1113a195726fSgovinda * This function is called to register MSI/Xs and PCIe message interrupts. 1114a195726fSgovinda */ 11157c478bd9Sstevel@tonic-gate int 11167c478bd9Sstevel@tonic-gate px_add_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 11177c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 1118*09b1eac2SEvan Yan msgcode_t msg_code, cpuid_t cpu_id, msiqid_t *msiq_id_p) 11197c478bd9Sstevel@tonic-gate { 11207c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 11217c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 11227c478bd9Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &ib_p->ib_msiq_state; 11237c478bd9Sstevel@tonic-gate devino_t ino; 11247c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 1125b0fc0e77Sgovinda px_ino_t *ino_p; 1126b0fc0e77Sgovinda px_ino_pil_t *ipil_p, *ipil_list; 11277c478bd9Sstevel@tonic-gate int32_t weight; 11287c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 11297c478bd9Sstevel@tonic-gate 1130*09b1eac2SEvan Yan DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=0x%x " 1131*09b1eac2SEvan Yan "arg1=0x%x arg2=0x%x cpu=0x%x\n", ddi_driver_name(rdip), 1132*09b1eac2SEvan Yan ddi_get_instance(rdip), hdlp->ih_cb_func, hdlp->ih_cb_arg1, 1133*09b1eac2SEvan Yan hdlp->ih_cb_arg2, cpu_id); 11347c478bd9Sstevel@tonic-gate 1135*09b1eac2SEvan Yan ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func, 1136*09b1eac2SEvan Yan hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code); 1137*09b1eac2SEvan Yan 1138*09b1eac2SEvan Yan mutex_enter(&ib_p->ib_ino_lst_mutex); 1139*09b1eac2SEvan Yan 1140*09b1eac2SEvan Yan ret = (cpu_id == -1) ? px_msiq_alloc(px_p, rec_type, msiq_id_p) : 1141*09b1eac2SEvan Yan px_msiq_alloc_based_on_cpuid(px_p, rec_type, cpu_id, msiq_id_p); 1142*09b1eac2SEvan Yan 1143*09b1eac2SEvan Yan if (ret != DDI_SUCCESS) { 11447c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 11457c478bd9Sstevel@tonic-gate "msiq allocation failed\n"); 1146*09b1eac2SEvan Yan goto fail; 11477c478bd9Sstevel@tonic-gate } 11487c478bd9Sstevel@tonic-gate 11497c478bd9Sstevel@tonic-gate ino = px_msiqid_to_devino(px_p, *msiq_id_p); 11507c478bd9Sstevel@tonic-gate 1151b0fc0e77Sgovinda ino_p = px_ib_locate_ino(ib_p, ino); 1152b0fc0e77Sgovinda ipil_list = ino_p ? ino_p->ino_ipil_p : NULL; 1153b0fc0e77Sgovinda 1154b0fc0e77Sgovinda /* Sharing ino */ 1155b0fc0e77Sgovinda if (ino_p && (ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) { 1156b0fc0e77Sgovinda if (px_ib_intr_locate_ih(ipil_p, rdip, 1157b0fc0e77Sgovinda hdlp->ih_inum, rec_type, msg_code)) { 11587c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 1159b0fc0e77Sgovinda "dup intr #%d\n", hdlp->ih_inum); 11607c478bd9Sstevel@tonic-gate 11617c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 11627c478bd9Sstevel@tonic-gate goto fail1; 11637c478bd9Sstevel@tonic-gate } 11647c478bd9Sstevel@tonic-gate 1165b0fc0e77Sgovinda /* Save mondo value in hdlp */ 1166b0fc0e77Sgovinda hdlp->ih_vector = ino_p->ino_sysino; 1167b0fc0e77Sgovinda 1168b0fc0e77Sgovinda if ((ret = px_ib_ino_add_intr(px_p, ipil_p, 1169b0fc0e77Sgovinda ih_p)) != DDI_SUCCESS) 11707c478bd9Sstevel@tonic-gate goto fail1; 11717c478bd9Sstevel@tonic-gate 1172b0fc0e77Sgovinda goto ino_done; 1173b0fc0e77Sgovinda } 11747c478bd9Sstevel@tonic-gate 1175b0fc0e77Sgovinda if (hdlp->ih_pri == 0) 1176614edcaeSEvan Yan hdlp->ih_pri = pci_class_to_pil(rdip); 11777c478bd9Sstevel@tonic-gate 1178b0fc0e77Sgovinda ipil_p = px_ib_new_ino_pil(ib_p, ino, hdlp->ih_pri, ih_p); 1179b0fc0e77Sgovinda ino_p = ipil_p->ipil_ino_p; 11807c478bd9Sstevel@tonic-gate 1181b0fc0e77Sgovinda ino_p->ino_msiq_p = msiq_state_p->msiq_p + 1182b0fc0e77Sgovinda (*msiq_id_p - msiq_state_p->msiq_1st_msiq_id); 11837c478bd9Sstevel@tonic-gate 1184b0fc0e77Sgovinda /* Save mondo value in hdlp */ 1185b0fc0e77Sgovinda hdlp->ih_vector = ino_p->ino_sysino; 11867c478bd9Sstevel@tonic-gate 1187b0fc0e77Sgovinda DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n", 1188b0fc0e77Sgovinda hdlp->ih_pri, hdlp->ih_vector); 11897c478bd9Sstevel@tonic-gate 1190b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 1191b0fc0e77Sgovinda (ddi_intr_handler_t *)px_msiq_intr, (caddr_t)ipil_p, NULL); 1192b0fc0e77Sgovinda 1193b0fc0e77Sgovinda ret = i_ddi_add_ivintr(hdlp); 1194b0fc0e77Sgovinda 1195b0fc0e77Sgovinda /* 1196b0fc0e77Sgovinda * Restore original interrupt handler 1197b0fc0e77Sgovinda * and arguments in interrupt handle. 1198b0fc0e77Sgovinda */ 1199b0fc0e77Sgovinda DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1200b0fc0e77Sgovinda ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 12017c478bd9Sstevel@tonic-gate 1202b0fc0e77Sgovinda if (ret != DDI_SUCCESS) 1203b0fc0e77Sgovinda goto fail2; 12047c478bd9Sstevel@tonic-gate 1205b0fc0e77Sgovinda /* Save the pil for this ino */ 1206b0fc0e77Sgovinda ipil_p->ipil_pil = hdlp->ih_pri; 1207b0fc0e77Sgovinda 1208b0fc0e77Sgovinda /* Select cpu, saving it for sharing and removal */ 1209b0fc0e77Sgovinda if (ipil_list == NULL) { 12107c478bd9Sstevel@tonic-gate /* Enable MSIQ */ 12117c478bd9Sstevel@tonic-gate px_lib_msiq_setstate(dip, *msiq_id_p, PCI_MSIQ_STATE_IDLE); 12127c478bd9Sstevel@tonic-gate px_lib_msiq_setvalid(dip, *msiq_id_p, PCI_MSIQ_VALID); 12137c478bd9Sstevel@tonic-gate 1214*09b1eac2SEvan Yan if (ino_p->ino_cpuid == -1) 1215*09b1eac2SEvan Yan ino_p->ino_cpuid = intr_dist_cpuid(); 1216*09b1eac2SEvan Yan 12177c478bd9Sstevel@tonic-gate /* Enable interrupt */ 1218b0fc0e77Sgovinda px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 12197c478bd9Sstevel@tonic-gate } 12207c478bd9Sstevel@tonic-gate 1221b0fc0e77Sgovinda ino_done: 1222*09b1eac2SEvan Yan hdlp->ih_target = ino_p->ino_cpuid; 1223*09b1eac2SEvan Yan 1224b0fc0e77Sgovinda /* Add weight to the cpu that we are already targeting */ 1225614edcaeSEvan Yan weight = pci_class_to_intr_weight(rdip); 12267c478bd9Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 12277c478bd9Sstevel@tonic-gate 1228b0fc0e77Sgovinda ih_p->ih_ipil_p = ipil_p; 12296d44af1bSesolom px_create_intr_kstats(ih_p); 12307c478bd9Sstevel@tonic-gate if (ih_p->ih_ksp) 12317c478bd9Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 12327c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 12337c478bd9Sstevel@tonic-gate 12347c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n", 12357c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 12367c478bd9Sstevel@tonic-gate 12377c478bd9Sstevel@tonic-gate return (ret); 12387c478bd9Sstevel@tonic-gate fail2: 1239b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 12407c478bd9Sstevel@tonic-gate fail1: 1241*09b1eac2SEvan Yan (void) px_msiq_free(px_p, *msiq_id_p); 1242*09b1eac2SEvan Yan fail: 12437c478bd9Sstevel@tonic-gate if (ih_p->ih_config_handle) 12447c478bd9Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 12457c478bd9Sstevel@tonic-gate 12467c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 12477c478bd9Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 12487c478bd9Sstevel@tonic-gate 12497c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n", 12507c478bd9Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 12517c478bd9Sstevel@tonic-gate 12527c478bd9Sstevel@tonic-gate return (ret); 12537c478bd9Sstevel@tonic-gate } 12547c478bd9Sstevel@tonic-gate 1255a195726fSgovinda /* 1256a195726fSgovinda * px_rem_msiq_intr: 1257a195726fSgovinda * 1258a195726fSgovinda * This function is called to unregister MSI/Xs and PCIe message interrupts. 1259a195726fSgovinda */ 12607c478bd9Sstevel@tonic-gate int 12617c478bd9Sstevel@tonic-gate px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 12627c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 12637c478bd9Sstevel@tonic-gate msgcode_t msg_code, msiqid_t msiq_id) 12647c478bd9Sstevel@tonic-gate { 12657c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 12667c478bd9Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 12677c478bd9Sstevel@tonic-gate devino_t ino = px_msiqid_to_devino(px_p, msiq_id); 12687c478bd9Sstevel@tonic-gate cpuid_t curr_cpu; 1269b0fc0e77Sgovinda px_ino_t *ino_p; 1270b0fc0e77Sgovinda px_ino_pil_t *ipil_p; 12717c478bd9Sstevel@tonic-gate px_ih_t *ih_p; 12727c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 12737c478bd9Sstevel@tonic-gate 12747c478bd9Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n", 12757c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), msiq_id, ino); 12767c478bd9Sstevel@tonic-gate 12777c478bd9Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 12787c478bd9Sstevel@tonic-gate 12797c478bd9Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 1280b0fc0e77Sgovinda ipil_p = px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri); 1281b0fc0e77Sgovinda ih_p = px_ib_intr_locate_ih(ipil_p, rdip, hdlp->ih_inum, rec_type, 1282b0fc0e77Sgovinda msg_code); 12837c478bd9Sstevel@tonic-gate 12847c478bd9Sstevel@tonic-gate /* Get the current cpu */ 12857c478bd9Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 12867c478bd9Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 12877c478bd9Sstevel@tonic-gate goto fail; 12887c478bd9Sstevel@tonic-gate 1289b0fc0e77Sgovinda if ((ret = px_ib_ino_rem_intr(px_p, ipil_p, ih_p)) != DDI_SUCCESS) 12907c478bd9Sstevel@tonic-gate goto fail; 12917c478bd9Sstevel@tonic-gate 12927c478bd9Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 12937c478bd9Sstevel@tonic-gate 1294b0fc0e77Sgovinda if (ipil_p->ipil_ih_size == 0) { 12957c478bd9Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 12967c478bd9Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 12977c478bd9Sstevel@tonic-gate 1298b0fc0e77Sgovinda px_ib_delete_ino_pil(ib_p, ipil_p); 1299b0fc0e77Sgovinda 1300b0fc0e77Sgovinda if (ino_p->ino_ipil_size == 0) 1301b0fc0e77Sgovinda px_lib_msiq_setvalid(dip, 1302b0fc0e77Sgovinda px_devino_to_msiqid(px_p, ino), PCI_MSIQ_INVALID); 1303b0fc0e77Sgovinda } 1304b0fc0e77Sgovinda 1305*09b1eac2SEvan Yan (void) px_msiq_free(px_p, msiq_id); 1306*09b1eac2SEvan Yan 1307*09b1eac2SEvan Yan if (ino_p->ino_ipil_size) { 13080d2a6fcfSegillett /* Re-enable interrupt only if mapping register still shared */ 13090d2a6fcfSegillett PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 13107c478bd9Sstevel@tonic-gate } 13117c478bd9Sstevel@tonic-gate 13127c478bd9Sstevel@tonic-gate fail: 13137c478bd9Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 13147c478bd9Sstevel@tonic-gate return (ret); 13157c478bd9Sstevel@tonic-gate } 1316