xref: /illumos-gate/usr/src/uts/sun4/io/px/px_ib.h (revision c17ca212)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5b0fc0e77Sgovinda  * Common Development and Distribution License (the "License").
6b0fc0e77Sgovinda  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22*c17ca212SDavid Major  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
237c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate #ifndef	_SYS_PX_IB_H
267c478bd9Sstevel@tonic-gate #define	_SYS_PX_IB_H
287c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
297c478bd9Sstevel@tonic-gate extern "C" {
307c478bd9Sstevel@tonic-gate #endif
327c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h>
3369cd775fSschwartz #include <sys/pci_tools.h>
35b0fc0e77Sgovinda typedef struct px_ib		px_ib_t;
36b0fc0e77Sgovinda typedef struct px_ino		px_ino_t;
37b0fc0e77Sgovinda typedef struct px_ino_pil	px_ino_pil_t;
38b0fc0e77Sgovinda typedef struct px_ih		px_ih_t;
407c478bd9Sstevel@tonic-gate /*
417c478bd9Sstevel@tonic-gate  * interrupt block soft state structure:
427c478bd9Sstevel@tonic-gate  *
437c478bd9Sstevel@tonic-gate  * Each px node may share an interrupt block structure with its peer
447c478bd9Sstevel@tonic-gate  * node or have its own private interrupt block structure.
457c478bd9Sstevel@tonic-gate  */
467c478bd9Sstevel@tonic-gate struct px_ib {
477c478bd9Sstevel@tonic-gate 	px_t		*ib_px_p;	/* link back to px soft state */
48b0fc0e77Sgovinda 	px_ino_t	*ib_ino_lst;	/* ino link list */
497c478bd9Sstevel@tonic-gate 	kmutex_t	ib_ino_lst_mutex; /* mutex for ino link list */
507c478bd9Sstevel@tonic-gate 	kmutex_t	ib_intr_lock;	/* lock for internal intr  */
527c478bd9Sstevel@tonic-gate 	px_msiq_state_t	ib_msiq_state;	/* MSIQ soft state */
537c478bd9Sstevel@tonic-gate 	px_msi_state_t	ib_msi_state;	/* MSI soft state */
547c478bd9Sstevel@tonic-gate };
567c478bd9Sstevel@tonic-gate /*
57b0fc0e77Sgovinda  * ih structure: one per every consumer of each ino and pil pair with interrupt
58b0fc0e77Sgovinda  * registered.
597c478bd9Sstevel@tonic-gate  */
60b0fc0e77Sgovinda struct px_ih {
617c478bd9Sstevel@tonic-gate 	dev_info_t	*ih_dip;	/* devinfo structure */
627c478bd9Sstevel@tonic-gate 	uint32_t	ih_inum;	/* interrupt number for this device */
637c478bd9Sstevel@tonic-gate 	uint_t		(*ih_handler)(); /* interrupt handler */
647c478bd9Sstevel@tonic-gate 	caddr_t		ih_handler_arg1; /* interrupt handler argument #1 */
657c478bd9Sstevel@tonic-gate 	caddr_t		ih_handler_arg2; /* interrupt handler argument #2 */
667c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t ih_config_handle; /* config space reg map handle */
67b0fc0e77Sgovinda 	uint_t		ih_intr_state;	/* only used for fixed interrupts */
687c478bd9Sstevel@tonic-gate 	msiq_rec_type_t	ih_rec_type;	/* MSI or PCIe record type */
697c478bd9Sstevel@tonic-gate 	msgcode_t	ih_msg_code;	/* MSI number or PCIe message code */
70d17daf0bSScott Carter, SD IOSW 	uint8_t		ih_intr_flags;	/* interrupt handler status flags */
71b0fc0e77Sgovinda 	px_ih_t		*ih_next;	/* Next entry in list */
727c478bd9Sstevel@tonic-gate 	uint64_t	ih_ticks;	/* ticks spent in this handler */
737c478bd9Sstevel@tonic-gate 	uint64_t	ih_nsec;	/* nsec spent in this handler */
74b0fc0e77Sgovinda 	kstat_t		*ih_ksp;	/* pointer to kstat information */
75b0fc0e77Sgovinda 	px_ino_pil_t	*ih_ipil_p;	/* only for use by kstat */
76b0fc0e77Sgovinda };
787c478bd9Sstevel@tonic-gate /* Only used for fixed or legacy interrupts */
797c478bd9Sstevel@tonic-gate #define	PX_INTR_STATE_DISABLE	0	/* disabled */
807c478bd9Sstevel@tonic-gate #define	PX_INTR_STATE_ENABLE	1	/* enabled */
82d17daf0bSScott Carter, SD IOSW /* Only used for MSI/X to track interrupt handler status */
83d17daf0bSScott Carter, SD IOSW #define	PX_INTR_IDLE		0x0	/* handler is idle */
84d17daf0bSScott Carter, SD IOSW #define	PX_INTR_RETARGET	0x1	/* retarget in progress */
85d17daf0bSScott Carter, SD IOSW #define	PX_INTR_PENDING		0x2	/* handler is pending */
86d17daf0bSScott Carter, SD IOSW 
877c478bd9Sstevel@tonic-gate /*
88b0fc0e77Sgovinda  * ino_pil structure: one per each ino and pil pair with interrupt registered
89b0fc0e77Sgovinda  */
90b0fc0e77Sgovinda struct px_ino_pil {
91b0fc0e77Sgovinda 	ushort_t	ipil_pil;	/* pil for this ino */
92b0fc0e77Sgovinda 	ushort_t	ipil_ih_size;	/* size of px_ih_t list */
93b0fc0e77Sgovinda 	px_ih_t		*ipil_ih_head;	/* px_ih_t list head */
94b0fc0e77Sgovinda 	px_ih_t		*ipil_ih_tail;	/* px_ih_t list tail */
95b0fc0e77Sgovinda 	px_ih_t		*ipil_ih_start;	/* starting point in px_ih_t list  */
96b0fc0e77Sgovinda 	px_ino_t	*ipil_ino_p;	/* pointer to px_ino_t structure */
97b0fc0e77Sgovinda 	px_ino_pil_t	*ipil_next_p;	/* pointer to next px_ino_pil_t */
98b0fc0e77Sgovinda };
100b0fc0e77Sgovinda /*
101b0fc0e77Sgovinda  * ino structure: one per each ino with interrupt registered
1027c478bd9Sstevel@tonic-gate  */
103b0fc0e77Sgovinda struct px_ino {
1047c478bd9Sstevel@tonic-gate 	devino_t	ino_ino;	/* INO number - 8 bit */
1057c478bd9Sstevel@tonic-gate 	sysino_t	ino_sysino;	/* Virtual inumber */
1067c478bd9Sstevel@tonic-gate 	px_ib_t		*ino_ib_p;	/* link back to interrupt block state */
107b0fc0e77Sgovinda 	uint_t		ino_unclaimed_intrs; /* number of unclaimed intrs */
1087c478bd9Sstevel@tonic-gate 	clock_t		ino_spurintr_begin; /* begin time of spurious intr */
10909b1eac2SEvan Yan 	cpuid_t		ino_cpuid;	/* current cpu for this ino */
11009b1eac2SEvan Yan 	cpuid_t		ino_default_cpuid; /* default cpu for this ino */
1117c478bd9Sstevel@tonic-gate 	int32_t		ino_intr_weight; /* intr wt of devices sharing ino */
112b0fc0e77Sgovinda 	ushort_t	ino_ipil_size;	/* no of px_ino_pil_t sharing ino */
113b0fc0e77Sgovinda 	ushort_t	ino_lopil;	/* lowest pil sharing ino */
114b0fc0e77Sgovinda 	ushort_t	ino_claimed;	/* pil bit masks, who claimed intr */
115b0fc0e77Sgovinda 	px_msiq_t	*ino_msiq_p;	/* pointer to MSIQ used */
116b0fc0e77Sgovinda 	px_ino_pil_t	*ino_ipil_p;	/* pointer to first px_ino_pil_t */
117b0fc0e77Sgovinda 	px_ino_t	*ino_next_p;	/* pointer to next px_ino_t */
1184bd2626cSDaniel Ice 	ushort_t	ino_ipil_cntr;	/* counter for pil sharing ino */
1197c478bd9Sstevel@tonic-gate };
1217c478bd9Sstevel@tonic-gate #define	IB_INTR_WAIT	1		/* wait for interrupt completion */
1227c478bd9Sstevel@tonic-gate #define	IB_INTR_NOWAIT	0		/* already handling intr, no wait */
1247c478bd9Sstevel@tonic-gate #define	PX_INTR_ENABLE(dip, sysino, cpuid) \
12569cd775fSschwartz 	(void) px_lib_intr_settarget(dip, sysino, cpuid); \
12669cd775fSschwartz 	(void) px_lib_intr_setvalid(dip, sysino, INTR_VALID);
1287c478bd9Sstevel@tonic-gate #define	PX_INTR_DISABLE(dip, sysino) \
12969cd775fSschwartz 	(void) px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID);
1317c478bd9Sstevel@tonic-gate extern int px_ib_attach(px_t *px_p);
1327c478bd9Sstevel@tonic-gate extern void px_ib_detach(px_t *px_p);
1337c478bd9Sstevel@tonic-gate extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino);
1347c478bd9Sstevel@tonic-gate extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait);
135*c17ca212SDavid Major extern int px_ib_intr_pend(dev_info_t *dip, sysino_t sysino);
13669cd775fSschwartz extern void px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino,
13769cd775fSschwartz     boolean_t wait_flag);
139b0fc0e77Sgovinda extern px_ino_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num);
1407c478bd9Sstevel@tonic-gate extern void px_ib_free_ino_all(px_ib_t *ib_p);
142b0fc0e77Sgovinda extern px_ino_pil_t *px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil);
14309b1eac2SEvan Yan extern px_ino_t *px_ib_alloc_ino(px_ib_t *ib_p, devino_t ino_num);
144b0fc0e77Sgovinda extern px_ino_pil_t *px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num,
145b0fc0e77Sgovinda     uint_t pil, px_ih_t *ih_p);
146b0fc0e77Sgovinda extern void px_ib_delete_ino_pil(px_ib_t *ib_p, px_ino_pil_t *ipil_p);
147b0fc0e77Sgovinda extern int px_ib_ino_add_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
148b0fc0e77Sgovinda extern int px_ib_ino_rem_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
150b0fc0e77Sgovinda extern px_ih_t *px_ib_intr_locate_ih(px_ino_pil_t *ipil_p, dev_info_t *dip,
1517c478bd9Sstevel@tonic-gate 	uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code);
1527c478bd9Sstevel@tonic-gate extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
1537c478bd9Sstevel@tonic-gate 	uint_t (*int_handler)(caddr_t int_handler_arg1,
1547c478bd9Sstevel@tonic-gate 	caddr_t int_handler_arg2), caddr_t int_handler_arg1,
1557c478bd9Sstevel@tonic-gate 	caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code);
1567c478bd9Sstevel@tonic-gate extern void px_ib_free_ih(px_ih_t *ih_p);
1577c478bd9Sstevel@tonic-gate extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum,
158b0fc0e77Sgovinda 	devino_t ino, uint_t pil, uint_t new_intr_state,
159b0fc0e77Sgovinda 	msiq_rec_type_t rec_type, msgcode_t msg_code);
16009b1eac2SEvan Yan extern int px_ib_get_intr_target(px_t *px_p, devino_t ino, cpuid_t *cpu_id_p);
16109b1eac2SEvan Yan extern int px_ib_set_intr_target(px_t *px_p, devino_t ino, cpuid_t cpu_id);
16209b1eac2SEvan Yan extern int px_ib_set_msix_target(px_t *px_p, ddi_intr_handle_impl_t *hdlp,
16309b1eac2SEvan Yan 	msinum_t msi_num, cpuid_t cpuid);
16469cd775fSschwartz extern uint8_t pxtool_ib_get_ino_devs(px_t *px_p, uint32_t ino,
16509b1eac2SEvan Yan 	uint32_t msi_num, uint8_t *devs_ret, pcitool_intr_dev_t *devs);
16609b1eac2SEvan Yan extern int pxtool_ib_get_msi_info(px_t *px_p, devino_t ino, msinum_t msi_num,
16709b1eac2SEvan Yan 	ddi_intr_handle_impl_t *hdlp);
16809b1eac2SEvan Yan extern void px_ib_log_new_cpu(px_ib_t *ib_p, cpuid_t old_cpu_id,
16909b1eac2SEvan Yan 	cpuid_t new_cpu_id, uint32_t ino);
1717c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
1727c478bd9Sstevel@tonic-gate }
1737c478bd9Sstevel@tonic-gate #endif
1757c478bd9Sstevel@tonic-gate #endif	/* _SYS_PX_IB_H */