17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*b0fc0e77Sgovinda * Common Development and Distribution License (the "License"). 6*b0fc0e77Sgovinda * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22*b0fc0e77Sgovinda * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_PX_IB_H 277c478bd9Sstevel@tonic-gate #define _SYS_PX_IB_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #ifdef __cplusplus 327c478bd9Sstevel@tonic-gate extern "C" { 337c478bd9Sstevel@tonic-gate #endif 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h> 3669cd775fSschwartz #include <sys/pci_tools.h> 377c478bd9Sstevel@tonic-gate 38*b0fc0e77Sgovinda typedef struct px_ib px_ib_t; 39*b0fc0e77Sgovinda typedef struct px_ino px_ino_t; 40*b0fc0e77Sgovinda typedef struct px_ino_pil px_ino_pil_t; 41*b0fc0e77Sgovinda typedef struct px_ih px_ih_t; 427c478bd9Sstevel@tonic-gate 437c478bd9Sstevel@tonic-gate /* 447c478bd9Sstevel@tonic-gate * interrupt block soft state structure: 457c478bd9Sstevel@tonic-gate * 467c478bd9Sstevel@tonic-gate * Each px node may share an interrupt block structure with its peer 477c478bd9Sstevel@tonic-gate * node or have its own private interrupt block structure. 487c478bd9Sstevel@tonic-gate */ 497c478bd9Sstevel@tonic-gate struct px_ib { 507c478bd9Sstevel@tonic-gate px_t *ib_px_p; /* link back to px soft state */ 51*b0fc0e77Sgovinda px_ino_t *ib_ino_lst; /* ino link list */ 527c478bd9Sstevel@tonic-gate kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 537c478bd9Sstevel@tonic-gate kmutex_t ib_intr_lock; /* lock for internal intr */ 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate px_msiq_state_t ib_msiq_state; /* MSIQ soft state */ 567c478bd9Sstevel@tonic-gate px_msi_state_t ib_msi_state; /* MSI soft state */ 577c478bd9Sstevel@tonic-gate }; 587c478bd9Sstevel@tonic-gate 597c478bd9Sstevel@tonic-gate /* 60*b0fc0e77Sgovinda * ih structure: one per every consumer of each ino and pil pair with interrupt 61*b0fc0e77Sgovinda * registered. 627c478bd9Sstevel@tonic-gate */ 63*b0fc0e77Sgovinda struct px_ih { 647c478bd9Sstevel@tonic-gate dev_info_t *ih_dip; /* devinfo structure */ 657c478bd9Sstevel@tonic-gate uint32_t ih_inum; /* interrupt number for this device */ 667c478bd9Sstevel@tonic-gate uint_t (*ih_handler)(); /* interrupt handler */ 677c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 687c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 697c478bd9Sstevel@tonic-gate ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 70*b0fc0e77Sgovinda uint_t ih_intr_state; /* only used for fixed interrupts */ 717c478bd9Sstevel@tonic-gate msiq_rec_type_t ih_rec_type; /* MSI or PCIe record type */ 727c478bd9Sstevel@tonic-gate msgcode_t ih_msg_code; /* MSI number or PCIe message code */ 73*b0fc0e77Sgovinda px_ih_t *ih_next; /* Next entry in list */ 747c478bd9Sstevel@tonic-gate uint64_t ih_ticks; /* ticks spent in this handler */ 757c478bd9Sstevel@tonic-gate uint64_t ih_nsec; /* nsec spent in this handler */ 76*b0fc0e77Sgovinda kstat_t *ih_ksp; /* pointer to kstat information */ 77*b0fc0e77Sgovinda px_ino_pil_t *ih_ipil_p; /* only for use by kstat */ 78*b0fc0e77Sgovinda }; 797c478bd9Sstevel@tonic-gate 807c478bd9Sstevel@tonic-gate /* Only used for fixed or legacy interrupts */ 817c478bd9Sstevel@tonic-gate #define PX_INTR_STATE_DISABLE 0 /* disabled */ 827c478bd9Sstevel@tonic-gate #define PX_INTR_STATE_ENABLE 1 /* enabled */ 837c478bd9Sstevel@tonic-gate 847c478bd9Sstevel@tonic-gate /* 85*b0fc0e77Sgovinda * ino_pil structure: one per each ino and pil pair with interrupt registered 86*b0fc0e77Sgovinda */ 87*b0fc0e77Sgovinda struct px_ino_pil { 88*b0fc0e77Sgovinda ushort_t ipil_pil; /* pil for this ino */ 89*b0fc0e77Sgovinda ushort_t ipil_ih_size; /* size of px_ih_t list */ 90*b0fc0e77Sgovinda px_ih_t *ipil_ih_head; /* px_ih_t list head */ 91*b0fc0e77Sgovinda px_ih_t *ipil_ih_tail; /* px_ih_t list tail */ 92*b0fc0e77Sgovinda px_ih_t *ipil_ih_start; /* starting point in px_ih_t list */ 93*b0fc0e77Sgovinda px_ino_t *ipil_ino_p; /* pointer to px_ino_t structure */ 94*b0fc0e77Sgovinda px_ino_pil_t *ipil_next_p; /* pointer to next px_ino_pil_t */ 95*b0fc0e77Sgovinda }; 96*b0fc0e77Sgovinda 97*b0fc0e77Sgovinda /* 98*b0fc0e77Sgovinda * ino structure: one per each ino with interrupt registered 997c478bd9Sstevel@tonic-gate */ 100*b0fc0e77Sgovinda struct px_ino { 1017c478bd9Sstevel@tonic-gate devino_t ino_ino; /* INO number - 8 bit */ 1027c478bd9Sstevel@tonic-gate sysino_t ino_sysino; /* Virtual inumber */ 1037c478bd9Sstevel@tonic-gate px_ib_t *ino_ib_p; /* link back to interrupt block state */ 104*b0fc0e77Sgovinda uint_t ino_unclaimed_intrs; /* number of unclaimed intrs */ 1057c478bd9Sstevel@tonic-gate clock_t ino_spurintr_begin; /* begin time of spurious intr */ 1067c478bd9Sstevel@tonic-gate cpuid_t ino_cpuid; /* cpu that ino is targeting */ 1077c478bd9Sstevel@tonic-gate int32_t ino_intr_weight; /* intr wt of devices sharing ino */ 108*b0fc0e77Sgovinda ushort_t ino_ipil_size; /* no of px_ino_pil_t sharing ino */ 109*b0fc0e77Sgovinda ushort_t ino_lopil; /* lowest pil sharing ino */ 110*b0fc0e77Sgovinda ushort_t ino_claimed; /* pil bit masks, who claimed intr */ 111*b0fc0e77Sgovinda px_msiq_t *ino_msiq_p; /* pointer to MSIQ used */ 112*b0fc0e77Sgovinda px_ino_pil_t *ino_ipil_p; /* pointer to first px_ino_pil_t */ 113*b0fc0e77Sgovinda px_ino_t *ino_next_p; /* pointer to next px_ino_t */ 1147c478bd9Sstevel@tonic-gate }; 1157c478bd9Sstevel@tonic-gate 1167c478bd9Sstevel@tonic-gate #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 1177c478bd9Sstevel@tonic-gate #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate #define PX_INTR_ENABLE(dip, sysino, cpuid) \ 12069cd775fSschwartz (void) px_lib_intr_settarget(dip, sysino, cpuid); \ 12169cd775fSschwartz (void) px_lib_intr_setvalid(dip, sysino, INTR_VALID); 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate #define PX_INTR_DISABLE(dip, sysino) \ 12469cd775fSschwartz (void) px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID); 1257c478bd9Sstevel@tonic-gate 1267c478bd9Sstevel@tonic-gate extern int px_ib_attach(px_t *px_p); 1277c478bd9Sstevel@tonic-gate extern void px_ib_detach(px_t *px_p); 1287c478bd9Sstevel@tonic-gate extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino); 1297c478bd9Sstevel@tonic-gate extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait); 13069cd775fSschwartz extern void px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino, 13169cd775fSschwartz boolean_t wait_flag); 1327c478bd9Sstevel@tonic-gate 133*b0fc0e77Sgovinda extern px_ino_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num); 1347c478bd9Sstevel@tonic-gate extern void px_ib_free_ino_all(px_ib_t *ib_p); 135*b0fc0e77Sgovinda 136*b0fc0e77Sgovinda extern px_ino_pil_t *px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil); 137*b0fc0e77Sgovinda extern px_ino_pil_t *px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num, 138*b0fc0e77Sgovinda uint_t pil, px_ih_t *ih_p); 139*b0fc0e77Sgovinda extern void px_ib_delete_ino_pil(px_ib_t *ib_p, px_ino_pil_t *ipil_p); 140*b0fc0e77Sgovinda extern int px_ib_ino_add_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p); 141*b0fc0e77Sgovinda extern int px_ib_ino_rem_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p); 142*b0fc0e77Sgovinda 143*b0fc0e77Sgovinda extern px_ih_t *px_ib_intr_locate_ih(px_ino_pil_t *ipil_p, dev_info_t *dip, 1447c478bd9Sstevel@tonic-gate uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code); 1457c478bd9Sstevel@tonic-gate extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum, 1467c478bd9Sstevel@tonic-gate uint_t (*int_handler)(caddr_t int_handler_arg1, 1477c478bd9Sstevel@tonic-gate caddr_t int_handler_arg2), caddr_t int_handler_arg1, 1487c478bd9Sstevel@tonic-gate caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code); 1497c478bd9Sstevel@tonic-gate extern void px_ib_free_ih(px_ih_t *ih_p); 1507c478bd9Sstevel@tonic-gate extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum, 151*b0fc0e77Sgovinda devino_t ino, uint_t pil, uint_t new_intr_state, 152*b0fc0e77Sgovinda msiq_rec_type_t rec_type, msgcode_t msg_code); 153*b0fc0e77Sgovinda 15469cd775fSschwartz extern uint8_t pxtool_ib_get_ino_devs(px_t *px_p, uint32_t ino, 15569cd775fSschwartz uint8_t *devs_ret, pcitool_intr_dev_t *devs); 15669cd775fSschwartz extern void px_ib_log_new_cpu(px_ib_t *ib_p, uint32_t old_cpu_id, 15769cd775fSschwartz uint32_t new_cpu_id, uint32_t ino); 15869cd775fSschwartz 1597c478bd9Sstevel@tonic-gate 1607c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1617c478bd9Sstevel@tonic-gate } 1627c478bd9Sstevel@tonic-gate #endif 1637c478bd9Sstevel@tonic-gate 1647c478bd9Sstevel@tonic-gate #endif /* _SYS_PX_IB_H */ 165