17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #ifndef _SYS_PX_IB_H 287c478bd9Sstevel@tonic-gate #define _SYS_PX_IB_H 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #ifdef __cplusplus 337c478bd9Sstevel@tonic-gate extern "C" { 347c478bd9Sstevel@tonic-gate #endif 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h> 37*69cd775fSschwartz #include <sys/pci_tools.h> 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate typedef struct px_ib_ino_info px_ib_ino_info_t; 407c478bd9Sstevel@tonic-gate 417c478bd9Sstevel@tonic-gate /* 427c478bd9Sstevel@tonic-gate * interrupt block soft state structure: 437c478bd9Sstevel@tonic-gate * 447c478bd9Sstevel@tonic-gate * Each px node may share an interrupt block structure with its peer 457c478bd9Sstevel@tonic-gate * node or have its own private interrupt block structure. 467c478bd9Sstevel@tonic-gate */ 477c478bd9Sstevel@tonic-gate typedef struct px_ib px_ib_t; 487c478bd9Sstevel@tonic-gate struct px_ib { 497c478bd9Sstevel@tonic-gate px_t *ib_px_p; /* link back to px soft state */ 507c478bd9Sstevel@tonic-gate px_ib_ino_info_t *ib_ino_lst; /* ino link list */ 517c478bd9Sstevel@tonic-gate kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 527c478bd9Sstevel@tonic-gate kmutex_t ib_intr_lock; /* lock for internal intr */ 537c478bd9Sstevel@tonic-gate 547c478bd9Sstevel@tonic-gate px_msiq_state_t ib_msiq_state; /* MSIQ soft state */ 557c478bd9Sstevel@tonic-gate px_msi_state_t ib_msi_state; /* MSI soft state */ 567c478bd9Sstevel@tonic-gate }; 577c478bd9Sstevel@tonic-gate 587c478bd9Sstevel@tonic-gate /* 597c478bd9Sstevel@tonic-gate * The following structure represents an interrupt entry for an INO. 607c478bd9Sstevel@tonic-gate */ 617c478bd9Sstevel@tonic-gate typedef struct px_ih { 627c478bd9Sstevel@tonic-gate dev_info_t *ih_dip; /* devinfo structure */ 637c478bd9Sstevel@tonic-gate uint32_t ih_inum; /* interrupt number for this device */ 647c478bd9Sstevel@tonic-gate uint_t (*ih_handler)(); /* interrupt handler */ 657c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 667c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 677c478bd9Sstevel@tonic-gate ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 687c478bd9Sstevel@tonic-gate uint_t ih_intr_state; /* Only used for fixed interrupts */ 697c478bd9Sstevel@tonic-gate msiq_rec_type_t ih_rec_type; /* MSI or PCIe record type */ 707c478bd9Sstevel@tonic-gate msgcode_t ih_msg_code; /* MSI number or PCIe message code */ 717c478bd9Sstevel@tonic-gate struct px_ih *ih_next; /* next entry in list */ 727c478bd9Sstevel@tonic-gate uint64_t ih_ticks; /* ticks spent in this handler */ 737c478bd9Sstevel@tonic-gate uint64_t ih_nsec; /* nsec spent in this handler */ 747c478bd9Sstevel@tonic-gate kstat_t *ih_ksp; 757c478bd9Sstevel@tonic-gate struct px_ib_ino_info *ih_ino_p; /* only for use by kstat */ 767c478bd9Sstevel@tonic-gate } px_ih_t; 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate /* Only used for fixed or legacy interrupts */ 797c478bd9Sstevel@tonic-gate #define PX_INTR_STATE_DISABLE 0 /* disabled */ 807c478bd9Sstevel@tonic-gate #define PX_INTR_STATE_ENABLE 1 /* enabled */ 817c478bd9Sstevel@tonic-gate 827c478bd9Sstevel@tonic-gate /* 837c478bd9Sstevel@tonic-gate * ino structure : one per each ino with interrupt registered 847c478bd9Sstevel@tonic-gate */ 857c478bd9Sstevel@tonic-gate struct px_ib_ino_info { 867c478bd9Sstevel@tonic-gate devino_t ino_ino; /* INO number - 8 bit */ 877c478bd9Sstevel@tonic-gate sysino_t ino_sysino; /* Virtual inumber */ 887c478bd9Sstevel@tonic-gate uint16_t ino_ih_size; /* size of the px intrspec list */ 897c478bd9Sstevel@tonic-gate px_ih_t *ino_ih_head; /* intr spec (part of ppd) list head */ 907c478bd9Sstevel@tonic-gate px_ih_t *ino_ih_tail; /* intr spec (part of ppd) list tail */ 917c478bd9Sstevel@tonic-gate px_ih_t *ino_ih_start; /* starting point in intr spec list */ 927c478bd9Sstevel@tonic-gate px_ib_t *ino_ib_p; /* link back to interrupt block state */ 937c478bd9Sstevel@tonic-gate uint32_t ino_pil; /* PIL for this ino */ 947c478bd9Sstevel@tonic-gate uint_t ino_unclaimed; /* number of unclaimed interrupts */ 957c478bd9Sstevel@tonic-gate clock_t ino_spurintr_begin; /* begin time of spurious intr */ 967c478bd9Sstevel@tonic-gate cpuid_t ino_cpuid; /* cpu that ino is targeting */ 977c478bd9Sstevel@tonic-gate int32_t ino_intr_weight; /* intr wt of devices sharing ino */ 987c478bd9Sstevel@tonic-gate px_msiq_t *ino_msiq_p; /* Pointer to MSIQ used */ 997c478bd9Sstevel@tonic-gate struct px_ib_ino_info *ino_next; 1007c478bd9Sstevel@tonic-gate }; 1017c478bd9Sstevel@tonic-gate 1027c478bd9Sstevel@tonic-gate #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 1037c478bd9Sstevel@tonic-gate #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 1047c478bd9Sstevel@tonic-gate 1057c478bd9Sstevel@tonic-gate #define PX_INTR_ENABLE(dip, sysino, cpuid) \ 106*69cd775fSschwartz (void) px_lib_intr_settarget(dip, sysino, cpuid); \ 107*69cd775fSschwartz (void) px_lib_intr_setstate(dip, sysino, INTR_IDLE_STATE); \ 108*69cd775fSschwartz (void) px_lib_intr_setvalid(dip, sysino, INTR_VALID); 1097c478bd9Sstevel@tonic-gate 1107c478bd9Sstevel@tonic-gate #define PX_INTR_DISABLE(dip, sysino) \ 111*69cd775fSschwartz (void) px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID); 1127c478bd9Sstevel@tonic-gate 1137c478bd9Sstevel@tonic-gate extern int px_ib_attach(px_t *px_p); 1147c478bd9Sstevel@tonic-gate extern void px_ib_detach(px_t *px_p); 1157c478bd9Sstevel@tonic-gate extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino); 1167c478bd9Sstevel@tonic-gate extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait); 117*69cd775fSschwartz extern void px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino, 118*69cd775fSschwartz boolean_t wait_flag); 1197c478bd9Sstevel@tonic-gate 1207c478bd9Sstevel@tonic-gate extern px_ib_ino_info_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num); 1217c478bd9Sstevel@tonic-gate extern px_ib_ino_info_t *px_ib_new_ino(px_ib_t *ib_p, devino_t ino_num, 1227c478bd9Sstevel@tonic-gate px_ih_t *ih_p); 1237c478bd9Sstevel@tonic-gate extern void px_ib_delete_ino(px_ib_t *ib_p, px_ib_ino_info_t *ino_p); 1247c478bd9Sstevel@tonic-gate extern void px_ib_free_ino_all(px_ib_t *ib_p); 1257c478bd9Sstevel@tonic-gate extern int px_ib_ino_add_intr(px_t *px_p, px_ib_ino_info_t *ino_p, 1267c478bd9Sstevel@tonic-gate px_ih_t *ih_p); 1277c478bd9Sstevel@tonic-gate extern int px_ib_ino_rem_intr(px_t *px_p, px_ib_ino_info_t *ino_p, 1287c478bd9Sstevel@tonic-gate px_ih_t *ih_p); 1297c478bd9Sstevel@tonic-gate extern px_ih_t *px_ib_ino_locate_intr(px_ib_ino_info_t *ino_p, dev_info_t *dip, 1307c478bd9Sstevel@tonic-gate uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code); 1317c478bd9Sstevel@tonic-gate extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum, 1327c478bd9Sstevel@tonic-gate uint_t (*int_handler)(caddr_t int_handler_arg1, 1337c478bd9Sstevel@tonic-gate caddr_t int_handler_arg2), caddr_t int_handler_arg1, 1347c478bd9Sstevel@tonic-gate caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code); 1357c478bd9Sstevel@tonic-gate extern void px_ib_free_ih(px_ih_t *ih_p); 1367c478bd9Sstevel@tonic-gate extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum, 1377c478bd9Sstevel@tonic-gate devino_t ino, uint_t new_intr_state); 138*69cd775fSschwartz extern uint8_t pxtool_ib_get_ino_devs(px_t *px_p, uint32_t ino, 139*69cd775fSschwartz uint8_t *devs_ret, pcitool_intr_dev_t *devs); 140*69cd775fSschwartz extern void px_ib_log_new_cpu(px_ib_t *ib_p, uint32_t old_cpu_id, 141*69cd775fSschwartz uint32_t new_cpu_id, uint32_t ino); 142*69cd775fSschwartz 1437c478bd9Sstevel@tonic-gate 1447c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1457c478bd9Sstevel@tonic-gate } 1467c478bd9Sstevel@tonic-gate #endif 1477c478bd9Sstevel@tonic-gate 1487c478bd9Sstevel@tonic-gate #endif /* _SYS_PX_IB_H */ 149