xref: /illumos-gate/usr/src/uts/sun4/io/px/px_ib.c (revision 25cf1a30)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * PX Interrupt Block implementation
30  */
31 
32 #include <sys/types.h>
33 #include <sys/kmem.h>
34 #include <sys/async.h>
35 #include <sys/systm.h>		/* panicstr */
36 #include <sys/spl.h>
37 #include <sys/sunddi.h>
38 #include <sys/machsystm.h>	/* intr_dist_add */
39 #include <sys/ddi_impldefs.h>
40 #include <sys/cpuvar.h>
41 #include <sys/time.h>
42 #include "px_obj.h"
43 
44 /*LINTLIBRARY*/
45 
46 static void px_ib_intr_redist(void *arg, int32_t weight_max, int32_t weight);
47 static void px_ib_cpu_ticks_to_ih_nsec(px_ib_t *ib_p, px_ih_t *ih_p,
48     uint32_t cpu_id);
49 static uint_t px_ib_intr_reset(void *arg);
50 static void px_fill_in_intr_devs(pcitool_intr_dev_t *dev, char *driver_name,
51     char *path_name, int instance);
52 
53 extern uint64_t xc_tick_jump_limit;
54 
55 int
56 px_ib_attach(px_t *px_p)
57 {
58 	dev_info_t	*dip = px_p->px_dip;
59 	px_ib_t		*ib_p;
60 	sysino_t	sysino;
61 	px_fault_t	*fault_p = &px_p->px_fault;
62 
63 	DBG(DBG_IB, dip, "px_ib_attach\n");
64 
65 	if (px_lib_intr_devino_to_sysino(px_p->px_dip,
66 	    px_p->px_inos[PX_INTR_PEC], &sysino) != DDI_SUCCESS)
67 		return (DDI_FAILURE);
68 
69 	/*
70 	 * Allocate interrupt block state structure and link it to
71 	 * the px state structure.
72 	 */
73 	ib_p = kmem_zalloc(sizeof (px_ib_t), KM_SLEEP);
74 	px_p->px_ib_p = ib_p;
75 	ib_p->ib_px_p = px_p;
76 	ib_p->ib_ino_lst = (px_ib_ino_info_t *)NULL;
77 
78 	mutex_init(&ib_p->ib_intr_lock, NULL, MUTEX_DRIVER, NULL);
79 	mutex_init(&ib_p->ib_ino_lst_mutex, NULL, MUTEX_DRIVER, NULL);
80 
81 	bus_func_register(BF_TYPE_RESINTR, px_ib_intr_reset, ib_p);
82 
83 	intr_dist_add_weighted(px_ib_intr_redist, ib_p);
84 
85 	/*
86 	 * Initialize PEC fault data structure
87 	 */
88 	fault_p->px_fh_dip = dip;
89 	fault_p->px_fh_sysino = sysino;
90 	fault_p->px_err_func = px_err_dmc_pec_intr;
91 	fault_p->px_intr_ino = px_p->px_inos[PX_INTR_PEC];
92 
93 	return (DDI_SUCCESS);
94 }
95 
96 void
97 px_ib_detach(px_t *px_p)
98 {
99 	px_ib_t		*ib_p = px_p->px_ib_p;
100 	dev_info_t	*dip = px_p->px_dip;
101 
102 	DBG(DBG_IB, dip, "px_ib_detach\n");
103 
104 	bus_func_unregister(BF_TYPE_RESINTR, px_ib_intr_reset, ib_p);
105 	intr_dist_rem_weighted(px_ib_intr_redist, ib_p);
106 
107 	mutex_destroy(&ib_p->ib_ino_lst_mutex);
108 	mutex_destroy(&ib_p->ib_intr_lock);
109 
110 	px_ib_free_ino_all(ib_p);
111 
112 	px_p->px_ib_p = NULL;
113 	kmem_free(ib_p, sizeof (px_ib_t));
114 }
115 
116 void
117 px_ib_intr_enable(px_t *px_p, cpuid_t cpu_id, devino_t ino)
118 {
119 	px_ib_t		*ib_p = px_p->px_ib_p;
120 	sysino_t	sysino;
121 
122 	/*
123 	 * Determine the cpu for the interrupt
124 	 */
125 	mutex_enter(&ib_p->ib_intr_lock);
126 
127 	DBG(DBG_IB, px_p->px_dip,
128 	    "px_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id);
129 
130 	if (px_lib_intr_devino_to_sysino(px_p->px_dip, ino,
131 	    &sysino) != DDI_SUCCESS) {
132 		DBG(DBG_IB, px_p->px_dip,
133 		    "px_ib_intr_enable: px_intr_devino_to_sysino() failed\n");
134 
135 		mutex_exit(&ib_p->ib_intr_lock);
136 		return;
137 	}
138 
139 	PX_INTR_ENABLE(px_p->px_dip, sysino, cpu_id);
140 	px_lib_intr_setstate(px_p->px_dip, sysino, INTR_IDLE_STATE);
141 
142 	mutex_exit(&ib_p->ib_intr_lock);
143 }
144 
145 /*ARGSUSED*/
146 void
147 px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait)
148 {
149 	sysino_t	sysino;
150 
151 	mutex_enter(&ib_p->ib_intr_lock);
152 
153 	DBG(DBG_IB, ib_p->ib_px_p->px_dip, "px_ib_intr_disable: ino=%x\n", ino);
154 
155 	/* Disable the interrupt */
156 	if (px_lib_intr_devino_to_sysino(ib_p->ib_px_p->px_dip, ino,
157 	    &sysino) != DDI_SUCCESS) {
158 		DBG(DBG_IB, ib_p->ib_px_p->px_dip,
159 		    "px_ib_intr_disable: px_intr_devino_to_sysino() failed\n");
160 
161 		mutex_exit(&ib_p->ib_intr_lock);
162 		return;
163 	}
164 
165 	PX_INTR_DISABLE(ib_p->ib_px_p->px_dip, sysino);
166 
167 	mutex_exit(&ib_p->ib_intr_lock);
168 }
169 
170 
171 void
172 px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino,
173     boolean_t wait_flag)
174 {
175 	uint32_t	old_cpu_id;
176 	sysino_t	sysino;
177 	intr_valid_state_t	enabled = 0;
178 	hrtime_t	start_time, prev, curr, interval, jump;
179 	hrtime_t	intr_timeout;
180 	intr_state_t	intr_state;
181 	int		e = DDI_SUCCESS;
182 
183 	DBG(DBG_IB, dip, "px_ib_intr_dist_en: ino=0x%x\n", ino);
184 
185 	if (px_lib_intr_devino_to_sysino(dip, ino, &sysino) != DDI_SUCCESS) {
186 		DBG(DBG_IB, dip, "px_ib_intr_dist_en: "
187 		    "px_intr_devino_to_sysino() failed, ino 0x%x\n", ino);
188 		return;
189 	}
190 
191 	/* Skip enabling disabled interrupts */
192 	if (px_lib_intr_getvalid(dip, sysino, &enabled) != DDI_SUCCESS) {
193 		DBG(DBG_IB, dip, "px_ib_intr_dist_en: px_intr_getvalid() "
194 		    "failed, sysino 0x%x\n", sysino);
195 		return;
196 	}
197 	if (!enabled)
198 		return;
199 
200 	/* Done if redistributed onto the same cpuid */
201 	if (px_lib_intr_gettarget(dip, sysino, &old_cpu_id) != DDI_SUCCESS) {
202 		DBG(DBG_IB, dip, "px_ib_intr_dist_en: "
203 		    "px_intr_gettarget() failed\n");
204 		return;
205 	}
206 	if (cpu_id == old_cpu_id)
207 		return;
208 
209 	if (!wait_flag)
210 		goto done;
211 
212 	/* Busy wait on pending interrupts */
213 	PX_INTR_DISABLE(dip, sysino);
214 
215 	intr_timeout = px_intrpend_timeout;
216 	jump = TICK_TO_NSEC(xc_tick_jump_limit);
217 
218 	for (curr = start_time = gethrtime(); !panicstr &&
219 	    ((e = px_lib_intr_getstate(dip, sysino, &intr_state)) ==
220 		DDI_SUCCESS) &&
221 	    (intr_state == INTR_DELIVERED_STATE); /* */) {
222 		/*
223 		 * If we have a really large jump in hrtime, it is most
224 		 * probably because we entered the debugger (or OBP,
225 		 * in general). So, we adjust the timeout accordingly
226 		 * to prevent declaring an interrupt timeout. The
227 		 * master-interrupt mechanism in OBP should deliver
228 		 * the interrupts properly.
229 		 */
230 		prev = curr;
231 		curr = gethrtime();
232 		interval = curr - prev;
233 		if (interval > jump)
234 			intr_timeout += interval;
235 		if (curr - start_time > intr_timeout) {
236 			cmn_err(CE_WARN,
237 			    "%s%d: px_ib_intr_dist_en: sysino 0x%lx(ino 0x%x) "
238 			    "from cpu id 0x%x to 0x%x timeout",
239 			    ddi_driver_name(dip), ddi_get_instance(dip),
240 			    sysino, ino, old_cpu_id, cpu_id);
241 
242 			e = DDI_FAILURE;
243 			break;
244 		}
245 	}
246 
247 	if (e != DDI_SUCCESS)
248 		DBG(DBG_IB, dip, "px_ib_intr_dist_en: failed, "
249 		    "ino 0x%x sysino 0x%x\n", ino, sysino);
250 
251 done:
252 	PX_INTR_ENABLE(dip, sysino, cpu_id);
253 }
254 
255 static void
256 px_ib_cpu_ticks_to_ih_nsec(px_ib_t *ib_p, px_ih_t *ih_p, uint32_t cpu_id)
257 {
258 	extern kmutex_t pxintr_ks_template_lock;
259 	hrtime_t ticks;
260 
261 	/*
262 	 * Because we are updating two fields in ih_t we must lock
263 	 * pxintr_ks_template_lock to prevent someone from reading the
264 	 * kstats after we set ih_ticks to 0 and before we increment
265 	 * ih_nsec to compensate.
266 	 *
267 	 * We must also protect against the interrupt arriving and incrementing
268 	 * ih_ticks between the time we read it and when we reset it to 0.
269 	 * To do this we use atomic_swap.
270 	 */
271 
272 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
273 
274 	mutex_enter(&pxintr_ks_template_lock);
275 	ticks = atomic_swap_64(&ih_p->ih_ticks, 0);
276 	ih_p->ih_nsec += (uint64_t)tick2ns(ticks, cpu_id);
277 	mutex_exit(&pxintr_ks_template_lock);
278 }
279 
280 
281 /*
282  * Redistribute interrupts of the specified weight. The first call has a weight
283  * of weight_max, which can be used to trigger initialization for
284  * redistribution. The inos with weight [weight_max, inf.) should be processed
285  * on the "weight == weight_max" call.  This first call is followed by calls
286  * of decreasing weights, inos of that weight should be processed.  The final
287  * call specifies a weight of zero, this can be used to trigger processing of
288  * stragglers.
289  */
290 static void
291 px_ib_intr_redist(void *arg, int32_t weight_max, int32_t weight)
292 {
293 	px_ib_t		*ib_p = (px_ib_t *)arg;
294 	px_t		*px_p = ib_p->ib_px_p;
295 	dev_info_t	*dip = px_p->px_dip;
296 	px_ib_ino_info_t *ino_p;
297 	px_ih_t		*ih_lst;
298 	int32_t		dweight = 0;
299 	int		i;
300 
301 	/* Redistribute internal interrupts */
302 	if (weight == 0) {
303 		mutex_enter(&ib_p->ib_intr_lock);
304 		px_ib_intr_dist_en(dip, intr_dist_cpuid(),
305 		    px_p->px_inos[PX_INTR_PEC], B_FALSE);
306 		mutex_exit(&ib_p->ib_intr_lock);
307 
308 		px_cb_intr_redist(px_p);
309 	}
310 
311 	/* Redistribute device interrupts */
312 	mutex_enter(&ib_p->ib_ino_lst_mutex);
313 
314 	for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) {
315 		uint32_t orig_cpuid;
316 
317 		/*
318 		 * Recomputes the sum of interrupt weights of devices that
319 		 * share the same ino upon first call marked by
320 		 * (weight == weight_max).
321 		 */
322 		if (weight == weight_max) {
323 			ino_p->ino_intr_weight = 0;
324 			for (i = 0, ih_lst = ino_p->ino_ih_head;
325 			    i < ino_p->ino_ih_size;
326 			    i++, ih_lst = ih_lst->ih_next) {
327 				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
328 				if (dweight > 0)
329 					ino_p->ino_intr_weight += dweight;
330 			}
331 		}
332 
333 		/*
334 		 * As part of redistributing weighted interrupts over cpus,
335 		 * nexus redistributes device interrupts and updates
336 		 * cpu weight. The purpose is for the most light weighted
337 		 * cpu to take the next interrupt and gain weight, therefore
338 		 * attention demanding device gains more cpu attention by
339 		 * making itself heavy.
340 		 */
341 		if ((weight == ino_p->ino_intr_weight) ||
342 		    ((weight >= weight_max) &&
343 		    (ino_p->ino_intr_weight >= weight_max))) {
344 			orig_cpuid = ino_p->ino_cpuid;
345 			if (cpu[orig_cpuid] == NULL)
346 				orig_cpuid = CPU->cpu_id;
347 
348 			/* select cpuid to target and mark ino established */
349 			ino_p->ino_cpuid = intr_dist_cpuid();
350 
351 			/* Add device weight to targeted cpu. */
352 			for (i = 0, ih_lst = ino_p->ino_ih_head;
353 			    i < ino_p->ino_ih_size;
354 			    i++, ih_lst = ih_lst->ih_next) {
355 
356 				dweight = i_ddi_get_intr_weight(ih_lst->ih_dip);
357 				intr_dist_cpuid_add_device_weight(
358 				    ino_p->ino_cpuid, ih_lst->ih_dip, dweight);
359 
360 				/*
361 				 * Different cpus may have different clock
362 				 * speeds. to account for this, whenever an
363 				 * interrupt is moved to a new CPU, we
364 				 * convert the accumulated ticks into nsec,
365 				 * based upon the clock rate of the prior
366 				 * CPU.
367 				 *
368 				 * It is possible that the prior CPU no longer
369 				 * exists. In this case, fall back to using
370 				 * this CPU's clock rate.
371 				 *
372 				 * Note that the value in ih_ticks has already
373 				 * been corrected for any power savings mode
374 				 * which might have been in effect.
375 				 */
376 				px_ib_cpu_ticks_to_ih_nsec(ib_p, ih_lst,
377 				    orig_cpuid);
378 			}
379 
380 			/* enable interrupt on new targeted cpu */
381 			px_ib_intr_dist_en(dip, ino_p->ino_cpuid,
382 			    ino_p->ino_ino, B_TRUE);
383 		}
384 	}
385 	mutex_exit(&ib_p->ib_ino_lst_mutex);
386 }
387 
388 /*
389  * Reset interrupts to IDLE.  This function is called during
390  * panic handling after redistributing interrupts; it's needed to
391  * support dumping to network devices after 'sync' from OBP.
392  *
393  * N.B.  This routine runs in a context where all other threads
394  * are permanently suspended.
395  */
396 static uint_t
397 px_ib_intr_reset(void *arg)
398 {
399 	px_ib_t		*ib_p = (px_ib_t *)arg;
400 
401 	DBG(DBG_IB, ib_p->ib_px_p->px_dip, "px_ib_intr_reset\n");
402 
403 	if (px_lib_intr_reset(ib_p->ib_px_p->px_dip) != DDI_SUCCESS)
404 		return (BF_FATAL);
405 
406 	return (BF_NONE);
407 }
408 
409 /*
410  * Locate ino_info structure on ib_p->ib_ino_lst according to ino#
411  * returns NULL if not found.
412  */
413 px_ib_ino_info_t *
414 px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num)
415 {
416 	px_ib_ino_info_t	*ino_p = ib_p->ib_ino_lst;
417 
418 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
419 
420 	for (; ino_p && ino_p->ino_ino != ino_num; ino_p = ino_p->ino_next);
421 
422 	return (ino_p);
423 }
424 
425 px_ib_ino_info_t *
426 px_ib_new_ino(px_ib_t *ib_p, devino_t ino_num, px_ih_t *ih_p)
427 {
428 	px_ib_ino_info_t	*ino_p = kmem_alloc(sizeof (px_ib_ino_info_t),
429 	    KM_SLEEP);
430 	sysino_t	sysino;
431 
432 	ino_p->ino_ino = ino_num;
433 	ino_p->ino_ib_p = ib_p;
434 	ino_p->ino_unclaimed = 0;
435 
436 	if (px_lib_intr_devino_to_sysino(ib_p->ib_px_p->px_dip, ino_p->ino_ino,
437 	    &sysino) != DDI_SUCCESS)
438 		return (NULL);
439 
440 	ino_p->ino_sysino = sysino;
441 
442 	/*
443 	 * Cannot disable interrupt since we might share slot
444 	 */
445 	ih_p->ih_next = ih_p;
446 	ino_p->ino_ih_head = ih_p;
447 	ino_p->ino_ih_tail = ih_p;
448 	ino_p->ino_ih_start = ih_p;
449 	ino_p->ino_ih_size = 1;
450 
451 	ino_p->ino_next = ib_p->ib_ino_lst;
452 	ib_p->ib_ino_lst = ino_p;
453 
454 	return (ino_p);
455 }
456 
457 /*
458  * The ino_p is retrieved by previous call to px_ib_locate_ino().
459  */
460 void
461 px_ib_delete_ino(px_ib_t *ib_p, px_ib_ino_info_t *ino_p)
462 {
463 	px_ib_ino_info_t	*list = ib_p->ib_ino_lst;
464 
465 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
466 
467 	if (list == ino_p)
468 		ib_p->ib_ino_lst = list->ino_next;
469 	else {
470 		for (; list->ino_next != ino_p; list = list->ino_next);
471 		list->ino_next = ino_p->ino_next;
472 	}
473 }
474 
475 /*
476  * Free all ino when we are detaching.
477  */
478 void
479 px_ib_free_ino_all(px_ib_t *ib_p)
480 {
481 	px_ib_ino_info_t	*tmp = ib_p->ib_ino_lst;
482 	px_ib_ino_info_t	*next = NULL;
483 
484 	while (tmp) {
485 		next = tmp->ino_next;
486 		kmem_free(tmp, sizeof (px_ib_ino_info_t));
487 		tmp = next;
488 	}
489 }
490 
491 int
492 px_ib_ino_add_intr(px_t *px_p, px_ib_ino_info_t *ino_p, px_ih_t *ih_p)
493 {
494 	px_ib_t		*ib_p = ino_p->ino_ib_p;
495 	devino_t	ino = ino_p->ino_ino;
496 	sysino_t	sysino = ino_p->ino_sysino;
497 	dev_info_t	*dip = px_p->px_dip;
498 	cpuid_t		curr_cpu;
499 	hrtime_t	start_time;
500 	intr_state_t	intr_state;
501 	int		ret = DDI_SUCCESS;
502 
503 	ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex));
504 	ASSERT(ib_p == px_p->px_ib_p);
505 
506 	DBG(DBG_IB, dip, "px_ib_ino_add_intr ino=%x\n", ino_p->ino_ino);
507 
508 	/* Disable the interrupt */
509 	if ((ret = px_lib_intr_gettarget(dip, sysino,
510 	    &curr_cpu)) != DDI_SUCCESS) {
511 		DBG(DBG_IB, dip,
512 		    "px_ib_ino_add_intr px_intr_gettarget() failed\n");
513 
514 		return (ret);
515 	}
516 
517 	PX_INTR_DISABLE(dip, sysino);
518 
519 	/* Busy wait on pending interrupt */
520 	for (start_time = gethrtime(); !panicstr &&
521 	    ((ret = px_lib_intr_getstate(dip, sysino, &intr_state))
522 	    == DDI_SUCCESS) && (intr_state == INTR_DELIVERED_STATE); /* */) {
523 		if (gethrtime() - start_time > px_intrpend_timeout) {
524 			cmn_err(CE_WARN, "%s%d: px_ib_ino_add_intr: pending "
525 			    "sysino 0x%lx(ino 0x%x) timeout",
526 			    ddi_driver_name(dip), ddi_get_instance(dip),
527 			    sysino, ino);
528 
529 			ret = DDI_FAILURE;
530 			break;
531 		}
532 	}
533 
534 	if (ret != DDI_SUCCESS) {
535 		DBG(DBG_IB, dip, "px_ib_ino_add_intr: failed, "
536 		    "ino 0x%x sysino 0x%x\n", ino, sysino);
537 
538 		return (ret);
539 	}
540 
541 	/* Link up px_ispec_t portion of the ppd */
542 	ih_p->ih_next = ino_p->ino_ih_head;
543 	ino_p->ino_ih_tail->ih_next = ih_p;
544 	ino_p->ino_ih_tail = ih_p;
545 
546 	ino_p->ino_ih_start = ino_p->ino_ih_head;
547 	ino_p->ino_ih_size++;
548 
549 	/*
550 	 * If the interrupt was previously blocked (left in pending state)
551 	 * because of jabber we need to clear the pending state in case the
552 	 * jabber has gone away.
553 	 */
554 	if (ino_p->ino_unclaimed > px_unclaimed_intr_max) {
555 		cmn_err(CE_WARN,
556 		    "%s%d: px_ib_ino_add_intr: ino 0x%x has been unblocked",
557 		    ddi_driver_name(dip), ddi_get_instance(dip), ino);
558 
559 		ino_p->ino_unclaimed = 0;
560 		if ((ret = px_lib_intr_setstate(dip, sysino,
561 		    INTR_IDLE_STATE)) != DDI_SUCCESS) {
562 			DBG(DBG_IB, px_p->px_dip,
563 			    "px_ib_ino_add_intr px_intr_setstate failed\n");
564 
565 			return (ret);
566 		}
567 	}
568 
569 	/* Re-enable interrupt */
570 	PX_INTR_ENABLE(dip, sysino, curr_cpu);
571 
572 	return (ret);
573 }
574 
575 /*
576  * Removes px_ispec_t from the ino's link list.
577  * uses hardware mutex to lock out interrupt threads.
578  * Side effects: interrupt belongs to that ino is turned off on return.
579  * if we are sharing PX slot with other inos, the caller needs
580  * to turn it back on.
581  */
582 int
583 px_ib_ino_rem_intr(px_t *px_p, px_ib_ino_info_t *ino_p, px_ih_t *ih_p)
584 {
585 	devino_t	ino = ino_p->ino_ino;
586 	sysino_t	sysino = ino_p->ino_sysino;
587 	dev_info_t	*dip = px_p->px_dip;
588 	px_ih_t		*ih_lst = ino_p->ino_ih_head;
589 	hrtime_t	start_time;
590 	intr_state_t	intr_state;
591 	int		i, ret = DDI_SUCCESS;
592 
593 	ASSERT(MUTEX_HELD(&ino_p->ino_ib_p->ib_ino_lst_mutex));
594 
595 	DBG(DBG_IB, px_p->px_dip, "px_ib_ino_rem_intr ino=%x\n",
596 	    ino_p->ino_ino);
597 
598 	/* Disable the interrupt */
599 	PX_INTR_DISABLE(px_p->px_dip, sysino);
600 
601 	if (ino_p->ino_ih_size == 1) {
602 		if (ih_lst != ih_p)
603 			goto not_found;
604 
605 		/* No need to set head/tail as ino_p will be freed */
606 		goto reset;
607 	}
608 
609 	/* Busy wait on pending interrupt */
610 	for (start_time = gethrtime(); !panicstr &&
611 	    ((ret = px_lib_intr_getstate(dip, sysino, &intr_state))
612 	    == DDI_SUCCESS) && (intr_state == INTR_DELIVERED_STATE); /* */) {
613 		if (gethrtime() - start_time > px_intrpend_timeout) {
614 			cmn_err(CE_WARN, "%s%d: px_ib_ino_rem_intr: pending "
615 			    "sysino 0x%lx(ino 0x%x) timeout",
616 			    ddi_driver_name(dip), ddi_get_instance(dip),
617 			    sysino, ino);
618 
619 			ret = DDI_FAILURE;
620 			break;
621 		}
622 	}
623 
624 	if (ret != DDI_SUCCESS) {
625 		DBG(DBG_IB, dip, "px_ib_ino_rem_intr: failed, "
626 		    "ino 0x%x sysino 0x%x\n", ino, sysino);
627 
628 		return (ret);
629 	}
630 
631 	/*
632 	 * If the interrupt was previously blocked (left in pending state)
633 	 * because of jabber we need to clear the pending state in case the
634 	 * jabber has gone away.
635 	 */
636 	if (ino_p->ino_unclaimed > px_unclaimed_intr_max) {
637 		cmn_err(CE_WARN, "%s%d: px_ib_ino_rem_intr: "
638 		    "ino 0x%x has been unblocked",
639 		    ddi_driver_name(dip), ddi_get_instance(dip), ino);
640 
641 		ino_p->ino_unclaimed = 0;
642 		if ((ret = px_lib_intr_setstate(dip, sysino,
643 		    INTR_IDLE_STATE)) != DDI_SUCCESS) {
644 			DBG(DBG_IB, px_p->px_dip,
645 			    "px_ib_ino_rem_intr px_intr_setstate failed\n");
646 
647 			return (ret);
648 		}
649 	}
650 
651 	/* Search the link list for ih_p */
652 	for (i = 0; (i < ino_p->ino_ih_size) &&
653 	    (ih_lst->ih_next != ih_p); i++, ih_lst = ih_lst->ih_next);
654 
655 	if (ih_lst->ih_next != ih_p)
656 		goto not_found;
657 
658 	/* Remove ih_p from the link list and maintain the head/tail */
659 	ih_lst->ih_next = ih_p->ih_next;
660 
661 	if (ino_p->ino_ih_head == ih_p)
662 		ino_p->ino_ih_head = ih_p->ih_next;
663 	if (ino_p->ino_ih_tail == ih_p)
664 		ino_p->ino_ih_tail = ih_lst;
665 
666 	ino_p->ino_ih_start = ino_p->ino_ih_head;
667 
668 reset:
669 	if (ih_p->ih_config_handle)
670 		pci_config_teardown(&ih_p->ih_config_handle);
671 	if (ih_p->ih_ksp != NULL)
672 		kstat_delete(ih_p->ih_ksp);
673 
674 	kmem_free(ih_p, sizeof (px_ih_t));
675 	ino_p->ino_ih_size--;
676 
677 	return (ret);
678 
679 not_found:
680 	DBG(DBG_R_INTX, ino_p->ino_ib_p->ib_px_p->px_dip,
681 		"ino_p=%x does not have ih_p=%x\n", ino_p, ih_p);
682 
683 	return (DDI_FAILURE);
684 }
685 
686 px_ih_t *
687 px_ib_ino_locate_intr(px_ib_ino_info_t *ino_p, dev_info_t *rdip,
688     uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code)
689 {
690 	px_ih_t	*ih_lst = ino_p->ino_ih_head;
691 	int	i;
692 
693 	for (i = 0; i < ino_p->ino_ih_size; i++, ih_lst = ih_lst->ih_next) {
694 		if ((ih_lst->ih_dip == rdip) && (ih_lst->ih_inum == inum) &&
695 		    (ih_lst->ih_rec_type == rec_type) &&
696 		    (ih_lst->ih_msg_code == msg_code))
697 			return (ih_lst);
698 	}
699 
700 	return ((px_ih_t *)NULL);
701 }
702 
703 px_ih_t *
704 px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
705     uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
706     caddr_t int_handler_arg1, caddr_t int_handler_arg2,
707     msiq_rec_type_t rec_type, msgcode_t msg_code)
708 {
709 	px_ih_t	*ih_p;
710 
711 	ih_p = kmem_alloc(sizeof (px_ih_t), KM_SLEEP);
712 	ih_p->ih_dip = rdip;
713 	ih_p->ih_inum = inum;
714 	ih_p->ih_intr_state = PX_INTR_STATE_DISABLE;
715 	ih_p->ih_handler = int_handler;
716 	ih_p->ih_handler_arg1 = int_handler_arg1;
717 	ih_p->ih_handler_arg2 = int_handler_arg2;
718 	ih_p->ih_config_handle = NULL;
719 	ih_p->ih_rec_type = rec_type;
720 	ih_p->ih_msg_code = msg_code;
721 	ih_p->ih_nsec = 0;
722 	ih_p->ih_ticks = 0;
723 	ih_p->ih_ksp = NULL;
724 
725 	return (ih_p);
726 }
727 
728 int
729 px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip,
730     uint_t inum, devino_t ino, uint_t new_intr_state,
731     msiq_rec_type_t rec_type, msgcode_t msg_code)
732 {
733 	px_ib_t		*ib_p = px_p->px_ib_p;
734 	px_ib_ino_info_t *ino_p;
735 	px_ih_t		*ih_p;
736 	int		ret = DDI_FAILURE;
737 
738 	DBG(DBG_IB, px_p->px_dip, "ib_update_intr_state: %s%d "
739 	    "inum %x devino %x state %x\n", ddi_driver_name(rdip),
740 	    ddi_get_instance(rdip), inum, ino, new_intr_state);
741 
742 	mutex_enter(&ib_p->ib_ino_lst_mutex);
743 
744 	if (ino_p = px_ib_locate_ino(ib_p, ino)) {
745 		if (ih_p = px_ib_ino_locate_intr(ino_p, rdip, inum, rec_type,
746 		    msg_code)) {
747 			ih_p->ih_intr_state = new_intr_state;
748 			ret = DDI_SUCCESS;
749 		}
750 	}
751 
752 	mutex_exit(&ib_p->ib_ino_lst_mutex);
753 	return (ret);
754 }
755 
756 
757 static void
758 px_fill_in_intr_devs(pcitool_intr_dev_t *dev, char *driver_name,
759     char *path_name, int instance)
760 {
761 	(void) strncpy(dev->driver_name, driver_name, MAXMODCONFNAME-1);
762 	dev->driver_name[MAXMODCONFNAME] = '\0';
763 	(void) strncpy(dev->path, path_name, MAXPATHLEN-1);
764 	dev->dev_inst = instance;
765 }
766 
767 
768 /*
769  * Return the dips or number of dips associated with a given interrupt block.
770  * Size of dips array arg is passed in as dips_ret arg.
771  * Number of dips returned is returned in dips_ret arg.
772  * Array of dips gets returned in the dips argument.
773  * Function returns number of dips existing for the given interrupt block.
774  *
775  * Note: this function assumes an enabled/valid INO, which is why it returns
776  * the px node and (Internal) when it finds no other devices (and *devs_ret > 0)
777  */
778 uint8_t
779 pxtool_ib_get_ino_devs(
780     px_t *px_p, uint32_t ino, uint8_t *devs_ret, pcitool_intr_dev_t *devs)
781 {
782 	px_ib_t *ib_p = px_p->px_ib_p;
783 	px_ib_ino_info_t *ino_p;
784 	px_ih_t *ih_p;
785 	uint32_t num_devs = 0;
786 	char pathname[MAXPATHLEN];
787 	int i;
788 
789 	mutex_enter(&ib_p->ib_ino_lst_mutex);
790 	ino_p = px_ib_locate_ino(ib_p, ino);
791 	if (ino_p != NULL) {
792 		num_devs = ino_p->ino_ih_size;
793 		for (i = 0, ih_p = ino_p->ino_ih_head;
794 		    ((i < ino_p->ino_ih_size) && (i < *devs_ret));
795 		    i++, ih_p = ih_p->ih_next) {
796 			(void) ddi_pathname(ih_p->ih_dip, pathname);
797 			px_fill_in_intr_devs(&devs[i],
798 			    (char *)ddi_driver_name(ih_p->ih_dip),  pathname,
799 			    ddi_get_instance(ih_p->ih_dip));
800 		}
801 		*devs_ret = i;
802 
803 	} else if (*devs_ret > 0) {
804 		(void) ddi_pathname(px_p->px_dip, pathname);
805 		strcat(pathname, " (Internal)");
806 		px_fill_in_intr_devs(&devs[0],
807 		    (char *)ddi_driver_name(px_p->px_dip),  pathname,
808 		    ddi_get_instance(px_p->px_dip));
809 		num_devs = *devs_ret = 1;
810 	}
811 
812 	mutex_exit(&ib_p->ib_ino_lst_mutex);
813 
814 	return (num_devs);
815 }
816 
817 
818 void
819 px_ib_log_new_cpu(px_ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id,
820     uint32_t ino)
821 {
822 	px_ib_ino_info_t *ino_p;
823 
824 	mutex_enter(&ib_p->ib_ino_lst_mutex);
825 
826 	/* Log in OS data structures the new CPU. */
827 	ino_p = px_ib_locate_ino(ib_p, ino);
828 	if (ino_p != NULL) {
829 
830 		/* Log in OS data structures the new CPU. */
831 		ino_p->ino_cpuid = new_cpu_id;
832 
833 		/* Account for any residual time to be logged for old cpu. */
834 		px_ib_cpu_ticks_to_ih_nsec(ib_p, ino_p->ino_ih_head,
835 		    old_cpu_id);
836 	}
837 
838 	mutex_exit(&ib_p->ib_ino_lst_mutex);
839 }
840