17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate * CDDL HEADER START
37c478bd9Sstevel@tonic-gate *
47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
57aadd8d4Skini * Common Development and Distribution License (the "License").
67aadd8d4Skini * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate *
87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate * and limitations under the License.
127c478bd9Sstevel@tonic-gate *
137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate *
197c478bd9Sstevel@tonic-gate * CDDL HEADER END
207c478bd9Sstevel@tonic-gate */
21788cfa89SDavid Woods
227c478bd9Sstevel@tonic-gate /*
23788cfa89SDavid Woods * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
247c478bd9Sstevel@tonic-gate */
257c478bd9Sstevel@tonic-gate
267c478bd9Sstevel@tonic-gate /*
2726947304SEvan Yan * SPARC Host to PCI Express nexus driver
287c478bd9Sstevel@tonic-gate */
297c478bd9Sstevel@tonic-gate
307c478bd9Sstevel@tonic-gate #include <sys/types.h>
317c478bd9Sstevel@tonic-gate #include <sys/conf.h> /* nulldev */
327c478bd9Sstevel@tonic-gate #include <sys/stat.h> /* devctl */
337c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
347c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
357c478bd9Sstevel@tonic-gate #include <sys/sunndi.h>
367c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h>
371a887b2eSjchu #include <sys/spl.h>
387c478bd9Sstevel@tonic-gate #include <sys/epm.h>
397c478bd9Sstevel@tonic-gate #include <sys/iommutsb.h>
407c478bd9Sstevel@tonic-gate #include "px_obj.h"
4126947304SEvan Yan #include <sys/hotplug/pci/pcie_hp.h>
4269cd775fSschwartz #include <sys/pci_tools.h>
43d4476ccbSschwartz #include "px_tools_ext.h"
44d4bc0535SKrishna Elango #include <sys/pcie_pwr.h>
45c0da6274SZhi-Jun Robin Fu #include <sys/pci_cfgacc.h>
467c478bd9Sstevel@tonic-gate
477c478bd9Sstevel@tonic-gate /*
487c478bd9Sstevel@tonic-gate * function prototypes for dev ops routines:
497c478bd9Sstevel@tonic-gate */
507c478bd9Sstevel@tonic-gate static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
517c478bd9Sstevel@tonic-gate static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
52e6b21d58SErwin T Tsaur static int px_enable_err_intr(px_t *px_p);
53e6b21d58SErwin T Tsaur static void px_disable_err_intr(px_t *px_p);
547c478bd9Sstevel@tonic-gate static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
557c478bd9Sstevel@tonic-gate void *arg, void **result);
5601689544Sjchu static int px_cb_attach(px_t *);
577c478bd9Sstevel@tonic-gate static int px_pwr_setup(dev_info_t *dip);
587c478bd9Sstevel@tonic-gate static void px_pwr_teardown(dev_info_t *dip);
590114761dSAlan Adamson, SD OSSD static void px_set_mps(px_t *px_p);
600114761dSAlan Adamson, SD OSSD
61c0da6274SZhi-Jun Robin Fu extern void pci_cfgacc_acc(pci_cfgacc_req_t *);
620114761dSAlan Adamson, SD OSSD extern int pcie_max_mps;
63c0da6274SZhi-Jun Robin Fu extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *);
647c478bd9Sstevel@tonic-gate /*
657c478bd9Sstevel@tonic-gate * bus ops and dev ops structures:
667c478bd9Sstevel@tonic-gate */
677c478bd9Sstevel@tonic-gate static struct bus_ops px_bus_ops = {
687c478bd9Sstevel@tonic-gate BUSO_REV,
697c478bd9Sstevel@tonic-gate px_map,
707c478bd9Sstevel@tonic-gate 0,
717c478bd9Sstevel@tonic-gate 0,
727c478bd9Sstevel@tonic-gate 0,
737c478bd9Sstevel@tonic-gate i_ddi_map_fault,
747c478bd9Sstevel@tonic-gate px_dma_setup,
757c478bd9Sstevel@tonic-gate px_dma_allochdl,
767c478bd9Sstevel@tonic-gate px_dma_freehdl,
777c478bd9Sstevel@tonic-gate px_dma_bindhdl,
787c478bd9Sstevel@tonic-gate px_dma_unbindhdl,
797c478bd9Sstevel@tonic-gate px_lib_dma_sync,
807c478bd9Sstevel@tonic-gate px_dma_win,
817c478bd9Sstevel@tonic-gate px_dma_ctlops,
827c478bd9Sstevel@tonic-gate px_ctlops,
837c478bd9Sstevel@tonic-gate ddi_bus_prop_op,
847c478bd9Sstevel@tonic-gate ndi_busop_get_eventcookie,
857c478bd9Sstevel@tonic-gate ndi_busop_add_eventcall,
867c478bd9Sstevel@tonic-gate ndi_busop_remove_eventcall,
877c478bd9Sstevel@tonic-gate ndi_post_event,
887c478bd9Sstevel@tonic-gate NULL,
897c478bd9Sstevel@tonic-gate NULL, /* (*bus_config)(); */
907c478bd9Sstevel@tonic-gate NULL, /* (*bus_unconfig)(); */
917c478bd9Sstevel@tonic-gate px_fm_init_child, /* (*bus_fm_init)(); */
927c478bd9Sstevel@tonic-gate NULL, /* (*bus_fm_fini)(); */
93f8d2de6bSjchu px_bus_enter, /* (*bus_fm_access_enter)(); */
94f8d2de6bSjchu px_bus_exit, /* (*bus_fm_access_fini)(); */
957c478bd9Sstevel@tonic-gate pcie_bus_power, /* (*bus_power)(); */
9626947304SEvan Yan px_intr_ops, /* (*bus_intr_op)(); */
9726947304SEvan Yan pcie_hp_common_ops /* (*bus_hp_op)(); */
987c478bd9Sstevel@tonic-gate };
997c478bd9Sstevel@tonic-gate
1007c478bd9Sstevel@tonic-gate extern struct cb_ops px_cb_ops;
1017c478bd9Sstevel@tonic-gate
1027c478bd9Sstevel@tonic-gate static struct dev_ops px_ops = {
1037c478bd9Sstevel@tonic-gate DEVO_REV,
1047c478bd9Sstevel@tonic-gate 0,
1057c478bd9Sstevel@tonic-gate px_info,
1067c478bd9Sstevel@tonic-gate nulldev,
1077c478bd9Sstevel@tonic-gate 0,
1087c478bd9Sstevel@tonic-gate px_attach,
1097c478bd9Sstevel@tonic-gate px_detach,
1107c478bd9Sstevel@tonic-gate nodev,
1117c478bd9Sstevel@tonic-gate &px_cb_ops,
1127c478bd9Sstevel@tonic-gate &px_bus_ops,
11319397407SSherry Moore nulldev,
11419397407SSherry Moore ddi_quiesce_not_needed, /* quiesce */
1157c478bd9Sstevel@tonic-gate };
1167c478bd9Sstevel@tonic-gate
1177c478bd9Sstevel@tonic-gate /*
1187c478bd9Sstevel@tonic-gate * module definitions:
1197c478bd9Sstevel@tonic-gate */
1207c478bd9Sstevel@tonic-gate #include <sys/modctl.h>
1217c478bd9Sstevel@tonic-gate extern struct mod_ops mod_driverops;
1227c478bd9Sstevel@tonic-gate
1237c478bd9Sstevel@tonic-gate static struct modldrv modldrv = {
12426947304SEvan Yan &mod_driverops, /* Type of module - driver */
12526947304SEvan Yan #if defined(sun4u)
12626947304SEvan Yan "Sun4u Host to PCIe nexus driver", /* Name of module. */
12726947304SEvan Yan #elif defined(sun4v)
12826947304SEvan Yan "Sun4v Host to PCIe nexus driver", /* Name of module. */
12926947304SEvan Yan #endif
13026947304SEvan Yan &px_ops, /* driver ops */
1317c478bd9Sstevel@tonic-gate };
1327c478bd9Sstevel@tonic-gate
1337c478bd9Sstevel@tonic-gate static struct modlinkage modlinkage = {
1347c478bd9Sstevel@tonic-gate MODREV_1, (void *)&modldrv, NULL
1357c478bd9Sstevel@tonic-gate };
1367c478bd9Sstevel@tonic-gate
1377c478bd9Sstevel@tonic-gate /* driver soft state */
1387c478bd9Sstevel@tonic-gate void *px_state_p;
1397c478bd9Sstevel@tonic-gate
140788cfa89SDavid Woods int px_force_intx_support = 1;
141788cfa89SDavid Woods
1427c478bd9Sstevel@tonic-gate int
_init(void)1437c478bd9Sstevel@tonic-gate _init(void)
1447c478bd9Sstevel@tonic-gate {
1457c478bd9Sstevel@tonic-gate int e;
1467c478bd9Sstevel@tonic-gate
1477c478bd9Sstevel@tonic-gate /*
1487c478bd9Sstevel@tonic-gate * Initialize per-px bus soft state pointer.
1497c478bd9Sstevel@tonic-gate */
1507c478bd9Sstevel@tonic-gate e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1);
1517c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS)
1527c478bd9Sstevel@tonic-gate return (e);
1537c478bd9Sstevel@tonic-gate
1547c478bd9Sstevel@tonic-gate /*
1557c478bd9Sstevel@tonic-gate * Install the module.
1567c478bd9Sstevel@tonic-gate */
1577c478bd9Sstevel@tonic-gate e = mod_install(&modlinkage);
1587c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS)
1597c478bd9Sstevel@tonic-gate ddi_soft_state_fini(&px_state_p);
1607c478bd9Sstevel@tonic-gate return (e);
1617c478bd9Sstevel@tonic-gate }
1627c478bd9Sstevel@tonic-gate
1637c478bd9Sstevel@tonic-gate int
_fini(void)1647c478bd9Sstevel@tonic-gate _fini(void)
1657c478bd9Sstevel@tonic-gate {
1667c478bd9Sstevel@tonic-gate int e;
1677c478bd9Sstevel@tonic-gate
1687c478bd9Sstevel@tonic-gate /*
1697c478bd9Sstevel@tonic-gate * Remove the module.
1707c478bd9Sstevel@tonic-gate */
1717c478bd9Sstevel@tonic-gate e = mod_remove(&modlinkage);
1727c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS)
1737c478bd9Sstevel@tonic-gate return (e);
1747c478bd9Sstevel@tonic-gate
1757c478bd9Sstevel@tonic-gate /* Free px soft state */
1767c478bd9Sstevel@tonic-gate ddi_soft_state_fini(&px_state_p);
1777c478bd9Sstevel@tonic-gate
1787c478bd9Sstevel@tonic-gate return (e);
1797c478bd9Sstevel@tonic-gate }
1807c478bd9Sstevel@tonic-gate
1817c478bd9Sstevel@tonic-gate int
_info(struct modinfo * modinfop)1827c478bd9Sstevel@tonic-gate _info(struct modinfo *modinfop)
1837c478bd9Sstevel@tonic-gate {
1847c478bd9Sstevel@tonic-gate return (mod_info(&modlinkage, modinfop));
1857c478bd9Sstevel@tonic-gate }
1867c478bd9Sstevel@tonic-gate
1877c478bd9Sstevel@tonic-gate /* ARGSUSED */
1887c478bd9Sstevel@tonic-gate static int
px_info(dev_info_t * dip,ddi_info_cmd_t infocmd,void * arg,void ** result)1897c478bd9Sstevel@tonic-gate px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
1907c478bd9Sstevel@tonic-gate {
19126947304SEvan Yan minor_t minor = getminor((dev_t)arg);
19226947304SEvan Yan int instance = PCI_MINOR_NUM_TO_INSTANCE(minor);
1937c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(instance);
19426947304SEvan Yan int ret = DDI_SUCCESS;
1957c478bd9Sstevel@tonic-gate
1967c478bd9Sstevel@tonic-gate switch (infocmd) {
1977c478bd9Sstevel@tonic-gate case DDI_INFO_DEVT2INSTANCE:
198b40cec45Skrishnae *result = (void *)(intptr_t)instance;
19926947304SEvan Yan break;
2007c478bd9Sstevel@tonic-gate case DDI_INFO_DEVT2DEVINFO:
20126947304SEvan Yan if (px_p == NULL) {
20226947304SEvan Yan ret = DDI_FAILURE;
20326947304SEvan Yan break;
20426947304SEvan Yan }
2057c478bd9Sstevel@tonic-gate
20626947304SEvan Yan *result = (void *)px_p->px_dip;
20726947304SEvan Yan break;
2087c478bd9Sstevel@tonic-gate default:
20926947304SEvan Yan ret = DDI_FAILURE;
21026947304SEvan Yan break;
2117c478bd9Sstevel@tonic-gate }
21226947304SEvan Yan
21326947304SEvan Yan return (ret);
2147c478bd9Sstevel@tonic-gate }
2157c478bd9Sstevel@tonic-gate
2167c478bd9Sstevel@tonic-gate /* device driver entry points */
2177c478bd9Sstevel@tonic-gate /*
2187c478bd9Sstevel@tonic-gate * attach entry point:
2197c478bd9Sstevel@tonic-gate */
2207c478bd9Sstevel@tonic-gate /*ARGSUSED*/
2217c478bd9Sstevel@tonic-gate static int
px_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)2227c478bd9Sstevel@tonic-gate px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2237c478bd9Sstevel@tonic-gate {
2247c478bd9Sstevel@tonic-gate px_t *px_p; /* per bus state pointer */
2257c478bd9Sstevel@tonic-gate int instance = DIP_TO_INST(dip);
2267c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS;
227*e214b19eSToomas Soome devhandle_t dev_hdl = 0;
22826947304SEvan Yan pcie_hp_regops_t regops;
229c0da6274SZhi-Jun Robin Fu pcie_bus_t *bus_p;
2307c478bd9Sstevel@tonic-gate
2317c478bd9Sstevel@tonic-gate switch (cmd) {
2327c478bd9Sstevel@tonic-gate case DDI_ATTACH:
2337c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "DDI_ATTACH\n");
2347c478bd9Sstevel@tonic-gate
235c0da6274SZhi-Jun Robin Fu /* See pci_cfgacc.c */
236c0da6274SZhi-Jun Robin Fu pci_cfgacc_acc_p = pci_cfgacc_acc;
237c0da6274SZhi-Jun Robin Fu
2387c478bd9Sstevel@tonic-gate /*
2397c478bd9Sstevel@tonic-gate * Allocate and get the per-px soft state structure.
2407c478bd9Sstevel@tonic-gate */
2417c478bd9Sstevel@tonic-gate if (ddi_soft_state_zalloc(px_state_p, instance)
2427c478bd9Sstevel@tonic-gate != DDI_SUCCESS) {
2437c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: can't allocate px state",
244eae2e508Skrishnae ddi_driver_name(dip), instance);
2457c478bd9Sstevel@tonic-gate goto err_bad_px_softstate;
2467c478bd9Sstevel@tonic-gate }
2477c478bd9Sstevel@tonic-gate px_p = INST_TO_STATE(instance);
2487c478bd9Sstevel@tonic-gate px_p->px_dip = dip;
2497c478bd9Sstevel@tonic-gate mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL);
25026947304SEvan Yan px_p->px_soft_state = PCI_SOFT_STATE_CLOSED;
2517c478bd9Sstevel@tonic-gate
252b65731f1Skini (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip,
253eae2e508Skrishnae "device_type", "pciex");
254bf8fc234Set
255bf8fc234Set /* Initialize px_dbg for high pil printing */
256bf8fc234Set px_dbg_attach(dip, &px_p->px_dbg_hdl);
25726947304SEvan Yan pcie_rc_init_bus(dip);
258bf8fc234Set
2597c478bd9Sstevel@tonic-gate /*
2607c478bd9Sstevel@tonic-gate * Get key properties of the pci bridge node and
2617c478bd9Sstevel@tonic-gate * determine it's type (psycho, schizo, etc ...).
2627c478bd9Sstevel@tonic-gate */
2637c478bd9Sstevel@tonic-gate if (px_get_props(px_p, dip) == DDI_FAILURE)
2647c478bd9Sstevel@tonic-gate goto err_bad_px_prop;
2657c478bd9Sstevel@tonic-gate
2667c478bd9Sstevel@tonic-gate if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS)
2677c478bd9Sstevel@tonic-gate goto err_bad_dev_init;
2687c478bd9Sstevel@tonic-gate
26920036fe5Segillett /* Initialize device handle */
2707c478bd9Sstevel@tonic-gate px_p->px_dev_hdl = dev_hdl;
2717c478bd9Sstevel@tonic-gate
2727ea9b230Set /* Cache the BDF of the root port nexus */
2737ea9b230Set px_p->px_bdf = px_lib_get_bdf(px_p);
2747ea9b230Set
2757c478bd9Sstevel@tonic-gate /*
2767c478bd9Sstevel@tonic-gate * Initialize interrupt block. Note that this
2777c478bd9Sstevel@tonic-gate * initialize error handling for the PEC as well.
2787c478bd9Sstevel@tonic-gate */
2797c478bd9Sstevel@tonic-gate if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS)
2807c478bd9Sstevel@tonic-gate goto err_bad_ib;
2817c478bd9Sstevel@tonic-gate
2827c478bd9Sstevel@tonic-gate if (px_cb_attach(px_p) != DDI_SUCCESS)
2837c478bd9Sstevel@tonic-gate goto err_bad_cb;
2847c478bd9Sstevel@tonic-gate
2857c478bd9Sstevel@tonic-gate /*
2867c478bd9Sstevel@tonic-gate * Start creating the modules.
2877c478bd9Sstevel@tonic-gate * Note that attach() routines should
2887c478bd9Sstevel@tonic-gate * register and enable their own interrupts.
2897c478bd9Sstevel@tonic-gate */
2907c478bd9Sstevel@tonic-gate
2917c478bd9Sstevel@tonic-gate if ((px_mmu_attach(px_p)) != DDI_SUCCESS)
2927c478bd9Sstevel@tonic-gate goto err_bad_mmu;
2937c478bd9Sstevel@tonic-gate
2947c478bd9Sstevel@tonic-gate if ((px_msiq_attach(px_p)) != DDI_SUCCESS)
2957c478bd9Sstevel@tonic-gate goto err_bad_msiq;
2967c478bd9Sstevel@tonic-gate
2977c478bd9Sstevel@tonic-gate if ((px_msi_attach(px_p)) != DDI_SUCCESS)
2987c478bd9Sstevel@tonic-gate goto err_bad_msi;
2997c478bd9Sstevel@tonic-gate
3007c478bd9Sstevel@tonic-gate if ((px_pec_attach(px_p)) != DDI_SUCCESS)
3017c478bd9Sstevel@tonic-gate goto err_bad_pec;
3027c478bd9Sstevel@tonic-gate
3037c478bd9Sstevel@tonic-gate if ((px_dma_attach(px_p)) != DDI_SUCCESS)
3049c81f298Sjchu goto err_bad_dma; /* nothing to uninitialize on DMA */
3057c478bd9Sstevel@tonic-gate
3063c4226f9Spjha if ((px_fm_attach(px_p)) != DDI_SUCCESS)
3073c4226f9Spjha goto err_bad_dma;
3083c4226f9Spjha
3097c478bd9Sstevel@tonic-gate /*
3107c478bd9Sstevel@tonic-gate * All of the error handlers have been registered
311e6b21d58SErwin T Tsaur * by now so it's time to activate all the interrupt.
3127c478bd9Sstevel@tonic-gate */
313e6b21d58SErwin T Tsaur if ((px_enable_err_intr(px_p)) != DDI_SUCCESS)
3143c4226f9Spjha goto err_bad_intr;
3157c478bd9Sstevel@tonic-gate
31626947304SEvan Yan if (px_lib_hotplug_init(dip, (void *)®ops) == DDI_SUCCESS) {
31726947304SEvan Yan pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
31826947304SEvan Yan
31926947304SEvan Yan bus_p->bus_hp_sup_modes |= PCIE_NATIVE_HP_MODE;
32026947304SEvan Yan }
321b65731f1Skini
3220114761dSAlan Adamson, SD OSSD (void) px_set_mps(px_p);
3230114761dSAlan Adamson, SD OSSD
32426947304SEvan Yan if (pcie_init(dip, (caddr_t)®ops) != DDI_SUCCESS)
32526947304SEvan Yan goto err_bad_hotplug;
32669cd775fSschwartz
32770f83219SEvan Yan (void) pcie_hpintr_enable(dip);
32870f83219SEvan Yan
32969cd775fSschwartz if (pxtool_init(dip) != DDI_SUCCESS)
33069cd775fSschwartz goto err_bad_pcitool_node;
33169cd775fSschwartz
3327c478bd9Sstevel@tonic-gate /*
3337c478bd9Sstevel@tonic-gate * power management setup. Even if it fails, attach will
3347c478bd9Sstevel@tonic-gate * succeed as this is a optional feature. Since we are
3357c478bd9Sstevel@tonic-gate * always at full power, this is not critical.
3367c478bd9Sstevel@tonic-gate */
3377c478bd9Sstevel@tonic-gate if (pwr_common_setup(dip) != DDI_SUCCESS) {
3387c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "pwr_common_setup failed\n");
3397c478bd9Sstevel@tonic-gate } else if (px_pwr_setup(dip) != DDI_SUCCESS) {
3407c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "px_pwr_setup failed \n");
3417c478bd9Sstevel@tonic-gate pwr_common_teardown(dip);
3427c478bd9Sstevel@tonic-gate }
3437c478bd9Sstevel@tonic-gate
344817a6df8Sjchu /*
345817a6df8Sjchu * add cpr callback
346817a6df8Sjchu */
347817a6df8Sjchu px_cpr_add_callb(px_p);
348817a6df8Sjchu
349fc256490SJason Beloro /*
350fc256490SJason Beloro * do fabric sync in case we don't need to wait for
351fc256490SJason Beloro * any bridge driver to be ready
352fc256490SJason Beloro */
353fc256490SJason Beloro (void) px_lib_fabric_sync(dip);
354fc256490SJason Beloro
3557c478bd9Sstevel@tonic-gate ddi_report_dev(dip);
3567c478bd9Sstevel@tonic-gate
3577c478bd9Sstevel@tonic-gate px_p->px_state = PX_ATTACHED;
358c0da6274SZhi-Jun Robin Fu
359c0da6274SZhi-Jun Robin Fu /*
360c0da6274SZhi-Jun Robin Fu * save base addr in bus_t for pci_cfgacc_xxx(), this
361c0da6274SZhi-Jun Robin Fu * depends of px structure being properly initialized.
362c0da6274SZhi-Jun Robin Fu */
363c0da6274SZhi-Jun Robin Fu bus_p = PCIE_DIP2BUS(dip);
364c0da6274SZhi-Jun Robin Fu bus_p->bus_cfgacc_base = px_lib_get_cfgacc_base(dip);
365c0da6274SZhi-Jun Robin Fu
366c0da6274SZhi-Jun Robin Fu /*
367c0da6274SZhi-Jun Robin Fu * Partially populate bus_t for all devices in this fabric
368c0da6274SZhi-Jun Robin Fu * for device type macros to work.
369c0da6274SZhi-Jun Robin Fu */
370c0da6274SZhi-Jun Robin Fu /*
371c0da6274SZhi-Jun Robin Fu * Populate bus_t for all devices in this fabric, after FMA
372c0da6274SZhi-Jun Robin Fu * is initializated, so that config access errors could
373c0da6274SZhi-Jun Robin Fu * trigger panic.
374c0da6274SZhi-Jun Robin Fu */
375c0da6274SZhi-Jun Robin Fu pcie_fab_init_bus(dip, PCIE_BUS_ALL);
376c0da6274SZhi-Jun Robin Fu
3777c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "attach success\n");
3787c478bd9Sstevel@tonic-gate break;
3797c478bd9Sstevel@tonic-gate
38069cd775fSschwartz err_bad_pcitool_node:
38170f83219SEvan Yan (void) pcie_hpintr_disable(dip);
38226947304SEvan Yan (void) pcie_uninit(dip);
38326947304SEvan Yan err_bad_hotplug:
38426947304SEvan Yan (void) px_lib_hotplug_uninit(dip);
385e6b21d58SErwin T Tsaur px_disable_err_intr(px_p);
3863c4226f9Spjha err_bad_intr:
3873c4226f9Spjha px_fm_detach(px_p);
3889c81f298Sjchu err_bad_dma:
3897c478bd9Sstevel@tonic-gate px_pec_detach(px_p);
3907c478bd9Sstevel@tonic-gate err_bad_pec:
3917c478bd9Sstevel@tonic-gate px_msi_detach(px_p);
3927c478bd9Sstevel@tonic-gate err_bad_msi:
3937c478bd9Sstevel@tonic-gate px_msiq_detach(px_p);
3947c478bd9Sstevel@tonic-gate err_bad_msiq:
3957c478bd9Sstevel@tonic-gate px_mmu_detach(px_p);
3967c478bd9Sstevel@tonic-gate err_bad_mmu:
3977c478bd9Sstevel@tonic-gate err_bad_cb:
3987c478bd9Sstevel@tonic-gate px_ib_detach(px_p);
3997c478bd9Sstevel@tonic-gate err_bad_ib:
400d8d130aeSanbui if (px_lib_dev_fini(dip) != DDI_SUCCESS) {
401d8d130aeSanbui DBG(DBG_ATTACH, dip, "px_lib_dev_fini failed\n");
402d8d130aeSanbui }
4037c478bd9Sstevel@tonic-gate err_bad_dev_init:
4047c478bd9Sstevel@tonic-gate px_free_props(px_p);
4057c478bd9Sstevel@tonic-gate err_bad_px_prop:
40626947304SEvan Yan pcie_rc_fini_bus(dip);
407bf8fc234Set px_dbg_detach(dip, &px_p->px_dbg_hdl);
4087c478bd9Sstevel@tonic-gate mutex_destroy(&px_p->px_mutex);
4097c478bd9Sstevel@tonic-gate ddi_soft_state_free(px_state_p, instance);
4107c478bd9Sstevel@tonic-gate err_bad_px_softstate:
4117c478bd9Sstevel@tonic-gate ret = DDI_FAILURE;
4127c478bd9Sstevel@tonic-gate break;
4137c478bd9Sstevel@tonic-gate
4147c478bd9Sstevel@tonic-gate case DDI_RESUME:
4157c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "DDI_RESUME\n");
4167c478bd9Sstevel@tonic-gate
4177c478bd9Sstevel@tonic-gate px_p = INST_TO_STATE(instance);
4187c478bd9Sstevel@tonic-gate
4197c478bd9Sstevel@tonic-gate mutex_enter(&px_p->px_mutex);
4207c478bd9Sstevel@tonic-gate
4217c478bd9Sstevel@tonic-gate /* suspend might have not succeeded */
4227c478bd9Sstevel@tonic-gate if (px_p->px_state != PX_SUSPENDED) {
4237c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, px_p->px_dip,
4247c478bd9Sstevel@tonic-gate "instance NOT suspended\n");
4257c478bd9Sstevel@tonic-gate ret = DDI_FAILURE;
4267c478bd9Sstevel@tonic-gate break;
4277c478bd9Sstevel@tonic-gate }
4287c478bd9Sstevel@tonic-gate
429023ccc1eSegillett px_msiq_resume(px_p);
4307c478bd9Sstevel@tonic-gate px_lib_resume(dip);
4317c478bd9Sstevel@tonic-gate (void) pcie_pwr_resume(dip);
4327c478bd9Sstevel@tonic-gate px_p->px_state = PX_ATTACHED;
4337c478bd9Sstevel@tonic-gate
4347c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex);
4357c478bd9Sstevel@tonic-gate
4367c478bd9Sstevel@tonic-gate break;
4377c478bd9Sstevel@tonic-gate default:
4387c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "unsupported attach op\n");
4397c478bd9Sstevel@tonic-gate ret = DDI_FAILURE;
4407c478bd9Sstevel@tonic-gate break;
4417c478bd9Sstevel@tonic-gate }
4427c478bd9Sstevel@tonic-gate
4437c478bd9Sstevel@tonic-gate return (ret);
4447c478bd9Sstevel@tonic-gate }
4457c478bd9Sstevel@tonic-gate
4467c478bd9Sstevel@tonic-gate /*
4477c478bd9Sstevel@tonic-gate * detach entry point:
4487c478bd9Sstevel@tonic-gate */
4497c478bd9Sstevel@tonic-gate /*ARGSUSED*/
4507c478bd9Sstevel@tonic-gate static int
px_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)4517c478bd9Sstevel@tonic-gate px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
4527c478bd9Sstevel@tonic-gate {
45326947304SEvan Yan int instance = ddi_get_instance(dip);
45426947304SEvan Yan px_t *px_p = INST_TO_STATE(instance);
45526947304SEvan Yan pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
45626947304SEvan Yan int ret;
4577c478bd9Sstevel@tonic-gate
4587c478bd9Sstevel@tonic-gate /*
4597c478bd9Sstevel@tonic-gate * Make sure we are currently attached
4607c478bd9Sstevel@tonic-gate */
4617c478bd9Sstevel@tonic-gate if (px_p->px_state != PX_ATTACHED) {
46201689544Sjchu DBG(DBG_DETACH, dip, "Instance not attached\n");
4637c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
4647c478bd9Sstevel@tonic-gate }
4657c478bd9Sstevel@tonic-gate
4667c478bd9Sstevel@tonic-gate mutex_enter(&px_p->px_mutex);
4677c478bd9Sstevel@tonic-gate
4687c478bd9Sstevel@tonic-gate switch (cmd) {
4697c478bd9Sstevel@tonic-gate case DDI_DETACH:
4707c478bd9Sstevel@tonic-gate DBG(DBG_DETACH, dip, "DDI_DETACH\n");
4717c478bd9Sstevel@tonic-gate
472817a6df8Sjchu /*
473817a6df8Sjchu * remove cpr callback
474817a6df8Sjchu */
475817a6df8Sjchu px_cpr_rem_callb(px_p);
476817a6df8Sjchu
47770f83219SEvan Yan (void) pcie_hpintr_disable(dip);
47870f83219SEvan Yan
47926947304SEvan Yan if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p))
48026947304SEvan Yan (void) px_lib_hotplug_uninit(dip);
48126947304SEvan Yan
48226947304SEvan Yan if (pcie_uninit(dip) != DDI_SUCCESS) {
48326947304SEvan Yan mutex_exit(&px_p->px_mutex);
48426947304SEvan Yan return (DDI_FAILURE);
48526947304SEvan Yan }
4867c478bd9Sstevel@tonic-gate
487c0da6274SZhi-Jun Robin Fu /* Destroy bus_t for the whole fabric */
488c0da6274SZhi-Jun Robin Fu pcie_fab_fini_bus(dip, PCIE_BUS_ALL);
489c0da6274SZhi-Jun Robin Fu
4907c478bd9Sstevel@tonic-gate /*
4917c478bd9Sstevel@tonic-gate * things which used to be done in obj_destroy
4927c478bd9Sstevel@tonic-gate * are now in-lined here.
4937c478bd9Sstevel@tonic-gate */
4947c478bd9Sstevel@tonic-gate
4957c478bd9Sstevel@tonic-gate px_p->px_state = PX_DETACHED;
4967c478bd9Sstevel@tonic-gate
49769cd775fSschwartz pxtool_uninit(dip);
49869cd775fSschwartz
499e6b21d58SErwin T Tsaur px_disable_err_intr(px_p);
5003c4226f9Spjha px_fm_detach(px_p);
5017c478bd9Sstevel@tonic-gate px_pec_detach(px_p);
5029c75c6bfSgovinda px_pwr_teardown(dip);
5039c75c6bfSgovinda pwr_common_teardown(dip);
5047c478bd9Sstevel@tonic-gate px_msi_detach(px_p);
5057c478bd9Sstevel@tonic-gate px_msiq_detach(px_p);
5067c478bd9Sstevel@tonic-gate px_mmu_detach(px_p);
5077c478bd9Sstevel@tonic-gate px_ib_detach(px_p);
508d8d130aeSanbui if (px_lib_dev_fini(dip) != DDI_SUCCESS) {
509d8d130aeSanbui DBG(DBG_DETACH, dip, "px_lib_dev_fini failed\n");
510d8d130aeSanbui }
5117c478bd9Sstevel@tonic-gate
5127c478bd9Sstevel@tonic-gate /*
5137c478bd9Sstevel@tonic-gate * Free the px soft state structure and the rest of the
5147c478bd9Sstevel@tonic-gate * resources it's using.
5157c478bd9Sstevel@tonic-gate */
5167c478bd9Sstevel@tonic-gate px_free_props(px_p);
51726947304SEvan Yan pcie_rc_fini_bus(dip);
518bf8fc234Set px_dbg_detach(dip, &px_p->px_dbg_hdl);
5197c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex);
5207c478bd9Sstevel@tonic-gate mutex_destroy(&px_p->px_mutex);
5217c478bd9Sstevel@tonic-gate
522*e214b19eSToomas Soome px_p->px_dev_hdl = 0;
523dabea0dbSschwartz ddi_soft_state_free(px_state_p, instance);
5247c478bd9Sstevel@tonic-gate
5257c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
5267c478bd9Sstevel@tonic-gate
5277c478bd9Sstevel@tonic-gate case DDI_SUSPEND:
5287c478bd9Sstevel@tonic-gate if (pcie_pwr_suspend(dip) != DDI_SUCCESS) {
5297c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex);
5307c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
5317c478bd9Sstevel@tonic-gate }
5327c478bd9Sstevel@tonic-gate if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS)
5337c478bd9Sstevel@tonic-gate px_p->px_state = PX_SUSPENDED;
5347c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex);
5357c478bd9Sstevel@tonic-gate
5367c478bd9Sstevel@tonic-gate return (ret);
5377c478bd9Sstevel@tonic-gate
5387c478bd9Sstevel@tonic-gate default:
5397c478bd9Sstevel@tonic-gate DBG(DBG_DETACH, dip, "unsupported detach op\n");
5407c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex);
5417c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
5427c478bd9Sstevel@tonic-gate }
5437c478bd9Sstevel@tonic-gate }
5447c478bd9Sstevel@tonic-gate
545e6b21d58SErwin T Tsaur static int
px_enable_err_intr(px_t * px_p)546e6b21d58SErwin T Tsaur px_enable_err_intr(px_t *px_p)
547e6b21d58SErwin T Tsaur {
548e6b21d58SErwin T Tsaur /* Add FMA Callback handler for failed PIO Loads */
549e6b21d58SErwin T Tsaur px_fm_cb_enable(px_p);
550e6b21d58SErwin T Tsaur
551e6b21d58SErwin T Tsaur /* Add Common Block mondo handler */
552e6b21d58SErwin T Tsaur if (px_cb_add_intr(&px_p->px_cb_fault) != DDI_SUCCESS)
553e6b21d58SErwin T Tsaur goto cb_bad;
554e6b21d58SErwin T Tsaur
555e6b21d58SErwin T Tsaur /* Add PEU Block Mondo Handler */
556e6b21d58SErwin T Tsaur if (px_err_add_intr(&px_p->px_fault) != DDI_SUCCESS)
557e6b21d58SErwin T Tsaur goto peu_bad;
558e6b21d58SErwin T Tsaur
559e6b21d58SErwin T Tsaur /* Enable interrupt handler for PCIE Fabric Error Messages */
560e6b21d58SErwin T Tsaur if (px_pec_msg_add_intr(px_p) != DDI_SUCCESS)
561e6b21d58SErwin T Tsaur goto msg_bad;
562e6b21d58SErwin T Tsaur
563e6b21d58SErwin T Tsaur return (DDI_SUCCESS);
564e6b21d58SErwin T Tsaur
565e6b21d58SErwin T Tsaur msg_bad:
566e6b21d58SErwin T Tsaur px_err_rem_intr(&px_p->px_fault);
567e6b21d58SErwin T Tsaur peu_bad:
568e6b21d58SErwin T Tsaur px_cb_rem_intr(&px_p->px_cb_fault);
569e6b21d58SErwin T Tsaur cb_bad:
570e6b21d58SErwin T Tsaur px_fm_cb_disable(px_p);
571e6b21d58SErwin T Tsaur
572e6b21d58SErwin T Tsaur return (DDI_FAILURE);
573e6b21d58SErwin T Tsaur }
574e6b21d58SErwin T Tsaur
575e6b21d58SErwin T Tsaur static void
px_disable_err_intr(px_t * px_p)576e6b21d58SErwin T Tsaur px_disable_err_intr(px_t *px_p)
577e6b21d58SErwin T Tsaur {
578e6b21d58SErwin T Tsaur px_pec_msg_rem_intr(px_p);
579e6b21d58SErwin T Tsaur px_err_rem_intr(&px_p->px_fault);
580e6b21d58SErwin T Tsaur px_cb_rem_intr(&px_p->px_cb_fault);
581e6b21d58SErwin T Tsaur px_fm_cb_disable(px_p);
582e6b21d58SErwin T Tsaur }
583e6b21d58SErwin T Tsaur
58401689544Sjchu int
px_cb_attach(px_t * px_p)58501689544Sjchu px_cb_attach(px_t *px_p)
58601689544Sjchu {
58701689544Sjchu px_fault_t *fault_p = &px_p->px_cb_fault;
58801689544Sjchu dev_info_t *dip = px_p->px_dip;
58901689544Sjchu sysino_t sysino;
59001689544Sjchu
59101689544Sjchu if (px_lib_intr_devino_to_sysino(dip,
59201689544Sjchu px_p->px_inos[PX_INTR_XBC], &sysino) != DDI_SUCCESS)
59301689544Sjchu return (DDI_FAILURE);
59401689544Sjchu
59501689544Sjchu fault_p->px_fh_dip = dip;
59601689544Sjchu fault_p->px_fh_sysino = sysino;
59701689544Sjchu fault_p->px_err_func = px_err_cb_intr;
59801689544Sjchu fault_p->px_intr_ino = px_p->px_inos[PX_INTR_XBC];
59901689544Sjchu
600e6b21d58SErwin T Tsaur return (DDI_SUCCESS);
60101689544Sjchu }
60201689544Sjchu
6037c478bd9Sstevel@tonic-gate /*
6047c478bd9Sstevel@tonic-gate * power management related initialization specific to px
6057c478bd9Sstevel@tonic-gate * called by px_attach()
6067c478bd9Sstevel@tonic-gate */
6077c478bd9Sstevel@tonic-gate static int
px_pwr_setup(dev_info_t * dip)6087c478bd9Sstevel@tonic-gate px_pwr_setup(dev_info_t *dip)
6097c478bd9Sstevel@tonic-gate {
6107c478bd9Sstevel@tonic-gate pcie_pwr_t *pwr_p;
6111a887b2eSjchu int instance = ddi_get_instance(dip);
6121a887b2eSjchu px_t *px_p = INST_TO_STATE(instance);
6137c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t hdl;
6147c478bd9Sstevel@tonic-gate
6157c478bd9Sstevel@tonic-gate ASSERT(PCIE_PMINFO(dip));
6167c478bd9Sstevel@tonic-gate pwr_p = PCIE_NEXUS_PMINFO(dip);
6177c478bd9Sstevel@tonic-gate ASSERT(pwr_p);
6187c478bd9Sstevel@tonic-gate
6197c478bd9Sstevel@tonic-gate /*
6207c478bd9Sstevel@tonic-gate * indicate support LDI (Layered Driver Interface)
6217c478bd9Sstevel@tonic-gate * Create the property, if it is not already there
6227c478bd9Sstevel@tonic-gate */
6237c478bd9Sstevel@tonic-gate if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
6247c478bd9Sstevel@tonic-gate DDI_KERNEL_IOCTL)) {
6257c478bd9Sstevel@tonic-gate if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP,
6267c478bd9Sstevel@tonic-gate DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) {
6277c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n");
6287c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
6297c478bd9Sstevel@tonic-gate }
6307c478bd9Sstevel@tonic-gate }
6317c478bd9Sstevel@tonic-gate /* No support for device PM. We are always at full power */
6327c478bd9Sstevel@tonic-gate pwr_p->pwr_func_lvl = PM_LEVEL_D0;
6337c478bd9Sstevel@tonic-gate
6341a887b2eSjchu mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER,
635a195726fSgovinda DDI_INTR_PRI(px_pwr_pil));
6361a887b2eSjchu cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL);
6371a887b2eSjchu
63820036fe5Segillett /* Initialize handle */
63920036fe5Segillett bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
6401a887b2eSjchu hdl.ih_cb_arg1 = px_p;
6417c478bd9Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION;
6427c478bd9Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC;
6437c478bd9Sstevel@tonic-gate hdl.ih_dip = dip;
6447c478bd9Sstevel@tonic-gate hdl.ih_pri = px_pwr_pil;
6457c478bd9Sstevel@tonic-gate
6467c478bd9Sstevel@tonic-gate /* Add PME_TO_ACK message handler */
6471a887b2eSjchu hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr;
6487c478bd9Sstevel@tonic-gate if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC,
64909b1eac2SEvan Yan (msgcode_t)PCIE_PME_ACK_MSG, -1,
65009b1eac2SEvan Yan &px_p->px_pm_msiq_id) != DDI_SUCCESS) {
6511a887b2eSjchu DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add "
6521a887b2eSjchu " PME_TO_ACK intr\n");
653f9721e07Sjchu goto pwr_setup_err1;
6547c478bd9Sstevel@tonic-gate }
6551a887b2eSjchu px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id);
6567c478bd9Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID);
6577c478bd9Sstevel@tonic-gate
65836fe4a92Segillett if (px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
659b0fc0e77Sgovinda px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil,
66036fe4a92Segillett PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) {
66136fe4a92Segillett DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt"
66236fe4a92Segillett " state failed\n");
66336fe4a92Segillett goto px_pwrsetup_err_state;
66436fe4a92Segillett }
66536fe4a92Segillett
6667c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
6677c478bd9Sstevel@tonic-gate
66836fe4a92Segillett px_pwrsetup_err_state:
66936fe4a92Segillett px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
67036fe4a92Segillett (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
67136fe4a92Segillett px_p->px_pm_msiq_id);
6721a887b2eSjchu pwr_setup_err1:
6731a887b2eSjchu mutex_destroy(&px_p->px_l23ready_lock);
6741a887b2eSjchu cv_destroy(&px_p->px_l23ready_cv);
6751a887b2eSjchu
6767c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
6777c478bd9Sstevel@tonic-gate }
6787c478bd9Sstevel@tonic-gate
6797c478bd9Sstevel@tonic-gate /*
6807c478bd9Sstevel@tonic-gate * undo whatever is done in px_pwr_setup. called by px_detach()
6817c478bd9Sstevel@tonic-gate */
6827c478bd9Sstevel@tonic-gate static void
px_pwr_teardown(dev_info_t * dip)6837c478bd9Sstevel@tonic-gate px_pwr_teardown(dev_info_t *dip)
6847c478bd9Sstevel@tonic-gate {
6851a887b2eSjchu int instance = ddi_get_instance(dip);
6861a887b2eSjchu px_t *px_p = INST_TO_STATE(instance);
6871a887b2eSjchu ddi_intr_handle_impl_t hdl;
6887c478bd9Sstevel@tonic-gate
689*e214b19eSToomas Soome if (PCIE_PMINFO(dip) == NULL || PCIE_NEXUS_PMINFO(dip) == NULL)
6907c478bd9Sstevel@tonic-gate return;
6917c478bd9Sstevel@tonic-gate
69220036fe5Segillett /* Initialize handle */
69320036fe5Segillett bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
6947c478bd9Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION;
6957c478bd9Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC;
6967c478bd9Sstevel@tonic-gate hdl.ih_dip = dip;
697665a7fcaSgovinda hdl.ih_pri = px_pwr_pil;
6987c478bd9Sstevel@tonic-gate
6997c478bd9Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
7007c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
7011a887b2eSjchu px_p->px_pm_msiq_id);
7027c478bd9Sstevel@tonic-gate
70336fe4a92Segillett (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
704b0fc0e77Sgovinda px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil,
70536fe4a92Segillett PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG);
70636fe4a92Segillett
707055d7c80Scarlsonj px_p->px_pm_msiq_id = (msiqid_t)-1;
7087c478bd9Sstevel@tonic-gate
7091a887b2eSjchu cv_destroy(&px_p->px_l23ready_cv);
7101a887b2eSjchu mutex_destroy(&px_p->px_l23ready_lock);
7117c478bd9Sstevel@tonic-gate }
7127c478bd9Sstevel@tonic-gate
7137c478bd9Sstevel@tonic-gate /* bus driver entry points */
7147c478bd9Sstevel@tonic-gate
7157c478bd9Sstevel@tonic-gate /*
7167c478bd9Sstevel@tonic-gate * bus map entry point:
7177c478bd9Sstevel@tonic-gate *
7187c478bd9Sstevel@tonic-gate * if map request is for an rnumber
7197c478bd9Sstevel@tonic-gate * get the corresponding regspec from device node
7207c478bd9Sstevel@tonic-gate * build a new regspec in our parent's format
7217c478bd9Sstevel@tonic-gate * build a new map_req with the new regspec
7227c478bd9Sstevel@tonic-gate * call up the tree to complete the mapping
7237c478bd9Sstevel@tonic-gate */
7247c478bd9Sstevel@tonic-gate int
px_map(dev_info_t * dip,dev_info_t * rdip,ddi_map_req_t * mp,off_t off,off_t len,caddr_t * addrp)7257c478bd9Sstevel@tonic-gate px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
7267c478bd9Sstevel@tonic-gate off_t off, off_t len, caddr_t *addrp)
7277c478bd9Sstevel@tonic-gate {
7287c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
7297c478bd9Sstevel@tonic-gate struct regspec p_regspec;
7307c478bd9Sstevel@tonic-gate ddi_map_req_t p_mapreq;
7317c478bd9Sstevel@tonic-gate int reglen, rval, r_no;
7327c478bd9Sstevel@tonic-gate pci_regspec_t reloc_reg, *rp = &reloc_reg;
7337c478bd9Sstevel@tonic-gate
7347c478bd9Sstevel@tonic-gate DBG(DBG_MAP, dip, "rdip=%s%d:",
735eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip));
7367c478bd9Sstevel@tonic-gate
7377c478bd9Sstevel@tonic-gate if (mp->map_flags & DDI_MF_USER_MAPPING)
7387c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED);
7397c478bd9Sstevel@tonic-gate
7407c478bd9Sstevel@tonic-gate switch (mp->map_type) {
7417c478bd9Sstevel@tonic-gate case DDI_MT_REGSPEC:
7427c478bd9Sstevel@tonic-gate reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */
7437c478bd9Sstevel@tonic-gate break;
7447c478bd9Sstevel@tonic-gate
7457c478bd9Sstevel@tonic-gate case DDI_MT_RNUMBER:
7467c478bd9Sstevel@tonic-gate r_no = mp->map_obj.rnumber;
7477c478bd9Sstevel@tonic-gate DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no);
7487c478bd9Sstevel@tonic-gate
749a3282898Scth if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS,
750eae2e508Skrishnae "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS)
751eae2e508Skrishnae return (DDI_ME_RNUMBER_RANGE);
7527c478bd9Sstevel@tonic-gate
7537c478bd9Sstevel@tonic-gate if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) {
7547c478bd9Sstevel@tonic-gate kmem_free(rp, reglen);
7557c478bd9Sstevel@tonic-gate return (DDI_ME_RNUMBER_RANGE);
7567c478bd9Sstevel@tonic-gate }
7577c478bd9Sstevel@tonic-gate rp += r_no;
7587c478bd9Sstevel@tonic-gate break;
7597c478bd9Sstevel@tonic-gate
7607c478bd9Sstevel@tonic-gate default:
7617c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL);
7627c478bd9Sstevel@tonic-gate }
7637c478bd9Sstevel@tonic-gate DBG(DBG_MAP | DBG_CONT, dip, "\n");
7647c478bd9Sstevel@tonic-gate
7657c478bd9Sstevel@tonic-gate if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) {
7667c478bd9Sstevel@tonic-gate /*
7677c478bd9Sstevel@tonic-gate * There may be a need to differentiate between PCI
7687c478bd9Sstevel@tonic-gate * and PCI-Ex devices so the following range check is
7697c478bd9Sstevel@tonic-gate * done correctly, depending on the implementation of
770d4bc0535SKrishna Elango * pcieb bridge nexus driver.
7717c478bd9Sstevel@tonic-gate */
7727c478bd9Sstevel@tonic-gate if ((off >= PCIE_CONF_HDR_SIZE) ||
773eae2e508Skrishnae (len > PCIE_CONF_HDR_SIZE) ||
774eae2e508Skrishnae (off + len > PCIE_CONF_HDR_SIZE))
7757c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL);
7767c478bd9Sstevel@tonic-gate /*
7777c478bd9Sstevel@tonic-gate * the following function returning a DDI_FAILURE assumes
7787c478bd9Sstevel@tonic-gate * that there are no virtual config space access services
7797c478bd9Sstevel@tonic-gate * defined in this layer. Otherwise it is availed right
7807c478bd9Sstevel@tonic-gate * here and we return.
7817c478bd9Sstevel@tonic-gate */
7827c478bd9Sstevel@tonic-gate rval = px_lib_map_vconfig(dip, mp, off, rp, addrp);
7837c478bd9Sstevel@tonic-gate if (rval == DDI_SUCCESS)
7847c478bd9Sstevel@tonic-gate goto done;
7857c478bd9Sstevel@tonic-gate }
7867c478bd9Sstevel@tonic-gate
7877c478bd9Sstevel@tonic-gate /*
7887c478bd9Sstevel@tonic-gate * No virtual config space services or we are mapping
7897c478bd9Sstevel@tonic-gate * a region of memory mapped config/IO/memory space, so proceed
7907c478bd9Sstevel@tonic-gate * to the parent.
7917c478bd9Sstevel@tonic-gate */
7927c478bd9Sstevel@tonic-gate
7937c478bd9Sstevel@tonic-gate /* relocate within 64-bit pci space through "assigned-addresses" */
7947c478bd9Sstevel@tonic-gate if (rval = px_reloc_reg(dip, rdip, px_p, rp))
7957c478bd9Sstevel@tonic-gate goto done;
7967c478bd9Sstevel@tonic-gate
7977c478bd9Sstevel@tonic-gate if (len) /* adjust regspec according to mapping request */
7987c478bd9Sstevel@tonic-gate rp->pci_size_low = len; /* MIN ? */
7997c478bd9Sstevel@tonic-gate rp->pci_phys_low += off;
8007c478bd9Sstevel@tonic-gate
8017c478bd9Sstevel@tonic-gate /* translate relocated pci regspec into parent space through "ranges" */
8027c478bd9Sstevel@tonic-gate if (rval = px_xlate_reg(px_p, rp, &p_regspec))
8037c478bd9Sstevel@tonic-gate goto done;
8047c478bd9Sstevel@tonic-gate
8057c478bd9Sstevel@tonic-gate p_mapreq = *mp; /* dup the whole structure */
8067c478bd9Sstevel@tonic-gate p_mapreq.map_type = DDI_MT_REGSPEC;
8077c478bd9Sstevel@tonic-gate p_mapreq.map_obj.rp = &p_regspec;
8084fbb58f6Sjchu px_lib_map_attr_check(&p_mapreq);
8097c478bd9Sstevel@tonic-gate rval = ddi_map(dip, &p_mapreq, 0, 0, addrp);
8107c478bd9Sstevel@tonic-gate
8117c478bd9Sstevel@tonic-gate if (rval == DDI_SUCCESS) {
8127c478bd9Sstevel@tonic-gate /*
8137c478bd9Sstevel@tonic-gate * Set-up access functions for FM access error capable drivers.
8147c478bd9Sstevel@tonic-gate */
815eae2e508Skrishnae if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)))
816eae2e508Skrishnae px_fm_acc_setup(mp, rdip, rp);
8177c478bd9Sstevel@tonic-gate }
8187c478bd9Sstevel@tonic-gate
8197c478bd9Sstevel@tonic-gate done:
8207c478bd9Sstevel@tonic-gate if (mp->map_type == DDI_MT_RNUMBER)
8217c478bd9Sstevel@tonic-gate kmem_free(rp - r_no, reglen);
8227c478bd9Sstevel@tonic-gate
8237c478bd9Sstevel@tonic-gate return (rval);
8247c478bd9Sstevel@tonic-gate }
8257c478bd9Sstevel@tonic-gate
8267c478bd9Sstevel@tonic-gate /*
8277c478bd9Sstevel@tonic-gate * bus dma map entry point
8287c478bd9Sstevel@tonic-gate * return value:
8297c478bd9Sstevel@tonic-gate * DDI_DMA_PARTIAL_MAP 1
8307c478bd9Sstevel@tonic-gate * DDI_DMA_MAPOK 0
8317c478bd9Sstevel@tonic-gate * DDI_DMA_MAPPED 0
8327c478bd9Sstevel@tonic-gate * DDI_DMA_NORESOURCES -1
8337c478bd9Sstevel@tonic-gate * DDI_DMA_NOMAPPING -2
8347c478bd9Sstevel@tonic-gate * DDI_DMA_TOOBIG -3
8357c478bd9Sstevel@tonic-gate */
8367c478bd9Sstevel@tonic-gate int
px_dma_setup(dev_info_t * dip,dev_info_t * rdip,ddi_dma_req_t * dmareq,ddi_dma_handle_t * handlep)8377c478bd9Sstevel@tonic-gate px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq,
8387c478bd9Sstevel@tonic-gate ddi_dma_handle_t *handlep)
8397c478bd9Sstevel@tonic-gate {
8407c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
8417c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p;
8427c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp;
8437c478bd9Sstevel@tonic-gate int ret;
8447c478bd9Sstevel@tonic-gate
8457c478bd9Sstevel@tonic-gate DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n",
846eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip),
847eae2e508Skrishnae handlep ? "alloc" : "advisory");
8487c478bd9Sstevel@tonic-gate
849*e214b19eSToomas Soome mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq);
850*e214b19eSToomas Soome if (mp == NULL)
8517c478bd9Sstevel@tonic-gate return (DDI_DMA_NORESOURCES);
8527c478bd9Sstevel@tonic-gate if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING)
8537c478bd9Sstevel@tonic-gate return (DDI_DMA_NOMAPPING);
8547c478bd9Sstevel@tonic-gate if (ret = px_dma_type(px_p, dmareq, mp))
8557c478bd9Sstevel@tonic-gate goto freehandle;
8567c478bd9Sstevel@tonic-gate if (ret = px_dma_pfn(px_p, dmareq, mp))
8577c478bd9Sstevel@tonic-gate goto freehandle;
8587c478bd9Sstevel@tonic-gate
8597c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) {
860*e214b19eSToomas Soome case PX_DMAI_FLAGS_DVMA:
861*e214b19eSToomas Soome ret = px_dvma_win(px_p, dmareq, mp);
862*e214b19eSToomas Soome if (ret != 0 || handlep == NULL)
8637c478bd9Sstevel@tonic-gate goto freehandle;
8647c478bd9Sstevel@tonic-gate if (!PX_DMA_CANCACHE(mp)) { /* try fast track */
8657c478bd9Sstevel@tonic-gate if (PX_DMA_CANFAST(mp)) {
8667c478bd9Sstevel@tonic-gate if (!px_dvma_map_fast(mmu_p, mp))
8677c478bd9Sstevel@tonic-gate break;
8687c478bd9Sstevel@tonic-gate } else {
8697c478bd9Sstevel@tonic-gate PX_DVMA_FASTTRAK_PROF(mp);
8707c478bd9Sstevel@tonic-gate }
8717c478bd9Sstevel@tonic-gate }
8727c478bd9Sstevel@tonic-gate if (ret = px_dvma_map(mp, dmareq, mmu_p))
8737c478bd9Sstevel@tonic-gate goto freehandle;
8747c478bd9Sstevel@tonic-gate break;
875*e214b19eSToomas Soome case PX_DMAI_FLAGS_PTP:
876*e214b19eSToomas Soome ret = px_dma_physwin(px_p, dmareq, mp);
877*e214b19eSToomas Soome if (ret == 0 || handlep == NULL)
8787c478bd9Sstevel@tonic-gate goto freehandle;
8797c478bd9Sstevel@tonic-gate break;
88036fe4a92Segillett case PX_DMAI_FLAGS_BYPASS:
8817c478bd9Sstevel@tonic-gate default:
8827c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x",
883eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip),
884eae2e508Skrishnae PX_DMA_TYPE(mp));
8857c478bd9Sstevel@tonic-gate /*NOTREACHED*/
8867c478bd9Sstevel@tonic-gate }
8877c478bd9Sstevel@tonic-gate *handlep = (ddi_dma_handle_t)mp;
88836fe4a92Segillett mp->dmai_flags |= PX_DMAI_FLAGS_INUSE;
8897c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
8907c478bd9Sstevel@tonic-gate
8917c478bd9Sstevel@tonic-gate return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
8927c478bd9Sstevel@tonic-gate freehandle:
8937c478bd9Sstevel@tonic-gate if (ret == DDI_DMA_NORESOURCES)
8947c478bd9Sstevel@tonic-gate px_dma_freemp(mp); /* don't run_callback() */
8957c478bd9Sstevel@tonic-gate else
8967c478bd9Sstevel@tonic-gate (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
8977c478bd9Sstevel@tonic-gate return (ret);
8987c478bd9Sstevel@tonic-gate }
8997c478bd9Sstevel@tonic-gate
9007c478bd9Sstevel@tonic-gate
9017c478bd9Sstevel@tonic-gate /*
9027c478bd9Sstevel@tonic-gate * bus dma alloc handle entry point:
9037c478bd9Sstevel@tonic-gate */
9047c478bd9Sstevel@tonic-gate int
px_dma_allochdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_attr_t * attrp,int (* waitfp)(caddr_t),caddr_t arg,ddi_dma_handle_t * handlep)9057c478bd9Sstevel@tonic-gate px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
9067c478bd9Sstevel@tonic-gate int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep)
9077c478bd9Sstevel@tonic-gate {
9087c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
9097c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp;
9107c478bd9Sstevel@tonic-gate int rval;
9117c478bd9Sstevel@tonic-gate
9127c478bd9Sstevel@tonic-gate DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n",
913eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip));
9147c478bd9Sstevel@tonic-gate
9157c478bd9Sstevel@tonic-gate if (attrp->dma_attr_version != DMA_ATTR_V0)
9167c478bd9Sstevel@tonic-gate return (DDI_DMA_BADATTR);
9177c478bd9Sstevel@tonic-gate
918*e214b19eSToomas Soome mp = px_dma_allocmp(dip, rdip, waitfp, arg);
919*e214b19eSToomas Soome if (mp == NULL)
9207c478bd9Sstevel@tonic-gate return (DDI_DMA_NORESOURCES);
9217c478bd9Sstevel@tonic-gate
9227c478bd9Sstevel@tonic-gate /*
9237c478bd9Sstevel@tonic-gate * Save requestor's information
9247c478bd9Sstevel@tonic-gate */
9257c478bd9Sstevel@tonic-gate mp->dmai_attr = *attrp; /* whole object - augmented later */
92636fe4a92Segillett *PX_DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */
9277c478bd9Sstevel@tonic-gate DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp);
9287c478bd9Sstevel@tonic-gate
9297c478bd9Sstevel@tonic-gate /* check and convert dma attributes to handle parameters */
9307c478bd9Sstevel@tonic-gate if (rval = px_dma_attr2hdl(px_p, mp)) {
9317c478bd9Sstevel@tonic-gate px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
9327c478bd9Sstevel@tonic-gate *handlep = NULL;
9337c478bd9Sstevel@tonic-gate return (rval);
9347c478bd9Sstevel@tonic-gate }
9357c478bd9Sstevel@tonic-gate *handlep = (ddi_dma_handle_t)mp;
9367c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
9377c478bd9Sstevel@tonic-gate }
9387c478bd9Sstevel@tonic-gate
9397c478bd9Sstevel@tonic-gate
9407c478bd9Sstevel@tonic-gate /*
9417c478bd9Sstevel@tonic-gate * bus dma free handle entry point:
9427c478bd9Sstevel@tonic-gate */
9437c478bd9Sstevel@tonic-gate /*ARGSUSED*/
9447c478bd9Sstevel@tonic-gate int
px_dma_freehdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle)9457c478bd9Sstevel@tonic-gate px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
9467c478bd9Sstevel@tonic-gate {
9477c478bd9Sstevel@tonic-gate DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n",
948eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
9497c478bd9Sstevel@tonic-gate px_dma_freemp((ddi_dma_impl_t *)handle);
9507c478bd9Sstevel@tonic-gate
9517c478bd9Sstevel@tonic-gate if (px_kmem_clid) {
9527c478bd9Sstevel@tonic-gate DBG(DBG_DMA_FREEH, dip, "run handle callback\n");
9537c478bd9Sstevel@tonic-gate ddi_run_callback(&px_kmem_clid);
9547c478bd9Sstevel@tonic-gate }
9557c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
9567c478bd9Sstevel@tonic-gate }
9577c478bd9Sstevel@tonic-gate
9587c478bd9Sstevel@tonic-gate
9597c478bd9Sstevel@tonic-gate /*
9607c478bd9Sstevel@tonic-gate * bus dma bind handle entry point:
9617c478bd9Sstevel@tonic-gate */
9627c478bd9Sstevel@tonic-gate int
px_dma_bindhdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle,ddi_dma_req_t * dmareq,ddi_dma_cookie_t * cookiep,uint_t * ccountp)9637c478bd9Sstevel@tonic-gate px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
9647c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
9657c478bd9Sstevel@tonic-gate ddi_dma_cookie_t *cookiep, uint_t *ccountp)
9667c478bd9Sstevel@tonic-gate {
9677c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
9687c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p;
9697c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
9707c478bd9Sstevel@tonic-gate int ret;
9717c478bd9Sstevel@tonic-gate
9727c478bd9Sstevel@tonic-gate DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n",
973eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq);
9747c478bd9Sstevel@tonic-gate
97536fe4a92Segillett if (mp->dmai_flags & PX_DMAI_FLAGS_INUSE)
9767c478bd9Sstevel@tonic-gate return (DDI_DMA_INUSE);
9777c478bd9Sstevel@tonic-gate
97836fe4a92Segillett ASSERT((mp->dmai_flags & ~PX_DMAI_FLAGS_PRESERVE) == 0);
97936fe4a92Segillett mp->dmai_flags |= PX_DMAI_FLAGS_INUSE;
9807c478bd9Sstevel@tonic-gate
9817c478bd9Sstevel@tonic-gate if (ret = px_dma_type(px_p, dmareq, mp))
9827c478bd9Sstevel@tonic-gate goto err;
9837c478bd9Sstevel@tonic-gate if (ret = px_dma_pfn(px_p, dmareq, mp))
9847c478bd9Sstevel@tonic-gate goto err;
9857c478bd9Sstevel@tonic-gate
9867c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) {
98736fe4a92Segillett case PX_DMAI_FLAGS_DVMA:
9887c478bd9Sstevel@tonic-gate if (ret = px_dvma_win(px_p, dmareq, mp))
9897c478bd9Sstevel@tonic-gate goto map_err;
9907c478bd9Sstevel@tonic-gate if (!PX_DMA_CANCACHE(mp)) { /* try fast track */
9917c478bd9Sstevel@tonic-gate if (PX_DMA_CANFAST(mp)) {
9927c478bd9Sstevel@tonic-gate if (!px_dvma_map_fast(mmu_p, mp))
993*e214b19eSToomas Soome goto mapped;
9947c478bd9Sstevel@tonic-gate } else {
9957c478bd9Sstevel@tonic-gate PX_DVMA_FASTTRAK_PROF(mp);
9967c478bd9Sstevel@tonic-gate }
9977c478bd9Sstevel@tonic-gate }
9987c478bd9Sstevel@tonic-gate if (ret = px_dvma_map(mp, dmareq, mmu_p))
9997c478bd9Sstevel@tonic-gate goto map_err;
10007c478bd9Sstevel@tonic-gate mapped:
10017c478bd9Sstevel@tonic-gate *ccountp = 1;
10027c478bd9Sstevel@tonic-gate MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size);
10039a63ec27SRobert Mustacchi mp->dmai_ncookies = 1;
10049a63ec27SRobert Mustacchi mp->dmai_curcookie = 1;
10057c478bd9Sstevel@tonic-gate break;
100636fe4a92Segillett case PX_DMAI_FLAGS_BYPASS:
100736fe4a92Segillett case PX_DMAI_FLAGS_PTP:
10087c478bd9Sstevel@tonic-gate if (ret = px_dma_physwin(px_p, dmareq, mp))
10097c478bd9Sstevel@tonic-gate goto map_err;
101036fe4a92Segillett *ccountp = PX_WINLST(mp)->win_ncookies;
101136fe4a92Segillett *cookiep =
101236fe4a92Segillett *(ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); /* wholeobj */
10139a63ec27SRobert Mustacchi /*
10149a63ec27SRobert Mustacchi * mp->dmai_ncookies and mp->dmai_curcookie are set by
10159a63ec27SRobert Mustacchi * px_dma_physwin().
10169a63ec27SRobert Mustacchi */
10177c478bd9Sstevel@tonic-gate break;
10187c478bd9Sstevel@tonic-gate default:
10197c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type",
1020eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
10217c478bd9Sstevel@tonic-gate /*NOTREACHED*/
10227c478bd9Sstevel@tonic-gate }
102369cd775fSschwartz DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n",
1024eae2e508Skrishnae cookiep->dmac_address, cookiep->dmac_size);
10257c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
1026f8d2de6bSjchu
1027f8d2de6bSjchu /* insert dma handle into FMA cache */
1028567c0b92SStephen Hanson if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR)
1029eae2e508Skrishnae mp->dmai_error.err_cf = px_err_dma_hdl_check;
1030f8d2de6bSjchu
10317c478bd9Sstevel@tonic-gate return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
10327c478bd9Sstevel@tonic-gate map_err:
10337c478bd9Sstevel@tonic-gate px_dma_freepfn(mp);
10347c478bd9Sstevel@tonic-gate err:
103536fe4a92Segillett mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE;
10367c478bd9Sstevel@tonic-gate return (ret);
10377c478bd9Sstevel@tonic-gate }
10387c478bd9Sstevel@tonic-gate
10397c478bd9Sstevel@tonic-gate
10407c478bd9Sstevel@tonic-gate /*
10417c478bd9Sstevel@tonic-gate * bus dma unbind handle entry point:
10427c478bd9Sstevel@tonic-gate */
10437c478bd9Sstevel@tonic-gate /*ARGSUSED*/
10447c478bd9Sstevel@tonic-gate int
px_dma_unbindhdl(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle)10457c478bd9Sstevel@tonic-gate px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
10467c478bd9Sstevel@tonic-gate {
10477c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
10487c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
10497c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p;
10507c478bd9Sstevel@tonic-gate
10517c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n",
1052eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
105336fe4a92Segillett if ((mp->dmai_flags & PX_DMAI_FLAGS_INUSE) == 0) {
10547c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n");
10557c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
10567c478bd9Sstevel@tonic-gate }
10577c478bd9Sstevel@tonic-gate
1058567c0b92SStephen Hanson mp->dmai_error.err_cf = NULL;
1059f8d2de6bSjchu
10607c478bd9Sstevel@tonic-gate /*
10617c478bd9Sstevel@tonic-gate * Here if the handle is using the iommu. Unload all the iommu
10627c478bd9Sstevel@tonic-gate * translations.
10637c478bd9Sstevel@tonic-gate */
10647c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) {
106536fe4a92Segillett case PX_DMAI_FLAGS_DVMA:
10667c478bd9Sstevel@tonic-gate px_mmu_unmap_window(mmu_p, mp);
10677c478bd9Sstevel@tonic-gate px_dvma_unmap(mmu_p, mp);
10687c478bd9Sstevel@tonic-gate px_dma_freepfn(mp);
10697c478bd9Sstevel@tonic-gate break;
107036fe4a92Segillett case PX_DMAI_FLAGS_BYPASS:
107136fe4a92Segillett case PX_DMAI_FLAGS_PTP:
10727c478bd9Sstevel@tonic-gate px_dma_freewin(mp);
10737c478bd9Sstevel@tonic-gate break;
10747c478bd9Sstevel@tonic-gate default:
10757c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p",
1076eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
10777c478bd9Sstevel@tonic-gate /*NOTREACHED*/
10787c478bd9Sstevel@tonic-gate }
10797c478bd9Sstevel@tonic-gate if (mmu_p->mmu_dvma_clid != 0) {
10807c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n");
10817c478bd9Sstevel@tonic-gate ddi_run_callback(&mmu_p->mmu_dvma_clid);
10827c478bd9Sstevel@tonic-gate }
10837c478bd9Sstevel@tonic-gate if (px_kmem_clid) {
10847c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n");
10857c478bd9Sstevel@tonic-gate ddi_run_callback(&px_kmem_clid);
10867c478bd9Sstevel@tonic-gate }
108736fe4a92Segillett mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE;
10889a63ec27SRobert Mustacchi mp->dmai_ncookies = 0;
10899a63ec27SRobert Mustacchi mp->dmai_curcookie = 0;
1090f8d2de6bSjchu
10917c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
10927c478bd9Sstevel@tonic-gate }
10937c478bd9Sstevel@tonic-gate
10947c478bd9Sstevel@tonic-gate /*
10957c478bd9Sstevel@tonic-gate * bus dma win entry point:
10967c478bd9Sstevel@tonic-gate */
10977c478bd9Sstevel@tonic-gate int
px_dma_win(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle,uint_t win,off_t * offp,size_t * lenp,ddi_dma_cookie_t * cookiep,uint_t * ccountp)10987c478bd9Sstevel@tonic-gate px_dma_win(dev_info_t *dip, dev_info_t *rdip,
10997c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, uint_t win, off_t *offp,
11007c478bd9Sstevel@tonic-gate size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp)
11017c478bd9Sstevel@tonic-gate {
11027c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
11037c478bd9Sstevel@tonic-gate int ret;
11047c478bd9Sstevel@tonic-gate
11057c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n",
1106eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip));
11077c478bd9Sstevel@tonic-gate
11087c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_WIN, dip, mp);
11097c478bd9Sstevel@tonic-gate if (win >= mp->dmai_nwin) {
11107c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, "%x out of range\n", win);
11117c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
11127c478bd9Sstevel@tonic-gate }
11137c478bd9Sstevel@tonic-gate
11147c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) {
111536fe4a92Segillett case PX_DMAI_FLAGS_DVMA:
11167c478bd9Sstevel@tonic-gate if (win != PX_DMA_CURWIN(mp)) {
11177c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
11187c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p;
11197c478bd9Sstevel@tonic-gate px_mmu_unmap_window(mmu_p, mp);
11207c478bd9Sstevel@tonic-gate
11217c478bd9Sstevel@tonic-gate /* map_window sets dmai_mapping/size/offset */
11227c478bd9Sstevel@tonic-gate px_mmu_map_window(mmu_p, mp, win);
11237c478bd9Sstevel@tonic-gate if ((ret = px_mmu_map_window(mmu_p,
11247c478bd9Sstevel@tonic-gate mp, win)) != DDI_SUCCESS)
11257c478bd9Sstevel@tonic-gate return (ret);
11267c478bd9Sstevel@tonic-gate }
11277c478bd9Sstevel@tonic-gate if (cookiep)
11287c478bd9Sstevel@tonic-gate MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping,
1129eae2e508Skrishnae mp->dmai_size);
11307c478bd9Sstevel@tonic-gate if (ccountp)
11317c478bd9Sstevel@tonic-gate *ccountp = 1;
11329a63ec27SRobert Mustacchi mp->dmai_ncookies = 1;
11339a63ec27SRobert Mustacchi mp->dmai_curcookie = 1;
11347c478bd9Sstevel@tonic-gate break;
113536fe4a92Segillett case PX_DMAI_FLAGS_PTP:
113636fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: {
11377c478bd9Sstevel@tonic-gate int i;
11387c478bd9Sstevel@tonic-gate ddi_dma_cookie_t *ck_p;
11397c478bd9Sstevel@tonic-gate px_dma_win_t *win_p = mp->dmai_winlst;
11407c478bd9Sstevel@tonic-gate
1141eae2e508Skrishnae for (i = 0; i < win; win_p = win_p->win_next, i++) {};
11427c478bd9Sstevel@tonic-gate ck_p = (ddi_dma_cookie_t *)(win_p + 1);
11437c478bd9Sstevel@tonic-gate *cookiep = *ck_p;
11447c478bd9Sstevel@tonic-gate mp->dmai_offset = win_p->win_offset;
11457c478bd9Sstevel@tonic-gate mp->dmai_size = win_p->win_size;
11467c478bd9Sstevel@tonic-gate mp->dmai_mapping = ck_p->dmac_laddress;
11477c478bd9Sstevel@tonic-gate mp->dmai_cookie = ck_p + 1;
11487c478bd9Sstevel@tonic-gate win_p->win_curseg = 0;
11497c478bd9Sstevel@tonic-gate if (ccountp)
11507c478bd9Sstevel@tonic-gate *ccountp = win_p->win_ncookies;
11519a63ec27SRobert Mustacchi mp->dmai_ncookies = win_p->win_ncookies;
11529a63ec27SRobert Mustacchi mp->dmai_curcookie = 1;
11537c478bd9Sstevel@tonic-gate }
11547c478bd9Sstevel@tonic-gate break;
11557c478bd9Sstevel@tonic-gate default:
11567c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x",
1157eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip),
1158eae2e508Skrishnae PX_DMA_TYPE(mp));
11597c478bd9Sstevel@tonic-gate return (DDI_FAILURE);
11607c478bd9Sstevel@tonic-gate }
11617c478bd9Sstevel@tonic-gate if (cookiep)
11627c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip,
1163eae2e508Skrishnae "cookie - dmac_address=%x dmac_size=%x\n",
1164eae2e508Skrishnae cookiep->dmac_address, cookiep->dmac_size);
11657c478bd9Sstevel@tonic-gate if (offp)
11667c478bd9Sstevel@tonic-gate *offp = (off_t)mp->dmai_offset;
11677c478bd9Sstevel@tonic-gate if (lenp)
11687c478bd9Sstevel@tonic-gate *lenp = mp->dmai_size;
11697c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
11707c478bd9Sstevel@tonic-gate }
11717c478bd9Sstevel@tonic-gate
11727c478bd9Sstevel@tonic-gate #ifdef DEBUG
11737c478bd9Sstevel@tonic-gate static char *px_dmactl_str[] = {
11747c478bd9Sstevel@tonic-gate "DDI_DMA_FREE",
11757c478bd9Sstevel@tonic-gate "DDI_DMA_SYNC",
11767c478bd9Sstevel@tonic-gate "DDI_DMA_HTOC",
11777c478bd9Sstevel@tonic-gate "DDI_DMA_KVADDR",
11787c478bd9Sstevel@tonic-gate "DDI_DMA_MOVWIN",
11797c478bd9Sstevel@tonic-gate "DDI_DMA_REPWIN",
11807c478bd9Sstevel@tonic-gate "DDI_DMA_GETERR",
11817c478bd9Sstevel@tonic-gate "DDI_DMA_COFF",
11827c478bd9Sstevel@tonic-gate "DDI_DMA_NEXTWIN",
11837c478bd9Sstevel@tonic-gate "DDI_DMA_NEXTSEG",
11847c478bd9Sstevel@tonic-gate "DDI_DMA_SEGTOC",
11857c478bd9Sstevel@tonic-gate "DDI_DMA_RESERVE",
11867c478bd9Sstevel@tonic-gate "DDI_DMA_RELEASE",
11877c478bd9Sstevel@tonic-gate "DDI_DMA_RESETH",
11887c478bd9Sstevel@tonic-gate "DDI_DMA_CKSYNC",
11897c478bd9Sstevel@tonic-gate "DDI_DMA_IOPB_ALLOC",
11907c478bd9Sstevel@tonic-gate "DDI_DMA_IOPB_FREE",
11917c478bd9Sstevel@tonic-gate "DDI_DMA_SMEM_ALLOC",
11927c478bd9Sstevel@tonic-gate "DDI_DMA_SMEM_FREE",
11937c478bd9Sstevel@tonic-gate "DDI_DMA_SET_SBUS64"
11947c478bd9Sstevel@tonic-gate };
11957c478bd9Sstevel@tonic-gate #endif /* DEBUG */
11967c478bd9Sstevel@tonic-gate
11977c478bd9Sstevel@tonic-gate /*
11987c478bd9Sstevel@tonic-gate * bus dma control entry point:
11997c478bd9Sstevel@tonic-gate */
12007c478bd9Sstevel@tonic-gate /*ARGSUSED*/
12017c478bd9Sstevel@tonic-gate int
px_dma_ctlops(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle,enum ddi_dma_ctlops cmd,off_t * offp,size_t * lenp,caddr_t * objp,uint_t cache_flags)12027c478bd9Sstevel@tonic-gate px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
12037c478bd9Sstevel@tonic-gate enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
12047c478bd9Sstevel@tonic-gate uint_t cache_flags)
12057c478bd9Sstevel@tonic-gate {
12067c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
12077c478bd9Sstevel@tonic-gate
12087c478bd9Sstevel@tonic-gate #ifdef DEBUG
12097c478bd9Sstevel@tonic-gate DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd],
1210eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip));
12117c478bd9Sstevel@tonic-gate #endif /* DEBUG */
12127c478bd9Sstevel@tonic-gate
12137c478bd9Sstevel@tonic-gate switch (cmd) {
12147c478bd9Sstevel@tonic-gate case DDI_DMA_FREE:
12157c478bd9Sstevel@tonic-gate (void) px_dma_unbindhdl(dip, rdip, handle);
12167c478bd9Sstevel@tonic-gate (void) px_dma_freehdl(dip, rdip, handle);
12177c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
12187c478bd9Sstevel@tonic-gate case DDI_DMA_RESERVE: {
12197c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
12207c478bd9Sstevel@tonic-gate return (px_fdvma_reserve(dip, rdip, px_p,
1221eae2e508Skrishnae (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp));
12227c478bd9Sstevel@tonic-gate }
12237c478bd9Sstevel@tonic-gate case DDI_DMA_RELEASE: {
12247c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
12257c478bd9Sstevel@tonic-gate return (px_fdvma_release(dip, px_p, mp));
12267c478bd9Sstevel@tonic-gate }
12277c478bd9Sstevel@tonic-gate default:
12287c478bd9Sstevel@tonic-gate break;
12297c478bd9Sstevel@tonic-gate }
12307c478bd9Sstevel@tonic-gate
12317c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) {
123236fe4a92Segillett case PX_DMAI_FLAGS_DVMA:
12337c478bd9Sstevel@tonic-gate return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
1234eae2e508Skrishnae cache_flags));
123536fe4a92Segillett case PX_DMAI_FLAGS_PTP:
123636fe4a92Segillett case PX_DMAI_FLAGS_BYPASS:
12377c478bd9Sstevel@tonic-gate return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
1238eae2e508Skrishnae cache_flags));
12397c478bd9Sstevel@tonic-gate default:
12407c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x",
1241eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip), cmd,
1242eae2e508Skrishnae mp->dmai_flags);
12437c478bd9Sstevel@tonic-gate /*NOTREACHED*/
12447c478bd9Sstevel@tonic-gate }
1245b40cec45Skrishnae return (0);
12467c478bd9Sstevel@tonic-gate }
12477c478bd9Sstevel@tonic-gate
12487c478bd9Sstevel@tonic-gate /*
12497c478bd9Sstevel@tonic-gate * control ops entry point:
12507c478bd9Sstevel@tonic-gate *
12517c478bd9Sstevel@tonic-gate * Requests handled completely:
12527c478bd9Sstevel@tonic-gate * DDI_CTLOPS_INITCHILD see init_child() for details
12537c478bd9Sstevel@tonic-gate * DDI_CTLOPS_UNINITCHILD
12547c478bd9Sstevel@tonic-gate * DDI_CTLOPS_REPORTDEV see report_dev() for details
12557c478bd9Sstevel@tonic-gate * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1
12567c478bd9Sstevel@tonic-gate * DDI_CTLOPS_REGSIZE
12577c478bd9Sstevel@tonic-gate * DDI_CTLOPS_NREGS
12587c478bd9Sstevel@tonic-gate * DDI_CTLOPS_DVMAPAGESIZE
12597c478bd9Sstevel@tonic-gate * DDI_CTLOPS_POKE
12607c478bd9Sstevel@tonic-gate * DDI_CTLOPS_PEEK
12617c478bd9Sstevel@tonic-gate *
12627c478bd9Sstevel@tonic-gate * All others passed to parent.
12637c478bd9Sstevel@tonic-gate */
12647c478bd9Sstevel@tonic-gate int
px_ctlops(dev_info_t * dip,dev_info_t * rdip,ddi_ctl_enum_t op,void * arg,void * result)12657c478bd9Sstevel@tonic-gate px_ctlops(dev_info_t *dip, dev_info_t *rdip,
12667c478bd9Sstevel@tonic-gate ddi_ctl_enum_t op, void *arg, void *result)
12677c478bd9Sstevel@tonic-gate {
12687c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip);
12697c478bd9Sstevel@tonic-gate struct detachspec *ds;
12707c478bd9Sstevel@tonic-gate struct attachspec *as;
12717c478bd9Sstevel@tonic-gate
12727c478bd9Sstevel@tonic-gate switch (op) {
12737c478bd9Sstevel@tonic-gate case DDI_CTLOPS_INITCHILD:
12747c478bd9Sstevel@tonic-gate return (px_init_child(px_p, (dev_info_t *)arg));
12757c478bd9Sstevel@tonic-gate
12767c478bd9Sstevel@tonic-gate case DDI_CTLOPS_UNINITCHILD:
12777c478bd9Sstevel@tonic-gate return (px_uninit_child(px_p, (dev_info_t *)arg));
12787c478bd9Sstevel@tonic-gate
12797c478bd9Sstevel@tonic-gate case DDI_CTLOPS_ATTACH:
12806e8a7b44Sjchu if (!pcie_is_child(dip, rdip))
12816e8a7b44Sjchu return (DDI_SUCCESS);
12826e8a7b44Sjchu
12837c478bd9Sstevel@tonic-gate as = (struct attachspec *)arg;
12847c478bd9Sstevel@tonic-gate switch (as->when) {
12857c478bd9Sstevel@tonic-gate case DDI_PRE:
12867c478bd9Sstevel@tonic-gate if (as->cmd == DDI_ATTACH) {
12877c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n",
12887c478bd9Sstevel@tonic-gate ddi_driver_name(rdip),
12897c478bd9Sstevel@tonic-gate ddi_get_instance(rdip));
12907c478bd9Sstevel@tonic-gate return (pcie_pm_hold(dip));
12917c478bd9Sstevel@tonic-gate }
12928bc7d88aSet if (as->cmd == DDI_RESUME) {
12938bc7d88aSet DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n",
12948bc7d88aSet ddi_driver_name(rdip),
12958bc7d88aSet ddi_get_instance(rdip));
12968bc7d88aSet
1297eae2e508Skrishnae pcie_clear_errors(rdip);
12988bc7d88aSet }
12997c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
13007c478bd9Sstevel@tonic-gate
13017c478bd9Sstevel@tonic-gate case DDI_POST:
13027c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n",
13037c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip));
1304c2cc6e07SRamesh Chitrothu if (as->cmd == DDI_ATTACH &&
1305c2cc6e07SRamesh Chitrothu as->result != DDI_SUCCESS) {
1306c2cc6e07SRamesh Chitrothu /*
1307c2cc6e07SRamesh Chitrothu * Attach failed for the child device. The child
1308c2cc6e07SRamesh Chitrothu * driver may have made PM calls before the
1309c2cc6e07SRamesh Chitrothu * attach failed. pcie_pm_remove_child() should
1310c2cc6e07SRamesh Chitrothu * cleanup PM state and holds (if any)
1311c2cc6e07SRamesh Chitrothu * associated with the child device.
1312c2cc6e07SRamesh Chitrothu */
1313c2cc6e07SRamesh Chitrothu return (pcie_pm_remove_child(dip, rdip));
1314c2cc6e07SRamesh Chitrothu }
131513683ea2Skrishnae
1316e0d05aa9Skrishnae if (as->result == DDI_SUCCESS)
1317e0d05aa9Skrishnae pf_init(rdip, (void *)px_p->px_fm_ibc, as->cmd);
1318bf8fc234Set
131913683ea2Skrishnae (void) pcie_postattach_child(rdip);
132013683ea2Skrishnae
13217c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
13227c478bd9Sstevel@tonic-gate default:
13237c478bd9Sstevel@tonic-gate break;
13247c478bd9Sstevel@tonic-gate }
13257c478bd9Sstevel@tonic-gate break;
13267c478bd9Sstevel@tonic-gate
13277c478bd9Sstevel@tonic-gate case DDI_CTLOPS_DETACH:
1328025c5d04Sjchu if (!pcie_is_child(dip, rdip))
1329025c5d04Sjchu return (DDI_SUCCESS);
1330025c5d04Sjchu
13317c478bd9Sstevel@tonic-gate ds = (struct detachspec *)arg;
13327c478bd9Sstevel@tonic-gate switch (ds->when) {
13337c478bd9Sstevel@tonic-gate case DDI_POST:
13347c478bd9Sstevel@tonic-gate if (ds->cmd == DDI_DETACH &&
13357c478bd9Sstevel@tonic-gate ds->result == DDI_SUCCESS) {
13367c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n",
13377c478bd9Sstevel@tonic-gate ddi_driver_name(rdip),
13387c478bd9Sstevel@tonic-gate ddi_get_instance(rdip));
13397c478bd9Sstevel@tonic-gate return (pcie_pm_remove_child(dip, rdip));
13407c478bd9Sstevel@tonic-gate }
13417c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
1342bf8fc234Set case DDI_PRE:
13430c5eba8cSkrishnae pf_fini(rdip, ds->cmd);
1344bf8fc234Set return (DDI_SUCCESS);
13457c478bd9Sstevel@tonic-gate default:
13467c478bd9Sstevel@tonic-gate break;
13477c478bd9Sstevel@tonic-gate }
13487c478bd9Sstevel@tonic-gate break;
13497c478bd9Sstevel@tonic-gate
13507c478bd9Sstevel@tonic-gate case DDI_CTLOPS_REPORTDEV:
1351fc256490SJason Beloro if (ddi_get_parent(rdip) == dip)
1352fc256490SJason Beloro return (px_report_dev(rdip));
1353fc256490SJason Beloro
1354fc256490SJason Beloro (void) px_lib_fabric_sync(rdip);
1355fc256490SJason Beloro return (DDI_SUCCESS);
13567c478bd9Sstevel@tonic-gate
13577c478bd9Sstevel@tonic-gate case DDI_CTLOPS_IOMIN:
13587c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
13597c478bd9Sstevel@tonic-gate
13607c478bd9Sstevel@tonic-gate case DDI_CTLOPS_REGSIZE:
13617c478bd9Sstevel@tonic-gate *((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg));
1362f8d2de6bSjchu return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS);
13637c478bd9Sstevel@tonic-gate
13647c478bd9Sstevel@tonic-gate case DDI_CTLOPS_NREGS:
13657c478bd9Sstevel@tonic-gate *((uint_t *)result) = px_get_nreg_set(rdip);
13667c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
13677c478bd9Sstevel@tonic-gate
13687c478bd9Sstevel@tonic-gate case DDI_CTLOPS_DVMAPAGESIZE:
13697c478bd9Sstevel@tonic-gate *((ulong_t *)result) = MMU_PAGE_SIZE;
13707c478bd9Sstevel@tonic-gate return (DDI_SUCCESS);
13717c478bd9Sstevel@tonic-gate
13727c478bd9Sstevel@tonic-gate case DDI_CTLOPS_POKE: /* platform dependent implementation. */
13737c478bd9Sstevel@tonic-gate return (px_lib_ctlops_poke(dip, rdip,
13747c478bd9Sstevel@tonic-gate (peekpoke_ctlops_t *)arg));
13757c478bd9Sstevel@tonic-gate
13767c478bd9Sstevel@tonic-gate case DDI_CTLOPS_PEEK: /* platform dependent implementation. */
13777c478bd9Sstevel@tonic-gate return (px_lib_ctlops_peek(dip, rdip,
13787c478bd9Sstevel@tonic-gate (peekpoke_ctlops_t *)arg, result));
13797c478bd9Sstevel@tonic-gate
13807c478bd9Sstevel@tonic-gate case DDI_CTLOPS_POWER:
13817c478bd9Sstevel@tonic-gate default:
13827c478bd9Sstevel@tonic-gate break;
13837c478bd9Sstevel@tonic-gate }
13847c478bd9Sstevel@tonic-gate
13857c478bd9Sstevel@tonic-gate /*
13867c478bd9Sstevel@tonic-gate * Now pass the request up to our parent.
13877c478bd9Sstevel@tonic-gate */
13887c478bd9Sstevel@tonic-gate DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n",
1389eae2e508Skrishnae ddi_driver_name(rdip), ddi_get_instance(rdip));
13907c478bd9Sstevel@tonic-gate return (ddi_ctlops(dip, rdip, op, arg, result));
13917c478bd9Sstevel@tonic-gate }
13927c478bd9Sstevel@tonic-gate
13937c478bd9Sstevel@tonic-gate /* ARGSUSED */
13947c478bd9Sstevel@tonic-gate int
px_intr_ops(dev_info_t * dip,dev_info_t * rdip,ddi_intr_op_t intr_op,ddi_intr_handle_impl_t * hdlp,void * result)13957c478bd9Sstevel@tonic-gate px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
13967c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result)
13977c478bd9Sstevel@tonic-gate {
13987c478bd9Sstevel@tonic-gate int intr_types, ret = DDI_SUCCESS;
1399fc256490SJason Beloro px_t *px_p = DIP_TO_STATE(dip);
14007c478bd9Sstevel@tonic-gate
14017c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n",
14027c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip));
14037c478bd9Sstevel@tonic-gate
14047c478bd9Sstevel@tonic-gate /* Process DDI_INTROP_SUPPORTED_TYPES request here */
14057c478bd9Sstevel@tonic-gate if (intr_op == DDI_INTROP_SUPPORTED_TYPES) {
1406a54f81fbSanish *(int *)result = i_ddi_get_intx_nintrs(rdip) ?
14077c478bd9Sstevel@tonic-gate DDI_INTR_TYPE_FIXED : 0;
14087c478bd9Sstevel@tonic-gate
14097c478bd9Sstevel@tonic-gate if ((pci_msi_get_supported_type(rdip,
14107c478bd9Sstevel@tonic-gate &intr_types)) == DDI_SUCCESS) {
14117c478bd9Sstevel@tonic-gate /*
14127c478bd9Sstevel@tonic-gate * Double check supported interrupt types vs.
14137c478bd9Sstevel@tonic-gate * what the host bridge supports.
14147c478bd9Sstevel@tonic-gate */
141520036fe5Segillett *(int *)result |= intr_types;
14167c478bd9Sstevel@tonic-gate }
14177c478bd9Sstevel@tonic-gate
1418788cfa89SDavid Woods *(int *)result &=
1419788cfa89SDavid Woods (px_force_intx_support ?
1420788cfa89SDavid Woods (px_p->px_supp_intr_types | DDI_INTR_TYPE_FIXED) :
1421788cfa89SDavid Woods px_p->px_supp_intr_types);
1422fc256490SJason Beloro return (*(int *)result ? DDI_SUCCESS : DDI_FAILURE);
14237c478bd9Sstevel@tonic-gate }
14247c478bd9Sstevel@tonic-gate
14257c478bd9Sstevel@tonic-gate /*
14267c478bd9Sstevel@tonic-gate * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts.
14277c478bd9Sstevel@tonic-gate * Return failure if interrupt type is not supported.
14287c478bd9Sstevel@tonic-gate */
14297c478bd9Sstevel@tonic-gate switch (hdlp->ih_type) {
14307c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_FIXED:
14317c478bd9Sstevel@tonic-gate ret = px_intx_ops(dip, rdip, intr_op, hdlp, result);
14327c478bd9Sstevel@tonic-gate break;
14337c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_MSI:
14347c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_MSIX:
14357c478bd9Sstevel@tonic-gate ret = px_msix_ops(dip, rdip, intr_op, hdlp, result);
14367c478bd9Sstevel@tonic-gate break;
14377c478bd9Sstevel@tonic-gate default:
14387c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP;
14397c478bd9Sstevel@tonic-gate break;
14407c478bd9Sstevel@tonic-gate }
14417c478bd9Sstevel@tonic-gate
14427c478bd9Sstevel@tonic-gate return (ret);
14437c478bd9Sstevel@tonic-gate }
1444b65731f1Skini
14450114761dSAlan Adamson, SD OSSD static void
px_set_mps(px_t * px_p)14460114761dSAlan Adamson, SD OSSD px_set_mps(px_t *px_p)
14470114761dSAlan Adamson, SD OSSD {
14480114761dSAlan Adamson, SD OSSD dev_info_t *dip;
14490114761dSAlan Adamson, SD OSSD pcie_bus_t *bus_p;
14500114761dSAlan Adamson, SD OSSD int max_supported;
14510114761dSAlan Adamson, SD OSSD
14520114761dSAlan Adamson, SD OSSD dip = px_p->px_dip;
14530114761dSAlan Adamson, SD OSSD bus_p = PCIE_DIP2BUS(dip);
14540114761dSAlan Adamson, SD OSSD
14550114761dSAlan Adamson, SD OSSD bus_p->bus_mps = -1;
14560114761dSAlan Adamson, SD OSSD
14570114761dSAlan Adamson, SD OSSD if (pcie_root_port(dip) == DDI_FAILURE) {
14580114761dSAlan Adamson, SD OSSD if (px_lib_get_root_complex_mps(px_p, dip,
14590114761dSAlan Adamson, SD OSSD &max_supported) < 0) {
14600114761dSAlan Adamson, SD OSSD
14610114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Can not get RC MPS\n");
14620114761dSAlan Adamson, SD OSSD return;
14630114761dSAlan Adamson, SD OSSD }
14640114761dSAlan Adamson, SD OSSD
14650114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Root Complex MPS Cap of = %x\n",
14660114761dSAlan Adamson, SD OSSD max_supported);
14670114761dSAlan Adamson, SD OSSD
14680114761dSAlan Adamson, SD OSSD if (pcie_max_mps < max_supported)
14690114761dSAlan Adamson, SD OSSD max_supported = pcie_max_mps;
14700114761dSAlan Adamson, SD OSSD
14710114761dSAlan Adamson, SD OSSD (void) pcie_get_fabric_mps(dip, ddi_get_child(dip),
14720114761dSAlan Adamson, SD OSSD &max_supported);
14730114761dSAlan Adamson, SD OSSD
14740114761dSAlan Adamson, SD OSSD bus_p->bus_mps = max_supported;
14750114761dSAlan Adamson, SD OSSD
14760114761dSAlan Adamson, SD OSSD (void) px_lib_set_root_complex_mps(px_p, dip, bus_p->bus_mps);
14770114761dSAlan Adamson, SD OSSD
14780114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Root Complex MPS Set to = %x\n",
14790114761dSAlan Adamson, SD OSSD bus_p->bus_mps);
14800114761dSAlan Adamson, SD OSSD }
14810114761dSAlan Adamson, SD OSSD }
1482