17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5d64540e3Sgd * Common Development and Distribution License (the "License"). 6d64540e3Sgd * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22d64540e3Sgd * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23d64540e3Sgd * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_ERI_MAC_H 277c478bd9Sstevel@tonic-gate #define _SYS_ERI_MAC_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #ifdef __cplusplus 327c478bd9Sstevel@tonic-gate extern "C" { 337c478bd9Sstevel@tonic-gate #endif 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate /* 367c478bd9Sstevel@tonic-gate * HOST MEMORY DATA STRUCTURES 377c478bd9Sstevel@tonic-gate * Transmit and Receive Descriptor Rings 387c478bd9Sstevel@tonic-gate */ 397c478bd9Sstevel@tonic-gate 407c478bd9Sstevel@tonic-gate /* The Descriptor Ring base Addresses must be 2K-byte aligned */ 417c478bd9Sstevel@tonic-gate 427c478bd9Sstevel@tonic-gate #define ERI_GMDALIGN (2048) 437c478bd9Sstevel@tonic-gate 447c478bd9Sstevel@tonic-gate /* 457c478bd9Sstevel@tonic-gate * The transmit and receiver Descriptor Rings are organized as "wrap-around 467c478bd9Sstevel@tonic-gate * descriptors and are of programmable size. 477c478bd9Sstevel@tonic-gate * Each descriptor consists of two double-word entries: a control/status entry 487c478bd9Sstevel@tonic-gate * and a pointer to a data buffer. 497c478bd9Sstevel@tonic-gate * The no. of entries is programmable in binary increments, from 32 to 8192. 507c478bd9Sstevel@tonic-gate * TBD: Even though the Receive Desriptor ring size is 8k, provide for a user 517c478bd9Sstevel@tonic-gate * configurable variable to specify the max.no. of Rx buffers posted. 527c478bd9Sstevel@tonic-gate */ 537c478bd9Sstevel@tonic-gate 547c478bd9Sstevel@tonic-gate #define ERI_TMDMAX (4096) /* Transmit descriptor ring size */ 557c478bd9Sstevel@tonic-gate #define ERI_RMDMAX (4096) /* Receive descriptor ring size */ 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate /* 587c478bd9Sstevel@tonic-gate * ----------------------------- 597c478bd9Sstevel@tonic-gate * Transmit descriptor structure 607c478bd9Sstevel@tonic-gate * ----------------------------- 617c478bd9Sstevel@tonic-gate */ 627c478bd9Sstevel@tonic-gate 637c478bd9Sstevel@tonic-gate struct eri_tmd { 647c478bd9Sstevel@tonic-gate uint64_t tmd_flags; /* INTME, SOP, EOP, cksum, bufsize */ 657c478bd9Sstevel@tonic-gate uint64_t tmd_addr; /* buffer address */ 667c478bd9Sstevel@tonic-gate }; 677c478bd9Sstevel@tonic-gate 687c478bd9Sstevel@tonic-gate /* fields in the tmd_flags */ 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate #define ERI_TMD_BUFSIZE (0x7fff << 0) /* 0-14 : Tx Data buffer size */ 717c478bd9Sstevel@tonic-gate /* valid values in range 0 - 17k */ 727c478bd9Sstevel@tonic-gate #define ERI_TMD_CSSTART (0x3f << 15) /* 15-20 : Checksum start offset */ 737c478bd9Sstevel@tonic-gate /* value must be even */ 747c478bd9Sstevel@tonic-gate #define ERI_TMD_CSSTUFF (0xff << 21) /* 21-28 : Checksum stuff offset */ 757c478bd9Sstevel@tonic-gate /* value must be even */ 767c478bd9Sstevel@tonic-gate #define ERI_TMD_CSENABL (1 << 29) /* 29 : Enable checksum computation */ 777c478bd9Sstevel@tonic-gate #define ERI_TMD_EOP (1 << 30) /* 30 : End Of Packet flag */ 787c478bd9Sstevel@tonic-gate #define ERI_TMD_SOP ((uint64_t)1 << 31) /* 31 : Packet Start flag */ 797c478bd9Sstevel@tonic-gate #define ERI_TMD_INTME ((uint64_t)1 << 32) /* 32 : Interrupt me now */ 807c478bd9Sstevel@tonic-gate #define ERI_TMD_NOCRC ((uint64_t)1 << 33) /* 33 : Do not insert CRC */ 817c478bd9Sstevel@tonic-gate 827c478bd9Sstevel@tonic-gate #define ERI_TMD_CSSTART_SHIFT 15 /* checksum start bit position */ 837c478bd9Sstevel@tonic-gate #define ERI_TMD_CSSTUFF_SHIFT 21 /* checksum stuff bit position */ 847c478bd9Sstevel@tonic-gate 857c478bd9Sstevel@tonic-gate /* 867c478bd9Sstevel@tonic-gate * TCP Header offset within Ethernet Packet: 877c478bd9Sstevel@tonic-gate * 14 Bytes Ethernet Header + 20 IP Header. 887c478bd9Sstevel@tonic-gate */ 897c478bd9Sstevel@tonic-gate 907c478bd9Sstevel@tonic-gate #define ERI_TCPHDR_OFFSET 34 917c478bd9Sstevel@tonic-gate #define ERI_IPHDR_OFFSET 20 927c478bd9Sstevel@tonic-gate 937c478bd9Sstevel@tonic-gate /* 947c478bd9Sstevel@tonic-gate * TCP Checksum stuff offset within Ethernet packet: 957c478bd9Sstevel@tonic-gate * 34 Bytes up to TCP Header + 16 Bytes within TCP header 967c478bd9Sstevel@tonic-gate */ 977c478bd9Sstevel@tonic-gate 987c478bd9Sstevel@tonic-gate #define ERI_TCPCSUM_OFFSET 50 997c478bd9Sstevel@tonic-gate #define ERI_TMDCSUM_CTL (ERI_TMD_CSENABL | \ 1007c478bd9Sstevel@tonic-gate (ERI_TCPHDR_OFFSET << ERI_TMD_CSSTART_SHIFT) | \ 1017c478bd9Sstevel@tonic-gate (ERI_TCPCSUM_OFFSET << ERI_TMD_CSSTUFF_SHIFT)) 1027c478bd9Sstevel@tonic-gate /* 1037c478bd9Sstevel@tonic-gate * Programming Notes: 1047c478bd9Sstevel@tonic-gate * 1057c478bd9Sstevel@tonic-gate * 1. TX Kick Register is used to hand over TX descriptors to the hardware. 1067c478bd9Sstevel@tonic-gate * TX Completion Register is used by hardware to handover TX descriptors 1077c478bd9Sstevel@tonic-gate * back to the software. 1087c478bd9Sstevel@tonic-gate * 1097c478bd9Sstevel@tonic-gate * 2. ERI never writes back TX descriptors. 1107c478bd9Sstevel@tonic-gate * 1117c478bd9Sstevel@tonic-gate * 2. If a packet resides in more than one buffer, the Checksum_Enable, 1127c478bd9Sstevel@tonic-gate * Checksum_Stuff_Offset, Checksum_Start_Offset and Int_me fields need to 1137c478bd9Sstevel@tonic-gate * be set only in the first descriptor for the packet. 1147c478bd9Sstevel@tonic-gate * 1157c478bd9Sstevel@tonic-gate * 3. The hardware implementation relies on the fact that if a buffer 1167c478bd9Sstevel@tonic-gate * starts at an "odd" boundary, the DMA state machine can "rewind" 1177c478bd9Sstevel@tonic-gate * to the nearest burst boundary and execute a full DVMA burst Read. 1187c478bd9Sstevel@tonic-gate * 1197c478bd9Sstevel@tonic-gate * There is no other alignment restriction for the transmit data buffer. 1207c478bd9Sstevel@tonic-gate */ 1217c478bd9Sstevel@tonic-gate 1227c478bd9Sstevel@tonic-gate /* 1237c478bd9Sstevel@tonic-gate * ----------------------------- 1247c478bd9Sstevel@tonic-gate * Receive Descriptor structure 1257c478bd9Sstevel@tonic-gate * ---------------------------- 1267c478bd9Sstevel@tonic-gate */ 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate struct rmd { 1297c478bd9Sstevel@tonic-gate uint64_t rmd_flags; 1307c478bd9Sstevel@tonic-gate /* hash_val, hash_pass, bad, OWN, buf/data size, cksum */ 1317c478bd9Sstevel@tonic-gate uint64_t rmd_addr; /* 8-byte aligned buffer address */ 1327c478bd9Sstevel@tonic-gate }; 1337c478bd9Sstevel@tonic-gate 1347c478bd9Sstevel@tonic-gate /* 1357c478bd9Sstevel@tonic-gate * fields in the rmd_flags 1367c478bd9Sstevel@tonic-gate */ 1377c478bd9Sstevel@tonic-gate #define ERI_RMD_CKSUM (0xffff << 0) /* 0-15 : checksum computed */ 1387c478bd9Sstevel@tonic-gate #define ERI_RMD_BUFSIZE (0x7fff << 16) /* 16-30 : buffer/frame size */ 1397c478bd9Sstevel@tonic-gate #define ERI_RMD_OWN ((uint64_t)1 << 31) /* 31 : Ownership flag */ 1407c478bd9Sstevel@tonic-gate /* 0 - owned by software */ 1417c478bd9Sstevel@tonic-gate /* 1 - owned by hardware */ 1427c478bd9Sstevel@tonic-gate #define ERI_RMD_RESERVED1 ((uint64_t)0xfff << 32) /* 32-43 : Reserved */ 1437c478bd9Sstevel@tonic-gate #define ERI_RMD_HASHVAL ((uint64_t)0xffff << 44) /* 44-59 : hash value */ 1447c478bd9Sstevel@tonic-gate #define ERI_RMD_HASHPASS ((uint64_t)1 << 60) /* 60 : pass hash filter */ 1457c478bd9Sstevel@tonic-gate #define ERI_RMD_ALTERNATE ((uint64_t)1 << 61) 1467c478bd9Sstevel@tonic-gate /* 61 : matched alternate MAC adrs */ 1477c478bd9Sstevel@tonic-gate #define ERI_RMD_BAD ((uint64_t)1 << 62) /* 62 : bad CRC frame */ 1487c478bd9Sstevel@tonic-gate #define ERI_RMD_RESERVED2 ((uint64_t)1 << 63) /* 63 : Reserved */ 1497c478bd9Sstevel@tonic-gate 1507c478bd9Sstevel@tonic-gate #define ERI_RMD_BUFSIZE_SHIFT 16 /* buffer/data size bit position */ 1517c478bd9Sstevel@tonic-gate 1527c478bd9Sstevel@tonic-gate #define ERI__RMD_BUFALIGN 8 1537c478bd9Sstevel@tonic-gate 1547c478bd9Sstevel@tonic-gate /* 1557c478bd9Sstevel@tonic-gate * ERI REGISTER SPACE 1567c478bd9Sstevel@tonic-gate * The comments are in the following format: 1577c478bd9Sstevel@tonic-gate * Addres_Offset R/W Default Actual_size(bits) Description 1587c478bd9Sstevel@tonic-gate */ 1597c478bd9Sstevel@tonic-gate 1607c478bd9Sstevel@tonic-gate /* 1617c478bd9Sstevel@tonic-gate * Global Register Space : Paritally Modified for ERI 1627c478bd9Sstevel@tonic-gate */ 1637c478bd9Sstevel@tonic-gate struct global { 1647c478bd9Sstevel@tonic-gate uint32_t seb_state; /* 0x0000 RO 0x00000000 03 SEB State Register */ 1657c478bd9Sstevel@tonic-gate uint32_t config; /* 0x0004 RW 0x00000000 17 Configuration Register */ 1667c478bd9Sstevel@tonic-gate uint32_t reserved2; /* 0x0008 */ 1677c478bd9Sstevel@tonic-gate uint32_t status; /* 0x000C R-AC 0x00000000 25 Int. Status Register */ 1687c478bd9Sstevel@tonic-gate uint32_t intmask; /* 0x0010 RW 0xFFFFFFFF 12 Interrupt Mask Reg */ 1697c478bd9Sstevel@tonic-gate uint32_t intack; /* 0x0014 WO 0x00000000 06 Interrupt Ack Register */ 1707c478bd9Sstevel@tonic-gate uint32_t reserved3; /* 0x0018 */ 1717c478bd9Sstevel@tonic-gate uint32_t status_alias; /* 0x001C RO 0x00000000 25 Int. Stat Reg Alias */ 1727c478bd9Sstevel@tonic-gate uint32_t reserved4[1016]; /* To skip to 0x1000 */ 1737c478bd9Sstevel@tonic-gate uint32_t err_status; /* 0x1000 R-AC 0x00000000 03 PCI Error Status Reg. */ 1747c478bd9Sstevel@tonic-gate uint32_t reset; /* 0x1010 RW-AC 0x00 3 Software Reset Reg */ 1757c478bd9Sstevel@tonic-gate }; 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate /* 1787c478bd9Sstevel@tonic-gate * 1797c478bd9Sstevel@tonic-gate * SBus IO configuration (RW) 1807c478bd9Sstevel@tonic-gate * To configure parameters that define the DMA burst and internal arbitration. 1817c478bd9Sstevel@tonic-gate */ 1827c478bd9Sstevel@tonic-gate #define ERI_SIOCFG_BSIZE32 (0x1 << 0) /* 32 byte burst sizeb state */ 1837c478bd9Sstevel@tonic-gate #define ERI_SIOCFG_BSIZE64 (0x1 << 1) /* 64 byte burst sizeb state */ 1847c478bd9Sstevel@tonic-gate #define ERI_SIOCFG_BSIZE128 (0x1 << 2) /* 128 byte burst sizeb state */ 1857c478bd9Sstevel@tonic-gate #define ERI_SIOCFG_BMODE64 (0x1 << 3) /* Sbus 64 bit mode */ 1867c478bd9Sstevel@tonic-gate #define ERI_SIOCFG_PARITY (0x1 << 9) /* Sbus Parity enabled. */ 1877c478bd9Sstevel@tonic-gate 1887c478bd9Sstevel@tonic-gate /* 1897c478bd9Sstevel@tonic-gate * SEB State Register (RO) 1907c478bd9Sstevel@tonic-gate * Reflects the internal state of the arbitration between TX and RX 1917c478bd9Sstevel@tonic-gate * DMA Channels. Used for diagnostics only 1927c478bd9Sstevel@tonic-gate */ 1937c478bd9Sstevel@tonic-gate #define ERI_SEB_ARBSTS (0x2 << 0) /* Arbiter state */ 1947c478bd9Sstevel@tonic-gate #define ERI_SEB_RXWON (1 << 2) /* RX won the arbitration */ 1957c478bd9Sstevel@tonic-gate 1967c478bd9Sstevel@tonic-gate /* 1977c478bd9Sstevel@tonic-gate * Global Configuration Register (RW) 1987c478bd9Sstevel@tonic-gate * To configure parameters that define the DMA burst and internal arbitration. 1997c478bd9Sstevel@tonic-gate * TX/RX_DMA_LIMIT: No. of data transfers in 64-byte multiples 2007c478bd9Sstevel@tonic-gate * 0 - peririty changes at packet boundaries 2017c478bd9Sstevel@tonic-gate * default: 0x042 2027c478bd9Sstevel@tonic-gate */ 2037c478bd9Sstevel@tonic-gate #define ERI_G_CONFIG_BURST_SIZE (0x1 << 0) /* 0:infinite/64-byte burst */ 2047c478bd9Sstevel@tonic-gate #define ERI_G_CONFIG_TX_DMA_LIM (0x1f << 1) /* 5-1: TX_DMA_Limit */ 2057c478bd9Sstevel@tonic-gate #define ERI_G_CONFIG_RX_DMA_LIM (0x1f << 6) /* 10-6: RX_DMA_Limit */ 2067c478bd9Sstevel@tonic-gate 2077c478bd9Sstevel@tonic-gate #define ERI_G_CONFIG_BURST_64 0x0 /* max burst size 64 */ 2087c478bd9Sstevel@tonic-gate #define ERI_G_CONFIG_BURST_INF 0x1 /* infinite burst for whole pkt len */ 2097c478bd9Sstevel@tonic-gate 2107c478bd9Sstevel@tonic-gate #define ERI_G_CONFIG_TX_DMA_LIM_SHIFT 1 2117c478bd9Sstevel@tonic-gate #define ERI_G_CONFIG_RX_DMA_LIM_SHIFT 6 2127c478bd9Sstevel@tonic-gate 2137c478bd9Sstevel@tonic-gate /* 2147c478bd9Sstevel@tonic-gate * Global Interrupt Status Register (R-AC) 2157c478bd9Sstevel@tonic-gate * size: 32 bits: 0-31 2167c478bd9Sstevel@tonic-gate * default: 0x00000000 2177c478bd9Sstevel@tonic-gate * This is the top level register used to communicate to the software events 2187c478bd9Sstevel@tonic-gate * that were detected by the hardware. 2197c478bd9Sstevel@tonic-gate * Top level bits 0-6 are automatically cleared to 0 when the Status Register 2207c478bd9Sstevel@tonic-gate * is read. 2217c478bd9Sstevel@tonic-gate * Second level interrupts reported by bits 13-18 are cleared at the source. 2227c478bd9Sstevel@tonic-gate * The value of the TX Completion Register is replicated in bits 19-31. 2237c478bd9Sstevel@tonic-gate */ 2247c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_INT_ME (1 << 0) 2257c478bd9Sstevel@tonic-gate /* 0 - set when a frame with INT_ME bit set is transferred to FIFO */ 2267c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_ALL (1 << 1) /* 1 - TX desc. ring empty */ 2277c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_DONE (1 << 2) /* 2 - from host to TX FIFO */ 2287c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_RES1 (1 << 3) /* 3 - reserved */ 2297c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_RX_DONE (1 << 4) /* 4 - from RXFIFO to host */ 2307c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_RX_NO_BUF (1 << 5) /* 5 - no RX buff available */ 2317c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_RX_TAG_ERR (1 << 6) /* 6 - RX tag error */ 2327c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_PERR_INT (1 << 7) /* 7 - Parity Err sts reg */ 2337c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_RES2 (0x3f << 7) /* 7-12 : reserved */ 2347c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_PCS_INT (1 << 13) /* 13 - PCS Interrupt */ 2357c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_MAC_INT (1 << 14) /* 14 - TX MAC stat reg set */ 2367c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_RX_MAC_INT (1 << 15) /* 15 - RX MAC stat reg set */ 2377c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_MAC_CTRL_INT (1 << 16) /* 16 - MAC control reg */ 2387c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_MIF_INT (1 << 17) /* 17 - MIF status reg set */ 2397c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_BUS_ERR_INT (1 << 18) /* 18 - BUS Err sts reg */ 2407c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_COMPL (0xfff80000) /* 19-31: TX Completion reg */ 2417c478bd9Sstevel@tonic-gate 2427c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_INTR (0xffffffff & ~(ERI_G_STATUS_TX_DONE |\ 2437c478bd9Sstevel@tonic-gate ERI_G_STATUS_TX_ALL |\ 2447c478bd9Sstevel@tonic-gate ERI_G_STATUS_MAC_CTRL_INT | ERI_G_STATUS_TX_COMPL)) 2457c478bd9Sstevel@tonic-gate 2467c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_INT (ERI_G_STATUS_TX_DONE | ERI_G_STATUS_TX_ALL) 2477c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_RX_INT (~ERI_G_STATUS_TX_COMPL & ~ERI_G_STATUS_TX_INT) 2487c478bd9Sstevel@tonic-gate 2497c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_FATAL_ERR (ERI_G_STATUS_RX_TAG_ERR | \ 2507c478bd9Sstevel@tonic-gate ERI_G_STATUS_PERR_INT | \ 2517c478bd9Sstevel@tonic-gate ERI_G_STATUS_BUS_ERR_INT) 2527c478bd9Sstevel@tonic-gate 2537c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_NONFATAL_ERR (ERI_G_STATUS_TX_MAC_INT | \ 2547c478bd9Sstevel@tonic-gate ERI_G_STATUS_RX_MAC_INT | \ 2557c478bd9Sstevel@tonic-gate ERI_G_STATUS_MAC_CTRL_INT) 2567c478bd9Sstevel@tonic-gate 2577c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_COMPL_SHIFT 19 2587c478bd9Sstevel@tonic-gate #define ERI_G_STATUS_TX_COMPL_MASK 0x1fff 2597c478bd9Sstevel@tonic-gate 2607c478bd9Sstevel@tonic-gate /* 2617c478bd9Sstevel@tonic-gate * Global Interrupt Mask register (RW) 2627c478bd9Sstevel@tonic-gate * size: 32 bits 2637c478bd9Sstevel@tonic-gate * default: 0xFFFFFFFF 2647c478bd9Sstevel@tonic-gate * There is one-to-one correspondence between the bits in this register and 2657c478bd9Sstevel@tonic-gate * the Global Status register. 2667c478bd9Sstevel@tonic-gate * If a mask bit is 0, the corresponding event causes an interrupt. 2677c478bd9Sstevel@tonic-gate */ 2687c478bd9Sstevel@tonic-gate 2697c478bd9Sstevel@tonic-gate 2707c478bd9Sstevel@tonic-gate #define ERI_G_MASK_TX_INT_ME (1 << 0) 2717c478bd9Sstevel@tonic-gate /* 0 - set when a frame with INT_ME bit set is transferred to FIFO */ 2727c478bd9Sstevel@tonic-gate #define ERI_G_MASK_TX_ALL (1 << 1) /* 1 - TX desc. ring empty */ 2737c478bd9Sstevel@tonic-gate #define ERI_G_MASK_TX_DONE (1 << 2) /* 2 - from host to TX FIFO */ 2747c478bd9Sstevel@tonic-gate #define ERI_G_MASK_RES1 (1 << 3) /* 3 - reserved */ 2757c478bd9Sstevel@tonic-gate #define ERI_G_MASK_RX_DONE (1 << 4) /* 4 - from RXFIFO to host */ 2767c478bd9Sstevel@tonic-gate #define ERI_G_MASK_RX_NO_BUF (1 << 5) /* 5 - no RX bufer available */ 2777c478bd9Sstevel@tonic-gate #define ERI_G_MASK_RX_TAG_ERR (1 << 6) /* 6 - RX tag error */ 2787c478bd9Sstevel@tonic-gate #define ERI_G_MASK_RES2 (0x3f << 7) /* 7-13 : reserved */ 2797c478bd9Sstevel@tonic-gate #define ERI_G_MASK_PCS_INT (1 << 13) /* 13 - PCS Interrupt */ 2807c478bd9Sstevel@tonic-gate #define ERI_G_MASK_TX_MAC_INT (1 << 14) /* 14 - TX MAC status reg set */ 2817c478bd9Sstevel@tonic-gate #define ERI_G_MASK_RX_MAC_INT (1 << 15) /* 15 - RX MAC status reg set */ 2827c478bd9Sstevel@tonic-gate #define ERI_G_MASK_MAC_CTRL_INT (1 << 16) /* 16 - MAC control reg set */ 2837c478bd9Sstevel@tonic-gate #define ERI_G_MASK_MIF_INT (1 << 17) /* 17 - MIF status reg set */ 2847c478bd9Sstevel@tonic-gate #define ERI_G_MASK_BUS_ERR_INT (1 << 18) /* 18 - BUS Error sts reg set */ 2857c478bd9Sstevel@tonic-gate 2867c478bd9Sstevel@tonic-gate #define ERI_G_MASK_INTR (~ERI_G_STATUS_INTR | ERI_G_MASK_PCS_INT) 2877c478bd9Sstevel@tonic-gate #define ERI_G_MASK_ALL (0xffffffffu) 2887c478bd9Sstevel@tonic-gate 2897c478bd9Sstevel@tonic-gate 2907c478bd9Sstevel@tonic-gate /* 2917c478bd9Sstevel@tonic-gate * Interrupt Ack Register (WO) 2927c478bd9Sstevel@tonic-gate * Its layout corresponds to the layout of the top level bits of the Interrupt 2937c478bd9Sstevel@tonic-gate * Status register. 2947c478bd9Sstevel@tonic-gate * Bit positions written high will be cleared, while bit positions written low 2957c478bd9Sstevel@tonic-gate * have no effect on the Interrupt Status Register. 2967c478bd9Sstevel@tonic-gate */ 2977c478bd9Sstevel@tonic-gate 2987c478bd9Sstevel@tonic-gate /* 2997c478bd9Sstevel@tonic-gate * Status Register Alias (RO) 3007c478bd9Sstevel@tonic-gate * This location presents the same view as the Interrupt Status Register, except 3017c478bd9Sstevel@tonic-gate * that reading from this location does not automatically clear any of the 3027c478bd9Sstevel@tonic-gate * register bits. 3037c478bd9Sstevel@tonic-gate */ 3047c478bd9Sstevel@tonic-gate 3057c478bd9Sstevel@tonic-gate /* 3067c478bd9Sstevel@tonic-gate * PCI Error Status Register (R-AC) 3077c478bd9Sstevel@tonic-gate * Other PCI bus errors : The specific error may be read from 3087c478bd9Sstevel@tonic-gate * the PCI Status Register in PCI Configuration space 3097c478bd9Sstevel@tonic-gate */ 3107c478bd9Sstevel@tonic-gate #define ERI_G_STS_BADACK (1 << 0) /* no ACK64# during ABS64 */ 3117c478bd9Sstevel@tonic-gate #define ERI_G_STS_DTRTO (1 << 1) /* Delayed trans timeout */ 3127c478bd9Sstevel@tonic-gate #define ERI_G_STS_OTHERS (1 << 2) 3137c478bd9Sstevel@tonic-gate 3147c478bd9Sstevel@tonic-gate /* 3157c478bd9Sstevel@tonic-gate * PCI Error Mask Register (RW) 3167c478bd9Sstevel@tonic-gate * size: 32 bits 3177c478bd9Sstevel@tonic-gate * default: 0xffffffff 3187c478bd9Sstevel@tonic-gate * Same layout as the PCI Error Status Register 3197c478bd9Sstevel@tonic-gate */ 3207c478bd9Sstevel@tonic-gate #define ERI_G_PCI_ERROR_MASK 0x00 3217c478bd9Sstevel@tonic-gate 3227c478bd9Sstevel@tonic-gate /* 3237c478bd9Sstevel@tonic-gate * BIF Configuration Register 3247c478bd9Sstevel@tonic-gate * default: 0x0 3257c478bd9Sstevel@tonic-gate * Used to configure specific system information for the BIF block to optimize. 3267c478bd9Sstevel@tonic-gate * Default values indicate no special knowledge is assumed by BIF. 3277c478bd9Sstevel@tonic-gate * M66EN is RO bit. 3287c478bd9Sstevel@tonic-gate * 66 MHz operation (RO) May be used by the driver to sense 3297c478bd9Sstevel@tonic-gate * whether ERI is operating in a 66MHz or 33 MHz PCI segment 3307c478bd9Sstevel@tonic-gate */ 3317c478bd9Sstevel@tonic-gate #define ERI_G_BIFCFG_SLOWCLK (1 << 0) /* for parity error timing */ 3327c478bd9Sstevel@tonic-gate #define ERI_G_BIFCFG_HOST_64 (1 << 1) /* 64-bit host */ 3337c478bd9Sstevel@tonic-gate #define ERI_G_BIFCFG_B64D_DIS (1 << 2) /* no 64-bit wide data */ 3347c478bd9Sstevel@tonic-gate #define ERI_G_BIFCFG_M66EN (1 << 3) 3357c478bd9Sstevel@tonic-gate 3367c478bd9Sstevel@tonic-gate /* 3377c478bd9Sstevel@tonic-gate * BIF Diagnostic register (RW) 3387c478bd9Sstevel@tonic-gate * TBD 3397c478bd9Sstevel@tonic-gate */ 3407c478bd9Sstevel@tonic-gate 3417c478bd9Sstevel@tonic-gate /* 3427c478bd9Sstevel@tonic-gate * Global Software Reset Register - RW-AC 3437c478bd9Sstevel@tonic-gate * The lower 2bits are used to perform an individual Software Reset to the 3447c478bd9Sstevel@tonic-gate * TX or RX functions (when the corresponding bit is set), or 3457c478bd9Sstevel@tonic-gate * a Global Software Reset to the ERI (when both bits are set). 3467c478bd9Sstevel@tonic-gate * These bits become "self cleared" after the corresponding reset command 3477c478bd9Sstevel@tonic-gate * has been executed. After a reset, the software must poll this register 3487c478bd9Sstevel@tonic-gate * till both the bits are read as 0's. 3497c478bd9Sstevel@tonic-gate * The third bit (RSTOUT) is not self clearing and is used to activate 3507c478bd9Sstevel@tonic-gate * the RSTOUT# pin, when set. When clear, RSTOUT# follows the level of the 3517c478bd9Sstevel@tonic-gate * PCI reset input pin. 3527c478bd9Sstevel@tonic-gate */ 3537c478bd9Sstevel@tonic-gate #define ERI_G_RESET_ETX (1 << 0) /* Reset ETX */ 3547c478bd9Sstevel@tonic-gate #define ERI_G_RESET_ERX (1 << 1) /* Reset ERX */ 3557c478bd9Sstevel@tonic-gate #define ERI_G_RESET_RSTOUT (1 << 2) /* force the RSTOUT# pin active */ 3567c478bd9Sstevel@tonic-gate #define ERI_G_CACHE_BIT 16 3577c478bd9Sstevel@tonic-gate #define ERI_G_CACHE_LINE_SIZE_16 16 /* cache line size of 64 bytes */ 3587c478bd9Sstevel@tonic-gate #define ERI_G_CACHE_LINE_SIZE_32 32 /* cache line size of 128 bytes */ 3597c478bd9Sstevel@tonic-gate #define ERI_G_CACHE_16 (ERI_G_CACHE_LINE_SIZE_16 << ERI_G_CACHE_BIT) 3607c478bd9Sstevel@tonic-gate #define ERI_G_CACHE_32 (ERI_G_CACHE_LINE_SIZE_32 << ERI_G_CACHE_BIT) 3617c478bd9Sstevel@tonic-gate 3627c478bd9Sstevel@tonic-gate #define ERI_G_RESET_GLOBAL (ERI_G_RESET_ETX | ERI_G_RESET_ERX) 3637c478bd9Sstevel@tonic-gate 3647c478bd9Sstevel@tonic-gate /* 3657c478bd9Sstevel@tonic-gate * Transmit DMA Register set 3667c478bd9Sstevel@tonic-gate * tx_kick and tx_completion registers are set to 0 when ETX is reset. 3677c478bd9Sstevel@tonic-gate */ 3687c478bd9Sstevel@tonic-gate 3697c478bd9Sstevel@tonic-gate struct etx { 3707c478bd9Sstevel@tonic-gate uint32_t tx_kick; /* 0x2000 RW Transmit Kick Register */ 3717c478bd9Sstevel@tonic-gate uint32_t config; /* 0x2004 RW ETX Configuration Register */ 3727c478bd9Sstevel@tonic-gate uint32_t txring_lo; /* 0x2008 RW Transmit Descriptor Base Low */ 3737c478bd9Sstevel@tonic-gate uint32_t txring_hi; /* 0x200C RW Transmit Descriptor Base Low */ 3747c478bd9Sstevel@tonic-gate uint32_t reserved1; /* 0x2010 */ 3757c478bd9Sstevel@tonic-gate uint32_t txfifo_wr_ptr; /* 0x2014 RW TxFIFO Write Pointer */ 3767c478bd9Sstevel@tonic-gate uint32_t txfifo_sdwr_ptr; /* 0x2018 RW TxFIFO Shadow Write Pointer */ 3777c478bd9Sstevel@tonic-gate uint32_t txfifo_rd_ptr; /* 0x201C RW TxFIFO Read Pointer */ 3787c478bd9Sstevel@tonic-gate uint32_t txfifo_sdrd_ptr; /* 0x2020 RW TxFIFO Shadow Read Pointer */ 3797c478bd9Sstevel@tonic-gate uint32_t txfifo_pkt_cnt; /* 0x2024 RO TxFIFO Packet Counter */ 3807c478bd9Sstevel@tonic-gate uint32_t state_mach; /* 0x2028 RO ETX State Machine Reg */ 3817c478bd9Sstevel@tonic-gate uint32_t reserved2; /* 0x202C */ 3827c478bd9Sstevel@tonic-gate uint32_t txdata_ptr_lo; /* 0x2030 RO ETX State Machine Register */ 3837c478bd9Sstevel@tonic-gate uint32_t txdata_ptr_hi; /* 0x2034 RO ETX State Machine Register */ 3847c478bd9Sstevel@tonic-gate uint32_t reserved3[50]; /* 0x2038 - 0x20FC */ 3857c478bd9Sstevel@tonic-gate 3867c478bd9Sstevel@tonic-gate uint32_t tx_completion; /* 0x2100 RO ETX Completion Register */ 3877c478bd9Sstevel@tonic-gate uint32_t txfifo_adrs; /* 0x2104 RW ETX FIFO address */ 3887c478bd9Sstevel@tonic-gate uint32_t txfifo_tag; /* 0x2108 RO ETX FIFO tag */ 3897c478bd9Sstevel@tonic-gate uint32_t txfifo_data_lo; /* 0x210C RW ETX FIFO data low */ 3907c478bd9Sstevel@tonic-gate uint32_t txfifo_data_hi_T1; /* 0x2110 RW ETX FIFO data high T1 */ 3917c478bd9Sstevel@tonic-gate uint32_t txfifo_data_hi_T0; /* 0x2114 RW ETX FIFO data high T0 */ 3927c478bd9Sstevel@tonic-gate uint32_t txfifo_size; /* 0x2118 RO ETX FIFO size */ 3937c478bd9Sstevel@tonic-gate 3947c478bd9Sstevel@tonic-gate uint32_t reserved4[964]; /* 0x211C - 0x3024 */ 3957c478bd9Sstevel@tonic-gate 3967c478bd9Sstevel@tonic-gate uint32_t txdebug; /* 0x3028 RW ETX Debug Register */ 3977c478bd9Sstevel@tonic-gate }; 3987c478bd9Sstevel@tonic-gate 3997c478bd9Sstevel@tonic-gate 4007c478bd9Sstevel@tonic-gate /* 4017c478bd9Sstevel@tonic-gate * TX Kick Register (RW) 4027c478bd9Sstevel@tonic-gate * size: 13-bits 4037c478bd9Sstevel@tonic-gate * default: 0x0 4047c478bd9Sstevel@tonic-gate * Written by the host CPU with the descriptor value that follows the last 4057c478bd9Sstevel@tonic-gate * valid Transmit descriptor. 4067c478bd9Sstevel@tonic-gate */ 4077c478bd9Sstevel@tonic-gate 4087c478bd9Sstevel@tonic-gate /* 4097c478bd9Sstevel@tonic-gate * TX Completion Register 4107c478bd9Sstevel@tonic-gate * size: 13-bits 4117c478bd9Sstevel@tonic-gate * default: 0x0 4127c478bd9Sstevel@tonic-gate * This register stores the descriptor value that follows the last descriptor 4137c478bd9Sstevel@tonic-gate * already processed by ERI. 4147c478bd9Sstevel@tonic-gate * 4157c478bd9Sstevel@tonic-gate */ 4167c478bd9Sstevel@tonic-gate #define ETX_COMPLETION_MASK 0x1fff 4177c478bd9Sstevel@tonic-gate 4187c478bd9Sstevel@tonic-gate /* 4197c478bd9Sstevel@tonic-gate * ETX Configuration Register 4207c478bd9Sstevel@tonic-gate * default: 0x118010 4217c478bd9Sstevel@tonic-gate * This register stores parameters that control the operation of the transmit 4227c478bd9Sstevel@tonic-gate * DMA channel. 4237c478bd9Sstevel@tonic-gate * If the desire is to buffer an entire standard Ethernet frame before its 4247c478bd9Sstevel@tonic-gate * transmission is enabled, the Tx-FIFO-Threshold field has to be programmed 4257c478bd9Sstevel@tonic-gate * to a value = > 0xC8. (CHECK). Default value is 0x460. 4267c478bd9Sstevel@tonic-gate * Matewos: Changed the above to 0x400. Getting FIFO Underflow in the 4277c478bd9Sstevel@tonic-gate * case if Giga bit speed. 4287c478bd9Sstevel@tonic-gate * Bit 21 is used to modify the functionality of the Tx_All interrupt. 4297c478bd9Sstevel@tonic-gate * If it is 0, Tx_All interrupt is generated after processing the last 4307c478bd9Sstevel@tonic-gate * transmit descriptor. 4317c478bd9Sstevel@tonic-gate * If it is 1, Tx_All interrupt is generated only after the entire 4327c478bd9Sstevel@tonic-gate * Transmit FIFO has been drained. 4337c478bd9Sstevel@tonic-gate */ 4347c478bd9Sstevel@tonic-gate 4357c478bd9Sstevel@tonic-gate #define GET_CONFIG_TXDMA_EN (1 << 0) /* 0 - Enable Tx DMA */ 4367c478bd9Sstevel@tonic-gate #define GET_CONFIG_TXRING_SZ (0xf << 1) /* 1-4:Tx desc ring size */ 4377c478bd9Sstevel@tonic-gate #define GET_CONFIG_RESERVED (0x1f << 5) /* 5-9: Reserved */ 4387c478bd9Sstevel@tonic-gate #define GET_CONFIG_TXFIFOTH (0x7ff << 10) /* 10-20 :TX FIFO Threshold */ 4397c478bd9Sstevel@tonic-gate /* 4407c478bd9Sstevel@tonic-gate * RIO specific value: TXFIFO threshold needs to be set to 1518/8. 4417c478bd9Sstevel@tonic-gate * It was set to (0x4FF << 10) for GEM. 4427c478bd9Sstevel@tonic-gate * set it back to 0x4ff. 4437c478bd9Sstevel@tonic-gate * set it to 190 receive TXMAC underrun and hang 4447c478bd9Sstevel@tonic-gate * try 0x100 4457c478bd9Sstevel@tonic-gate * try 0x4ff 4467c478bd9Sstevel@tonic-gate * try 0x100 4477c478bd9Sstevel@tonic-gate */ 4487c478bd9Sstevel@tonic-gate #define ETX_ERI_THRESHOLD 0x100 4497c478bd9Sstevel@tonic-gate #define ETX_CONFIG_THRESHOLD (ETX_ERI_THRESHOLD << 10) 4507c478bd9Sstevel@tonic-gate 4517c478bd9Sstevel@tonic-gate #define GET_CONFIG_PACED_MODE (1 << 21) /* 21 - TX_all_int mod */ 4527c478bd9Sstevel@tonic-gate 4537c478bd9Sstevel@tonic-gate #define GET_CONFIG_THRESHOLD (0x400 << 10) /* For Ethernet Packets */ 4547c478bd9Sstevel@tonic-gate #define GET_CONFIG_RINGSZ (ERI_TMDMAX << 1) /* for 2048 descriptors */ 4557c478bd9Sstevel@tonic-gate /* 4567c478bd9Sstevel@tonic-gate * ETX TX ring size 4577c478bd9Sstevel@tonic-gate * This is a 4-bit value to determine the no. of descriptor entries in the 4587c478bd9Sstevel@tonic-gate * TX-ring. The number of entries can vary from 32 through 8192 in multiples 4597c478bd9Sstevel@tonic-gate * of 2. 4607c478bd9Sstevel@tonic-gate */ 4617c478bd9Sstevel@tonic-gate #define ERI_TX_RINGSZ_SHIFT 1 4627c478bd9Sstevel@tonic-gate 4637c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_32 0 4647c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_64 1 4657c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_128 2 4667c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_256 3 4677c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_512 4 4687c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_1024 5 4697c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_2048 6 4707c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_4096 7 4717c478bd9Sstevel@tonic-gate #define ETX_RINGSZ_8192 8 4727c478bd9Sstevel@tonic-gate /* values 9-15 are reserved. */ 4737c478bd9Sstevel@tonic-gate 4747c478bd9Sstevel@tonic-gate /* 4757c478bd9Sstevel@tonic-gate * Transmit Descriptor Base Low and High (RW) 4767c478bd9Sstevel@tonic-gate * The 53 most significant bits are used as the base address for the TX 4777c478bd9Sstevel@tonic-gate * descriptor ring. The 11 least significant bits are not stored and assumed 4787c478bd9Sstevel@tonic-gate * to be 0. 4797c478bd9Sstevel@tonic-gate * This register should be initialized to a 2KByte-aligned value after power-on 4807c478bd9Sstevel@tonic-gate * or Software Reset. 4817c478bd9Sstevel@tonic-gate */ 4827c478bd9Sstevel@tonic-gate 4837c478bd9Sstevel@tonic-gate 4847c478bd9Sstevel@tonic-gate /* 4857c478bd9Sstevel@tonic-gate * TX FIFO size (RO) 4867c478bd9Sstevel@tonic-gate * This 11-bit RO register indicates the size, in 64 byte multiples, of the 4877c478bd9Sstevel@tonic-gate * TX FIFO. 4887c478bd9Sstevel@tonic-gate * The value of this register is 0x90, indicating a 9Kbyte TX FIFO. 4897c478bd9Sstevel@tonic-gate */ 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate 4927c478bd9Sstevel@tonic-gate /* 4937c478bd9Sstevel@tonic-gate * ERX Register Set 4947c478bd9Sstevel@tonic-gate */ 4957c478bd9Sstevel@tonic-gate 4967c478bd9Sstevel@tonic-gate struct erx { 4977c478bd9Sstevel@tonic-gate uint32_t config; /* 0x4000 RW ERX Configuration Register */ 4987c478bd9Sstevel@tonic-gate uint32_t rxring_lo; /* 0x4004 RW Receive Descriptor Base low */ 4997c478bd9Sstevel@tonic-gate uint32_t rxring_hi; /* 0x4008 RW Receive Descriptor Base high */ 5007c478bd9Sstevel@tonic-gate uint32_t rxfifo_wr_ptr; /* 0x400C RW RxFIFO Write Pointer */ 5017c478bd9Sstevel@tonic-gate uint32_t rxfifo_sdwr_ptr; /* 0x4010 RW RxFIFO Shadow Write Pointer */ 5027c478bd9Sstevel@tonic-gate uint32_t rxfifo_rd_ptr; /* 0x4014 RW RxFIFO Read pointer */ 5037c478bd9Sstevel@tonic-gate uint32_t rxfifo_pkt_cnt; /* 0x4018 RO RxFIFO Packet Counter */ 5047c478bd9Sstevel@tonic-gate uint32_t state_mach; /* 0x401C RO ERX State Machine Register */ 5057c478bd9Sstevel@tonic-gate uint32_t rx_pause_threshold; /* 0x4020 RW ERX Pause thresholds */ 5067c478bd9Sstevel@tonic-gate uint32_t rxdata_ptr_lo; /* 0x4024 RO ERX Data Pointer low */ 5077c478bd9Sstevel@tonic-gate uint32_t rxdata_ptr_hi; /* 0x4028 RO ERX Data Pointer high */ 5087c478bd9Sstevel@tonic-gate uint32_t reserved1[53]; /* 0x402C - 0x40FC */ 5097c478bd9Sstevel@tonic-gate 5107c478bd9Sstevel@tonic-gate uint32_t rx_kick; /* 0x4100 RW ERX Kick Register */ 5117c478bd9Sstevel@tonic-gate uint32_t rx_completion; /* 0x4104 RO ERX Completion Register */ 5127c478bd9Sstevel@tonic-gate uint32_t rx_blanking; /* 0x4108 RO ERX Blanking Register */ 5137c478bd9Sstevel@tonic-gate uint32_t rxfifo_adrs; /* 0x410C RW ERX FIFO address */ 5147c478bd9Sstevel@tonic-gate uint32_t rxfifo_tag; /* 0x4110 RO ERX FIFO tag */ 5157c478bd9Sstevel@tonic-gate uint32_t rxfifo_data_lo; /* 0x4114 RW ERX FIFO data low */ 5167c478bd9Sstevel@tonic-gate uint32_t rxfifo_data_hi_T0; /* 0x4118 RW ERX FIFO data high T0 */ 5177c478bd9Sstevel@tonic-gate uint32_t rxfifo_data_hi_T1; /* 0x411C RW ERX FIFO data high T1 */ 5187c478bd9Sstevel@tonic-gate uint32_t rxfifo_size; /* 0x4120 RW ERX FIFO size */ 5197c478bd9Sstevel@tonic-gate }; 5207c478bd9Sstevel@tonic-gate 5217c478bd9Sstevel@tonic-gate /* 5227c478bd9Sstevel@tonic-gate * ERX Configuration Register - RW 5237c478bd9Sstevel@tonic-gate * This 27-bit register determines the ERX-specific parameters that control the 5247c478bd9Sstevel@tonic-gate * operation of the receive DMA channel. 5257c478bd9Sstevel@tonic-gate * Default : 0x1000010 5267c478bd9Sstevel@tonic-gate */ 5277c478bd9Sstevel@tonic-gate 5287c478bd9Sstevel@tonic-gate #define GET_CONFIG_RXDMA_EN (1 << 0) /* 0 : Enable Rx DMA */ 5297c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_RXRING_SZ (0xf << 1) /* 1-4 : RX ring size */ 5307c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_BATDIS (1 << 5) /* Disable RX desc batching */ 5317c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_RES1 (0xf << 6) /* 6-9 : reserverd */ 5327c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_FBOFFSET (0x7 << 10) /* 10-12 : 1st Byte Offset */ 5337c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_RX_CSSTART (0x7f << 13) /* 13-19:cksum start offset */ 5347c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_RES2 (0xf << 20) /* 20-23 : reserve */ 5357c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_RXFIFOTH (0x7 << 24) /* 24-26:RX DMA threshold */ 5367c478bd9Sstevel@tonic-gate 5377c478bd9Sstevel@tonic-gate #define ERI_RX_RINGSZ_SHIFT 1 5387c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_FBO_SHIFT 10 5397c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_RX_CSSTART_SHIFT 13 5407c478bd9Sstevel@tonic-gate #define ERI_RX_CONFIG_RXFIFOTH_SHIFT 24 5417c478bd9Sstevel@tonic-gate 5427c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_32 0 5437c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_64 1 5447c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_128 2 5457c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_256 3 5467c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_512 4 5477c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_1024 5 5487c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_2048 6 5497c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_4096 7 5507c478bd9Sstevel@tonic-gate #define ERX_RINGSZ_8192 8 5517c478bd9Sstevel@tonic-gate /* values 9-15 are reserved. */ 5527c478bd9Sstevel@tonic-gate 5537c478bd9Sstevel@tonic-gate 5547c478bd9Sstevel@tonic-gate #define ERI_RX_FIFOTH_64 0 5557c478bd9Sstevel@tonic-gate #define ERI_RX_FIFOTH_128 1 5567c478bd9Sstevel@tonic-gate #define ERI_RX_FIFOTH_256 2 5577c478bd9Sstevel@tonic-gate #define ERI_RX_FIFOTH_512 3 5587c478bd9Sstevel@tonic-gate #define ERI_RX_FIFOTH_1024 4 5597c478bd9Sstevel@tonic-gate #define ERI_RX_FIFOTH_2048 5 5607c478bd9Sstevel@tonic-gate /* 6 & 7 are reserved values */ 5617c478bd9Sstevel@tonic-gate 5627c478bd9Sstevel@tonic-gate /* 5637c478bd9Sstevel@tonic-gate * Receive Descriptor Base Low and High (RW) 5647c478bd9Sstevel@tonic-gate * The 53 most significant bits are used as the base address for the RX 5657c478bd9Sstevel@tonic-gate * descriptor ring. The 11 least significant bits are not stored and assumed 5667c478bd9Sstevel@tonic-gate * to be 0. 5677c478bd9Sstevel@tonic-gate * This register should be initialized to a 2KByte-aligned value after power-on 5687c478bd9Sstevel@tonic-gate * or Software Reset. 5697c478bd9Sstevel@tonic-gate */ 5707c478bd9Sstevel@tonic-gate 5717c478bd9Sstevel@tonic-gate 5727c478bd9Sstevel@tonic-gate /* 5737c478bd9Sstevel@tonic-gate * Pause Thresholds Register (RW) 5747c478bd9Sstevel@tonic-gate * default: 0x000f8 5757c478bd9Sstevel@tonic-gate * Two PAUSE thresholds are used to define when PAUSE flow control frames are 5767c478bd9Sstevel@tonic-gate * emitted by ERI. The granularity of these thresholds is in 64 byte increments. 5777c478bd9Sstevel@tonic-gate * XOFF PAUSE frames use the pause_time value pre-programmed in the 5787c478bd9Sstevel@tonic-gate * Send PAUSE MAC Register. 5797c478bd9Sstevel@tonic-gate * XON PAUSE frames use a pause_time of 0. 5807c478bd9Sstevel@tonic-gate */ 5817c478bd9Sstevel@tonic-gate 5827c478bd9Sstevel@tonic-gate #define ERI_RX_PTH_OFFTH (0x1ff << 0) 5837c478bd9Sstevel@tonic-gate /* 5847c478bd9Sstevel@tonic-gate * 0-8: XOFF PAUSE emitted when RX FIFO 5857c478bd9Sstevel@tonic-gate * occupancy rises above this value (times 64 bytes) 5867c478bd9Sstevel@tonic-gate */ 5877c478bd9Sstevel@tonic-gate #define ERI_RX_PTH_RES (0x7 << 9) /* 9-11: reserved */ 5887c478bd9Sstevel@tonic-gate #define ERI_RX_PTH_ONTH (0x1ff << 12) 5897c478bd9Sstevel@tonic-gate /* 5907c478bd9Sstevel@tonic-gate * 12-20: XON PAUSE emitted when RX FIFO 5917c478bd9Sstevel@tonic-gate * occupancy falls below this value (times 64 bytes) 5927c478bd9Sstevel@tonic-gate */ 5937c478bd9Sstevel@tonic-gate 5947c478bd9Sstevel@tonic-gate #define ERI_RX_PTH_ONTH_SHIFT 12 5957c478bd9Sstevel@tonic-gate 5967c478bd9Sstevel@tonic-gate /* 5977c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 5987c478bd9Sstevel@tonic-gate * RX Kick Register (RW) 5997c478bd9Sstevel@tonic-gate * This is a 13-bit register written by the host CPU. 6007c478bd9Sstevel@tonic-gate * The last valid RX descriptor is the one right before the value of the 6017c478bd9Sstevel@tonic-gate * register. 6027c478bd9Sstevel@tonic-gate * Initially set to 0 on reset. 6037c478bd9Sstevel@tonic-gate * RX descriptors must be posted in multiples of 4. 6047c478bd9Sstevel@tonic-gate * The first descriptor should be cache-line aligned for best performance. 6057c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 6067c478bd9Sstevel@tonic-gate */ 6077c478bd9Sstevel@tonic-gate 6087c478bd9Sstevel@tonic-gate /* 6097c478bd9Sstevel@tonic-gate * RX Completion Register (RO) 6107c478bd9Sstevel@tonic-gate * This 13-bit register indicates which descriptors are already used by ERI 6117c478bd9Sstevel@tonic-gate * for receive frames. 6127c478bd9Sstevel@tonic-gate * All descriptors upto but excluding the register value are ready to be 6137c478bd9Sstevel@tonic-gate * processed by the host. 6147c478bd9Sstevel@tonic-gate */ 6157c478bd9Sstevel@tonic-gate 6167c478bd9Sstevel@tonic-gate /* 6177c478bd9Sstevel@tonic-gate * RX Blanking Register (RW) 6187c478bd9Sstevel@tonic-gate * Defines the values used for receive interrupt blanking. 6197c478bd9Sstevel@tonic-gate * For INTR_TIME field, every count is 2048 PCI clock time. For 66 Mhz, each 6207c478bd9Sstevel@tonic-gate * count is about 16 us. 6217c478bd9Sstevel@tonic-gate */ 6227c478bd9Sstevel@tonic-gate #define ERI_RX_BLNK_INTR_PACKETS (0x1ff << 0) 6237c478bd9Sstevel@tonic-gate /* 6247c478bd9Sstevel@tonic-gate * 0-8:no.of pkts to be recvd since the last RX_DONE 6257c478bd9Sstevel@tonic-gate * interrupt, before a new interrupt 6267c478bd9Sstevel@tonic-gate */ 6277c478bd9Sstevel@tonic-gate #define ERI_RX_BLNK_RESERVED (0x7 << 9) /* 9-11 : reserved */ 6287c478bd9Sstevel@tonic-gate #define ERI_RX_BLNK_INTR_TIME (0xff << 12) 6297c478bd9Sstevel@tonic-gate /* 6307c478bd9Sstevel@tonic-gate * 12-19 : no. of clocks to be counted since the last 6317c478bd9Sstevel@tonic-gate * RX_DONE interrupt, before a new interrupt 6327c478bd9Sstevel@tonic-gate */ 6337c478bd9Sstevel@tonic-gate 6347c478bd9Sstevel@tonic-gate #define ERI_RX_BLNK_INTR_TIME_SHIFT 12 6357c478bd9Sstevel@tonic-gate 6367c478bd9Sstevel@tonic-gate /* 6377c478bd9Sstevel@tonic-gate * RX FIFO Size (RO) 6387c478bd9Sstevel@tonic-gate * This 11-bit RO register indicates the size, in 64-bit multiples, of the 6397c478bd9Sstevel@tonic-gate * RX FIFO. Software should use it to properly configure the PAUSE thresholds. 6407c478bd9Sstevel@tonic-gate * The value read is 0x140, indicating a 20kbyte RX FIFO. 6417c478bd9Sstevel@tonic-gate */ 6427c478bd9Sstevel@tonic-gate 6437c478bd9Sstevel@tonic-gate 6447c478bd9Sstevel@tonic-gate /* 6457c478bd9Sstevel@tonic-gate * Declarations and definitions specific to the ERI MAC functional block. 6467c478bd9Sstevel@tonic-gate * 6477c478bd9Sstevel@tonic-gate * The ERI MAC block will provide the MAC functons for 10 or 100 Mbps or 6487c478bd9Sstevel@tonic-gate * 1 Gbps CSMA/CD-protocol-based or full-duplex interface. 6497c478bd9Sstevel@tonic-gate */ 6507c478bd9Sstevel@tonic-gate 6517c478bd9Sstevel@tonic-gate /* 6527c478bd9Sstevel@tonic-gate * ERI MAC Register Set. 6537c478bd9Sstevel@tonic-gate * ERI MAC addresses map on a word boundry. So all registers are 6547c478bd9Sstevel@tonic-gate * declared for a size of 32 bits. Registers that use fewer than 32 6557c478bd9Sstevel@tonic-gate * bits will return 0 in the bits not used. 6567c478bd9Sstevel@tonic-gate * TBD: Define the constant values which should be used for initializing 6577c478bd9Sstevel@tonic-gate * these registers. 6587c478bd9Sstevel@tonic-gate */ 6597c478bd9Sstevel@tonic-gate struct bmac { 6607c478bd9Sstevel@tonic-gate uint32_t txrst; /* 0x6000 tx software reset (RW) */ 6617c478bd9Sstevel@tonic-gate uint32_t rxrst; /* 0x6004 rx software reset Reg (RW) */ 6627c478bd9Sstevel@tonic-gate uint32_t spcmd; /* 0x6008 Send Pause Command Reg (RW) */ 6637c478bd9Sstevel@tonic-gate uint32_t res1; /* 0x600C reserved */ 6647c478bd9Sstevel@tonic-gate uint32_t txsts; /* 0x6010 tx MAC status reg (R-AC) */ 6657c478bd9Sstevel@tonic-gate uint32_t rxsts; /* 0x6014 rx MAC status reg (R-AC) */ 6667c478bd9Sstevel@tonic-gate uint32_t macctl_sts; /* 0x6018 MAC Control Stat Reg (R-AC) */ 6677c478bd9Sstevel@tonic-gate uint32_t res2; /* 0x601C reserved */ 6687c478bd9Sstevel@tonic-gate uint32_t txmask; /* 0x6020 tx MAC Mask Register (RW) */ 6697c478bd9Sstevel@tonic-gate uint32_t rxmask; /* 0x6024 rx MAC Mask register (RW) */ 6707c478bd9Sstevel@tonic-gate uint32_t macctl_mask; /* 0x6028 MAC Control Mask Reg (RW) */ 6717c478bd9Sstevel@tonic-gate uint32_t res3; /* 0x602C reserved */ 6727c478bd9Sstevel@tonic-gate uint32_t txcfg; /* 0x6030 tx config reg [8-0] (RW) */ 6737c478bd9Sstevel@tonic-gate uint32_t rxcfg; /* 0x6034 rx config reg [7-0] (RW) */ 6747c478bd9Sstevel@tonic-gate uint32_t macctl_cfg; /* 0x6038 MAC Control Config Reg (RW) */ 6757c478bd9Sstevel@tonic-gate uint32_t xifc; /* 0x603C XIF Config. reg [7-0] (RW) */ 6767c478bd9Sstevel@tonic-gate uint32_t ipg0; /* 0x6040 Inter pkt Gap 0 [7-0] (RW) */ 6777c478bd9Sstevel@tonic-gate uint32_t ipg1; /* 0x6044 Inter pkt Gap 1 [7-0] (RW) */ 6787c478bd9Sstevel@tonic-gate uint32_t ipg2; /* 0x6048 Inter pkt Gap 2 [7-0] (RW) */ 6797c478bd9Sstevel@tonic-gate uint32_t slot; /* 0x604C slot time reg [7-0] (RW) */ 6807c478bd9Sstevel@tonic-gate uint32_t macmin; /* 0x6050 MAC min frame sze [9-0](RW) */ 6817c478bd9Sstevel@tonic-gate uint32_t macmax; /* 0x6054 MAC max pkt sze [14-0] (RW) */ 6827c478bd9Sstevel@tonic-gate uint32_t palen; /* 0x6058 preamble len reg [9-0] (RW) */ 6837c478bd9Sstevel@tonic-gate uint32_t jam; /* 0x605C jam size reg [3-0] (RW) */ 6847c478bd9Sstevel@tonic-gate uint32_t alimit; /* 0x6060 attempt limit reg [7-0](RW) */ 6857c478bd9Sstevel@tonic-gate uint32_t macctl_type; /* 0x6064 MAC Control Type Reg (RW) */ 6867c478bd9Sstevel@tonic-gate uint32_t res4[6]; /* reserved 0x6068 - 0x607C */ 6877c478bd9Sstevel@tonic-gate uint32_t madd0; /* 0x6080 Norm MAC adrs 0 [15-0] (RW) */ 6887c478bd9Sstevel@tonic-gate uint32_t madd1; /* 0x6084 Norm MAC adrs 1 [31-16](RW) */ 6897c478bd9Sstevel@tonic-gate uint32_t madd2; /* 0x6088 Norm MAC adrs 2 [47-32](RW) */ 6907c478bd9Sstevel@tonic-gate uint32_t madd3; /* 0x608C Alt. MAC adrs 0 [15-0](RW) */ 6917c478bd9Sstevel@tonic-gate uint32_t madd4; /* 0x6090 Alt. MAC adrs 1 [31-16](RW) */ 6927c478bd9Sstevel@tonic-gate uint32_t madd5; /* 0x6094 Alt. MAC adrs 2 [47-32](RW) */ 6937c478bd9Sstevel@tonic-gate uint32_t madd6; /* 0x6098 Control MAC adrs 0 [15-0](RW) */ 6947c478bd9Sstevel@tonic-gate uint32_t madd7; /* 0x609C Control MAC adrs 1 [31-16](RW) */ 6957c478bd9Sstevel@tonic-gate uint32_t madd8; /* 0x60A0 Control MAC adrs 2 [47-32](RW) */ 6967c478bd9Sstevel@tonic-gate uint32_t afr0; /* 0x60A4 addr filt reg 0_0 [15-0](RW) */ 6977c478bd9Sstevel@tonic-gate uint32_t afr1; /* 0x60A8 addr filt reg 0_1 [15-0](RW) */ 6987c478bd9Sstevel@tonic-gate uint32_t afr2; /* 0x60AC addr filt reg 0_2 [15-0](RW) */ 6997c478bd9Sstevel@tonic-gate uint32_t afmr1_2; /* 0x60B0 addr filt msk reg 1,2 [8-0](RW) */ 7007c478bd9Sstevel@tonic-gate uint32_t afmr0; /* 0x60B4 addr filt msk reg 0 [15-0](RW) */ 7017c478bd9Sstevel@tonic-gate uint32_t res5[2]; /* 0x60B8 - 0x60BC Reserved */ 7027c478bd9Sstevel@tonic-gate uint32_t hash0; /* 0x60C0 h-table 0 [15-0] (RW) */ 7037c478bd9Sstevel@tonic-gate uint32_t hash1; /* 0x60C4 h-table 1 [31-16] (RW) */ 7047c478bd9Sstevel@tonic-gate uint32_t hash2; /* 0x60C8 h-table 2 [47-32] (RW) */ 7057c478bd9Sstevel@tonic-gate uint32_t hash3; /* 0x60CC h-table 3 [63-48] (RW) */ 7067c478bd9Sstevel@tonic-gate uint32_t hash4; /* 0x60D0 h-table 4 [79-64] (RW) */ 7077c478bd9Sstevel@tonic-gate uint32_t hash5; /* 0x60D4 h-table 5 [95-80] (RW) */ 7087c478bd9Sstevel@tonic-gate uint32_t hash6; /* 0x60D8 h-table 6 [111-96] (RW) */ 7097c478bd9Sstevel@tonic-gate uint32_t hash7; /* 0x60DC h-table 7 [127-112] (RW) */ 7107c478bd9Sstevel@tonic-gate uint32_t hash8; /* 0x60E0 h-table 8 [143-128] (RW) */ 7117c478bd9Sstevel@tonic-gate uint32_t hash9; /* 0x60E4 h-table 9 [159-144] (RW) */ 7127c478bd9Sstevel@tonic-gate uint32_t hash10; /* 0x60E8 h-table 10 [175-160] (RW) */ 7137c478bd9Sstevel@tonic-gate uint32_t hash11; /* 0x60EC h-table 11 [191-176] (RW) */ 7147c478bd9Sstevel@tonic-gate uint32_t hash12; /* 0x60F0 h-table 12 [207-192] (RW) */ 7157c478bd9Sstevel@tonic-gate uint32_t hash13; /* 0x60F4 h-table 13 [223-208] (RW) */ 7167c478bd9Sstevel@tonic-gate uint32_t hash14; /* 0x60F8 h-table 14 [239-224] (RW) */ 7177c478bd9Sstevel@tonic-gate uint32_t hash15; /* 0x60FC h-table 15 [255-240] (RW) */ 7187c478bd9Sstevel@tonic-gate uint32_t nccnt; /* 0x6100 normal coll cnt [15-0] (RW) */ 7197c478bd9Sstevel@tonic-gate uint32_t fccnt; /* 0x6104 1st succes coll [15-0] (RW) */ 7207c478bd9Sstevel@tonic-gate uint32_t excnt; /* 0x6108 excess coll cnt[15-0] (RW) */ 7217c478bd9Sstevel@tonic-gate uint32_t ltcnt; /* 0x610C late coll cnt [15-0] (RW) */ 7227c478bd9Sstevel@tonic-gate uint32_t dcnt; /* 0x6110 defer timer cnt [15-0] (RW) */ 7237c478bd9Sstevel@tonic-gate uint32_t pattempts; /* 0x6114 peak attempt reg [7-0] (RW) */ 7247c478bd9Sstevel@tonic-gate uint32_t frcnt; /* 0x6118 rcv frame cnt [15-0] (RW) */ 7257c478bd9Sstevel@tonic-gate uint32_t lecnt; /* 0x611C rx len err cnt [15-0] (RW) */ 7267c478bd9Sstevel@tonic-gate uint32_t aecnt; /* 0x6120 rx align err cnt[15-0] (RW) */ 7277c478bd9Sstevel@tonic-gate uint32_t fecnt; /* 0x6124 rcv crc err cnt [15-0] (RW) */ 7287c478bd9Sstevel@tonic-gate uint32_t rxcv; /* 0x6128 rx code viol reg [15-0](RW) */ 7297c478bd9Sstevel@tonic-gate uint32_t res6; /* 0x612C Reserved */ 7307c478bd9Sstevel@tonic-gate uint32_t rseed; /* 0x6130 random num seed [9-0] (RW) */ 7317c478bd9Sstevel@tonic-gate uint32_t macsm; /* 0x6134 MAC state mach reg [7-0](R) */ 7327c478bd9Sstevel@tonic-gate }; 7337c478bd9Sstevel@tonic-gate 7347c478bd9Sstevel@tonic-gate #define BMAC_OVERFLOW_STATE 0x03800000 7357c478bd9Sstevel@tonic-gate 7367c478bd9Sstevel@tonic-gate /* 7377c478bd9Sstevel@tonic-gate * Constants used for initializing the MAC registers 7387c478bd9Sstevel@tonic-gate */ 7397c478bd9Sstevel@tonic-gate 7407c478bd9Sstevel@tonic-gate #define BMAC_SEND_PAUSE_CMD 0x1BF0 7417c478bd9Sstevel@tonic-gate #define BMAC_IPG0 0x00 7427c478bd9Sstevel@tonic-gate #define BMAC_IPG1 0x08 7437c478bd9Sstevel@tonic-gate #define BMAC_IPG2 0x04 7447c478bd9Sstevel@tonic-gate #define BMAC_SLOT_TIME 0x40 7457c478bd9Sstevel@tonic-gate #define BMAC_EXT_SLOT_TIME 0x200 7467c478bd9Sstevel@tonic-gate #define BMAC_MIN_FRAME_SIZE 0x40 747d64540e3Sgd #define BMAC_MAX_FRAME_SIZE (ETHERMTU + 18 + 4) /* enet + vlan */ 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate /* 7507c478bd9Sstevel@tonic-gate * Hardware bug: set MAC_FRAME_SIZE to 0x7fff to 7517c478bd9Sstevel@tonic-gate * get around the problem of tag errors 7527c478bd9Sstevel@tonic-gate */ 7537c478bd9Sstevel@tonic-gate #ifdef ERI_RX_TAG_ERROR_WORKAROUND 7547c478bd9Sstevel@tonic-gate #define BMAC_MAX_FRAME_SIZE_TAG 0x7fff 7557c478bd9Sstevel@tonic-gate #endif 7567c478bd9Sstevel@tonic-gate 7577c478bd9Sstevel@tonic-gate #define BMAC_MAX_BURST (0x2000 << 16) 7587c478bd9Sstevel@tonic-gate #define BMAC_PREAMBLE_SIZE 0x07 7597c478bd9Sstevel@tonic-gate #define BMAC_JAM_SIZE 0x04 7607c478bd9Sstevel@tonic-gate #define BMAC_ATTEMPT_LIMIT 0x10 7617c478bd9Sstevel@tonic-gate #define BMAC_CONTROL_TYPE 0x8808 7627c478bd9Sstevel@tonic-gate #define BMAC_ADDRESS_3 0x0000 7637c478bd9Sstevel@tonic-gate #define BMAC_ADDRESS_4 0x0000 7647c478bd9Sstevel@tonic-gate #define BMAC_ADDRESS_5 0x0000 7657c478bd9Sstevel@tonic-gate #define BMAC_ADDRESS_6 0x0001 7667c478bd9Sstevel@tonic-gate #define BMAC_ADDRESS_7 0xC200 7677c478bd9Sstevel@tonic-gate #define BMAC_ADDRESS_8 0x0180 7687c478bd9Sstevel@tonic-gate #define BMAC_AF_0 0x0000 7697c478bd9Sstevel@tonic-gate #define BMAC_AF_1 0x0000 7707c478bd9Sstevel@tonic-gate #define BMAC_AF_2 0x0000 7717c478bd9Sstevel@tonic-gate #define BMAC_AF21_MASK 0x00 7727c478bd9Sstevel@tonic-gate #define BMAC_AF0_MASK 0x0000 7737c478bd9Sstevel@tonic-gate #define BMAC_COUNTER 0x0000 /* for all MAC Counters */ 7747c478bd9Sstevel@tonic-gate 7757c478bd9Sstevel@tonic-gate /* 7767c478bd9Sstevel@tonic-gate * ERI MAC Register Bit Masks. 7777c478bd9Sstevel@tonic-gate */ 7787c478bd9Sstevel@tonic-gate 7797c478bd9Sstevel@tonic-gate /* 7807c478bd9Sstevel@tonic-gate * TX_MAC Software Reset Command Register (RW) 7817c478bd9Sstevel@tonic-gate * This bit is set to 1 when a PIO write is done. This bit becomes self-cleared. 7827c478bd9Sstevel@tonic-gate * after the command has been executed. 7837c478bd9Sstevel@tonic-gate */ 7847c478bd9Sstevel@tonic-gate 7857c478bd9Sstevel@tonic-gate #define BMAC_TX_RESET (1 << 0) /* TX_MAC Reset Command */ 7867c478bd9Sstevel@tonic-gate 7877c478bd9Sstevel@tonic-gate 7887c478bd9Sstevel@tonic-gate /* 7897c478bd9Sstevel@tonic-gate * RX_MAC Software Reset Command Register (RW) 7907c478bd9Sstevel@tonic-gate * This bit is set to 1 when a PIO write is done. This bit becomes self-cleared. 7917c478bd9Sstevel@tonic-gate * after the command has been executed. 7927c478bd9Sstevel@tonic-gate */ 7937c478bd9Sstevel@tonic-gate 7947c478bd9Sstevel@tonic-gate #define BMAC_RX_RESET (1 << 0) /* RX_MAC Reset Command */ 7957c478bd9Sstevel@tonic-gate 7967c478bd9Sstevel@tonic-gate /* 7977c478bd9Sstevel@tonic-gate * Send Pause Command Register (RW) 7987c478bd9Sstevel@tonic-gate * This command register executes a Pause Flow Control frame transmission. 7997c478bd9Sstevel@tonic-gate * Pause_Time_Sent field indicates to the MAC the value of the pause_time 8007c478bd9Sstevel@tonic-gate * operand that should be sent on the network using either the Send_Pause 8017c478bd9Sstevel@tonic-gate * Command bit or the flow control handshake on the RxDMA < - > MAC interface. 8027c478bd9Sstevel@tonic-gate * The pause-time is interpreted in terms of Slot times. 8037c478bd9Sstevel@tonic-gate */ 8047c478bd9Sstevel@tonic-gate 8057c478bd9Sstevel@tonic-gate /* 8067c478bd9Sstevel@tonic-gate * 0-15: value of pause_time operand 8077c478bd9Sstevel@tonic-gate * in terms of slot time 8087c478bd9Sstevel@tonic-gate */ 8097c478bd9Sstevel@tonic-gate 8107c478bd9Sstevel@tonic-gate #define ERI_MCTLSP_TIME (0xffff << 0) 8117c478bd9Sstevel@tonic-gate #define ERI_MCTLSP_SEND (1 << 16) /* send Pause flow control frame */ 8127c478bd9Sstevel@tonic-gate 8137c478bd9Sstevel@tonic-gate 8147c478bd9Sstevel@tonic-gate /* 8157c478bd9Sstevel@tonic-gate * TX_MAC Status Register (R-AC) 8167c478bd9Sstevel@tonic-gate */ 8177c478bd9Sstevel@tonic-gate 8187c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_XMIT_DONE (1 << 0) /* Frame transmitted */ 8197c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_TX_URUN (1 << 1) /* TX MAC Underrun */ 8207c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_MAXPKT_ERR (1 << 2) /* packet len exceeds max len */ 8217c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_NCC_EXP (1 << 3) /* Normal Collision cnt exp */ 8227c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_ECC_EXP (1 << 4) /* Excess Collision cnt exp */ 8237c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_LCC_EXP (1 << 5) /* Late Collision cnt exp */ 8247c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_FCC_EXP (1 << 6) /* First Collision cnt exp */ 8257c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_DEFER_EXP (1 << 7) /* Defer Timer exp */ 8267c478bd9Sstevel@tonic-gate #define BMAC_TXSTS_PEAK_EXP (1 << 8) /* Peak attempts cnt exp */ 8277c478bd9Sstevel@tonic-gate 8287c478bd9Sstevel@tonic-gate /* 8297c478bd9Sstevel@tonic-gate * TX_MAC Mask Register (RW) 8307c478bd9Sstevel@tonic-gate */ 8317c478bd9Sstevel@tonic-gate 8327c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_XMIT_DONE (1 << 0) /* Frame transmitted */ 8337c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_TX_URUN (1 << 1) /* TX MAC Underrun */ 8347c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_MAXPKT_ERR (1 << 2) /* packet len exceeds max len */ 8357c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_NCC_EXP (1 << 3) /* Normal Collision cnt exp */ 8367c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_ECC_EXP (1 << 4) /* Excess Collision cnt exp */ 8377c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_LCC_EXP (1 << 5) /* Late Collision cnt exp */ 8387c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_FCC_EXP (1 << 6) /* First Collision cnt exp */ 8397c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_DEFER_EXP (1 << 7) /* Defer Timer exp */ 8407c478bd9Sstevel@tonic-gate #define BMAC_TXMASK_PEAK_EXP (1 << 8) /* Peak attempts cnt exp */ 8417c478bd9Sstevel@tonic-gate /* Matewos added defer counter */ 8427c478bd9Sstevel@tonic-gate #define BMAC_TXINTR_MASK (BMAC_TXMASK_XMIT_DONE | BMAC_TXMASK_DEFER_EXP) 8437c478bd9Sstevel@tonic-gate 8447c478bd9Sstevel@tonic-gate /* 8457c478bd9Sstevel@tonic-gate * RX_MAC Status Register (R-AC) 8467c478bd9Sstevel@tonic-gate */ 8477c478bd9Sstevel@tonic-gate #define BMAC_RXSTS_RX_DONE (1 << 0) /* Frame Received */ 8487c478bd9Sstevel@tonic-gate #define BMAC_RXSTS_RX_OVF (1 << 1) /* RX MAC data path overflow */ 8497c478bd9Sstevel@tonic-gate #define BMAC_RXSTS_FRMCNT_EXP (1 << 2) /* RX Frame counter exp */ 8507c478bd9Sstevel@tonic-gate #define BMAC_RXSTS_ALE_EXP (1 << 3) /* RX Alignment error cnt exp */ 8517c478bd9Sstevel@tonic-gate #define BMAC_RXSTS_CRC_EXP (1 << 4) /* RX CRC error cnt exp */ 8527c478bd9Sstevel@tonic-gate #define BMAC_RXSTS_LEN_EXP (1 << 5) /* RX Length error cnt exp */ 8537c478bd9Sstevel@tonic-gate #define BMAC_RXSTS_CVI_EXP (1 << 6) /* RX Code violate err cnt exp */ 8547c478bd9Sstevel@tonic-gate 8557c478bd9Sstevel@tonic-gate /* 8567c478bd9Sstevel@tonic-gate * RX_MAC Mask Register (R-AC) 8577c478bd9Sstevel@tonic-gate */ 8587c478bd9Sstevel@tonic-gate #define BMAC_RXMASK_RX_DONE (1 << 0) /* Frame Received */ 8597c478bd9Sstevel@tonic-gate #define BMAC_RXMASK_RX_OVF (1 << 1) /* RX MAC data path overflow */ 8607c478bd9Sstevel@tonic-gate #define BMAC_RXMASK_FRMCNT_EXP (1 << 2) /* RX Frame counter exp */ 8617c478bd9Sstevel@tonic-gate #define BMAC_RXMASK_ALE_EXP (1 << 3) /* RX Alignment error cnt exp */ 8627c478bd9Sstevel@tonic-gate #define BMAC_RXMASK_CRC_EXP (1 << 4) /* RX CRC error cnt exp */ 8637c478bd9Sstevel@tonic-gate #define BMAC_RXMASK_LEN_EXP (1 << 5) /* RX Length error cnt exp */ 8647c478bd9Sstevel@tonic-gate #define BMAC_RXMASK_CVI_EXP (1 << 6) /* RX Code violate err cnt exp */ 8657c478bd9Sstevel@tonic-gate 8667c478bd9Sstevel@tonic-gate #define BMAC_RXINTR_MASK (BMAC_RXMASK_RX_DONE | BMAC_RXMASK_FRMCNT_EXP) 8677c478bd9Sstevel@tonic-gate 8687c478bd9Sstevel@tonic-gate /* 8697c478bd9Sstevel@tonic-gate * MAC Control Status Register (R-AC) 8707c478bd9Sstevel@tonic-gate */ 8717c478bd9Sstevel@tonic-gate #define ERI_MCTLSTS_PAUSE_RCVD (1 << 0) /* PAUSE received */ 8727c478bd9Sstevel@tonic-gate #define ERI_MCTLSTS_PAUSE_STATE (1 << 1) /* transition to PAUSE state */ 8737c478bd9Sstevel@tonic-gate #define ERI_MCTLSTS_NONPAUSE (1 << 2) /* change to non-PAUSE state */ 8747c478bd9Sstevel@tonic-gate #define ERI_MCTLSTS_RESERVED (0x1fff << 3) /* 3-15: reserved */ 8757c478bd9Sstevel@tonic-gate #define ERI_MCTLSTS_PAUSE_TIME (0xffff0000) /* 16-31: Pause time recvd */ 8767c478bd9Sstevel@tonic-gate 8777c478bd9Sstevel@tonic-gate #define ERI_MCTLSTS_PAUSE_TIME_SHIFT 16 8787c478bd9Sstevel@tonic-gate 8797c478bd9Sstevel@tonic-gate /* 8807c478bd9Sstevel@tonic-gate * MAC Control Mask Register (RW) 8817c478bd9Sstevel@tonic-gate * pause time is in slot-time units. 8827c478bd9Sstevel@tonic-gate */ 8837c478bd9Sstevel@tonic-gate #define ERI_MCTLMASK_PAUSE_RCVD (1 << 0) /* PAUSE received */ 8847c478bd9Sstevel@tonic-gate #define ERI_MCTLMASK_PAUSE_STATE (1 << 1) /* transition to PAUSE state */ 8857c478bd9Sstevel@tonic-gate #define ERI_MCTLMASK_NONPAUSE (1 << 2) /* change to non-PAUSE state */ 8867c478bd9Sstevel@tonic-gate #define ERI_MCTLMASK_RESERVED (0x1fff << 3) /* 3-15: reserved */ 8877c478bd9Sstevel@tonic-gate #define ERI_MCTLMASK_PAUSE_TIME (0xffff << 16) /* 16-31: Pause time recvd */ 8887c478bd9Sstevel@tonic-gate 8897c478bd9Sstevel@tonic-gate #define ERI_MACCTL_INTR_MASK 0x00000000 8907c478bd9Sstevel@tonic-gate 8917c478bd9Sstevel@tonic-gate /* 8927c478bd9Sstevel@tonic-gate * XIF Configuration Register 8937c478bd9Sstevel@tonic-gate * This register determines the parameters that control the operation of the 8947c478bd9Sstevel@tonic-gate * transceiver interface. 8957c478bd9Sstevel@tonic-gate * The Disable-echo bit should be 0 for full-duplex mode. 8967c478bd9Sstevel@tonic-gate * Default: 0x00 8977c478bd9Sstevel@tonic-gate */ 8987c478bd9Sstevel@tonic-gate 8997c478bd9Sstevel@tonic-gate #define BMAC_XIFC_TX_MII_OE (1 << 0) /* Enable XIF output drivers */ 9007c478bd9Sstevel@tonic-gate #define BMAC_XIFC_MIILPBK (1 << 1) /* Enable MII Loopback mode */ 9017c478bd9Sstevel@tonic-gate #define BMAC_XIFC_DIS_ECHO (1 << 2) /* Disable echo */ 9027c478bd9Sstevel@tonic-gate #define BMAC_XIFC_MII_MODE (1 << 3) /* Selects GMII/MII mode */ 9037c478bd9Sstevel@tonic-gate #define BMAC_XIFC_MIIBUF_OE (1 << 4) /* Enable MII Recv Buffers */ 9047c478bd9Sstevel@tonic-gate #define BMAC_XIFC_LINK_LED (1 << 5) /* force LINKLED# active */ 9057c478bd9Sstevel@tonic-gate #define BMAC_XIFC_FDPLX_LED (1 << 6) /* force FDPLXLED# active */ 9067c478bd9Sstevel@tonic-gate 9077c478bd9Sstevel@tonic-gate /* 9087c478bd9Sstevel@tonic-gate * TX_MAC Configuration Register 9097c478bd9Sstevel@tonic-gate * Ignore_Carrier_Sense should be set to 1 for full-duplex operation and 9107c478bd9Sstevel@tonic-gate * cleared to 0 for half-duplex operation.. 9117c478bd9Sstevel@tonic-gate * Ignore_collisions should be set to 1 for full-duplex operation and cleared 9127c478bd9Sstevel@tonic-gate * to 0 for half-duplex operation.. 9137c478bd9Sstevel@tonic-gate * To Ensure proper operation of the TX_MAC, the TX_MAC_Enable bit must always 9147c478bd9Sstevel@tonic-gate * be cleared to 0 and a delay imposed before a PIO write to any of the other 9157c478bd9Sstevel@tonic-gate * bits in the TX_MAC Configuration register or any of the MAC parameter 9167c478bd9Sstevel@tonic-gate * registers is done. 9177c478bd9Sstevel@tonic-gate * The amount of delay required depends on the time required to transmit a max. 9187c478bd9Sstevel@tonic-gate * size frame. 9197c478bd9Sstevel@tonic-gate * Default: TBD 9207c478bd9Sstevel@tonic-gate */ 9217c478bd9Sstevel@tonic-gate 9227c478bd9Sstevel@tonic-gate #define BMACTXRSTDELAY (125) /* 125 us wait period */ 9237c478bd9Sstevel@tonic-gate /* CHECK */ 9247c478bd9Sstevel@tonic-gate 9257c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_ENAB (1 << 0) /* tx enable */ 9267c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_IGNCS (1 << 1) /* Ignore carrier sense */ 9277c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_IGCOLL (1 << 2) /* Ignore collisions */ 9287c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_ENIPG0 (1 << 3) /* Extend Rx-to-Tx IPG */ 9297c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_NGU (1 << 4) /* Never Give Up */ 9307c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_NGU_LIMIT (1 << 5) /* Never Give Up limit */ 9317c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_NBKOFF (1 << 6) /* No Backoff */ 9327c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_SLOWDOWN (1 << 7) /* Slow down */ 9337c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_NFCS (1 << 8) /* no FCS will be generated */ 9347c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_CARR_EXT (1 << 9) 9357c478bd9Sstevel@tonic-gate /* 9367c478bd9Sstevel@tonic-gate * Enable TX Carrier Extension Carrier Extension is 9377c478bd9Sstevel@tonic-gate * required for half-duplex operation at Gbps 9387c478bd9Sstevel@tonic-gate */ 9397c478bd9Sstevel@tonic-gate 9407c478bd9Sstevel@tonic-gate #define BMAC_TXCFG_FDX (BMAC_TXCFG_IGNCS | BMAC_TXCFG_IGCOLL) 9417c478bd9Sstevel@tonic-gate 9427c478bd9Sstevel@tonic-gate /* 9437c478bd9Sstevel@tonic-gate * RX_MAC Configuration Register 9447c478bd9Sstevel@tonic-gate * A delay of 3.2 ms should be allowed after clearing Rx_MAC_Enable or 9457c478bd9Sstevel@tonic-gate * Hash_Filter_enable or Address_Filter_Enable bits. 9467c478bd9Sstevel@tonic-gate * Default: TBD 9477c478bd9Sstevel@tonic-gate */ 9487c478bd9Sstevel@tonic-gate /* CHECK 3ms or us */ 9497c478bd9Sstevel@tonic-gate /* GEM specification: 3.2msec (3200 usec) */ 9507c478bd9Sstevel@tonic-gate 9517c478bd9Sstevel@tonic-gate #define BMACRXRSTDELAY (3200) /* 3.2 ms wait period */ 9527c478bd9Sstevel@tonic-gate 9537c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_ENAB (1 << 0) /* rx enable */ 9547c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_STRIP_PAD (1 << 1) /* rx strip pad bytes */ 9557c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_STRIP_CRC (1 << 2) /* rx enable CRC stripping */ 9567c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_PROMIS (1 << 3) /* rx enable promiscous */ 9577c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_GRPROM (1 << 4) /* rx promiscuous group mode */ 9587c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_HASH (1 << 5) /* rx enable hash filter */ 9597c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_ADDR (1 << 6) /* rx enable address filter */ 9607c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_ERR (1 << 7) /* rx disable error checking */ 9617c478bd9Sstevel@tonic-gate #define BMAC_RXCFG_CARR_EXT (1 << 8) 9627c478bd9Sstevel@tonic-gate /* 9637c478bd9Sstevel@tonic-gate * Enable RX Carrier Extension. 9647c478bd9Sstevel@tonic-gate * Enables the reception of packet bursts 9657c478bd9Sstevel@tonic-gate * generated by Carrier Extension with 9667c478bd9Sstevel@tonic-gate * packet bursting senders 9677c478bd9Sstevel@tonic-gate */ 9687c478bd9Sstevel@tonic-gate 9697c478bd9Sstevel@tonic-gate /* 9707c478bd9Sstevel@tonic-gate * MAC Control Configuration Register (RW) 9717c478bd9Sstevel@tonic-gate * Default: 0x00 9727c478bd9Sstevel@tonic-gate */ 9737c478bd9Sstevel@tonic-gate 9747c478bd9Sstevel@tonic-gate #define ERI_MCTLCFG_TXPAUSE (1 << 0) /* Send_PAUSE Enable */ 9757c478bd9Sstevel@tonic-gate #define ERI_MCTLCFG_RXPAUSE (1 << 1) /* Receive_PAUSE Enable */ 9767c478bd9Sstevel@tonic-gate #define ERI_MCTLCFG_PASSPAUSE (1 << 2) /* Pass PAUSE up */ 9777c478bd9Sstevel@tonic-gate 9787c478bd9Sstevel@tonic-gate /* 9797c478bd9Sstevel@tonic-gate * MAC Control Type Register (RW) 9807c478bd9Sstevel@tonic-gate * This 16-bit register specifies the "type" field for the MAC Control frame. 9817c478bd9Sstevel@tonic-gate * Default: 0x8808 9827c478bd9Sstevel@tonic-gate */ 9837c478bd9Sstevel@tonic-gate 9847c478bd9Sstevel@tonic-gate 9857c478bd9Sstevel@tonic-gate /* 9867c478bd9Sstevel@tonic-gate * MAC Address Registers 0, 1, 2 9877c478bd9Sstevel@tonic-gate * Station's Normal peririty MAC address which must be a unicast address. 9887c478bd9Sstevel@tonic-gate * 0 - [15:0], 1 - [31:16], 2 - [47:32] 9897c478bd9Sstevel@tonic-gate */ 9907c478bd9Sstevel@tonic-gate 9917c478bd9Sstevel@tonic-gate /* 9927c478bd9Sstevel@tonic-gate * MAC Address Registers 3, 4, 5 9937c478bd9Sstevel@tonic-gate * Station's Alternate MAC address which may be a unicast or multicast address. 9947c478bd9Sstevel@tonic-gate * 3 - [15:0], 4 - [31:16], 5 - [47:32] 9957c478bd9Sstevel@tonic-gate */ 9967c478bd9Sstevel@tonic-gate 9977c478bd9Sstevel@tonic-gate /* 9987c478bd9Sstevel@tonic-gate * MAC Address Registers 6, 7, 8 9997c478bd9Sstevel@tonic-gate * Station's Control MAC address which must be the reserved multicast 10007c478bd9Sstevel@tonic-gate * address for MAC Control frames. 10017c478bd9Sstevel@tonic-gate * 6 - [15:0], 7 - [31:16], 8 - [47:32] 10027c478bd9Sstevel@tonic-gate */ 10037c478bd9Sstevel@tonic-gate 10047c478bd9Sstevel@tonic-gate /* 10057c478bd9Sstevel@tonic-gate * MII Transceiver Interface 10067c478bd9Sstevel@tonic-gate * 10077c478bd9Sstevel@tonic-gate * The Management Interface (MIF) allows the host to program and collect status 10087c478bd9Sstevel@tonic-gate * from two transceivers connected to the MII. MIF supports three modes of 10097c478bd9Sstevel@tonic-gate * operation: 10107c478bd9Sstevel@tonic-gate * 1. Bit-Bang Mode 10117c478bd9Sstevel@tonic-gate * This mode is imlemented using three 1-bit registers: data, clock, 10127c478bd9Sstevel@tonic-gate * and output_enable. 10137c478bd9Sstevel@tonic-gate * 10147c478bd9Sstevel@tonic-gate * 2. Frame Mode 10157c478bd9Sstevel@tonic-gate * This mode is supported using one 32-bit register: Frame register. 10167c478bd9Sstevel@tonic-gate * The software loads the Frame Register with avalid instaruction 10177c478bd9Sstevel@tonic-gate * ("frame"), and polls the Valid Bit for completion. 10187c478bd9Sstevel@tonic-gate * 10197c478bd9Sstevel@tonic-gate * 3. Polling Mode 10207c478bd9Sstevel@tonic-gate * The Polling mechanism is used for detecting a status change in the 10217c478bd9Sstevel@tonic-gate * transceiver. When this mode is enabled, the MIF will continuously 10227c478bd9Sstevel@tonic-gate * poll a specified transceiver register and generate a maskable 10237c478bd9Sstevel@tonic-gate * interrupt when a status change is detected. This mode of operation 10247c478bd9Sstevel@tonic-gate * can only be used when the MIF is in the "Frame mode". 10257c478bd9Sstevel@tonic-gate * 10267c478bd9Sstevel@tonic-gate */ 10277c478bd9Sstevel@tonic-gate 10287c478bd9Sstevel@tonic-gate struct mif { 10297c478bd9Sstevel@tonic-gate uint32_t mif_bbclk; /* 0x6200 (RW) MIF Bit Bang Clock */ 10307c478bd9Sstevel@tonic-gate uint32_t mif_bbdata; /* 0x6204 (RW) MIF Bit Bang Data */ 10317c478bd9Sstevel@tonic-gate uint32_t mif_bbopenb; /* 0x6208 (RW) MIF Bit Bang Output Enable */ 10327c478bd9Sstevel@tonic-gate uint32_t mif_frame; /* 0x620C (RW) MIF Frame - ctl and data */ 10337c478bd9Sstevel@tonic-gate uint32_t mif_cfg; /* 0x6210 (RW) MIF Configuration */ 10347c478bd9Sstevel@tonic-gate uint32_t mif_imask; /* 0x6214 (RW) MIF Interrupt mask */ 10357c478bd9Sstevel@tonic-gate uint32_t mif_bsts; /* 0x6218 (R-AC) MIF Basic/Status register */ 10367c478bd9Sstevel@tonic-gate uint32_t mif_fsm; /* 0x621C (RO) MIF State machine register */ 10377c478bd9Sstevel@tonic-gate }; 10387c478bd9Sstevel@tonic-gate 10397c478bd9Sstevel@tonic-gate /* 10407c478bd9Sstevel@tonic-gate * mif_bbclk - Bit Bang Clock register 10417c478bd9Sstevel@tonic-gate */ 10427c478bd9Sstevel@tonic-gate #define ERI_MIF_BBCLK (1 << 0); /* Bit Babg Clock */ 10437c478bd9Sstevel@tonic-gate 10447c478bd9Sstevel@tonic-gate #define ERI_BBCLK_LOW 0 10457c478bd9Sstevel@tonic-gate #define ERI_BBCLK_HIGH 1 10467c478bd9Sstevel@tonic-gate 10477c478bd9Sstevel@tonic-gate /* mif_bbdata - bit Bang Data register */ 10487c478bd9Sstevel@tonic-gate #define ERI_MIF_BBDATA (1 << 0); /* Bit Bang Data */ 10497c478bd9Sstevel@tonic-gate 10507c478bd9Sstevel@tonic-gate /* mif_bbopenb - Bit Bang oOutput Enable register */ 10517c478bd9Sstevel@tonic-gate #define ERI_MIF_BBOPENB (1 << 0); /* Bit Bang output Enable */ 10527c478bd9Sstevel@tonic-gate 10537c478bd9Sstevel@tonic-gate /* 10547c478bd9Sstevel@tonic-gate * Management Frame Structure: 10557c478bd9Sstevel@tonic-gate * <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE> 10567c478bd9Sstevel@tonic-gate * READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD> 10577c478bd9Sstevel@tonic-gate * WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD> 10587c478bd9Sstevel@tonic-gate */ 10597c478bd9Sstevel@tonic-gate 10607c478bd9Sstevel@tonic-gate /* 10617c478bd9Sstevel@tonic-gate * mif_frame - MIF control and data register 10627c478bd9Sstevel@tonic-gate */ 10637c478bd9Sstevel@tonic-gate #define ERI_MIF_FRDATA (0xffff << 0) /* 0-15 : data bits */ 10647c478bd9Sstevel@tonic-gate #define ERI_MIF_FRTA0 (0x1 << 16) /* 16 : TA bit, 1 for completion */ 10657c478bd9Sstevel@tonic-gate #define ERI_MIF_FRTA1 (0x1 << 17) /* 16-17 : TA bits */ 10667c478bd9Sstevel@tonic-gate #define ERI_MIF_FRREGAD (0x1f << 18) /* 18-22 : register address bits */ 10677c478bd9Sstevel@tonic-gate #define ERI_MIF_FRPHYAD (0x1f << 23) /* 23-27 : PHY ad, should be 0 */ 10687c478bd9Sstevel@tonic-gate #define ERI_MIF_FROP (0x3 << 28) /* 28-29 : Operation - Write/Read */ 10697c478bd9Sstevel@tonic-gate #define ERI_MIF_FRST (0xc0000000) /* 30-31 : START bits */ 10707c478bd9Sstevel@tonic-gate 10717c478bd9Sstevel@tonic-gate #define ERI_MIF_FRREGAD_SHIFT 18 10727c478bd9Sstevel@tonic-gate #define ERI_MIF_FRPHYAD_SHIFT 23 10737c478bd9Sstevel@tonic-gate #define ERI_MIF_FRREAD 0x60020000 10747c478bd9Sstevel@tonic-gate #define ERI_MIF_FRWRITE 0x50020000 10757c478bd9Sstevel@tonic-gate 10767c478bd9Sstevel@tonic-gate /* 10777c478bd9Sstevel@tonic-gate * maximum delay for MIF Register Read/Write operation 10787c478bd9Sstevel@tonic-gate */ 10797c478bd9Sstevel@tonic-gate #define ERI_MAX_MIF_DELAY (100) 10807c478bd9Sstevel@tonic-gate 10817c478bd9Sstevel@tonic-gate /* 10827c478bd9Sstevel@tonic-gate * maximum delay for Transceiver Reset 10837c478bd9Sstevel@tonic-gate */ 10847c478bd9Sstevel@tonic-gate #define ERI_PHYRST_MAXDELAY (500) 10857c478bd9Sstevel@tonic-gate #define ERI_PCS_PHYRST_MAXDELAY (500) 10867c478bd9Sstevel@tonic-gate 10877c478bd9Sstevel@tonic-gate /* 10887c478bd9Sstevel@tonic-gate * mif_cfg - MIF Configuration Register 10897c478bd9Sstevel@tonic-gate */ 10907c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGPS (1 << 0) /* PHY Select */ 10917c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGPE (1 << 1) /* Poll Enable */ 10927c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGBB (1 << 2) /* Bit Bang Enable */ 10937c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGPR (0x1f << 3) /* Poll Register address */ 10947c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGM0 (1 << 8) /* MDIO_0 Data / MDIO_0 attached */ 10957c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGM1 (1 << 9) /* MDIO_1 Data / MDIO_1 attached */ 10967c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGPD (0x1f << 10) /* Poll Device PHY address */ 10977c478bd9Sstevel@tonic-gate 10987c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGPR_SHIFT 3 10997c478bd9Sstevel@tonic-gate #define ERI_MIF_CFGPD_SHIFT 10 11007c478bd9Sstevel@tonic-gate #define ERI_MIF_POLL_DELAY 200 11017c478bd9Sstevel@tonic-gate 11027c478bd9Sstevel@tonic-gate /* 11037c478bd9Sstevel@tonic-gate * MDIO_0 corresponds to the On Board Transceiver. 11047c478bd9Sstevel@tonic-gate * MDIO_1 corresponds to the External Transceiver. 11057c478bd9Sstevel@tonic-gate * The PHYAD for both is 0. 11067c478bd9Sstevel@tonic-gate */ 11077c478bd9Sstevel@tonic-gate #define ERI_INTERNAL_PHYAD 1 /* PHY address for int. transceiver */ 11087c478bd9Sstevel@tonic-gate #define ERI_EXTERNAL_PHYAD 0 /* PHY address for ext. transceiver */ 11097c478bd9Sstevel@tonic-gate #define ERI_NOXCVR_PHYAD 99 /* PHY address for no transceiver */ 11107c478bd9Sstevel@tonic-gate 11117c478bd9Sstevel@tonic-gate 11127c478bd9Sstevel@tonic-gate /* mif_imask - MIF Interrupt Mask Register */ 11137c478bd9Sstevel@tonic-gate /* 11147c478bd9Sstevel@tonic-gate * This register is bit-to-bit same as Basic/Status Register 11157c478bd9Sstevel@tonic-gate */ 11167c478bd9Sstevel@tonic-gate #define ERI_MIF_INTMASK (0xffff << 0) /* 0-15 : Interrupt mask */ 11177c478bd9Sstevel@tonic-gate 11187c478bd9Sstevel@tonic-gate /* mif_bassts - MIF Basic - Status register */ 11197c478bd9Sstevel@tonic-gate /* 11207c478bd9Sstevel@tonic-gate * The Basic portion of this register indicates the last value of the register 11217c478bd9Sstevel@tonic-gate * read indicated in the POLL REG field of the Configuration Register. 11227c478bd9Sstevel@tonic-gate * The Status portion indicates bit(s) that have changed. 11237c478bd9Sstevel@tonic-gate * The MIF Mask register is corresponding to this register in terms of the 11247c478bd9Sstevel@tonic-gate * bit(s) that need to be masked for generating interrupt on the MIF Interrupt 11257c478bd9Sstevel@tonic-gate * Bit of the Global Status Rgister. 11267c478bd9Sstevel@tonic-gate */ 11277c478bd9Sstevel@tonic-gate 11287c478bd9Sstevel@tonic-gate #define ERI_MIF_STATUS (0xffff << 0) /* 0-15 : Status */ 11297c478bd9Sstevel@tonic-gate #define ERI_MIF_BASIC (0xffff << 16) /* 16-31 : Basic register */ 11307c478bd9Sstevel@tonic-gate 11317c478bd9Sstevel@tonic-gate /* mif_fsm - MIF State Machine register */ 11327c478bd9Sstevel@tonic-gate 11337c478bd9Sstevel@tonic-gate #define ERI_MIF_FSM (0x3ff << 0) /* 0-9 : MIF state */ 11347c478bd9Sstevel@tonic-gate 11357c478bd9Sstevel@tonic-gate /* 11367c478bd9Sstevel@tonic-gate * ERI PCS/Serial-Link 11377c478bd9Sstevel@tonic-gate */ 11387c478bd9Sstevel@tonic-gate struct pcslink { 11397c478bd9Sstevel@tonic-gate uint32_t pcs_ctl; /* 0x9000 (RW) PCS MII Control Reg */ 11407c478bd9Sstevel@tonic-gate uint32_t pcs_sts; /* 0x9004 (RO) PCS MII Status Register */ 11417c478bd9Sstevel@tonic-gate uint32_t pcs_anar; /* 0x9008 (RW) PCS MII Avertisement Reg */ 11427c478bd9Sstevel@tonic-gate uint32_t pcs_anlpar; /* 0x900C (RW) PCS MII LP Ability Reg */ 11437c478bd9Sstevel@tonic-gate uint32_t pcs_cfg; /* 0x9010 (RW) PCS Configuration Register */ 11447c478bd9Sstevel@tonic-gate uint32_t pcs_smr; /* 0x9014 (RW) PCS State Machine Reg */ 11457c478bd9Sstevel@tonic-gate uint32_t pcs_intsts; /* 0x9018 (R-AC) PCS Interrupt Status Reg */ 11467c478bd9Sstevel@tonic-gate uint32_t res1[13]; /* 0x901C - 0x904C Reserved */ 11477c478bd9Sstevel@tonic-gate uint32_t pcs_dmode; /* 0x9050 (RW) Datapath mode register */ 11487c478bd9Sstevel@tonic-gate uint32_t slink_ctl; /* 0x9054 (RW) Serial Link Control register */ 11497c478bd9Sstevel@tonic-gate uint32_t pcs_opsel; /* 0x9058 (RW) Shared Output Select register */ 11507c478bd9Sstevel@tonic-gate uint32_t slink_sts; /* 0x905C (RO) Serial Link Status register */ 11517c478bd9Sstevel@tonic-gate }; 11527c478bd9Sstevel@tonic-gate 11537c478bd9Sstevel@tonic-gate /* 11547c478bd9Sstevel@tonic-gate * PCS MII Basic Mode Control Register 11557c478bd9Sstevel@tonic-gate * Auto-Negotiation should always be used for 802.3z 8B/10B 11567c478bd9Sstevel@tonic-gate * link configuration. May be cleared for diagnostic purposes, or 11577c478bd9Sstevel@tonic-gate * as a workaround for possible early product interoperability problems. 11587c478bd9Sstevel@tonic-gate */ 11597c478bd9Sstevel@tonic-gate 11607c478bd9Sstevel@tonic-gate #define PCS_BMCR_RESET (1 << 15) /* Resets the PCS when set */ 11617c478bd9Sstevel@tonic-gate #define PCS_BMCR_LPBK (1 << 14) /* Loopback of the 10-bit i/f */ 11627c478bd9Sstevel@tonic-gate #define PCS_BMCR_1000M (1 << 13) /* Speed selection, always 0 */ 11637c478bd9Sstevel@tonic-gate #define PCS_BMCR_ANE (1 << 12) /* Auto Negotiation Enabled when set */ 11647c478bd9Sstevel@tonic-gate #define PCS_BMCR_PWRDN (1 << 11) /* Power down, always 0 */ 11657c478bd9Sstevel@tonic-gate #define PCS_BMCR_ISOLATE (1 << 10) /* Isolate PHY from MII, always 0 */ 11667c478bd9Sstevel@tonic-gate #define PCS_BMCR_RAN (1 << 9) /* Set to Restart Auto Negotiation */ 11677c478bd9Sstevel@tonic-gate #define PCS_BMCR_FDX (1 << 8) /* Full Duplex, always 0 */ 11687c478bd9Sstevel@tonic-gate #define PCS_BMCR_COLTST (1 << 7) /* Collision Test */ 11697c478bd9Sstevel@tonic-gate #define PCS_BMCR_RES1 (0x7f << 0) /* 0-6 Reserved */ 11707c478bd9Sstevel@tonic-gate 11717c478bd9Sstevel@tonic-gate #define PCS_AUTONEG_DISABLE 0 11727c478bd9Sstevel@tonic-gate 11737c478bd9Sstevel@tonic-gate /* 11747c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 11757c478bd9Sstevel@tonic-gate * PCS MII Basic Mode Status Register 11767c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 11777c478bd9Sstevel@tonic-gate */ 11787c478bd9Sstevel@tonic-gate 11797c478bd9Sstevel@tonic-gate 11807c478bd9Sstevel@tonic-gate #define PCS_BMSR_RES2 (0x1f << 11) /* 11-15 reserved, always 0 */ 11817c478bd9Sstevel@tonic-gate #define PCS_BMSR_GBFDX (1 << 10) /* PCS able to perform GBit FDX */ 11827c478bd9Sstevel@tonic-gate #define PCS_BMSR_GBHDX (1 << 9) /* PCS able to perform Gbit HDX */ 11837c478bd9Sstevel@tonic-gate #define PCS_BMSR_RES1 (0x7 << 6) /* 6-8 reserved */ 11847c478bd9Sstevel@tonic-gate #define PCS_BMSR_ANC (1 << 5) /* Auto Negotiation Completed */ 11857c478bd9Sstevel@tonic-gate #define PCS_BMSR_REMFLT (1 << 4) /* Remote Fault detected */ 11867c478bd9Sstevel@tonic-gate #define PCS_BMSR_ACFG (1 << 3) /* Able to do Auto Link Negotiation,1 */ 11877c478bd9Sstevel@tonic-gate #define PCS_BMSR_LNKSTS (1 << 2) /* Link Status */ 11887c478bd9Sstevel@tonic-gate #define PCS_BMSR_JABDET (1 << 1) /* Jabber Condition Detected, 0 */ 11897c478bd9Sstevel@tonic-gate #define PCS_BMSR_EXTCAP (1 << 0) /* Extended Register Capability, 0 */ 11907c478bd9Sstevel@tonic-gate 11917c478bd9Sstevel@tonic-gate #define PCS_CAPABILITY_MASK (PCS_BMSR_GBFDX | PCS_BMSR_GBHDX) 11927c478bd9Sstevel@tonic-gate 11937c478bd9Sstevel@tonic-gate 11947c478bd9Sstevel@tonic-gate /* 11957c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 11967c478bd9Sstevel@tonic-gate * PCS MII Auto-Negotiation Advertisement Register (nway1Reg) 11977c478bd9Sstevel@tonic-gate * This register will hold the different modes of operation to be advertised to 11987c478bd9Sstevel@tonic-gate * the far-end PHY. 11997c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 12007c478bd9Sstevel@tonic-gate */ 12017c478bd9Sstevel@tonic-gate 12027c478bd9Sstevel@tonic-gate #define PCS_ANAR_NP (1 << 15) /* Next Page bit, RO, always 0 */ 12037c478bd9Sstevel@tonic-gate #define PCS_ANAR_ACK (1 << 14) /* Acks reception of Link Partner */ 12047c478bd9Sstevel@tonic-gate /* Capability word */ 12057c478bd9Sstevel@tonic-gate #define PCS_ANAR_RF (0x2 << 12) /* Advertise Remote Fault det. cap. */ 12067c478bd9Sstevel@tonic-gate #define PCS_ANAR_RES1 (0x7 << 9) /* 9-11 reserved */ 12077c478bd9Sstevel@tonic-gate #define PCS_ANAR_PTX (1 << 8) /* Pause TX */ 12087c478bd9Sstevel@tonic-gate #define PCS_ANAR_PRX (1 << 7) /* Pause RX */ 12097c478bd9Sstevel@tonic-gate #define PCS_ANAR_PAUSE (1 << 7) /* Pause */ 12107c478bd9Sstevel@tonic-gate #define PCS_ANAR_ASM_DIR (1 << 8) /* Asymetric Direction */ 12117c478bd9Sstevel@tonic-gate #define PCS_ANAR_GBFDX (1 << 5) /* Advertise Gbit FDX Capability */ 12127c478bd9Sstevel@tonic-gate #define PCS_ANAR_GBHDX (1 << 6) /* Advertise Gbit HDX Capability */ 12137c478bd9Sstevel@tonic-gate #define PCS_ANAR_RES (0x1f << 0) /* 0-5 Reserved */ 12147c478bd9Sstevel@tonic-gate 12157c478bd9Sstevel@tonic-gate 12167c478bd9Sstevel@tonic-gate /* ************************************************************************ */ 12177c478bd9Sstevel@tonic-gate /* 12187c478bd9Sstevel@tonic-gate * PCS MII Auto-Negotiation Link Partner Ability Reg 12197c478bd9Sstevel@tonic-gate * This register contains the Link Partners capabilities after NWay 12207c478bd9Sstevel@tonic-gate * Auto-Negotiation is complete. 12217c478bd9Sstevel@tonic-gate */ 12227c478bd9Sstevel@tonic-gate 12237c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_NP (1 << 15) /* Next Page bit, RO, always 0 */ 12247c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_ACK (1 << 14) /* Acks reception of Link Partner */ 12257c478bd9Sstevel@tonic-gate /* Capability word */ 12267c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_RF (0x2 << 12) /* Advertise Remote Fault det. cap. */ 12277c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_RES1 (0x7 << 9) /* 9-11 reserved */ 12287c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_PTX (1 << 8) /* Pause TX */ 12297c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_PRX (1 << 7) /* Pause RX */ 12307c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_GBFDX (1 << 5) /* Advertise Gbit FDX Capability */ 12317c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_GBHDX (1 << 6) /* Advertise Gbit HDX Capability */ 12327c478bd9Sstevel@tonic-gate #define PCS_ANLPAR_RES (0x1f << 0) /* 0-5 Reserved */ 12337c478bd9Sstevel@tonic-gate 12347c478bd9Sstevel@tonic-gate 12357c478bd9Sstevel@tonic-gate /* 12367c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 12377c478bd9Sstevel@tonic-gate * PCS Configuration Register 12387c478bd9Sstevel@tonic-gate * Default = 0x8 12397c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 12407c478bd9Sstevel@tonic-gate */ 12417c478bd9Sstevel@tonic-gate 12427c478bd9Sstevel@tonic-gate #define PCS_CFG_RES (0xfff << 4) /* 4-15 Reserved */ 12437c478bd9Sstevel@tonic-gate #define PCS_CFG_TIMER (0x7 << 1) 12447c478bd9Sstevel@tonic-gate /* Timer values used for the 802.3z Clause 36 Link Monitor s/m timers */ 12457c478bd9Sstevel@tonic-gate #define PCS_CFG_ENABLE (1 << 0) /* Enable PCS, when set to 1 */ 12467c478bd9Sstevel@tonic-gate 12477c478bd9Sstevel@tonic-gate 12487c478bd9Sstevel@tonic-gate /* 12497c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 12507c478bd9Sstevel@tonic-gate * PCS Interrupt State Register 12517c478bd9Sstevel@tonic-gate * Presently only one bit is implemented, reflecting transitions on the link 12527c478bd9Sstevel@tonic-gate * status. Note that there is no mask register at this level. 12537c478bd9Sstevel@tonic-gate * THe PCS_INT bit may be masked at the Interrupt Status Register level. 12547c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 12557c478bd9Sstevel@tonic-gate */ 12567c478bd9Sstevel@tonic-gate 12577c478bd9Sstevel@tonic-gate #define PCS_STS_LNKSTS 2 /* Link Status Change */ 12587c478bd9Sstevel@tonic-gate 12597c478bd9Sstevel@tonic-gate 12607c478bd9Sstevel@tonic-gate /* 12617c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 12627c478bd9Sstevel@tonic-gate * Datapath Mode Register (RW) 12637c478bd9Sstevel@tonic-gate * This register controls which network interface is used. 12647c478bd9Sstevel@tonic-gate * Only one bit should be set in this register. 12657c478bd9Sstevel@tonic-gate * Default: 0x1 12667c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 12677c478bd9Sstevel@tonic-gate */ 12687c478bd9Sstevel@tonic-gate /* 12697c478bd9Sstevel@tonic-gate * Select MII/GMII and not PCS. 12707c478bd9Sstevel@tonic-gate * Selection between MII and GMII is 12717c478bd9Sstevel@tonic-gate * controlled by the XIF register 12727c478bd9Sstevel@tonic-gate */ 12737c478bd9Sstevel@tonic-gate #define ERI_PCS_MII (1 << 2) 12747c478bd9Sstevel@tonic-gate /* 12757c478bd9Sstevel@tonic-gate * Applicable only in Serial Mode 12767c478bd9Sstevel@tonic-gate * When set, makes the 10-bit Xmit data 12777c478bd9Sstevel@tonic-gate * visible at the GMII 12787c478bd9Sstevel@tonic-gate */ 12797c478bd9Sstevel@tonic-gate #define ERI_PCS_GMIIOUTEN (1 << 3) 12807c478bd9Sstevel@tonic-gate 12817c478bd9Sstevel@tonic-gate 12827c478bd9Sstevel@tonic-gate /* 12837c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 12847c478bd9Sstevel@tonic-gate * Serial Link Control register (RW) 12857c478bd9Sstevel@tonic-gate * This register controls the Serial link 12867c478bd9Sstevel@tonic-gate * Default: 0x000 12877c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 12887c478bd9Sstevel@tonic-gate */ 12897c478bd9Sstevel@tonic-gate #define ERI_SLC_LOOPBACK (1 << 0) /* Enables loopback at the SL o/p */ 12907c478bd9Sstevel@tonic-gate #define ERI_SLC_ENSYNCDT (1 << 1) /* Enable Sync char detection */ 12917c478bd9Sstevel@tonic-gate #define ERI_SLC_LOCKREF (1 << 2) /* Lock to reference clock */ 12927c478bd9Sstevel@tonic-gate #define ERI_SLC_EMP (0x2 << 3) /* Control o/p driver emphasis */ 12937c478bd9Sstevel@tonic-gate #define ERI_SLC_RES (1 << 5) /* Reserved */ 12947c478bd9Sstevel@tonic-gate #define ERI_SLC_SELFTEST (0x7 << 6) /* To select built-in self tests */ 12957c478bd9Sstevel@tonic-gate #define ERI_SLC_SW_PDOWN (1 << 9) /* Power down Serial link block */ 12967c478bd9Sstevel@tonic-gate 12977c478bd9Sstevel@tonic-gate /* 12987c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 12997c478bd9Sstevel@tonic-gate * Shared Output Select Register (RW) 13007c478bd9Sstevel@tonic-gate * Default: 0x00 13017c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 13027c478bd9Sstevel@tonic-gate */ 13037c478bd9Sstevel@tonic-gate 13047c478bd9Sstevel@tonic-gate /* 13057c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------ 13067c478bd9Sstevel@tonic-gate * Serial Link State Register (RO) 13077c478bd9Sstevel@tonic-gate * Indicates the progress of the Serial link boot up 13087c478bd9Sstevel@tonic-gate * 00 - Undergoing test 13097c478bd9Sstevel@tonic-gate * 01 - Waiting 500us while lockrefn is asserted 13107c478bd9Sstevel@tonic-gate * 10 - Waiting for comma detect 13117c478bd9Sstevel@tonic-gate * 11 - Receive Data is synchronized 13127c478bd9Sstevel@tonic-gate * ------------------------------------------------------------------------- 13137c478bd9Sstevel@tonic-gate */ 13147c478bd9Sstevel@tonic-gate #define ERI_SLS_STATE (0x2 << 0) /* state */ 13157c478bd9Sstevel@tonic-gate 13167c478bd9Sstevel@tonic-gate 13177c478bd9Sstevel@tonic-gate 13187c478bd9Sstevel@tonic-gate /* ************************************************************************ */ 13197c478bd9Sstevel@tonic-gate /* 13207c478bd9Sstevel@tonic-gate * Definition for the time required to wait after a software 13217c478bd9Sstevel@tonic-gate * reset has been issued. 13227c478bd9Sstevel@tonic-gate */ 13237c478bd9Sstevel@tonic-gate #define ERI_MAX_RST_DELAY (200) 13247c478bd9Sstevel@tonic-gate #define ERI_PERIOD (20) /* period to wait */ 13257c478bd9Sstevel@tonic-gate #define ERI_WAITPERIOD ERI_PERIOD 13267c478bd9Sstevel@tonic-gate 13277c478bd9Sstevel@tonic-gate #define ERI_DELAY(c, n) \ 13287c478bd9Sstevel@tonic-gate { \ 13297c478bd9Sstevel@tonic-gate register int N = n / ERI_WAITPERIOD; \ 13307c478bd9Sstevel@tonic-gate while (--N > 0) { \ 13317c478bd9Sstevel@tonic-gate if (c) \ 13327c478bd9Sstevel@tonic-gate break; \ 13337c478bd9Sstevel@tonic-gate drv_usecwait(ERI_WAITPERIOD); \ 13347c478bd9Sstevel@tonic-gate } \ 13357c478bd9Sstevel@tonic-gate } 13367c478bd9Sstevel@tonic-gate 13377c478bd9Sstevel@tonic-gate #define MIF_ERIDELAY(n, phyad, regad) \ 13387c478bd9Sstevel@tonic-gate { \ 13397c478bd9Sstevel@tonic-gate register int N = n / ERI_WAITPERIOD; \ 13407c478bd9Sstevel@tonic-gate PUT_MIFREG(mif_frame, \ 13417c478bd9Sstevel@tonic-gate (ERI_MIF_FRREAD | (phyad << ERI_MIF_FRPHYAD_SHIFT) | \ 13427c478bd9Sstevel@tonic-gate (regad << ERI_MIF_FRREGAD_SHIFT))); \ 13437c478bd9Sstevel@tonic-gate while (--N > 0) { \ 13447c478bd9Sstevel@tonic-gate if (GET_MIFREG(mif_frame) & ERI_MIF_FRTA0) \ 13457c478bd9Sstevel@tonic-gate break; \ 13467c478bd9Sstevel@tonic-gate drv_usecwait(ERI_WAITPERIOD); \ 13477c478bd9Sstevel@tonic-gate } \ 13487c478bd9Sstevel@tonic-gate } 13497c478bd9Sstevel@tonic-gate 13507c478bd9Sstevel@tonic-gate 13517c478bd9Sstevel@tonic-gate #ifdef __cplusplus 13527c478bd9Sstevel@tonic-gate } 13537c478bd9Sstevel@tonic-gate #endif 13547c478bd9Sstevel@tonic-gate 13557c478bd9Sstevel@tonic-gate #endif /* _SYS_ERI_MAC_H */ 1356