17aec1d6eScindi /* 27aec1d6eScindi * CDDL HEADER START 37aec1d6eScindi * 47aec1d6eScindi * The contents of this file are subject to the terms of the 580ab886dSwesolows * Common Development and Distribution License (the "License"). 680ab886dSwesolows * You may not use this file except in compliance with the License. 77aec1d6eScindi * 87aec1d6eScindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97aec1d6eScindi * or http://www.opensolaris.org/os/licensing. 107aec1d6eScindi * See the License for the specific language governing permissions 117aec1d6eScindi * and limitations under the License. 127aec1d6eScindi * 137aec1d6eScindi * When distributing Covered Code, include this CDDL HEADER in each 147aec1d6eScindi * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157aec1d6eScindi * If applicable, add the following below this CDDL HEADER, with the 167aec1d6eScindi * fields enclosed by brackets "[]" replaced with your own identifying 177aec1d6eScindi * information: Portions Copyright [yyyy] [name of copyright owner] 187aec1d6eScindi * 197aec1d6eScindi * CDDL HEADER END 207aec1d6eScindi */ 217aec1d6eScindi 227aec1d6eScindi /* 23bb86c342Sgavinm * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 247aec1d6eScindi * Use is subject to license terms. 257aec1d6eScindi */ 267aec1d6eScindi 277aec1d6eScindi #ifndef _SYS_MCA_AMD_H 287aec1d6eScindi #define _SYS_MCA_AMD_H 297aec1d6eScindi 3020c794b3Sgavinm #include <sys/mca_x86.h> 3120c794b3Sgavinm 327aec1d6eScindi /* 3320c794b3Sgavinm * Constants for the Machine Check Architecture as implemented on AMD CPUs. 347aec1d6eScindi */ 357aec1d6eScindi 367aec1d6eScindi #ifdef __cplusplus 377aec1d6eScindi extern "C" { 387aec1d6eScindi #endif 397aec1d6eScindi 407aec1d6eScindi #define AMD_MSR_MCG_CAP 0x179 417aec1d6eScindi #define AMD_MSR_MCG_STATUS 0x17a 427aec1d6eScindi #define AMD_MSR_MCG_CTL 0x17b 437aec1d6eScindi 447aec1d6eScindi #define AMD_MCA_BANK_DC 0 /* Data Cache */ 457aec1d6eScindi #define AMD_MCA_BANK_IC 1 /* Instruction Cache */ 467aec1d6eScindi #define AMD_MCA_BANK_BU 2 /* Bus Unit */ 477aec1d6eScindi #define AMD_MCA_BANK_LS 3 /* Load/Store Unit */ 487aec1d6eScindi #define AMD_MCA_BANK_NB 4 /* Northbridge */ 497aec1d6eScindi #define AMD_MCA_BANK_COUNT 5 507aec1d6eScindi 517aec1d6eScindi #define AMD_MSR_DC_CTL 0x400 527aec1d6eScindi #define AMD_MSR_DC_MASK 0xc0010044 537aec1d6eScindi #define AMD_MSR_DC_STATUS 0x401 547aec1d6eScindi #define AMD_MSR_DC_ADDR 0x402 558a40a695Sgavinm #define AMD_MSR_DC_MISC 0x403 567aec1d6eScindi 577aec1d6eScindi #define AMD_MSR_IC_CTL 0x404 587aec1d6eScindi #define AMD_MSR_IC_MASK 0xc0010045 597aec1d6eScindi #define AMD_MSR_IC_STATUS 0x405 607aec1d6eScindi #define AMD_MSR_IC_ADDR 0x406 618a40a695Sgavinm #define AMD_MSR_IC_MISC 0x407 627aec1d6eScindi 637aec1d6eScindi #define AMD_MSR_BU_CTL 0x408 647aec1d6eScindi #define AMD_MSR_BU_MASK 0xc0010046 657aec1d6eScindi #define AMD_MSR_BU_STATUS 0x409 667aec1d6eScindi #define AMD_MSR_BU_ADDR 0x40a 678a40a695Sgavinm #define AMD_MSR_BU_MISC 0x40b 687aec1d6eScindi 697aec1d6eScindi #define AMD_MSR_LS_CTL 0x40c 707aec1d6eScindi #define AMD_MSR_LS_MASK 0xc0010047 717aec1d6eScindi #define AMD_MSR_LS_STATUS 0x40d 727aec1d6eScindi #define AMD_MSR_LS_ADDR 0x40e 738a40a695Sgavinm #define AMD_MSR_LS_MISC 0x40f 747aec1d6eScindi 757aec1d6eScindi #define AMD_MSR_NB_CTL 0x410 767aec1d6eScindi #define AMD_MSR_NB_MASK 0xc0010048 777aec1d6eScindi #define AMD_MSR_NB_STATUS 0x411 787aec1d6eScindi #define AMD_MSR_NB_ADDR 0x412 798a40a695Sgavinm #define AMD_MSR_NB_MISC 0x413 807aec1d6eScindi 817aec1d6eScindi #define AMD_MCG_EN_DC 0x01 827aec1d6eScindi #define AMD_MCG_EN_IC 0x02 837aec1d6eScindi #define AMD_MCG_EN_BU 0x04 847aec1d6eScindi #define AMD_MCG_EN_LS 0x08 857aec1d6eScindi #define AMD_MCG_EN_NB 0x10 867aec1d6eScindi 877aec1d6eScindi /* 887aec1d6eScindi * Data Cache (DC) bank error-detection enabling bits and CTL register 897aec1d6eScindi * initializer value. 907aec1d6eScindi */ 917aec1d6eScindi 927aec1d6eScindi #define AMD_DC_EN_ECCI 0x00000001ULL 937aec1d6eScindi #define AMD_DC_EN_ECCM 0x00000002ULL 947aec1d6eScindi #define AMD_DC_EN_DECC 0x00000004ULL 957aec1d6eScindi #define AMD_DC_EN_DMTP 0x00000008ULL 967aec1d6eScindi #define AMD_DC_EN_DSTP 0x00000010ULL 977aec1d6eScindi #define AMD_DC_EN_L1TP 0x00000020ULL 987aec1d6eScindi #define AMD_DC_EN_L2TP 0x00000040ULL 997aec1d6eScindi 1008a40a695Sgavinm #define AMD_DC_CTL_INIT_CMN \ 1017aec1d6eScindi (AMD_DC_EN_ECCI | AMD_DC_EN_ECCM | AMD_DC_EN_DECC | AMD_DC_EN_DMTP | \ 1027aec1d6eScindi AMD_DC_EN_DSTP | AMD_DC_EN_L1TP | AMD_DC_EN_L2TP) 1037aec1d6eScindi 1047aec1d6eScindi /* 1057aec1d6eScindi * Instruction Cache (IC) bank error-detection enabling bits and CTL register 1067aec1d6eScindi * initializer value. 1077aec1d6eScindi * 1087aec1d6eScindi * The Northbridge will handle Read Data errors. Our initializer will enable 1097aec1d6eScindi * all but the RDDE detector. 1107aec1d6eScindi */ 1117aec1d6eScindi 1127aec1d6eScindi #define AMD_IC_EN_ECCI 0x00000001ULL 1137aec1d6eScindi #define AMD_IC_EN_ECCM 0x00000002ULL 1147aec1d6eScindi #define AMD_IC_EN_IDP 0x00000004ULL 1157aec1d6eScindi #define AMD_IC_EN_IMTP 0x00000008ULL 1167aec1d6eScindi #define AMD_IC_EN_ISTP 0x00000010ULL 1177aec1d6eScindi #define AMD_IC_EN_L1TP 0x00000020ULL 1187aec1d6eScindi #define AMD_IC_EN_L2TP 0x00000040ULL 1197aec1d6eScindi #define AMD_IC_EN_RDDE 0x00000200ULL 1207aec1d6eScindi 1218a40a695Sgavinm #define AMD_IC_CTL_INIT_CMN \ 1227aec1d6eScindi (AMD_IC_EN_ECCI | AMD_IC_EN_ECCM | AMD_IC_EN_IDP | AMD_IC_EN_IMTP | \ 1237aec1d6eScindi AMD_IC_EN_ISTP | AMD_IC_EN_L1TP | AMD_IC_EN_L2TP) 1247aec1d6eScindi 1257aec1d6eScindi /* 1267aec1d6eScindi * Bus Unit (BU) bank error-detection enabling bits and CTL register 1277aec1d6eScindi * initializer value. 1287aec1d6eScindi * 1297aec1d6eScindi * The Northbridge will handle Read Data errors. Our initializer will enable 1307aec1d6eScindi * all but the S_RDE_* detectors. 1317aec1d6eScindi */ 1327aec1d6eScindi 1337aec1d6eScindi #define AMD_BU_EN_S_RDE_HP 0x00000001ULL 1347aec1d6eScindi #define AMD_BU_EN_S_RDE_TLB 0x00000002ULL 1357aec1d6eScindi #define AMD_BU_EN_S_RDE_ALL 0x00000004ULL 1367aec1d6eScindi #define AMD_BU_EN_S_ECC1_TLB 0x00000008ULL 1377aec1d6eScindi #define AMD_BU_EN_S_ECC1_HP 0x00000010ULL 1387aec1d6eScindi #define AMD_BU_EN_S_ECCM_TLB 0x00000020ULL 1397aec1d6eScindi #define AMD_BU_EN_S_ECCM_HP 0x00000040ULL 1407aec1d6eScindi #define AMD_BU_EN_L2T_PAR_ICDC 0x00000080ULL 1417aec1d6eScindi #define AMD_BU_EN_L2T_PAR_TLB 0x00000100ULL 1427aec1d6eScindi #define AMD_BU_EN_L2T_PAR_SNP 0x00000200ULL 1437aec1d6eScindi #define AMD_BU_EN_L2T_PAR_CPB 0x00000400ULL 1447aec1d6eScindi #define AMD_BU_EN_L2T_PAR_SCR 0x00000800ULL 1457aec1d6eScindi #define AMD_BU_EN_L2D_ECC1_TLB 0x00001000ULL 1467aec1d6eScindi #define AMD_BU_EN_L2D_ECC1_SNP 0x00002000ULL 1477aec1d6eScindi #define AMD_BU_EN_L2D_ECC1_CPB 0x00004000ULL 1487aec1d6eScindi #define AMD_BU_EN_L2D_ECCM_TLB 0x00008000ULL 1497aec1d6eScindi #define AMD_BU_EN_L2D_ECCM_SNP 0x00010000ULL 1507aec1d6eScindi #define AMD_BU_EN_L2D_ECCM_CPB 0x00020000ULL 1517aec1d6eScindi #define AMD_BU_EN_L2T_ECC1_SCR 0x00040000ULL 1527aec1d6eScindi #define AMD_BU_EN_L2T_ECCM_SCR 0x00080000ULL 1537aec1d6eScindi 1548a40a695Sgavinm #define AMD_BU_CTL_INIT_CMN \ 1557aec1d6eScindi (AMD_BU_EN_S_ECC1_TLB | AMD_BU_EN_S_ECC1_HP | \ 1567aec1d6eScindi AMD_BU_EN_S_ECCM_TLB | AMD_BU_EN_S_ECCM_HP | \ 1577aec1d6eScindi AMD_BU_EN_L2T_PAR_ICDC | AMD_BU_EN_L2T_PAR_TLB | \ 1587aec1d6eScindi AMD_BU_EN_L2T_PAR_SNP | AMD_BU_EN_L2T_PAR_CPB | \ 1597aec1d6eScindi AMD_BU_EN_L2T_PAR_SCR | AMD_BU_EN_L2D_ECC1_TLB | \ 1607aec1d6eScindi AMD_BU_EN_L2D_ECC1_SNP | AMD_BU_EN_L2D_ECC1_CPB | \ 1617aec1d6eScindi AMD_BU_EN_L2D_ECCM_TLB | AMD_BU_EN_L2D_ECCM_SNP | \ 1627aec1d6eScindi AMD_BU_EN_L2D_ECCM_CPB | AMD_BU_EN_L2T_ECC1_SCR | \ 1637aec1d6eScindi AMD_BU_EN_L2T_ECCM_SCR) 1647aec1d6eScindi 1657aec1d6eScindi /* 1667aec1d6eScindi * Load/Store (LS) bank error-detection enabling bits and CTL register 1677aec1d6eScindi * initializer value. 1687aec1d6eScindi * 1697aec1d6eScindi * The Northbridge will handle Read Data errors. That's the only type of 1707aec1d6eScindi * error the LS unit can detect at present, so we won't be enabling any 1717aec1d6eScindi * LS detectors. 1727aec1d6eScindi */ 1737aec1d6eScindi 1747aec1d6eScindi #define AMD_LS_EN_S_RDE_S 0x00000001ULL 1757aec1d6eScindi #define AMD_LS_EN_S_RDE_L 0x00000002ULL 1767aec1d6eScindi 1778a40a695Sgavinm #define AMD_LS_CTL_INIT_CMN 0ULL 1788a40a695Sgavinm 1798a40a695Sgavinm /* 1808a40a695Sgavinm * NorthBridge (NB) MCi_MISC - DRAM Errors Threshold Register. 1818a40a695Sgavinm */ 1828a40a695Sgavinm #define AMD_NB_MISC_VALID (0x1ULL << 63) 1838a40a695Sgavinm #define AMD_NB_MISC_CTRP (0x1ULL << 62) 1848a40a695Sgavinm #define AMD_NB_MISC_LOCKED (0x1ULL << 61) 1858a40a695Sgavinm #define AMD_NB_MISC_CNTEN (0x1ULL << 51) 1868a40a695Sgavinm #define AMD_NB_MISC_INTTYPE (0x1ULL << 49) 1878a40a695Sgavinm #define AMD_NB_MISC_INTTYPE_MASK (0x3ULL << 49) 1888a40a695Sgavinm #define AMD_NB_MISC_OVRFLW (0x1ULL << 48) 1898a40a695Sgavinm #define AMD_NB_MISC_ERRCOUNT_MASK (0xfffULL << 32) 1907aec1d6eScindi 1917aec1d6eScindi /* 1927aec1d6eScindi * The Northbridge (NB) is configured using both the standard MCA CTL register 1937aec1d6eScindi * and a NB-specific configuration register (NB CFG). The AMD_NB_EN_* macros 1947aec1d6eScindi * are the detector enabling bits for the NB MCA CTL register. The 1957aec1d6eScindi * AMD_NB_CFG_* bits are for the NB CFG register. 1967aec1d6eScindi * 1977aec1d6eScindi * The CTL register can be initialized statically, but portions of the NB CFG 1987aec1d6eScindi * register must be initialized based on the current machine's configuration. 1997aec1d6eScindi * 2008a40a695Sgavinm * The MCA NB Control Register maps to MC4_CTL[31:0], but we initialize it 2018a40a695Sgavinm * via and MSR write of 64 bits so define all as ULL. 2027aec1d6eScindi * 2037aec1d6eScindi */ 2048a40a695Sgavinm #define AMD_NB_EN_CORRECC 0x00000001ULL 2058a40a695Sgavinm #define AMD_NB_EN_UNCORRECC 0x00000002ULL 2068a40a695Sgavinm #define AMD_NB_EN_CRCERR0 0x00000004ULL 2078a40a695Sgavinm #define AMD_NB_EN_CRCERR1 0x00000008ULL 2088a40a695Sgavinm #define AMD_NB_EN_CRCERR2 0x00000010ULL 2098a40a695Sgavinm #define AMD_NB_EN_SYNCPKT0 0x00000020ULL 2108a40a695Sgavinm #define AMD_NB_EN_SYNCPKT1 0x00000040ULL 2118a40a695Sgavinm #define AMD_NB_EN_SYNCPKT2 0x00000080ULL 2128a40a695Sgavinm #define AMD_NB_EN_MSTRABRT 0x00000100ULL 2138a40a695Sgavinm #define AMD_NB_EN_TGTABRT 0x00000200ULL 2148a40a695Sgavinm #define AMD_NB_EN_GARTTBLWK 0x00000400ULL 2158a40a695Sgavinm #define AMD_NB_EN_ATOMICRMW 0x00000800ULL 2168a40a695Sgavinm #define AMD_NB_EN_WCHDOGTMR 0x00001000ULL 2178a40a695Sgavinm #define AMD_NB_EN_DRAMPAR 0x00040000ULL /* revs F and G */ 2188a40a695Sgavinm 2198a40a695Sgavinm #define AMD_NB_CTL_INIT_CMN /* Revs B to G; All but GARTTBLWK */ \ 2207aec1d6eScindi (AMD_NB_EN_CORRECC | AMD_NB_EN_UNCORRECC | \ 2217aec1d6eScindi AMD_NB_EN_CRCERR0 | AMD_NB_EN_CRCERR1 | AMD_NB_EN_CRCERR2 | \ 2227aec1d6eScindi AMD_NB_EN_SYNCPKT0 | AMD_NB_EN_SYNCPKT1 | AMD_NB_EN_SYNCPKT2 | \ 2237aec1d6eScindi AMD_NB_EN_MSTRABRT | AMD_NB_EN_TGTABRT | \ 2247aec1d6eScindi AMD_NB_EN_ATOMICRMW | AMD_NB_EN_WCHDOGTMR) 2257aec1d6eScindi 2268a40a695Sgavinm #define AMD_NB_CTL_INIT_REV_FG /* Additional bits for revs F and G */ \ 2278a40a695Sgavinm AMD_NB_EN_DRAMPAR 2288a40a695Sgavinm 2298a40a695Sgavinm /* 2308a40a695Sgavinm * NB MCA Configuration register 2318a40a695Sgavinm */ 2328a40a695Sgavinm #define AMD_NB_CFG_CPUECCERREN 0x00000001 2338a40a695Sgavinm #define AMD_NB_CFG_CPURDDATERREN 0x00000002 2348a40a695Sgavinm #define AMD_NB_CFG_SYNCONUCECCEN 0x00000004 2358a40a695Sgavinm #define AMD_NB_CFG_SYNCPKTGENDIS 0x00000008 2368a40a695Sgavinm #define AMD_NB_CFG_SYNCPKTPROPDIS 0x00000010 2378a40a695Sgavinm #define AMD_NB_CFG_IOMSTABORTDIS 0x00000020 2388a40a695Sgavinm #define AMD_NB_CFG_CPUERRDIS 0x00000040 2398a40a695Sgavinm #define AMD_NB_CFG_IOERRDIS 0x00000080 2408a40a695Sgavinm #define AMD_NB_CFG_WDOGTMRDIS 0x00000100 2418a40a695Sgavinm #define AMD_NB_CFG_SYNCONWDOGEN 0x00100000 2428a40a695Sgavinm #define AMD_NB_CFG_SYNCONANYERREN 0x00200000 2438a40a695Sgavinm #define AMD_NB_CFG_ECCEN 0x00400000 2448a40a695Sgavinm #define AMD_NB_CFG_CHIPKILLECCEN 0x00800000 2458a40a695Sgavinm #define AMD_NB_CFG_IORDDATERREN 0x01000000 2468a40a695Sgavinm #define AMD_NB_CFG_DISPCICFGCPUERRRSP 0x02000000 2478a40a695Sgavinm #define AMD_NB_CFG_NBMCATOMSTCPUEN 0x08000000 2488a40a695Sgavinm #define AMD_NB_CFG_DISTGTABTCPUERRRSP 0x10000000 2498a40a695Sgavinm #define AMD_NB_CFG_DISMSTABTCPUERRRSP 0x20000000 2508a40a695Sgavinm #define AMD_NB_CFG_SYNCONDRAMADRPARERREN 0x40000000 /* Revs F & G */ 2518a40a695Sgavinm 2528a40a695Sgavinm /* 2538a40a695Sgavinm * We do not initialize the NB config with an absolute value; instead we 2548a40a695Sgavinm * selectively add some bits and remove others. Note that 2558a40a695Sgavinm * AMD_NB_CFG_{ADD,REMOVE}_{CMN,REV_FG} below are not the whole 2568a40a695Sgavinm * story here - additional config is performed regarding the watchdog (see 2578a40a695Sgavinm * ao_mca.c for details). 2588a40a695Sgavinm */ 2598a40a695Sgavinm #define AMD_NB_CFG_ADD_CMN /* Revs B to G */ \ 2608a40a695Sgavinm (AMD_NB_CFG_DISPCICFGCPUERRRSP | AMD_NB_CFG_SYNCONUCECCEN | \ 2618a40a695Sgavinm AMD_NB_CFG_CPUECCERREN) 2628a40a695Sgavinm 2638a40a695Sgavinm #define AMD_NB_CFG_REMOVE_CMN /* Revs B to G */ \ 2648a40a695Sgavinm (AMD_NB_CFG_NBMCATOMSTCPUEN | \ 2658a40a695Sgavinm AMD_NB_CFG_IORDDATERREN | AMD_NB_CFG_SYNCONANYERREN | \ 2668a40a695Sgavinm AMD_NB_CFG_SYNCONWDOGEN | AMD_NB_CFG_IOERRDIS | \ 2678a40a695Sgavinm AMD_NB_CFG_IOMSTABORTDIS | AMD_NB_CFG_SYNCPKTPROPDIS | \ 2688a40a695Sgavinm AMD_NB_CFG_SYNCPKTGENDIS) 2698a40a695Sgavinm 2708a40a695Sgavinm #define AMD_NB_CFG_ADD_REV_FG /* Revs F and G */ \ 2718a40a695Sgavinm AMD_NB_CFG_SYNCONDRAMADRPARERREN 2728a40a695Sgavinm 2738a40a695Sgavinm #define AMD_NB_CFG_REMOVE_REV_FG 0x0 /* Revs F and G */ 2747aec1d6eScindi 2757aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_4095 0x00000000 2767aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_2047 0x00000200 2777aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_1023 0x00000400 2787aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_511 0x00000600 2797aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_255 0x00000800 2807aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_127 0x00000a00 2817aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_63 0x00000c00 2827aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_31 0x00000e00 2837aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_MASK 0x00000e00 2847aec1d6eScindi #define AMD_NB_CFG_WDOGTMRCNTSEL_SHIFT 9 2857aec1d6eScindi 2867aec1d6eScindi #define AMD_NB_CFG_WDOGTMRBASESEL_1MS 0x00000000 2877aec1d6eScindi #define AMD_NB_CFG_WDOGTMRBASESEL_1US 0x00001000 2887aec1d6eScindi #define AMD_NB_CFG_WDOGTMRBASESEL_5NS 0x00002000 2897aec1d6eScindi #define AMD_NB_CFG_WDOGTMRBASESEL_MASK 0x00003000 2907aec1d6eScindi #define AMD_NB_CFG_WDOGTMRBASESEL_SHIFT 12 2917aec1d6eScindi 2927aec1d6eScindi #define AMD_NB_CFG_LDTLINKSEL_MASK 0x0000c000 2937aec1d6eScindi #define AMD_NB_CFG_LDTLINKSEL_SHIFT 14 2947aec1d6eScindi 2957aec1d6eScindi #define AMD_NB_CFG_GENCRCERRBYTE0 0x00010000 2967aec1d6eScindi #define AMD_NB_CFG_GENCRCERRBYTE1 0x00020000 2977aec1d6eScindi 29820c794b3Sgavinm /* 29920c794b3Sgavinm * The AMD extended error code is just one nibble of the upper 16 bits 30020c794b3Sgavinm * of the bank status (the resy being used for syndrome etc). So we use 30120c794b3Sgavinm * AMD_EXT_ERRCODE to retrieve that extended error code, not the generic 30220c794b3Sgavinm * MCAX86_MSERRCODE. 30320c794b3Sgavinm */ 30420c794b3Sgavinm #define _AMD_ERREXT_MASK 0x00000000000f0000ULL 30520c794b3Sgavinm #define _AMD_ERREXT_SHIFT 16 30620c794b3Sgavinm #define AMD_EXT_ERRCODE(stat) \ 30720c794b3Sgavinm (((stat) & _AMD_ERREXT_MASK) >> _AMD_ERREXT_SHIFT) 30820c794b3Sgavinm #define AMD_EXT_MKERRCODE(errcode) \ 30920c794b3Sgavinm (((errcode) << _AMD_ERREXT_SHIFT) & _AMD_ERREXT_MASK) 31080ab886dSwesolows 31180ab886dSwesolows #define AMD_BANK_STAT_CECC 0x0000400000000000ULL 31280ab886dSwesolows #define AMD_BANK_STAT_UECC 0x0000200000000000ULL 31380ab886dSwesolows #define AMD_BANK_STAT_SCRUB 0x0000010000000000ULL 31480ab886dSwesolows 31580ab886dSwesolows /* syndrome[7:0] */ 31680ab886dSwesolows #define AMD_BANK_STAT_SYND_MASK 0x007f800000000000ULL 3177aec1d6eScindi #define AMD_BANK_STAT_SYND_SHIFT 47 3187aec1d6eScindi 3197aec1d6eScindi #define AMD_BANK_SYND(stat) \ 3207aec1d6eScindi (((stat) & AMD_BANK_STAT_SYND_MASK) >> AMD_BANK_STAT_SYND_SHIFT) 3217aec1d6eScindi #define AMD_BANK_MKSYND(synd) \ 3227aec1d6eScindi (((uint64_t)(synd) << AMD_BANK_STAT_SYND_SHIFT) & \ 3237aec1d6eScindi AMD_BANK_STAT_SYND_MASK) 3247aec1d6eScindi 3258a40a695Sgavinm #define AMD_NB_STAT_DRAMCHANNEL 0x0000020000000000ULL 3268a40a695Sgavinm #define AMD_NB_STAT_LDTLINK_MASK 0x0000007000000000ULL 3277aec1d6eScindi #define AMD_NB_STAT_LDTLINK_SHIFT 4 3288a40a695Sgavinm #define AMD_NB_STAT_ERRCPU1 0x0000000200000000ULL 3298a40a695Sgavinm #define AMD_NB_STAT_ERRCPU0 0x0000000100000000ULL 3308a40a695Sgavinm 3317aec1d6eScindi #define AMD_NB_STAT_CKSYND_MASK 0x00000000ff000000 /* syndrome[15:8] */ 3327aec1d6eScindi #define AMD_NB_STAT_CKSYND_SHIFT (24 - 8) /* shift [31:24] to [15:8] */ 3337aec1d6eScindi 3347aec1d6eScindi #define AMD_NB_STAT_CKSYND(stat) \ 3357aec1d6eScindi ((((stat) & AMD_NB_STAT_CKSYND_MASK) >> AMD_NB_STAT_CKSYND_SHIFT) | \ 3367aec1d6eScindi AMD_BANK_SYND((stat))) 3377aec1d6eScindi 3387aec1d6eScindi #define AMD_NB_STAT_MKCKSYND(synd) \ 3397aec1d6eScindi ((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \ 3407aec1d6eScindi AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd)) 3417aec1d6eScindi 3428a40a695Sgavinm #define AMD_ERREXT_MASK 0x00000000000f0000ULL 3437aec1d6eScindi #define AMD_ERREXT_SHIFT 16 3447aec1d6eScindi 3457aec1d6eScindi #define AMD_ERRCODE_TLB_BIT 4 3467aec1d6eScindi #define AMD_ERRCODE_MEM_BIT 8 3477aec1d6eScindi #define AMD_ERRCODE_BUS_BIT 11 3487aec1d6eScindi 3497aec1d6eScindi #define AMD_ERRCODE_TLB_MASK 0xfff0 3507aec1d6eScindi #define AMD_ERRCODE_MEM_MASK 0xff00 3517aec1d6eScindi #define AMD_ERRCODE_BUS_MASK 0xf800 35220c794b3Sgavinm 35320c794b3Sgavinm #define AMD_ERRCODE_MKTLB(tt, ll) MCAX86_MKERRCODE_TLB(tt, ll) 35420c794b3Sgavinm #define AMD_ERRCODE_ISTLB(code) MCAX86_ERRCODE_ISTLB(code) 35520c794b3Sgavinm 35620c794b3Sgavinm #define AMD_ERRCODE_MKMEM(r4, tt, ll) MCAX86_MKERRCODE_MEMHIER(r4, tt, ll) 35720c794b3Sgavinm #define AMD_ERRCODE_ISMEM(code) MCAX86_ERRCODE_ISMEMHIER(code) 3587aec1d6eScindi 3597aec1d6eScindi #define AMD_ERRCODE_MKBUS(pp, t, r4, ii, ll) \ 36020c794b3Sgavinm MCAX86_MKERRCODE_BUS_INTERCONNECT(pp, t, r4, ii, ll) 36120c794b3Sgavinm #define AMD_ERRCODE_ISBUS(code) MCAX86_ERRCODE_ISBUS_INTERCONNECT(code) 3627aec1d6eScindi 3637aec1d6eScindi #define AMD_NB_ADDRLO_MASK 0xfffffff8 3647aec1d6eScindi #define AMD_NB_ADDRHI_MASK 0x000000ff 3657aec1d6eScindi 3667aec1d6eScindi #define AMD_SYNDTYPE_ECC 0 3677aec1d6eScindi #define AMD_SYNDTYPE_CHIPKILL 1 3687aec1d6eScindi 3697aec1d6eScindi #define AMD_NB_SCRUBCTL_DRAM_MASK 0x0000001f 3707aec1d6eScindi #define AMD_NB_SCRUBCTL_DRAM_SHIFT 0 3717aec1d6eScindi #define AMD_NB_SCRUBCTL_L2_MASK 0x00001f00 3727aec1d6eScindi #define AMD_NB_SCRUBCTL_L2_SHIFT 8 3737aec1d6eScindi #define AMD_NB_SCRUBCTL_DC_MASK 0x001f0000 3747aec1d6eScindi #define AMD_NB_SCRUBCTL_DC_SHIFT 16 375*25f47677Sgavinm #define AMD_NB_SCRUBCTL_L3_MASK 0x1f000000 376*25f47677Sgavinm #define AMD_NB_SCRUBCTL_L3_SHIFT 24 3777aec1d6eScindi 3787aec1d6eScindi #define AMD_NB_SCRUBCTL_RATE_NONE 0 3797aec1d6eScindi #define AMD_NB_SCRUBCTL_RATE_MAX 0x16 3807aec1d6eScindi 3817aec1d6eScindi #define AMD_NB_SCRUBADDR_LO_MASK 0xffffffc0 38220c794b3Sgavinm #define AMD_NB_SCRUBADDR_LO_SHIFT 6 3837aec1d6eScindi #define AMD_NB_SCRUBADDR_LO_SCRUBREDIREN 0x1 3847aec1d6eScindi #define AMD_NB_SCRUBADDR_HI_MASK 0x000000ff 3857aec1d6eScindi 3867aec1d6eScindi #define AMD_NB_SCRUBADDR_MKLO(addr) \ 38720c794b3Sgavinm (((addr) & AMD_NB_SCRUBADDR_LO_MASK) >> AMD_NB_SCRUBADDR_LO_SHIFT) 3887aec1d6eScindi 3897aec1d6eScindi #define AMD_NB_SCRUBADDR_MKHI(addr) \ 3907aec1d6eScindi (((addr) >> 32) & AMD_NB_SCRUBADDR_HI_MASK) 3917aec1d6eScindi 392*25f47677Sgavinm #define AMD_NB_MKSCRUBCTL(l3, dc, l2, dr) ( \ 393*25f47677Sgavinm (((l3) << AMD_NB_SCRUBCTL_L3_SHIFT) & AMD_NB_SCRUBCTL_L3_MASK) | \ 3947aec1d6eScindi (((dc) << AMD_NB_SCRUBCTL_DC_SHIFT) & AMD_NB_SCRUBCTL_DC_MASK) | \ 3957aec1d6eScindi (((l2) << AMD_NB_SCRUBCTL_L2_SHIFT) & AMD_NB_SCRUBCTL_L2_MASK) | \ 3967aec1d6eScindi (((dr) << AMD_NB_SCRUBCTL_DRAM_SHIFT) & AMD_NB_SCRUBCTL_DRAM_MASK)) 3977aec1d6eScindi 3987aec1d6eScindi #ifdef __cplusplus 3997aec1d6eScindi } 4007aec1d6eScindi #endif 4017aec1d6eScindi 4027aec1d6eScindi #endif /* _SYS_MCA_AMD_H */ 403