xref: /illumos-gate/usr/src/uts/intel/sys/mc_intel.h (revision eb00b1c8)
120c794b3Sgavinm /*
220c794b3Sgavinm  * CDDL HEADER START
320c794b3Sgavinm  *
420c794b3Sgavinm  * The contents of this file are subject to the terms of the
520c794b3Sgavinm  * Common Development and Distribution License (the "License").
620c794b3Sgavinm  * You may not use this file except in compliance with the License.
720c794b3Sgavinm  *
820c794b3Sgavinm  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
920c794b3Sgavinm  * or http://www.opensolaris.org/os/licensing.
1020c794b3Sgavinm  * See the License for the specific language governing permissions
1120c794b3Sgavinm  * and limitations under the License.
1220c794b3Sgavinm  *
1320c794b3Sgavinm  * When distributing Covered Code, include this CDDL HEADER in each
1420c794b3Sgavinm  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1520c794b3Sgavinm  * If applicable, add the following below this CDDL HEADER, with the
1620c794b3Sgavinm  * fields enclosed by brackets "[]" replaced with your own identifying
1720c794b3Sgavinm  * information: Portions Copyright [yyyy] [name of copyright owner]
1820c794b3Sgavinm  *
1920c794b3Sgavinm  * CDDL HEADER END
2020c794b3Sgavinm  */
2120c794b3Sgavinm 
2220c794b3Sgavinm /*
23ee9ef9e5SAdrian Frost  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
2420c794b3Sgavinm  * Use is subject to license terms.
25*eb00b1c8SRobert Mustacchi  * Copyright 2019 Joyent, Inc.
2620c794b3Sgavinm  */
2720c794b3Sgavinm 
2820c794b3Sgavinm #ifndef _MC_INTEL_H
2920c794b3Sgavinm #define	_MC_INTEL_H
3020c794b3Sgavinm 
3120c794b3Sgavinm #ifdef __cplusplus
3220c794b3Sgavinm extern "C" {
3320c794b3Sgavinm #endif
3420c794b3Sgavinm 
3520c794b3Sgavinm #define	FM_EREPORT_CPU_INTEL	"intel"
3620c794b3Sgavinm 
3720c794b3Sgavinm #define	MCINTEL_NVLIST_VERSTR	"mcintel-nvlist-version"
3820c794b3Sgavinm #define	MCINTEL_NVLIST_VERS0	0
39*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_VERS1	1
4020c794b3Sgavinm 
4120c794b3Sgavinm #define	MCINTEL_NVLIST_VERS	MCINTEL_NVLIST_VERS0
4220c794b3Sgavinm 
43e3d60c9bSAdrian Frost #define	MCINTEL_NVLIST_MEM	"memory-controller"
44e3d60c9bSAdrian Frost #define	MCINTEL_NVLIST_NMEM	"memory-controllers"
4520c794b3Sgavinm #define	MCINTEL_NVLIST_MC	"memory-channels"
4620c794b3Sgavinm #define	MCINTEL_NVLIST_DIMMS	"memory-dimms"
4720c794b3Sgavinm #define	MCINTEL_NVLIST_DIMMSZ	"memory-dimm-size"
48e3d60c9bSAdrian Frost #define	MCINTEL_NVLIST_NRANKS	"dimm-max-ranks"
49491f61a1SYanmin Sun #define	MCINTEL_NVLIST_NDIMMS	"dimm-max-dimms"
5020c794b3Sgavinm #define	MCINTEL_NVLIST_RANKS	"dimm-ranks"
5185738508SVuong Nguyen #define	MCINTEL_NVLIST_1ST_RANK	"dimm-start-rank"
52491f61a1SYanmin Sun #define	MCINTEL_NVLIST_DIMM_NUM	"dimm-number"
5320c794b3Sgavinm #define	MCINTEL_NVLIST_ROWS	"dimm-rows"
5420c794b3Sgavinm #define	MCINTEL_NVLIST_COL	"dimm-column"
5520c794b3Sgavinm #define	MCINTEL_NVLIST_BANK	"dimm-banks"
5620c794b3Sgavinm #define	MCINTEL_NVLIST_WIDTH	"dimm-width"
5720c794b3Sgavinm #define	MCINTEL_NVLIST_MID	"dimm-manufacture-id"
5820c794b3Sgavinm #define	MCINTEL_NVLIST_MLOC	"dimm-manufacture-location"
5920c794b3Sgavinm #define	MCINTEL_NVLIST_MWEEK	"dimm-manufacture-week"
6020c794b3Sgavinm #define	MCINTEL_NVLIST_MYEAR	"dimm-manufacture-year"
6120c794b3Sgavinm #define	MCINTEL_NVLIST_SERIALNO	"dimm-serial-number"
6220c794b3Sgavinm #define	MCINTEL_NVLIST_PARTNO	"dimm-part-number"
6320c794b3Sgavinm #define	MCINTEL_NVLIST_REV	"dimm-part-rev"
6420c794b3Sgavinm 
65*eb00b1c8SRobert Mustacchi /*
66*eb00b1c8SRobert Mustacchi  * Version 1 payload. Whereas the version 0 payload uses a flat name space, we
67*eb00b1c8SRobert Mustacchi  * instead opt to use a hierarchical name space. This means that we can know how
68*eb00b1c8SRobert Mustacchi  * many devices there are at any level, as each level has this. Effectively,
69*eb00b1c8SRobert Mustacchi  * this means that we have an nvlist structure, for a socket that looks like:
70*eb00b1c8SRobert Mustacchi  *
71*eb00b1c8SRobert Mustacchi  * socket
72*eb00b1c8SRobert Mustacchi  *	string	version
73*eb00b1c8SRobert Mustacchi  *	uint8_t num-memory-controllers
74*eb00b1c8SRobert Mustacchi  *	nvlist array memory-controller[]
75*eb00b1c8SRobert Mustacchi  *		uint8_t num-channels
76*eb00b1c8SRobert Mustacchi  *		boolean ecc
77*eb00b1c8SRobert Mustacchi  *		string page policy
78*eb00b1c8SRobert Mustacchi  *		string lockstep || independent
79*eb00b1c8SRobert Mustacchi  *		nvlist array channel[]
80*eb00b1c8SRobert Mustacchi  *			uint8_t dpc
81*eb00b1c8SRobert Mustacchi  *			nvlist array dimm[]
82*eb00b1c8SRobert Mustacchi  *				boolean_t present;
83*eb00b1c8SRobert Mustacchi  *				uint32_t ncolumns
84*eb00b1c8SRobert Mustacchi  *				uint32_t nrows
85*eb00b1c8SRobert Mustacchi  *				uint64_t density (in bytes)
86*eb00b1c8SRobert Mustacchi  *				uint32_t width
87*eb00b1c8SRobert Mustacchi  *				uint32_t ranks
88*eb00b1c8SRobert Mustacchi  *				uint32_t banks
89*eb00b1c8SRobert Mustacchi  *				boolean_t array ranks_disabled
90*eb00b1c8SRobert Mustacchi  *				boolean_t hdrl-enabled
91*eb00b1c8SRobert Mustacchi  *				boolean_t hdrl-parity
92*eb00b1c8SRobert Mustacchi  *				uint32_t 3dnumranks
93*eb00b1c8SRobert Mustacchi  */
94*eb00b1c8SRobert Mustacchi 
95*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_NMC		"num-memory-controllers"
96*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MCS		"memory-controllers"
97*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_NCHAN	"num-memory-channels"
98*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_CHANNELS	"memory-controller-channels"
99*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_ECC	"memory-controller-ecc"
100*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_POLICY	"memory-controller-page-policy"
101*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_POLICY_OPEN	"open-page"
102*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_POLICY_CLOSED	"closed-page"
103*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_CHAN_MODE	"memory-controller-channel-mode"
104*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_CHAN_MODE_LOCK	"lockstep"
105*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_MC_CHAN_MODE_INDEP	"independent"
106*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_CHAN_NDPC	"memory-channel-dimms-per-channel"
107*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_CHAN_DIMMS	"memory-channel-dimms"
108*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_PRESENT	"dimm-present"
109*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_SIZE	"dimm-size"
110*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_NCOLS	"dimm-num-columns"
111*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_NROWS	"dimm-num-rows"
112*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_DENSITY	"dimm-density"
113*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_WIDTH	"dimm-width"
114*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_RANKS	"dimm-ranks"
115*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_BANKS	"dimm-banks"
116*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_RDIS	"dimm-ranks-disabled"
117*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_HDRL	"dimm-hdrl-enabled"
118*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_HDRLP	"dimm-hdrl-parity-enabled"
119*eb00b1c8SRobert Mustacchi #define	MCINTEL_NVLIST_V1_DIMM_3DRANK	"dimm-3dranks"
120*eb00b1c8SRobert Mustacchi 
12120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_GLOBAL		"ferr_global"
12220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_GLOBAL		"nerr_global"
12320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FSB			"fsb"
12420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FSB		"ferr_fat_fsb"
12520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FSB		"nerr_fat_fsb"
12620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FSB		"ferr_nf_fsb"
12720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FSB		"nerr_nf_fsb"
12820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB			"nrecfsb"
12920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB_ADDR		"nrecfsb_addr"
13020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFSB			"recfsb"
13120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX			"pex"
13220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_FERR		"pex_fat_ferr"
13320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_NERR		"pex_fat_nerr"
13420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_FERR	"pex_nf_corr_ferr"
13520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_NERR	"pex_nf_corr_nerr"
13620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSEV		"uncerrsev"
13720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RPERRSTS		"rperrsts"
13820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RPERRSID		"rperrsid"
13920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSTS		"uncerrsts"
14020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_AERRCAPCTRL		"aerrcapctrl"
14120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CORERRSTS		"corerrsts"
14220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
14320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_INT		"ferr_fat_int"
14420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_INT		"ferr_nf_int"
14520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_INT		"nerr_fat_int"
14620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_INT		"nerr_nf_int"
14720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECINT			"nrecint"
14820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECINT			"recint"
14920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECSF			"nrecsf"
15020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECSF			"recsf"
15120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RANK			"rank"
15220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK			"bank"
15320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CAS			"cas"
15420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RAS			"ras"
15520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FBD		"ferr_fat_fbd"
15620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FBD		"nerr_fat_fbd"
15785738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_VALIDLOG		"validlog"
15820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMA		"nrecmema"
15920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMB		"nrecmemb"
16020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFGLOG		"nrecfglog"
16120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDA		"nrecfbda"
16220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDB		"nrecfbdb"
16320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDC		"nrecfbdc"
16420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDD		"nrecfbdd"
16520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDE		"nrecfbde"
1665de8e333Saf #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDF		"nrecfbdf"
16720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_SPCPC			"spcpc"
16820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_SPCPS			"spcps"
16920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT			"uerrcnt"
17020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT_LAST		"uerrcnt_last"
17185738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_BADRAM			"badram"
17220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BADRAMA			"badrama"
17320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BADRAMB			"badramb"
17420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BADCNT			"badcnt"
17520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MC			"mc"
17620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MCA			"mca"
17720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_TOLM			"tolm"
17820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MIR			"mir"
17920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MTR			"mtr"
18020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_DMIR			"dmir"
18120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FBD		"ferr_nf_fbd"
18220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FBD		"nerr_nf_fbd"
18385738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_MEM		"ferr_nf_mem"
18485738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_MEM		"nerr_nf_mem"
18520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECMEMA			"recmema"
18620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECMEMB			"recmemb"
18785738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_REDMEMA			"redmema"
18885738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_REDMEMB			"redmemb"
18920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFGLOG		"recfglog"
19020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDA			"recfbda"
19120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDB			"recfbdb"
19220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDC			"recfbdc"
19320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDD			"recfbdd"
19420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDE			"recfbde"
1955de8e333Saf #define	FM_EREPORT_PAYLOAD_NAME_RECFBDF			"recfbdf"
19620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT			"cerrcnt"
19720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST		"cerrcnt_last"
19885738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT		"cerrcnt_ext"
19985738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT_LAST	"cerrcnt_ext_last"
2005f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA		"cerrcnta"
2015f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB		"cerrcntb"
2025f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC		"cerrcntc"
2035f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD		"cerrcntd"
2045f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA_LAST		"cerrcnta_last"
2055f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB_LAST		"cerrcntb_last"
2065f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC_LAST		"cerrcntc_last"
2075f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD_LAST		"cerrcntd_last"
20820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PCISTS			"pcists"
20920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
21020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_ERROR_NO		"intel-error-list"
21120c794b3Sgavinm 
2125f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CTSTS			"ctsts"
2135f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_THRTSTS			"thrtsts"
2145f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_THR		"ferr_fat_thr"
2155f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_THR		"nerr_fat_thr"
2165f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_THR		"ferr_nf_thr"
2175f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_THR		"nerr_nf_thr"
2185f28a827Saf 
21920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_ADDR			"addr"
22020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM		"bank-number"
22120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_MISC		"bank-misc"
22220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_STAT		"bank-status"
22320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_OFFSET		"bank-offset"
22420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MC_TYPE			"mc-type"
22520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_CPUID			"cpuid"
22620c794b3Sgavinm 
22720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BQR				"Bus-queue-request"
22820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BQET				"Bus-queue-error-type"
22920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_FRC				"FRC-error"
23020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BERR				"BERR"
23120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_INT_BINT			"Internal-BINT"
23220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_EXT_BINT			"External-BINT"
23320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BUS_BINT			"Bus-BINT"
23420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TO_BINT			"Timeout-BINT"
23520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_HARD				"Hard-error"
23620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_IERR				"IERR"
23720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_AERR				"AERR"
23820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_UERR				"UERR"
23920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_CECC				"CECC"
24020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_UECC				"UECC"
24120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_ECC_SYND			"ECC-syndrome"
24220c794b3Sgavinm 
24320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_FSB_PARITY			"fsb-address-parity"
24420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_RESP_HF			"response-hard-fail"
24520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_RESP_PARITY			"response-parity"
24620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_PARITY			"bus-data-parity"
24720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
24820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_PAD_SM			"pad-state-machine"
24920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_PAD_SG			"pad-strobe-glitch"
25020c794b3Sgavinm 
25120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG				"tag-error"
25220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG_CLEAN			"clean"
25320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG_HIT			"hit"
25420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG_MISS			"miss"
25520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA				"data-error"
25620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_SINGLE			"single-bit"
25720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_DBL_CLEAN		"double-bit-clean"
25820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_DBL_MOD			"double-bit-modified"
25920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_L3				"l3-cache"
26020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
26120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_CACHE_NERRORS		"cache-error-count"
26220c794b3Sgavinm 
263e3d60c9bSAdrian Frost #define	FM_EREPORT_PAYLOAD_NAME_RESOURCE		"resource"
264e3d60c9bSAdrian Frost #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_THIS	"mem_cor_ecc_counter"
265e3d60c9bSAdrian Frost #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_LAST	"mem_cor_ecc_counter_last"
266e3d60c9bSAdrian Frost 
26720c794b3Sgavinm #define	INTEL_NB_5000P	0x25d88086
26820c794b3Sgavinm #define	INTEL_NB_5000V	0x25d48086
26920c794b3Sgavinm #define	INTEL_NB_5000X	0x25c08086
27020c794b3Sgavinm #define	INTEL_NB_5000Z	0x25d08086
27185738508SVuong Nguyen #define	INTEL_NB_5100	0x65c08086
2725f28a827Saf #define	INTEL_NB_5400	0x40008086
2735f28a827Saf #define	INTEL_NB_5400A	0x40018086
2745f28a827Saf #define	INTEL_NB_5400B	0x40038086
27520c794b3Sgavinm #define	INTEL_NB_7300	0x36008086
27620c794b3Sgavinm 
277e3d60c9bSAdrian Frost #define	INTEL_NHM	0x2c408086
278e3d60c9bSAdrian Frost #define	INTEL_QP_IO	0x34008086
279e3d60c9bSAdrian Frost #define	INTEL_QP_36D	0x34068086
280e3d60c9bSAdrian Frost #define	INTEL_QP_24D	0x34038086
281ee9ef9e5SAdrian Frost #define	INTEL_QP_WP	0x34058086
282ee9ef9e5SAdrian Frost #define	INTEL_QP_U1	0x34018086
283ee9ef9e5SAdrian Frost #define	INTEL_QP_U2	0x34028086
284ee9ef9e5SAdrian Frost #define	INTEL_QP_U3	0x34048086
285ee9ef9e5SAdrian Frost #define	INTEL_QP_U4	0x34078086
28635366b93SAdrian Frost #define	INTEL_QP_JF	0x37208086
28735366b93SAdrian Frost #define	INTEL_QP_JF0	0x37008086
28835366b93SAdrian Frost #define	INTEL_QP_JF1	0x37018086
28935366b93SAdrian Frost #define	INTEL_QP_JF2	0x37028086
29035366b93SAdrian Frost #define	INTEL_QP_JF3	0x37038086
29135366b93SAdrian Frost #define	INTEL_QP_JF4	0x37048086
29235366b93SAdrian Frost #define	INTEL_QP_JF5	0x37058086
29335366b93SAdrian Frost #define	INTEL_QP_JF6	0x37068086
29435366b93SAdrian Frost #define	INTEL_QP_JF7	0x37078086
29535366b93SAdrian Frost #define	INTEL_QP_JF8	0x37088086
29635366b93SAdrian Frost #define	INTEL_QP_JF9	0x37098086
29735366b93SAdrian Frost #define	INTEL_QP_JFa	0x370a8086
29835366b93SAdrian Frost #define	INTEL_QP_JFb	0x370b8086
29935366b93SAdrian Frost #define	INTEL_QP_JFc	0x370c8086
30035366b93SAdrian Frost #define	INTEL_QP_JFd	0x370d8086
30135366b93SAdrian Frost #define	INTEL_QP_JFe	0x370e8086
30235366b93SAdrian Frost #define	INTEL_QP_JFf	0x370f8086
303e3d60c9bSAdrian Frost 
304e3d60c9bSAdrian Frost /* Intel QuickPath Bus Interconnect Errors */
305e3d60c9bSAdrian Frost 
306e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_HEADER_PARITY		(1 << 16)
307e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_DATA_PARITY		(1 << 17)
308e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_RETRIES_EXCEEDED	(1 << 18)
309e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_POISON		(1 << 19)
310e3d60c9bSAdrian Frost 
311e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_UNSUPPORTED_MSG	(1 << 22)
312e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_UNSUPPORTED_CREDIT	(1 << 23)
313e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_FLIT_BUF_OVER		(1 << 24)
314e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_FAILED_RESPONSE	(1 << 25)
315e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_CLOCK_JITTER		(1 << 26)
316e3d60c9bSAdrian Frost 
317e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_CLASS		0x000000ff
318e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_RTID		0x00003f00
319e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_RHNID		0x00070000
320e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_IIB		0x01000000
321e3d60c9bSAdrian Frost 
322e3d60c9bSAdrian Frost /* Intel QuickPath Memory Errors */
323e3d60c9bSAdrian Frost 
324e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY		0x0080
325e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_MASK		0xff80
326e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_TRANSACTION	0x0070
327e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_READ		0x0010
328e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_WRITE	0x0020
329e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_CMD		0x0030
330e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_CHANNEL	0x000f
331e3d60c9bSAdrian Frost 
332e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ECC_READ	(1 << 16)
333e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ECC_SCRUB	(1 << 17)
334e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_PARITY	(1 << 18)
335e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_REDUNDANT_MEM	(1 << 19)
336e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_SPARE_MEM	(1 << 20)
337e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ILLEGAL_ADDR	(1 << 21)
338e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_BAD_ID	(1 << 22)
339e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ADDR_PARITY	(1 << 23)
340e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_BYTE_PARITY	(1 << 24)
341e3d60c9bSAdrian Frost 
342e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_RTID		0x00000000000000ffULL
343e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_DIMM		0x0000000000030000ULL
344e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_DIMM_SHIFT	16
345e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_CHANNEL		0x00000000000c0000ULL
346e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_CHANNEL_SHIFT	18
347e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_SYNDROME	0xffffffff00000000ULL
348e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_SYNDROME_SHIFT	32
349e3d60c9bSAdrian Frost 
350f899e573SVuong Nguyen #define	OFFSET_ROW_BANK_COL	0x8000000000000000ULL
351f899e573SVuong Nguyen #define	OFFSET_RANK_SHIFT	52
352f899e573SVuong Nguyen #define	OFFSET_RAS_SHIFT	32
353f899e573SVuong Nguyen #define	OFFSET_BANK_SHIFT	24
354f899e573SVuong Nguyen #define	TCODE_OFFSET(rank, bank, ras, cas) (OFFSET_ROW_BANK_COL | \
355f899e573SVuong Nguyen 	((uint64_t)(rank) << OFFSET_RANK_SHIFT) | \
356f899e573SVuong Nguyen 	((uint64_t)(ras) << OFFSET_RAS_SHIFT) | \
357f899e573SVuong Nguyen 	((uint64_t)(bank) << OFFSET_BANK_SHIFT) | (cas))
358f899e573SVuong Nguyen 
359f899e573SVuong Nguyen #define	MAX_CAS_MASK	0xFFFFFF
360f899e573SVuong Nguyen #define	MAX_BANK_MASK	0xFF
361f899e573SVuong Nguyen #define	MAX_RAS_MASK	0xFFFFF
362f899e573SVuong Nguyen #define	MAX_RANK_MASK	0x7FF
363f899e573SVuong Nguyen #define	TCODE_OFFSET_RANK(tcode) \
364f899e573SVuong Nguyen 	(((tcode) >> OFFSET_RANK_SHIFT) & MAX_RANK_MASK)
365f899e573SVuong Nguyen #define	TCODE_OFFSET_RAS(tcode) (((tcode) >> OFFSET_RAS_SHIFT) & MAX_RAS_MASK)
366f899e573SVuong Nguyen #define	TCODE_OFFSET_BANK(tcode) \
367f899e573SVuong Nguyen 	(((tcode) >> OFFSET_BANK_SHIFT) & MAX_BANK_MASK)
368f899e573SVuong Nguyen #define	TCODE_OFFSET_CAS(tcode) ((tcode) & MAX_CAS_MASK)
369f899e573SVuong Nguyen 
37020c794b3Sgavinm #ifdef __cplusplus
37120c794b3Sgavinm }
37220c794b3Sgavinm #endif
37320c794b3Sgavinm 
37420c794b3Sgavinm #endif /* _MC_INTEL_H */
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