17aec1d6eScindi /* 27aec1d6eScindi * CDDL HEADER START 37aec1d6eScindi * 47aec1d6eScindi * The contents of this file are subject to the terms of the 58a40a695Sgavinm * Common Development and Distribution License (the "License"). 68a40a695Sgavinm * You may not use this file except in compliance with the License. 77aec1d6eScindi * 87aec1d6eScindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97aec1d6eScindi * or http://www.opensolaris.org/os/licensing. 107aec1d6eScindi * See the License for the specific language governing permissions 117aec1d6eScindi * and limitations under the License. 127aec1d6eScindi * 137aec1d6eScindi * When distributing Covered Code, include this CDDL HEADER in each 147aec1d6eScindi * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157aec1d6eScindi * If applicable, add the following below this CDDL HEADER, with the 167aec1d6eScindi * fields enclosed by brackets "[]" replaced with your own identifying 177aec1d6eScindi * information: Portions Copyright [yyyy] [name of copyright owner] 187aec1d6eScindi * 197aec1d6eScindi * CDDL HEADER END 207aec1d6eScindi * 2120c794b3Sgavinm * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 227aec1d6eScindi * Use is subject to license terms. 237aec1d6eScindi */ 24eb00b1c8SRobert Mustacchi /* 25eb00b1c8SRobert Mustacchi * Copyright 2019 Joyent, Inc. 26*71815ce7SRobert Mustacchi * Copyright 2022 Oxide Computer Company 27eb00b1c8SRobert Mustacchi */ 287aec1d6eScindi 297aec1d6eScindi #ifndef _SYS_MC_H 307aec1d6eScindi #define _SYS_MC_H 317aec1d6eScindi 327aec1d6eScindi /* 337aec1d6eScindi * Public interfaces exposed by the memory controller driver 347aec1d6eScindi */ 357aec1d6eScindi 367aec1d6eScindi #include <sys/cpuvar.h> 377aec1d6eScindi 387aec1d6eScindi #ifdef __cplusplus 397aec1d6eScindi extern "C" { 407aec1d6eScindi #endif 417aec1d6eScindi 427aec1d6eScindi #define MC_UNUM_NAMLEN 192 438a40a695Sgavinm #define MC_UNUM_NDIMM 2 447aec1d6eScindi 457aec1d6eScindi typedef struct mc_unum { 4620c794b3Sgavinm int unum_board; /* system board */ 4720c794b3Sgavinm int unum_chip; /* chip/socket */ 4820c794b3Sgavinm int unum_mc; /* memory-controller or branch */ 4920c794b3Sgavinm int unum_chan; /* DRAM channel */ 5020c794b3Sgavinm int unum_cs; /* chip-select */ 5120c794b3Sgavinm int unum_rank; /* rank */ 5220c794b3Sgavinm uint64_t unum_offset; /* row, column, bank-select etc */ 537aec1d6eScindi int unum_dimms[MC_UNUM_NDIMM]; 547aec1d6eScindi } mc_unum_t; 557aec1d6eScindi 568a40a695Sgavinm /* 578a40a695Sgavinm * Invalid marker used in some numeric properties 588a40a695Sgavinm */ 598a40a695Sgavinm #define MC_INVALNUM ((uint32_t)-1) 608a40a695Sgavinm 618a40a695Sgavinm /* 628a40a695Sgavinm * /dev/mc/mc* ioctl cmds 638a40a695Sgavinm */ 647aec1d6eScindi #define MC_IOC (0x4d43 << 16) 657aec1d6eScindi #define MC_IOC_SNAPSHOT_INFO (MC_IOC | 1) 667aec1d6eScindi #define MC_IOC_SNAPSHOT (MC_IOC | 2) 678a40a695Sgavinm #define MC_IOC_ONLINESPARE_EN (MC_IOC | 4) 68eb00b1c8SRobert Mustacchi #define MC_IOC_DECODE_PA (MC_IOC | 5) 69eb00b1c8SRobert Mustacchi #define MC_IOC_DECODE_SNAPSHOT_INFO (MC_IOC | 6) 70eb00b1c8SRobert Mustacchi #define MC_IOC_DECODE_SNAPSHOT (MC_IOC | 7) 717aec1d6eScindi 727aec1d6eScindi /* 737aec1d6eScindi * Prior to requesting a copy of the snapshot, consumers are advised to request 747aec1d6eScindi * information regarding the snapshot. An mc_snapshot_info_t will be returned, 757aec1d6eScindi * containing the snapshot size as well as the snapshot generation number. Note 767aec1d6eScindi * that, due to the potentially dynamic nature of the system, the snapshot may 777aec1d6eScindi * change at any time. As such, the information in the mc_snapshot_info_t may 787aec1d6eScindi * be out of date by the time it is used. The generation number is used to 797aec1d6eScindi * track snapshot changes. That is, the generation number will be updated each 807aec1d6eScindi * time the source data for the snapshot is updated. The consumer should not 817aec1d6eScindi * attach any meaning to the magnitude of a generation number change, and pay 827aec1d6eScindi * attention only to the fact that the number has changed. 837aec1d6eScindi */ 847aec1d6eScindi typedef struct mc_snapshot_info { 857aec1d6eScindi uint32_t mcs_size; /* snapshot size */ 867aec1d6eScindi uint_t mcs_gen; /* snapshot generation number */ 877aec1d6eScindi } mc_snapshot_info_t; 887aec1d6eScindi 89eb00b1c8SRobert Mustacchi /* 90eb00b1c8SRobert Mustacchi * Data used to simulate encoding or decoding of a physical / DIMM address. 91*71815ce7SRobert Mustacchi * These are used in different ways between AMD and Intel, so this is a bit of a 92*71815ce7SRobert Mustacchi * smorgasbord. Details about each field are listed below. 93eb00b1c8SRobert Mustacchi */ 94eb00b1c8SRobert Mustacchi typedef struct mc_encode_ioc { 95*71815ce7SRobert Mustacchi /* 96*71815ce7SRobert Mustacchi * The first three values here are different addresses. We have a 97*71815ce7SRobert Mustacchi * physical / system address. A DRAM-channel relative address, and 98*71815ce7SRobert Mustacchi * finally a rank-relative address. Where a platform does not support 99*71815ce7SRobert Mustacchi * one of these, UINT64_MAX is used. 100*71815ce7SRobert Mustacchi */ 101eb00b1c8SRobert Mustacchi uint64_t mcei_pa; 102*71815ce7SRobert Mustacchi uint64_t mcei_chan_addr; 103*71815ce7SRobert Mustacchi uint64_t mcei_rank_addr; 104*71815ce7SRobert Mustacchi /* 105*71815ce7SRobert Mustacchi * These next two provide a way for the memory controller software 106*71815ce7SRobert Mustacchi * driver to provide additional information. The mcei_err generally 107*71815ce7SRobert Mustacchi * corresponds to an enum that the driver has and the errdata is 108*71815ce7SRobert Mustacchi * error-specific data that can be useful. 109*71815ce7SRobert Mustacchi */ 110eb00b1c8SRobert Mustacchi uint64_t mcei_errdata; 111eb00b1c8SRobert Mustacchi uint32_t mcei_err; 112*71815ce7SRobert Mustacchi /* 113*71815ce7SRobert Mustacchi * This next set is used to identify information about where to find a 114*71815ce7SRobert Mustacchi * DIMM in question. The board and chip are used to uniquely identify a 115*71815ce7SRobert Mustacchi * socket. Generally on x86, there is only one board, so it would be 116*71815ce7SRobert Mustacchi * zero. The chip should correspond to the socket ID. The die refers to 117*71815ce7SRobert Mustacchi * a particular internal die if on a chiplet or MCP. The memory 118*71815ce7SRobert Mustacchi * controller and channel refer to a unique instance of both within a 119*71815ce7SRobert Mustacchi * given die. On platforms where the memory controller and channel are 120*71815ce7SRobert Mustacchi * 1:1 (that is each memory controller has only a single channel or 121*71815ce7SRobert Mustacchi * doesn't have a specific distinction between the two), set chan to 0 122*71815ce7SRobert Mustacchi * and set the mc to the logical channel value. The DIMM is a relative 123*71815ce7SRobert Mustacchi * DIMM in the channel, meaning it's usually going to be 0, 1, or 2. 124*71815ce7SRobert Mustacchi */ 125eb00b1c8SRobert Mustacchi uint32_t mcei_board; 126eb00b1c8SRobert Mustacchi uint32_t mcei_chip; 127*71815ce7SRobert Mustacchi uint32_t mcei_die; 128eb00b1c8SRobert Mustacchi uint32_t mcei_mc; 129eb00b1c8SRobert Mustacchi uint32_t mcei_chan; 130eb00b1c8SRobert Mustacchi uint32_t mcei_dimm; 131*71815ce7SRobert Mustacchi /* 132*71815ce7SRobert Mustacchi * These values all refer to information on the DIMM itself and identify 133*71815ce7SRobert Mustacchi * how to find the address. mcei_rank is meant to be a logical rank; 134*71815ce7SRobert Mustacchi * however, some systems phrase things that way while others phrase 135*71815ce7SRobert Mustacchi * things in terms of a chip select and rank multiplication. For unknown 136*71815ce7SRobert Mustacchi * entries use UINT8_MAX. 137*71815ce7SRobert Mustacchi */ 138eb00b1c8SRobert Mustacchi uint32_t mcei_row; 139eb00b1c8SRobert Mustacchi uint32_t mcei_column; 140*71815ce7SRobert Mustacchi uint8_t mcei_rank; 141*71815ce7SRobert Mustacchi uint8_t mcei_cs; 142*71815ce7SRobert Mustacchi uint8_t mcei_rm; 143*71815ce7SRobert Mustacchi uint8_t mcei_bank; 144*71815ce7SRobert Mustacchi uint8_t mcei_bank_group; 145*71815ce7SRobert Mustacchi uint8_t mcei_subchan; 146*71815ce7SRobert Mustacchi uint8_t mcei_pad[6]; 147eb00b1c8SRobert Mustacchi } mc_encode_ioc_t; 148eb00b1c8SRobert Mustacchi 1497aec1d6eScindi #ifdef __cplusplus 1507aec1d6eScindi } 1517aec1d6eScindi #endif 1527aec1d6eScindi 1537aec1d6eScindi #endif /* _SYS_MC_H */ 154