17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate * CDDL HEADER START
37c478bd9Sstevel@tonic-gate *
47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5346af85bScwb * Common Development and Distribution License (the "License").
6346af85bScwb * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate *
87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate * and limitations under the License.
127c478bd9Sstevel@tonic-gate *
137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate *
197c478bd9Sstevel@tonic-gate * CDDL HEADER END
207c478bd9Sstevel@tonic-gate */
217c478bd9Sstevel@tonic-gate /*
22e850fb01SKuriakose Kuruvilla * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
237c478bd9Sstevel@tonic-gate * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate */
257c478bd9Sstevel@tonic-gate
26c7a079a8SJonathan Haslam /*
27c7a079a8SJonathan Haslam * This file contains preset event names from the Performance Application
28c7a079a8SJonathan Haslam * Programming Interface v3.5 which included the following notice:
29c7a079a8SJonathan Haslam *
30c7a079a8SJonathan Haslam * Copyright (c) 2005,6
31c7a079a8SJonathan Haslam * Innovative Computing Labs
32c7a079a8SJonathan Haslam * Computer Science Department,
33c7a079a8SJonathan Haslam * University of Tennessee,
34c7a079a8SJonathan Haslam * Knoxville, TN.
35c7a079a8SJonathan Haslam * All Rights Reserved.
36c7a079a8SJonathan Haslam *
37c7a079a8SJonathan Haslam *
38c7a079a8SJonathan Haslam * Redistribution and use in source and binary forms, with or without
39c7a079a8SJonathan Haslam * modification, are permitted provided that the following conditions are met:
40c7a079a8SJonathan Haslam *
41c7a079a8SJonathan Haslam * * Redistributions of source code must retain the above copyright notice,
42c7a079a8SJonathan Haslam * this list of conditions and the following disclaimer.
43c7a079a8SJonathan Haslam * * Redistributions in binary form must reproduce the above copyright
44c7a079a8SJonathan Haslam * notice, this list of conditions and the following disclaimer in the
45c7a079a8SJonathan Haslam * documentation and/or other materials provided with the distribution.
46c7a079a8SJonathan Haslam * * Neither the name of the University of Tennessee nor the names of its
47c7a079a8SJonathan Haslam * contributors may be used to endorse or promote products derived from
48c7a079a8SJonathan Haslam * this software without specific prior written permission.
49c7a079a8SJonathan Haslam *
50c7a079a8SJonathan Haslam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51c7a079a8SJonathan Haslam * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52c7a079a8SJonathan Haslam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53c7a079a8SJonathan Haslam * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54c7a079a8SJonathan Haslam * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55c7a079a8SJonathan Haslam * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56c7a079a8SJonathan Haslam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57c7a079a8SJonathan Haslam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58c7a079a8SJonathan Haslam * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59c7a079a8SJonathan Haslam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60c7a079a8SJonathan Haslam * POSSIBILITY OF SUCH DAMAGE.
61c7a079a8SJonathan Haslam *
62c7a079a8SJonathan Haslam *
63c7a079a8SJonathan Haslam * This open source software license conforms to the BSD License template.
64c7a079a8SJonathan Haslam */
657c478bd9Sstevel@tonic-gate
66e850fb01SKuriakose Kuruvilla /*
67e850fb01SKuriakose Kuruvilla * Portions Copyright 2009 Advanced Micro Devices, Inc.
68d0e58ef5SRobert Mustacchi * Copyright 2019 Joyent, Inc.
69*cf618897SRobert Mustacchi * Copyright 2024 Oxide Computer Company
70e850fb01SKuriakose Kuruvilla */
71e850fb01SKuriakose Kuruvilla
727c478bd9Sstevel@tonic-gate /*
73*cf618897SRobert Mustacchi * Performance Counter Back-End for AMD Opteron, AMD Athlon 64, and Zen
74*cf618897SRobert Mustacchi * era processors.
757c478bd9Sstevel@tonic-gate */
767c478bd9Sstevel@tonic-gate
777c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h>
787c478bd9Sstevel@tonic-gate #include <sys/param.h>
797c478bd9Sstevel@tonic-gate #include <sys/systm.h>
807c478bd9Sstevel@tonic-gate #include <sys/cpc_pcbe.h>
817c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
827c478bd9Sstevel@tonic-gate #include <sys/sdt.h>
837c478bd9Sstevel@tonic-gate #include <sys/modctl.h>
847c478bd9Sstevel@tonic-gate #include <sys/errno.h>
857c478bd9Sstevel@tonic-gate #include <sys/debug.h>
867c478bd9Sstevel@tonic-gate #include <sys/archsystm.h>
877c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h>
887c478bd9Sstevel@tonic-gate #include <sys/privregs.h>
895d3a5ad8Srab #include <sys/ddi.h>
905d3a5ad8Srab #include <sys/sunddi.h>
917c478bd9Sstevel@tonic-gate
92d0e58ef5SRobert Mustacchi #include "opteron_pcbe_table.h"
93d0e58ef5SRobert Mustacchi #include <opteron_pcbe_cpcgen.h>
94d0e58ef5SRobert Mustacchi
957c478bd9Sstevel@tonic-gate static int opt_pcbe_init(void);
967c478bd9Sstevel@tonic-gate static uint_t opt_pcbe_ncounters(void);
977c478bd9Sstevel@tonic-gate static const char *opt_pcbe_impl_name(void);
987c478bd9Sstevel@tonic-gate static const char *opt_pcbe_cpuref(void);
997c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_events(uint_t picnum);
1007c478bd9Sstevel@tonic-gate static char *opt_pcbe_list_attrs(void);
1017c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_event_coverage(char *event);
1027c478bd9Sstevel@tonic-gate static uint64_t opt_pcbe_overflow_bitmap(void);
1037c478bd9Sstevel@tonic-gate static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset,
1047c478bd9Sstevel@tonic-gate uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data,
1057c478bd9Sstevel@tonic-gate void *token);
1067c478bd9Sstevel@tonic-gate static void opt_pcbe_program(void *token);
1077c478bd9Sstevel@tonic-gate static void opt_pcbe_allstop(void);
1087c478bd9Sstevel@tonic-gate static void opt_pcbe_sample(void *token);
1097c478bd9Sstevel@tonic-gate static void opt_pcbe_free(void *config);
1107c478bd9Sstevel@tonic-gate
1117c478bd9Sstevel@tonic-gate static pcbe_ops_t opt_pcbe_ops = {
1127c478bd9Sstevel@tonic-gate PCBE_VER_1,
1137c478bd9Sstevel@tonic-gate CPC_CAP_OVERFLOW_INTERRUPT,
1147c478bd9Sstevel@tonic-gate opt_pcbe_ncounters,
1157c478bd9Sstevel@tonic-gate opt_pcbe_impl_name,
1167c478bd9Sstevel@tonic-gate opt_pcbe_cpuref,
1177c478bd9Sstevel@tonic-gate opt_pcbe_list_events,
1187c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs,
1197c478bd9Sstevel@tonic-gate opt_pcbe_event_coverage,
1207c478bd9Sstevel@tonic-gate opt_pcbe_overflow_bitmap,
1217c478bd9Sstevel@tonic-gate opt_pcbe_configure,
1227c478bd9Sstevel@tonic-gate opt_pcbe_program,
1237c478bd9Sstevel@tonic-gate opt_pcbe_allstop,
1247c478bd9Sstevel@tonic-gate opt_pcbe_sample,
1257c478bd9Sstevel@tonic-gate opt_pcbe_free
1267c478bd9Sstevel@tonic-gate };
1277c478bd9Sstevel@tonic-gate
128d0e58ef5SRobert Mustacchi /*
129d0e58ef5SRobert Mustacchi * Base MSR addresses for the PerfEvtSel registers and the counters themselves.
130d0e58ef5SRobert Mustacchi * Add counter number to base address to get corresponding MSR address.
131d0e58ef5SRobert Mustacchi */
132d0e58ef5SRobert Mustacchi #define PES_BASE_ADDR 0xC0010000
133d0e58ef5SRobert Mustacchi #define PIC_BASE_ADDR 0xC0010004
134d0e58ef5SRobert Mustacchi
135d0e58ef5SRobert Mustacchi /*
136d0e58ef5SRobert Mustacchi * Base MSR addresses for the PerfEvtSel registers and counters. The counter and
137d0e58ef5SRobert Mustacchi * event select registers are interleaved, so one needs to multiply the counter
138d0e58ef5SRobert Mustacchi * number by two to determine what they should be set to.
139d0e58ef5SRobert Mustacchi */
140d0e58ef5SRobert Mustacchi #define PES_EXT_BASE_ADDR 0xC0010200
141d0e58ef5SRobert Mustacchi #define PIC_EXT_BASE_ADDR 0xC0010201
142d0e58ef5SRobert Mustacchi
143d0e58ef5SRobert Mustacchi /*
144d0e58ef5SRobert Mustacchi * The number of counters present depends on which CPU features are present.
145d0e58ef5SRobert Mustacchi */
146d0e58ef5SRobert Mustacchi #define OPT_PCBE_DEF_NCOUNTERS 4
147d0e58ef5SRobert Mustacchi #define OPT_PCBE_EXT_NCOUNTERS 6
148d0e58ef5SRobert Mustacchi
1497c478bd9Sstevel@tonic-gate /*
1507c478bd9Sstevel@tonic-gate * Define offsets and masks for the fields in the Performance
1517c478bd9Sstevel@tonic-gate * Event-Select (PES) registers.
1527c478bd9Sstevel@tonic-gate */
15331725658Sksadhukh #define OPT_PES_HOST_SHIFT 41
15431725658Sksadhukh #define OPT_PES_GUEST_SHIFT 40
155d0e58ef5SRobert Mustacchi #define OPT_PES_EVSELHI_SHIFT 32
1567c478bd9Sstevel@tonic-gate #define OPT_PES_CMASK_SHIFT 24
1577c478bd9Sstevel@tonic-gate #define OPT_PES_CMASK_MASK 0xFF
1587c478bd9Sstevel@tonic-gate #define OPT_PES_INV_SHIFT 23
1597c478bd9Sstevel@tonic-gate #define OPT_PES_ENABLE_SHIFT 22
1607c478bd9Sstevel@tonic-gate #define OPT_PES_INT_SHIFT 20
1617c478bd9Sstevel@tonic-gate #define OPT_PES_PC_SHIFT 19
1627c478bd9Sstevel@tonic-gate #define OPT_PES_EDGE_SHIFT 18
1637c478bd9Sstevel@tonic-gate #define OPT_PES_OS_SHIFT 17
1647c478bd9Sstevel@tonic-gate #define OPT_PES_USR_SHIFT 16
1657c478bd9Sstevel@tonic-gate #define OPT_PES_UMASK_SHIFT 8
1667c478bd9Sstevel@tonic-gate #define OPT_PES_UMASK_MASK 0xFF
1677c478bd9Sstevel@tonic-gate
16831725658Sksadhukh #define OPT_PES_INV (1ULL << OPT_PES_INV_SHIFT)
16931725658Sksadhukh #define OPT_PES_ENABLE (1ULL << OPT_PES_ENABLE_SHIFT)
17031725658Sksadhukh #define OPT_PES_INT (1ULL << OPT_PES_INT_SHIFT)
17131725658Sksadhukh #define OPT_PES_PC (1ULL << OPT_PES_PC_SHIFT)
17231725658Sksadhukh #define OPT_PES_EDGE (1ULL << OPT_PES_EDGE_SHIFT)
17331725658Sksadhukh #define OPT_PES_OS (1ULL << OPT_PES_OS_SHIFT)
17431725658Sksadhukh #define OPT_PES_USR (1ULL << OPT_PES_USR_SHIFT)
17531725658Sksadhukh #define OPT_PES_HOST (1ULL << OPT_PES_HOST_SHIFT)
17631725658Sksadhukh #define OPT_PES_GUEST (1ULL << OPT_PES_GUEST_SHIFT)
1777c478bd9Sstevel@tonic-gate
1787c478bd9Sstevel@tonic-gate typedef struct _opt_pcbe_config {
1797c478bd9Sstevel@tonic-gate uint8_t opt_picno; /* Counter number: 0, 1, 2, or 3 */
1807c478bd9Sstevel@tonic-gate uint64_t opt_evsel; /* Event Selection register */
1817c478bd9Sstevel@tonic-gate uint64_t opt_rawpic; /* Raw counter value */
1827c478bd9Sstevel@tonic-gate } opt_pcbe_config_t;
1837c478bd9Sstevel@tonic-gate
184d0e58ef5SRobert Mustacchi opt_pcbe_config_t nullcfgs[OPT_PCBE_EXT_NCOUNTERS] = {
1857c478bd9Sstevel@tonic-gate { 0, 0, 0 },
1867c478bd9Sstevel@tonic-gate { 1, 0, 0 },
1877c478bd9Sstevel@tonic-gate { 2, 0, 0 },
188d0e58ef5SRobert Mustacchi { 3, 0, 0 },
189d0e58ef5SRobert Mustacchi { 4, 0, 0 },
190d0e58ef5SRobert Mustacchi { 5, 0, 0 },
1917c478bd9Sstevel@tonic-gate };
1927c478bd9Sstevel@tonic-gate
193d0e58ef5SRobert Mustacchi typedef uint64_t (*opt_pcbe_addr_f)(uint_t);
1947c478bd9Sstevel@tonic-gate
195d0e58ef5SRobert Mustacchi typedef struct opt_pcbe_data {
196d0e58ef5SRobert Mustacchi uint_t opd_ncounters;
197d0e58ef5SRobert Mustacchi uint_t opd_cmask;
198d0e58ef5SRobert Mustacchi opt_pcbe_addr_f opd_pesf;
199d0e58ef5SRobert Mustacchi opt_pcbe_addr_f opd_picf;
200d0e58ef5SRobert Mustacchi } opt_pcbe_data_t;
201c7a079a8SJonathan Haslam
202d0e58ef5SRobert Mustacchi opt_pcbe_data_t opd;
2037c478bd9Sstevel@tonic-gate
2047c478bd9Sstevel@tonic-gate #define MASK48 0xFFFFFFFFFFFF
2057c478bd9Sstevel@tonic-gate
206e850fb01SKuriakose Kuruvilla #define EV_END {NULL, 0}
207c7a079a8SJonathan Haslam #define GEN_EV_END {NULL, NULL, 0 }
2087c478bd9Sstevel@tonic-gate
209d0e58ef5SRobert Mustacchi /*
210d0e58ef5SRobert Mustacchi * The following Macros are used to define tables of events that are used by
211d0e58ef5SRobert Mustacchi * various families and some generic classes of events.
212d0e58ef5SRobert Mustacchi *
213d0e58ef5SRobert Mustacchi * When programming a performance counter there are two different values that we
214d0e58ef5SRobert Mustacchi * need to set:
215d0e58ef5SRobert Mustacchi *
216d0e58ef5SRobert Mustacchi * o Event - Determines the general class of event that is being used.
217d0e58ef5SRobert Mustacchi * o Unit - A further breakdown that gives more specific value.
218d0e58ef5SRobert Mustacchi *
219d0e58ef5SRobert Mustacchi * Prior to the introduction of family 17h support, all family specific events
220d0e58ef5SRobert Mustacchi * were programmed based on their event. The generic events, which tried to
221d0e58ef5SRobert Mustacchi * provide PAPI mappings to events specified an additional unit mask.
222d0e58ef5SRobert Mustacchi *
223d0e58ef5SRobert Mustacchi * Starting with Family 17h, CPU performance counters default to using both the
224d0e58ef5SRobert Mustacchi * unit mask and the event select. Generic events are always aliases to a
225d0e58ef5SRobert Mustacchi * specific event/unit pair, hence why the units for them are always zero. In
226d0e58ef5SRobert Mustacchi * addition, the naming of events in family 17h has been changed to reflect
227d0e58ef5SRobert Mustacchi * AMD's guide. While this is a departure from what people are used to, it is
228d0e58ef5SRobert Mustacchi * believed that matching the more detailed literature that folks are told to
229d0e58ef5SRobert Mustacchi * reference is more valuable.
230d0e58ef5SRobert Mustacchi */
231d0e58ef5SRobert Mustacchi
232e850fb01SKuriakose Kuruvilla #define AMD_cmn_events \
233e850fb01SKuriakose Kuruvilla { "FP_dispatched_fpu_ops", 0x0 }, \
234e850fb01SKuriakose Kuruvilla { "FP_cycles_no_fpu_ops_retired", 0x1 }, \
235e850fb01SKuriakose Kuruvilla { "FP_dispatched_fpu_ops_ff", 0x2 }, \
236e850fb01SKuriakose Kuruvilla { "LS_seg_reg_load", 0x20 }, \
237e850fb01SKuriakose Kuruvilla { "LS_uarch_resync_self_modify", 0x21 }, \
238e850fb01SKuriakose Kuruvilla { "LS_uarch_resync_snoop", 0x22 }, \
239e850fb01SKuriakose Kuruvilla { "LS_buffer_2_full", 0x23 }, \
240e850fb01SKuriakose Kuruvilla { "LS_locked_operation", 0x24 }, \
241e850fb01SKuriakose Kuruvilla { "LS_retired_cflush", 0x26 }, \
242e850fb01SKuriakose Kuruvilla { "LS_retired_cpuid", 0x27 }, \
243e850fb01SKuriakose Kuruvilla { "DC_access", 0x40 }, \
244e850fb01SKuriakose Kuruvilla { "DC_miss", 0x41 }, \
245e850fb01SKuriakose Kuruvilla { "DC_refill_from_L2", 0x42 }, \
246e850fb01SKuriakose Kuruvilla { "DC_refill_from_system", 0x43 }, \
247e850fb01SKuriakose Kuruvilla { "DC_copyback", 0x44 }, \
248e850fb01SKuriakose Kuruvilla { "DC_dtlb_L1_miss_L2_hit", 0x45 }, \
249e850fb01SKuriakose Kuruvilla { "DC_dtlb_L1_miss_L2_miss", 0x46 }, \
250e850fb01SKuriakose Kuruvilla { "DC_misaligned_data_ref", 0x47 }, \
251e850fb01SKuriakose Kuruvilla { "DC_uarch_late_cancel_access", 0x48 }, \
252e850fb01SKuriakose Kuruvilla { "DC_uarch_early_cancel_access", 0x49 }, \
253e850fb01SKuriakose Kuruvilla { "DC_1bit_ecc_error_found", 0x4A }, \
254e850fb01SKuriakose Kuruvilla { "DC_dispatched_prefetch_instr", 0x4B }, \
255e850fb01SKuriakose Kuruvilla { "DC_dcache_accesses_by_locks", 0x4C }, \
256e850fb01SKuriakose Kuruvilla { "BU_memory_requests", 0x65 }, \
257e850fb01SKuriakose Kuruvilla { "BU_data_prefetch", 0x67 }, \
258e850fb01SKuriakose Kuruvilla { "BU_system_read_responses", 0x6C }, \
259e850fb01SKuriakose Kuruvilla { "BU_cpu_clk_unhalted", 0x76 }, \
260e850fb01SKuriakose Kuruvilla { "BU_internal_L2_req", 0x7D }, \
261e850fb01SKuriakose Kuruvilla { "BU_fill_req_missed_L2", 0x7E }, \
262e850fb01SKuriakose Kuruvilla { "BU_fill_into_L2", 0x7F }, \
263e850fb01SKuriakose Kuruvilla { "IC_fetch", 0x80 }, \
264e850fb01SKuriakose Kuruvilla { "IC_miss", 0x81 }, \
265e850fb01SKuriakose Kuruvilla { "IC_refill_from_L2", 0x82 }, \
266e850fb01SKuriakose Kuruvilla { "IC_refill_from_system", 0x83 }, \
267e850fb01SKuriakose Kuruvilla { "IC_itlb_L1_miss_L2_hit", 0x84 }, \
268e850fb01SKuriakose Kuruvilla { "IC_itlb_L1_miss_L2_miss", 0x85 }, \
269e850fb01SKuriakose Kuruvilla { "IC_uarch_resync_snoop", 0x86 }, \
270e850fb01SKuriakose Kuruvilla { "IC_instr_fetch_stall", 0x87 }, \
271e850fb01SKuriakose Kuruvilla { "IC_return_stack_hit", 0x88 }, \
272e850fb01SKuriakose Kuruvilla { "IC_return_stack_overflow", 0x89 }, \
273e850fb01SKuriakose Kuruvilla { "FR_retired_x86_instr_w_excp_intr", 0xC0 }, \
274e850fb01SKuriakose Kuruvilla { "FR_retired_uops", 0xC1 }, \
275e850fb01SKuriakose Kuruvilla { "FR_retired_branches_w_excp_intr", 0xC2 }, \
276e850fb01SKuriakose Kuruvilla { "FR_retired_branches_mispred", 0xC3 }, \
277e850fb01SKuriakose Kuruvilla { "FR_retired_taken_branches", 0xC4 }, \
278e850fb01SKuriakose Kuruvilla { "FR_retired_taken_branches_mispred", 0xC5 }, \
279e850fb01SKuriakose Kuruvilla { "FR_retired_far_ctl_transfer", 0xC6 }, \
280e850fb01SKuriakose Kuruvilla { "FR_retired_resyncs", 0xC7 }, \
281e850fb01SKuriakose Kuruvilla { "FR_retired_near_rets", 0xC8 }, \
282e850fb01SKuriakose Kuruvilla { "FR_retired_near_rets_mispred", 0xC9 }, \
283e850fb01SKuriakose Kuruvilla { "FR_retired_taken_branches_mispred_addr_miscomp", 0xCA },\
284e850fb01SKuriakose Kuruvilla { "FR_retired_fastpath_double_op_instr", 0xCC }, \
285e850fb01SKuriakose Kuruvilla { "FR_intr_masked_cycles", 0xCD }, \
286e850fb01SKuriakose Kuruvilla { "FR_intr_masked_while_pending_cycles", 0xCE }, \
287e850fb01SKuriakose Kuruvilla { "FR_taken_hardware_intrs", 0xCF }, \
288e850fb01SKuriakose Kuruvilla { "FR_nothing_to_dispatch", 0xD0 }, \
289e850fb01SKuriakose Kuruvilla { "FR_dispatch_stalls", 0xD1 }, \
290e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_branch_abort_to_retire", 0xD2 }, \
291e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_serialization", 0xD3 }, \
292e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_segment_load", 0xD4 }, \
293e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_reorder_buffer_full", 0xD5 }, \
294e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_resv_stations_full", 0xD6 }, \
295e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_fpu_full", 0xD7 }, \
296e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_ls_full", 0xD8 }, \
297e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_waiting_all_quiet", 0xD9 }, \
298e850fb01SKuriakose Kuruvilla { "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", 0xDA },\
299e850fb01SKuriakose Kuruvilla { "FR_fpu_exception", 0xDB }, \
300e850fb01SKuriakose Kuruvilla { "FR_num_brkpts_dr0", 0xDC }, \
301e850fb01SKuriakose Kuruvilla { "FR_num_brkpts_dr1", 0xDD }, \
302e850fb01SKuriakose Kuruvilla { "FR_num_brkpts_dr2", 0xDE }, \
303e850fb01SKuriakose Kuruvilla { "FR_num_brkpts_dr3", 0xDF }, \
304e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_page_access", 0xE0 }, \
305e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_turnaround", 0xE3 }, \
306e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_bypass_counter_saturation", 0xE4 }, \
307e850fb01SKuriakose Kuruvilla { "NB_cpu_io_to_mem_io", 0xE9 }, \
308e850fb01SKuriakose Kuruvilla { "NB_cache_block_commands", 0xEA }, \
309e850fb01SKuriakose Kuruvilla { "NB_sized_commands", 0xEB }, \
310e850fb01SKuriakose Kuruvilla { "NB_ht_bus0_bandwidth", 0xF6 }
311e850fb01SKuriakose Kuruvilla
312e850fb01SKuriakose Kuruvilla #define AMD_FAMILY_f_events \
313e850fb01SKuriakose Kuruvilla { "BU_quadwords_written_to_system", 0x6D }, \
314e850fb01SKuriakose Kuruvilla { "FR_retired_fpu_instr", 0xCB }, \
315e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_page_table_overflow", 0xE1 }, \
316e850fb01SKuriakose Kuruvilla { "NB_sized_blocks", 0xE5 }, \
317e850fb01SKuriakose Kuruvilla { "NB_ECC_errors", 0xE8 }, \
318e850fb01SKuriakose Kuruvilla { "NB_probe_result", 0xEC }, \
319e850fb01SKuriakose Kuruvilla { "NB_gart_events", 0xEE }, \
320e850fb01SKuriakose Kuruvilla { "NB_ht_bus1_bandwidth", 0xF7 }, \
321e850fb01SKuriakose Kuruvilla { "NB_ht_bus2_bandwidth", 0xF8 }
322e850fb01SKuriakose Kuruvilla
323e850fb01SKuriakose Kuruvilla #define AMD_FAMILY_10h_events \
324e850fb01SKuriakose Kuruvilla { "FP_retired_sse_ops", 0x3 }, \
325e850fb01SKuriakose Kuruvilla { "FP_retired_move_ops", 0x4 }, \
326e850fb01SKuriakose Kuruvilla { "FP_retired_serialize_ops", 0x5 }, \
327e850fb01SKuriakose Kuruvilla { "FP_serialize_ops_cycles", 0x6 }, \
328e850fb01SKuriakose Kuruvilla { "LS_cancelled_store_to_load_fwd_ops", 0x2A }, \
329e850fb01SKuriakose Kuruvilla { "LS_smi_received", 0x2B }, \
330e850fb01SKuriakose Kuruvilla { "DC_dtlb_L1_hit", 0x4D }, \
331e850fb01SKuriakose Kuruvilla { "LS_ineffective_prefetch", 0x52 }, \
332e850fb01SKuriakose Kuruvilla { "LS_global_tlb_flush", 0x54 }, \
333e850fb01SKuriakose Kuruvilla { "BU_octwords_written_to_system", 0x6D }, \
334e850fb01SKuriakose Kuruvilla { "Page_size_mismatches", 0x165 }, \
335e850fb01SKuriakose Kuruvilla { "IC_eviction", 0x8B }, \
336e850fb01SKuriakose Kuruvilla { "IC_cache_lines_invalidate", 0x8C }, \
337e850fb01SKuriakose Kuruvilla { "IC_itlb_reload", 0x99 }, \
338e850fb01SKuriakose Kuruvilla { "IC_itlb_reload_aborted", 0x9A }, \
339e850fb01SKuriakose Kuruvilla { "FR_retired_mmx_sse_fp_instr", 0xCB }, \
340e850fb01SKuriakose Kuruvilla { "Retired_x87_fp_ops", 0x1C0 }, \
341e850fb01SKuriakose Kuruvilla { "IBS_ops_tagged", 0x1CF }, \
342e850fb01SKuriakose Kuruvilla { "LFENCE_inst_retired", 0x1D3 }, \
343e850fb01SKuriakose Kuruvilla { "SFENCE_inst_retired", 0x1D4 }, \
344e850fb01SKuriakose Kuruvilla { "MFENCE_inst_retired", 0x1D5 }, \
345e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_page_table_overflow", 0xE1 }, \
346e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_dram_cmd_slots_missed", 0xE2 }, \
347e850fb01SKuriakose Kuruvilla { "NB_thermal_status", 0xE8 }, \
348e850fb01SKuriakose Kuruvilla { "NB_probe_results_upstream_req", 0xEC }, \
349e850fb01SKuriakose Kuruvilla { "NB_gart_events", 0xEE }, \
350e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_req", 0x1F0 }, \
351e850fb01SKuriakose Kuruvilla { "CB_cpu_to_dram_req_to_target", 0x1E0 }, \
352e850fb01SKuriakose Kuruvilla { "CB_io_to_dram_req_to_target", 0x1E1 }, \
353e850fb01SKuriakose Kuruvilla { "CB_cpu_read_cmd_latency_to_target_0_to_3", 0x1E2 }, \
354e850fb01SKuriakose Kuruvilla { "CB_cpu_read_cmd_req_to_target_0_to_3", 0x1E3 }, \
355e850fb01SKuriakose Kuruvilla { "CB_cpu_read_cmd_latency_to_target_4_to_7", 0x1E4 }, \
356e850fb01SKuriakose Kuruvilla { "CB_cpu_read_cmd_req_to_target_4_to_7", 0x1E5 }, \
357e850fb01SKuriakose Kuruvilla { "CB_cpu_cmd_latency_to_target_0_to_7", 0x1E6 }, \
358e850fb01SKuriakose Kuruvilla { "CB_cpu_req_to_target_0_to_7", 0x1E7 }, \
359e850fb01SKuriakose Kuruvilla { "NB_ht_bus1_bandwidth", 0xF7 }, \
360e850fb01SKuriakose Kuruvilla { "NB_ht_bus2_bandwidth", 0xF8 }, \
361e850fb01SKuriakose Kuruvilla { "NB_ht_bus3_bandwidth", 0x1F9 }, \
362e850fb01SKuriakose Kuruvilla { "L3_read_req", 0x4E0 }, \
363e850fb01SKuriakose Kuruvilla { "L3_miss", 0x4E1 }, \
364e850fb01SKuriakose Kuruvilla { "L3_l2_eviction_l3_fill", 0x4E2 }, \
365e850fb01SKuriakose Kuruvilla { "L3_eviction", 0x4E3 }
366e850fb01SKuriakose Kuruvilla
367e850fb01SKuriakose Kuruvilla #define AMD_FAMILY_11h_events \
368e850fb01SKuriakose Kuruvilla { "BU_quadwords_written_to_system", 0x6D }, \
369e850fb01SKuriakose Kuruvilla { "FR_retired_mmx_fp_instr", 0xCB }, \
370e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_page_table_events", 0xE1 }, \
371e850fb01SKuriakose Kuruvilla { "NB_thermal_status", 0xE8 }, \
372e850fb01SKuriakose Kuruvilla { "NB_probe_results_upstream_req", 0xEC }, \
373e850fb01SKuriakose Kuruvilla { "NB_dev_events", 0xEE }, \
374e850fb01SKuriakose Kuruvilla { "NB_mem_ctrlr_req", 0x1F0 }
37531725658Sksadhukh
376c7a079a8SJonathan Haslam #define AMD_cmn_generic_events \
377c7a079a8SJonathan Haslam { "PAPI_br_ins", "FR_retired_branches_w_excp_intr", 0x0 },\
378c7a079a8SJonathan Haslam { "PAPI_br_msp", "FR_retired_branches_mispred", 0x0 }, \
379c7a079a8SJonathan Haslam { "PAPI_br_tkn", "FR_retired_taken_branches", 0x0 }, \
380c7a079a8SJonathan Haslam { "PAPI_fp_ops", "FP_dispatched_fpu_ops", 0x3 }, \
381c7a079a8SJonathan Haslam { "PAPI_fad_ins", "FP_dispatched_fpu_ops", 0x1 }, \
382c7a079a8SJonathan Haslam { "PAPI_fml_ins", "FP_dispatched_fpu_ops", 0x2 }, \
383c7a079a8SJonathan Haslam { "PAPI_fpu_idl", "FP_cycles_no_fpu_ops_retired", 0x0 }, \
384c7a079a8SJonathan Haslam { "PAPI_tot_cyc", "BU_cpu_clk_unhalted", 0x0 }, \
385c7a079a8SJonathan Haslam { "PAPI_tot_ins", "FR_retired_x86_instr_w_excp_intr", 0x0 }, \
386c7a079a8SJonathan Haslam { "PAPI_l1_dca", "DC_access", 0x0 }, \
387c7a079a8SJonathan Haslam { "PAPI_l1_dcm", "DC_miss", 0x0 }, \
388c7a079a8SJonathan Haslam { "PAPI_l1_ldm", "DC_refill_from_L2", 0xe }, \
389c7a079a8SJonathan Haslam { "PAPI_l1_stm", "DC_refill_from_L2", 0x10 }, \
390c7a079a8SJonathan Haslam { "PAPI_l1_ica", "IC_fetch", 0x0 }, \
391c7a079a8SJonathan Haslam { "PAPI_l1_icm", "IC_miss", 0x0 }, \
392c7a079a8SJonathan Haslam { "PAPI_l1_icr", "IC_fetch", 0x0 }, \
393c7a079a8SJonathan Haslam { "PAPI_l2_dch", "DC_refill_from_L2", 0x1e }, \
394c7a079a8SJonathan Haslam { "PAPI_l2_dcm", "DC_refill_from_system", 0x1e }, \
395c7a079a8SJonathan Haslam { "PAPI_l2_dcr", "DC_refill_from_L2", 0xe }, \
396c7a079a8SJonathan Haslam { "PAPI_l2_dcw", "DC_refill_from_L2", 0x10 }, \
397c7a079a8SJonathan Haslam { "PAPI_l2_ich", "IC_refill_from_L2", 0x0 }, \
398c7a079a8SJonathan Haslam { "PAPI_l2_icm", "IC_refill_from_system", 0x0 }, \
399c7a079a8SJonathan Haslam { "PAPI_l2_ldm", "DC_refill_from_system", 0xe }, \
400c7a079a8SJonathan Haslam { "PAPI_l2_stm", "DC_refill_from_system", 0x10 }, \
401c7a079a8SJonathan Haslam { "PAPI_res_stl", "FR_dispatch_stalls", 0x0 }, \
402c7a079a8SJonathan Haslam { "PAPI_stl_icy", "FR_nothing_to_dispatch", 0x0 }, \
403c7a079a8SJonathan Haslam { "PAPI_hw_int", "FR_taken_hardware_intrs", 0x0 }
404c7a079a8SJonathan Haslam
405c7a079a8SJonathan Haslam #define OPT_cmn_generic_events \
406c7a079a8SJonathan Haslam { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss", 0x0 }, \
407c7a079a8SJonathan Haslam { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss", 0x0 }, \
408c7a079a8SJonathan Haslam { "PAPI_fp_ins", "FR_retired_fpu_instr", 0xd }, \
409c7a079a8SJonathan Haslam { "PAPI_vec_ins", "FR_retired_fpu_instr", 0x4 }
410c7a079a8SJonathan Haslam
411c7a079a8SJonathan Haslam #define AMD_FAMILY_10h_generic_events \
412c7a079a8SJonathan Haslam { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss", 0x7 }, \
413c7a079a8SJonathan Haslam { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss", 0x3 }, \
414c7a079a8SJonathan Haslam { "PAPI_l3_dcr", "L3_read_req", 0xf1 }, \
415c7a079a8SJonathan Haslam { "PAPI_l3_icr", "L3_read_req", 0xf2 }, \
416c7a079a8SJonathan Haslam { "PAPI_l3_tcr", "L3_read_req", 0xf7 }, \
417c7a079a8SJonathan Haslam { "PAPI_l3_stm", "L3_miss", 0xf4 }, \
418c7a079a8SJonathan Haslam { "PAPI_l3_ldm", "L3_miss", 0xf3 }, \
419c7a079a8SJonathan Haslam { "PAPI_l3_tcm", "L3_miss", 0xf7 }
420c7a079a8SJonathan Haslam
421d0e58ef5SRobert Mustacchi static const amd_event_t family_f_events[] = {
42231725658Sksadhukh AMD_cmn_events,
423e850fb01SKuriakose Kuruvilla AMD_FAMILY_f_events,
424fb47e43fSjhaslam EV_END
425fb47e43fSjhaslam };
426fb47e43fSjhaslam
427d0e58ef5SRobert Mustacchi static const amd_event_t family_10h_events[] = {
42831725658Sksadhukh AMD_cmn_events,
429e850fb01SKuriakose Kuruvilla AMD_FAMILY_10h_events,
4307c478bd9Sstevel@tonic-gate EV_END
4317c478bd9Sstevel@tonic-gate };
4327c478bd9Sstevel@tonic-gate
433d0e58ef5SRobert Mustacchi static const amd_event_t family_11h_events[] = {
43431725658Sksadhukh AMD_cmn_events,
435e850fb01SKuriakose Kuruvilla AMD_FAMILY_11h_events,
43631725658Sksadhukh EV_END
43731725658Sksadhukh };
43831725658Sksadhukh
439d0e58ef5SRobert Mustacchi static const amd_generic_event_t opt_generic_events[] = {
440c7a079a8SJonathan Haslam AMD_cmn_generic_events,
441c7a079a8SJonathan Haslam OPT_cmn_generic_events,
442c7a079a8SJonathan Haslam GEN_EV_END
443c7a079a8SJonathan Haslam };
444c7a079a8SJonathan Haslam
445d0e58ef5SRobert Mustacchi static const amd_generic_event_t family_10h_generic_events[] = {
446c7a079a8SJonathan Haslam AMD_cmn_generic_events,
447c7a079a8SJonathan Haslam AMD_FAMILY_10h_generic_events,
448c7a079a8SJonathan Haslam GEN_EV_END
449c7a079a8SJonathan Haslam };
450c7a079a8SJonathan Haslam
451d0e58ef5SRobert Mustacchi /*
452281939dfSRobert Mustacchi * For Family 17h and Family 19h, the cpcgen utility generates all of our events
453281939dfSRobert Mustacchi * including ones that need specific unit codes, therefore we leave all unit
454281939dfSRobert Mustacchi * codes out of these. Zen 1, Zen 2, and Zen 3 have different event sets that
455281939dfSRobert Mustacchi * they support.
456d0e58ef5SRobert Mustacchi */
45731aa6202SRobert Mustacchi static const amd_generic_event_t family_17h_zen1_papi_events[] = {
458d0e58ef5SRobert Mustacchi { "PAPI_br_cn", "ExRetCond" },
45931aa6202SRobert Mustacchi { "PAPI_br_ins", "ExRetBrn" },
460d0e58ef5SRobert Mustacchi { "PAPI_fpu_idl", "FpSchedEmpty" },
461d0e58ef5SRobert Mustacchi { "PAPI_tot_cyc", "LsNotHaltedCyc" },
462d0e58ef5SRobert Mustacchi { "PAPI_tot_ins", "ExRetInstr" },
463d0e58ef5SRobert Mustacchi { "PAPI_tlb_dm", "LsL1DTlbMiss" },
464d0e58ef5SRobert Mustacchi { "PAPI_tlb_im", "BpL1TlbMissL2Miss" },
465d0e58ef5SRobert Mustacchi GEN_EV_END
466d0e58ef5SRobert Mustacchi };
467d0e58ef5SRobert Mustacchi
46831aa6202SRobert Mustacchi static const amd_generic_event_t family_17h_zen2_papi_events[] = {
46931aa6202SRobert Mustacchi { "PAPI_br_cn", "ExRetCond" },
47031aa6202SRobert Mustacchi { "PAPI_br_ins", "ExRetBrn" },
47131aa6202SRobert Mustacchi { "PAPI_tot_cyc", "LsNotHaltedCyc" },
47231aa6202SRobert Mustacchi { "PAPI_tot_ins", "ExRetInstr" },
47331aa6202SRobert Mustacchi { "PAPI_tlb_dm", "LsL1DTlbMiss" },
47431aa6202SRobert Mustacchi { "PAPI_tlb_im", "BpL1TlbMissL2Miss" },
47531aa6202SRobert Mustacchi GEN_EV_END
47631aa6202SRobert Mustacchi };
47731aa6202SRobert Mustacchi
478281939dfSRobert Mustacchi static const amd_generic_event_t family_19h_zen3_papi_events[] = {
479281939dfSRobert Mustacchi { "PAPI_br_cn", "ExRetCond" },
480281939dfSRobert Mustacchi { "PAPI_br_ins", "ExRetBrn" },
481281939dfSRobert Mustacchi { "PAPI_tot_cyc", "LsNotHaltedCyc" },
482281939dfSRobert Mustacchi { "PAPI_tot_ins", "ExRetInstr" },
483281939dfSRobert Mustacchi { "PAPI_tlb_dm", "LsL1DTlbMiss" },
484281939dfSRobert Mustacchi { "PAPI_tlb_im", "BpL1TlbMissL2TlbMiss" },
485e6bda3ffSRobert Mustacchi GEN_EV_END
486e6bda3ffSRobert Mustacchi };
487e6bda3ffSRobert Mustacchi
488e6bda3ffSRobert Mustacchi static const amd_generic_event_t family_19h_zen4_papi_events[] = {
489e6bda3ffSRobert Mustacchi { "PAPI_br_cn", "ExRetCond" },
490e6bda3ffSRobert Mustacchi { "PAPI_br_ins", "ExRetBrn" },
491281939dfSRobert Mustacchi { "PAPI_tot_cyc", "LsNotHaltedCyc" },
492e6bda3ffSRobert Mustacchi { "PAPI_tot_ins", "ExRetInstr" },
493e6bda3ffSRobert Mustacchi { "PAPI_tlb_dm", "LsL1DTlbMiss" },
494e6bda3ffSRobert Mustacchi { "PAPI_tlb_im", "BpL1TlbMissL2TlbMiss" },
495281939dfSRobert Mustacchi GEN_EV_END
496281939dfSRobert Mustacchi };
497281939dfSRobert Mustacchi
498*cf618897SRobert Mustacchi static const amd_generic_event_t family_1ah_zen5_papi_events[] = {
499*cf618897SRobert Mustacchi { "PAPI_br_cn", "Retired_Conditional_Branch_Instructions" },
500*cf618897SRobert Mustacchi { "PAPI_br_ins", "Retired_Branch_Instructions" },
501*cf618897SRobert Mustacchi { "PAPI_br_msp",
502*cf618897SRobert Mustacchi "Retired_Conditional_Branch_Instructions_Mispredicted" },
503*cf618897SRobert Mustacchi { "PAPI_br_ucn", "Retired_Unconditional_Branch_Instructions" },
504*cf618897SRobert Mustacchi { "PAPI_tot_cyc", "Cycles_Not_in_Halt" },
505*cf618897SRobert Mustacchi { "PAPI_tot_ins", "Retired_Instructions" },
506*cf618897SRobert Mustacchi { "PAPI_hw_int", "Interrupts_Taken" },
507*cf618897SRobert Mustacchi { "PAPI_tlb_sd", "TLB_Flush_Events" },
508*cf618897SRobert Mustacchi GEN_EV_END
509*cf618897SRobert Mustacchi };
51031aa6202SRobert Mustacchi
5117c478bd9Sstevel@tonic-gate static char *evlist;
5127c478bd9Sstevel@tonic-gate static size_t evlist_sz;
513d0e58ef5SRobert Mustacchi static const amd_event_t *amd_events = NULL;
514d0e58ef5SRobert Mustacchi static uint_t amd_family, amd_model;
515d0e58ef5SRobert Mustacchi static const amd_generic_event_t *amd_generic_events = NULL;
5167c478bd9Sstevel@tonic-gate
517d0e58ef5SRobert Mustacchi static char amd_fam_f_rev_ae_bkdg[] = "See \"BIOS and Kernel Developer's "
518e850fb01SKuriakose Kuruvilla "Guide for AMD Athlon 64 and AMD Opteron Processors\" (AMD publication 26094)";
519d0e58ef5SRobert Mustacchi static char amd_fam_f_NPT_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
520e850fb01SKuriakose Kuruvilla "for AMD NPT Family 0Fh Processors\" (AMD publication 32559)";
521d0e58ef5SRobert Mustacchi static char amd_fam_10h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
522e850fb01SKuriakose Kuruvilla "(BKDG) For AMD Family 10h Processors\" (AMD publication 31116)";
523d0e58ef5SRobert Mustacchi static char amd_fam_11h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
524e850fb01SKuriakose Kuruvilla "(BKDG) For AMD Family 11h Processors\" (AMD publication 41256)";
52531aa6202SRobert Mustacchi static char amd_fam_17h_zen1_reg[] = "See \"Open-Source Register Reference For "
526d0e58ef5SRobert Mustacchi "AMD Family 17h Processors Models 00h-2Fh\" (AMD publication 56255) and "
52731aa6202SRobert Mustacchi "amd_f17h_zen1_events(3CPC)";
52831aa6202SRobert Mustacchi static char amd_fam_17h_zen2_reg[] = "See \"Preliminary Processor Programming "
52931aa6202SRobert Mustacchi "Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors\" "
53031aa6202SRobert Mustacchi "(AMD publication 55803), \"Processor Programming Reference (PPR) for AMD "
53131aa6202SRobert Mustacchi "Family 17h Model 71h, Revision B0 Processors\" (AMD publication 56176), and "
53231aa6202SRobert Mustacchi "amd_f17h_zen2_events(3CPC)";
533281939dfSRobert Mustacchi static char amd_fam_19h_zen3_reg[] = "See \"Preliminary Processor Programming "
534281939dfSRobert Mustacchi "Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors Volume "
5358efb7381SRobert Mustacchi "1 of 2\" (AMD publication 55898), \"Processor Programming Reference (PPR) "
5368efb7381SRobert Mustacchi "for AMD Family 19h Model 21h, Revision B0 Processors\" (AMD publication "
537e6bda3ffSRobert Mustacchi "56214), and amd_f19h_zen3_events(3CPC)";
538e6bda3ffSRobert Mustacchi static char amd_fam_19h_zen4_reg[] = "See \"Processor Programming Reference "
539e6bda3ffSRobert Mustacchi "(PPR) for AMD Family 19h Model 11h, Revision B1 Processors Volume 1 of 6\" "
540e6bda3ffSRobert Mustacchi "(AMD publication 55901), \"Processor Programming Reference (PPR) for AMD "
541e6bda3ffSRobert Mustacchi "Family 19h Model 61h, Revision B1 Processors\" (AMD publication 56713), "
542e6bda3ffSRobert Mustacchi "\"Processor Programming Reference (PPR) for AMD Family 19h Model 70h, "
543e6bda3ffSRobert Mustacchi "Revision A0 Processors\" (AMD publication 57019), and "
544e6bda3ffSRobert Mustacchi "amd_f19h_zen4_events(3CPC)";
545*cf618897SRobert Mustacchi static char amd_fam_1ah_zen5_reg[] = "See \"Performance Monitor Counters "
546*cf618897SRobert Mustacchi "for AMD Family 1Ah Model 00h-Fh Processors\" (AMD publication 58550) and "
547*cf618897SRobert Mustacchi "amd_f1ah_zen5_events(3CPC)";
548e850fb01SKuriakose Kuruvilla
549e850fb01SKuriakose Kuruvilla static char amd_pcbe_impl_name[64];
550e850fb01SKuriakose Kuruvilla static char *amd_pcbe_cpuref;
551e850fb01SKuriakose Kuruvilla
552e850fb01SKuriakose Kuruvilla
5537c478bd9Sstevel@tonic-gate #define BITS(v, u, l) \
5547c478bd9Sstevel@tonic-gate (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
5557c478bd9Sstevel@tonic-gate
556d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pes_addr(uint_t counter)557d0e58ef5SRobert Mustacchi opt_pcbe_pes_addr(uint_t counter)
558d0e58ef5SRobert Mustacchi {
559d0e58ef5SRobert Mustacchi ASSERT3U(counter, <, opd.opd_ncounters);
560d0e58ef5SRobert Mustacchi return (PES_BASE_ADDR + counter);
561d0e58ef5SRobert Mustacchi }
562d0e58ef5SRobert Mustacchi
563d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pes_ext_addr(uint_t counter)564d0e58ef5SRobert Mustacchi opt_pcbe_pes_ext_addr(uint_t counter)
565d0e58ef5SRobert Mustacchi {
566d0e58ef5SRobert Mustacchi ASSERT3U(counter, <, opd.opd_ncounters);
567d0e58ef5SRobert Mustacchi return (PES_EXT_BASE_ADDR + 2 * counter);
568d0e58ef5SRobert Mustacchi }
569d0e58ef5SRobert Mustacchi
570d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pic_addr(uint_t counter)571d0e58ef5SRobert Mustacchi opt_pcbe_pic_addr(uint_t counter)
572d0e58ef5SRobert Mustacchi {
573d0e58ef5SRobert Mustacchi ASSERT3U(counter, <, opd.opd_ncounters);
574abc23ffaSRobert Mustacchi return (PIC_BASE_ADDR + counter);
575d0e58ef5SRobert Mustacchi }
576d0e58ef5SRobert Mustacchi
577d0e58ef5SRobert Mustacchi static uint64_t
opt_pcbe_pic_ext_addr(uint_t counter)578d0e58ef5SRobert Mustacchi opt_pcbe_pic_ext_addr(uint_t counter)
579d0e58ef5SRobert Mustacchi {
580d0e58ef5SRobert Mustacchi ASSERT3U(counter, <, opd.opd_ncounters);
581d0e58ef5SRobert Mustacchi return (PIC_EXT_BASE_ADDR + 2 * counter);
582d0e58ef5SRobert Mustacchi }
5837c478bd9Sstevel@tonic-gate
5847c478bd9Sstevel@tonic-gate static int
opt_pcbe_init(void)5857c478bd9Sstevel@tonic-gate opt_pcbe_init(void)
5867c478bd9Sstevel@tonic-gate {
587d0e58ef5SRobert Mustacchi const amd_event_t *evp;
588d0e58ef5SRobert Mustacchi const amd_generic_event_t *gevp;
589e6bda3ffSRobert Mustacchi x86_uarchrev_t uarchrev;
5907c478bd9Sstevel@tonic-gate
59131725658Sksadhukh amd_family = cpuid_getfamily(CPU);
592d0e58ef5SRobert Mustacchi amd_model = cpuid_getmodel(CPU);
593e6bda3ffSRobert Mustacchi uarchrev = cpuid_getuarchrev(CPU);
59431725658Sksadhukh
5957c478bd9Sstevel@tonic-gate /*
5967c478bd9Sstevel@tonic-gate * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel
5977c478bd9Sstevel@tonic-gate * loads this module based on its name in the module directory, but it
5987c478bd9Sstevel@tonic-gate * could have been renamed.
5997c478bd9Sstevel@tonic-gate */
6009b0429a1SPu Wen if ((cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf) &&
6019b0429a1SPu Wen cpuid_getvendor(CPU) != X86_VENDOR_HYGON)
6027c478bd9Sstevel@tonic-gate return (-1);
6037c478bd9Sstevel@tonic-gate
604d0e58ef5SRobert Mustacchi if (amd_family == 0xf) {
605e850fb01SKuriakose Kuruvilla /* Some tools expect this string for family 0fh */
606c1374a13SSurya Prakki (void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
607e850fb01SKuriakose Kuruvilla "AMD Opteron & Athlon64");
608d0e58ef5SRobert Mustacchi } else {
609c1374a13SSurya Prakki (void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
6109b0429a1SPu Wen "%s Family %02xh",
6119b0429a1SPu Wen cpuid_getvendor(CPU) == X86_VENDOR_HYGON ? "Hygon" : "AMD",
6129b0429a1SPu Wen amd_family);
613d0e58ef5SRobert Mustacchi }
614d0e58ef5SRobert Mustacchi
615d0e58ef5SRobert Mustacchi /*
616d0e58ef5SRobert Mustacchi * Determine whether or not the extended counter set is supported on
617d0e58ef5SRobert Mustacchi * this processor.
618d0e58ef5SRobert Mustacchi */
619d0e58ef5SRobert Mustacchi if (is_x86_feature(x86_featureset, X86FSET_AMD_PCEC)) {
620d0e58ef5SRobert Mustacchi opd.opd_ncounters = OPT_PCBE_EXT_NCOUNTERS;
621d0e58ef5SRobert Mustacchi opd.opd_pesf = opt_pcbe_pes_ext_addr;
622d0e58ef5SRobert Mustacchi opd.opd_picf = opt_pcbe_pic_ext_addr;
623d0e58ef5SRobert Mustacchi } else {
624d0e58ef5SRobert Mustacchi opd.opd_ncounters = OPT_PCBE_DEF_NCOUNTERS;
625d0e58ef5SRobert Mustacchi opd.opd_pesf = opt_pcbe_pes_addr;
626d0e58ef5SRobert Mustacchi opd.opd_picf = opt_pcbe_pic_addr;
627d0e58ef5SRobert Mustacchi }
628d0e58ef5SRobert Mustacchi opd.opd_cmask = (1 << opd.opd_ncounters) - 1;
629e850fb01SKuriakose Kuruvilla
630fb47e43fSjhaslam /*
631fb47e43fSjhaslam * Figure out processor revision here and assign appropriate
632fb47e43fSjhaslam * event configuration.
633fb47e43fSjhaslam */
634e6bda3ffSRobert Mustacchi switch (uarchrev_uarch(uarchrev)) {
635e6bda3ffSRobert Mustacchi case X86_UARCH_AMD_LEGACY:
636e6bda3ffSRobert Mustacchi switch (amd_family) {
637e6bda3ffSRobert Mustacchi case 0xf: {
638e6bda3ffSRobert Mustacchi x86_chiprev_t rev;
639e6bda3ffSRobert Mustacchi
640e6bda3ffSRobert Mustacchi rev = cpuid_getchiprev(CPU);
641e6bda3ffSRobert Mustacchi
642e6bda3ffSRobert Mustacchi if (chiprev_at_least(rev,
643e6bda3ffSRobert Mustacchi X86_CHIPREV_AMD_LEGACY_F_REV_F)) {
644e6bda3ffSRobert Mustacchi amd_pcbe_cpuref = amd_fam_f_NPT_bkdg;
645e6bda3ffSRobert Mustacchi } else {
646e6bda3ffSRobert Mustacchi amd_pcbe_cpuref = amd_fam_f_rev_ae_bkdg;
647e6bda3ffSRobert Mustacchi }
648e6bda3ffSRobert Mustacchi amd_events = family_f_events;
649e6bda3ffSRobert Mustacchi amd_generic_events = opt_generic_events;
650e6bda3ffSRobert Mustacchi break;
651e6bda3ffSRobert Mustacchi }
652e6bda3ffSRobert Mustacchi case 0x10:
653e6bda3ffSRobert Mustacchi amd_pcbe_cpuref = amd_fam_10h_bkdg;
654e6bda3ffSRobert Mustacchi amd_events = family_10h_events;
655e6bda3ffSRobert Mustacchi amd_generic_events = family_10h_generic_events;
656e6bda3ffSRobert Mustacchi break;
657e6bda3ffSRobert Mustacchi case 0x11:
658e6bda3ffSRobert Mustacchi amd_pcbe_cpuref = amd_fam_11h_bkdg;
659e6bda3ffSRobert Mustacchi amd_events = family_11h_events;
660e6bda3ffSRobert Mustacchi amd_generic_events = opt_generic_events;
661e6bda3ffSRobert Mustacchi break;
662e6bda3ffSRobert Mustacchi default:
663e6bda3ffSRobert Mustacchi return (-1);
664e6bda3ffSRobert Mustacchi }
665e6bda3ffSRobert Mustacchi break;
666e6bda3ffSRobert Mustacchi case X86_UARCH_AMD_ZEN1:
667e6bda3ffSRobert Mustacchi case X86_UARCH_AMD_ZENPLUS:
66831aa6202SRobert Mustacchi amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
66931aa6202SRobert Mustacchi amd_events = opteron_pcbe_f17h_zen1_events;
67031aa6202SRobert Mustacchi amd_generic_events = family_17h_zen1_papi_events;
671e6bda3ffSRobert Mustacchi break;
672e6bda3ffSRobert Mustacchi case X86_UARCH_AMD_ZEN2:
67331aa6202SRobert Mustacchi amd_pcbe_cpuref = amd_fam_17h_zen2_reg;
67431aa6202SRobert Mustacchi amd_events = opteron_pcbe_f17h_zen2_events;
67531aa6202SRobert Mustacchi amd_generic_events = family_17h_zen2_papi_events;
676e6bda3ffSRobert Mustacchi break;
677e6bda3ffSRobert Mustacchi case X86_UARCH_AMD_ZEN3:
678281939dfSRobert Mustacchi amd_pcbe_cpuref = amd_fam_19h_zen3_reg;
679281939dfSRobert Mustacchi amd_events = opteron_pcbe_f19h_zen3_events;
680281939dfSRobert Mustacchi amd_generic_events = family_19h_zen3_papi_events;
681e6bda3ffSRobert Mustacchi break;
682e6bda3ffSRobert Mustacchi case X86_UARCH_AMD_ZEN4:
683e6bda3ffSRobert Mustacchi amd_pcbe_cpuref = amd_fam_19h_zen4_reg;
684e6bda3ffSRobert Mustacchi amd_events = opteron_pcbe_f19h_zen4_events;
685e6bda3ffSRobert Mustacchi amd_generic_events = family_19h_zen4_papi_events;
686e6bda3ffSRobert Mustacchi break;
687*cf618897SRobert Mustacchi case X86_UARCH_AMD_ZEN5:
688*cf618897SRobert Mustacchi amd_pcbe_cpuref = amd_fam_1ah_zen5_reg;
689*cf618897SRobert Mustacchi amd_events = opteron_pcbe_f1ah_zen5_events;
690*cf618897SRobert Mustacchi amd_generic_events = family_1ah_zen5_papi_events;
691*cf618897SRobert Mustacchi break;
692e6bda3ffSRobert Mustacchi default:
693e850fb01SKuriakose Kuruvilla /*
694d0e58ef5SRobert Mustacchi * Different families have different meanings on events and even
695d0e58ef5SRobert Mustacchi * worse (like family 15h), different constraints around
696d0e58ef5SRobert Mustacchi * programming these values.
697e850fb01SKuriakose Kuruvilla */
698d0e58ef5SRobert Mustacchi return (-1);
69931725658Sksadhukh }
700fb47e43fSjhaslam
7017c478bd9Sstevel@tonic-gate /*
7027c478bd9Sstevel@tonic-gate * Construct event list.
7037c478bd9Sstevel@tonic-gate *
7047c478bd9Sstevel@tonic-gate * First pass: Calculate size needed. We'll need an additional byte
7057c478bd9Sstevel@tonic-gate * for the NULL pointer during the last strcat.
7067c478bd9Sstevel@tonic-gate *
7077c478bd9Sstevel@tonic-gate * Second pass: Copy strings.
7087c478bd9Sstevel@tonic-gate */
70931725658Sksadhukh for (evp = amd_events; evp->name != NULL; evp++)
7107c478bd9Sstevel@tonic-gate evlist_sz += strlen(evp->name) + 1;
7117c478bd9Sstevel@tonic-gate
712c7a079a8SJonathan Haslam for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
713c7a079a8SJonathan Haslam evlist_sz += strlen(gevp->name) + 1;
714c7a079a8SJonathan Haslam
7157c478bd9Sstevel@tonic-gate evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP);
7167c478bd9Sstevel@tonic-gate evlist[0] = '\0';
7177c478bd9Sstevel@tonic-gate
71831725658Sksadhukh for (evp = amd_events; evp->name != NULL; evp++) {
7197c478bd9Sstevel@tonic-gate (void) strcat(evlist, evp->name);
7207c478bd9Sstevel@tonic-gate (void) strcat(evlist, ",");
7217c478bd9Sstevel@tonic-gate }
722c7a079a8SJonathan Haslam
723c7a079a8SJonathan Haslam for (gevp = amd_generic_events; gevp->name != NULL; gevp++) {
724c7a079a8SJonathan Haslam (void) strcat(evlist, gevp->name);
725c7a079a8SJonathan Haslam (void) strcat(evlist, ",");
726c7a079a8SJonathan Haslam }
727c7a079a8SJonathan Haslam
7287c478bd9Sstevel@tonic-gate /*
7297c478bd9Sstevel@tonic-gate * Remove trailing comma.
7307c478bd9Sstevel@tonic-gate */
7317c478bd9Sstevel@tonic-gate evlist[evlist_sz - 1] = '\0';
7327c478bd9Sstevel@tonic-gate
7337c478bd9Sstevel@tonic-gate return (0);
7347c478bd9Sstevel@tonic-gate }
7357c478bd9Sstevel@tonic-gate
7367c478bd9Sstevel@tonic-gate static uint_t
opt_pcbe_ncounters(void)7377c478bd9Sstevel@tonic-gate opt_pcbe_ncounters(void)
7387c478bd9Sstevel@tonic-gate {
739d0e58ef5SRobert Mustacchi return (opd.opd_ncounters);
7407c478bd9Sstevel@tonic-gate }
7417c478bd9Sstevel@tonic-gate
7427c478bd9Sstevel@tonic-gate static const char *
opt_pcbe_impl_name(void)7437c478bd9Sstevel@tonic-gate opt_pcbe_impl_name(void)
7447c478bd9Sstevel@tonic-gate {
745e850fb01SKuriakose Kuruvilla return (amd_pcbe_impl_name);
7467c478bd9Sstevel@tonic-gate }
7477c478bd9Sstevel@tonic-gate
7487c478bd9Sstevel@tonic-gate static const char *
opt_pcbe_cpuref(void)7497c478bd9Sstevel@tonic-gate opt_pcbe_cpuref(void)
7507c478bd9Sstevel@tonic-gate {
751e850fb01SKuriakose Kuruvilla
752e850fb01SKuriakose Kuruvilla return (amd_pcbe_cpuref);
7537c478bd9Sstevel@tonic-gate }
7547c478bd9Sstevel@tonic-gate
7557c478bd9Sstevel@tonic-gate /*ARGSUSED*/
7567c478bd9Sstevel@tonic-gate static char *
opt_pcbe_list_events(uint_t picnum)7577c478bd9Sstevel@tonic-gate opt_pcbe_list_events(uint_t picnum)
7587c478bd9Sstevel@tonic-gate {
7597c478bd9Sstevel@tonic-gate return (evlist);
7607c478bd9Sstevel@tonic-gate }
7617c478bd9Sstevel@tonic-gate
7627c478bd9Sstevel@tonic-gate static char *
opt_pcbe_list_attrs(void)7637c478bd9Sstevel@tonic-gate opt_pcbe_list_attrs(void)
7647c478bd9Sstevel@tonic-gate {
7657c478bd9Sstevel@tonic-gate return ("edge,pc,inv,cmask,umask");
7667c478bd9Sstevel@tonic-gate }
7677c478bd9Sstevel@tonic-gate
768d0e58ef5SRobert Mustacchi static const amd_generic_event_t *
find_generic_event(char * name)769c7a079a8SJonathan Haslam find_generic_event(char *name)
770c7a079a8SJonathan Haslam {
771d0e58ef5SRobert Mustacchi const amd_generic_event_t *gevp;
772c7a079a8SJonathan Haslam
773c7a079a8SJonathan Haslam for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
774c7a079a8SJonathan Haslam if (strcmp(name, gevp->name) == 0)
775c7a079a8SJonathan Haslam return (gevp);
776c7a079a8SJonathan Haslam
777c7a079a8SJonathan Haslam return (NULL);
778c7a079a8SJonathan Haslam }
779c7a079a8SJonathan Haslam
780d0e58ef5SRobert Mustacchi static const amd_event_t *
find_event(char * name)7817c478bd9Sstevel@tonic-gate find_event(char *name)
7827c478bd9Sstevel@tonic-gate {
783d0e58ef5SRobert Mustacchi const amd_event_t *evp;
7847c478bd9Sstevel@tonic-gate
78531725658Sksadhukh for (evp = amd_events; evp->name != NULL; evp++)
7867c478bd9Sstevel@tonic-gate if (strcmp(name, evp->name) == 0)
7877c478bd9Sstevel@tonic-gate return (evp);
7887c478bd9Sstevel@tonic-gate
7897c478bd9Sstevel@tonic-gate return (NULL);
7907c478bd9Sstevel@tonic-gate }
7917c478bd9Sstevel@tonic-gate
792b885580bSAlexander Kolbasov /*ARGSUSED*/
793b885580bSAlexander Kolbasov static uint64_t
opt_pcbe_event_coverage(char * event)794b885580bSAlexander Kolbasov opt_pcbe_event_coverage(char *event)
795b885580bSAlexander Kolbasov {
796b885580bSAlexander Kolbasov /*
797b885580bSAlexander Kolbasov * Check whether counter event is supported
798b885580bSAlexander Kolbasov */
799b885580bSAlexander Kolbasov if (find_event(event) == NULL && find_generic_event(event) == NULL)
800b885580bSAlexander Kolbasov return (0);
801b885580bSAlexander Kolbasov
802b885580bSAlexander Kolbasov /*
803b885580bSAlexander Kolbasov * Fortunately, all counters can count all events.
804b885580bSAlexander Kolbasov */
805d0e58ef5SRobert Mustacchi return (opd.opd_cmask);
806b885580bSAlexander Kolbasov }
807b885580bSAlexander Kolbasov
808b885580bSAlexander Kolbasov static uint64_t
opt_pcbe_overflow_bitmap(void)809b885580bSAlexander Kolbasov opt_pcbe_overflow_bitmap(void)
810b885580bSAlexander Kolbasov {
811b885580bSAlexander Kolbasov /*
812b885580bSAlexander Kolbasov * Unfortunately, this chip cannot detect which counter overflowed, so
813b885580bSAlexander Kolbasov * we must act as if they all did.
814b885580bSAlexander Kolbasov */
815d0e58ef5SRobert Mustacchi return (opd.opd_cmask);
816b885580bSAlexander Kolbasov }
817b885580bSAlexander Kolbasov
8187c478bd9Sstevel@tonic-gate /*ARGSUSED*/
8197c478bd9Sstevel@tonic-gate static int
opt_pcbe_configure(uint_t picnum,char * event,uint64_t preset,uint32_t flags,uint_t nattrs,kcpc_attr_t * attrs,void ** data,void * token)8207c478bd9Sstevel@tonic-gate opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags,
8217c478bd9Sstevel@tonic-gate uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token)
8227c478bd9Sstevel@tonic-gate {
823d0e58ef5SRobert Mustacchi opt_pcbe_config_t *cfg;
824d0e58ef5SRobert Mustacchi const amd_event_t *evp;
825d0e58ef5SRobert Mustacchi amd_event_t ev_raw = { "raw", 0};
826d0e58ef5SRobert Mustacchi const amd_generic_event_t *gevp;
827d0e58ef5SRobert Mustacchi int i;
828d0e58ef5SRobert Mustacchi uint64_t evsel = 0, evsel_tmp = 0;
8297c478bd9Sstevel@tonic-gate
8307c478bd9Sstevel@tonic-gate /*
8317c478bd9Sstevel@tonic-gate * If we've been handed an existing configuration, we need only preset
8327c478bd9Sstevel@tonic-gate * the counter value.
8337c478bd9Sstevel@tonic-gate */
8347c478bd9Sstevel@tonic-gate if (*data != NULL) {
8357c478bd9Sstevel@tonic-gate cfg = *data;
8367c478bd9Sstevel@tonic-gate cfg->opt_rawpic = preset & MASK48;
8377c478bd9Sstevel@tonic-gate return (0);
8387c478bd9Sstevel@tonic-gate }
8397c478bd9Sstevel@tonic-gate
840d0e58ef5SRobert Mustacchi if (picnum >= opd.opd_ncounters)
8417c478bd9Sstevel@tonic-gate return (CPC_INVALID_PICNUM);
8427c478bd9Sstevel@tonic-gate
8435d3a5ad8Srab if ((evp = find_event(event)) == NULL) {
844c7a079a8SJonathan Haslam if ((gevp = find_generic_event(event)) != NULL) {
845c7a079a8SJonathan Haslam evp = find_event(gevp->event);
846c7a079a8SJonathan Haslam ASSERT(evp != NULL);
8475d3a5ad8Srab
848c7a079a8SJonathan Haslam if (nattrs > 0)
849c7a079a8SJonathan Haslam return (CPC_ATTRIBUTE_OUT_OF_RANGE);
8505d3a5ad8Srab
851c7a079a8SJonathan Haslam evsel |= gevp->umask << OPT_PES_UMASK_SHIFT;
852c7a079a8SJonathan Haslam } else {
853c7a079a8SJonathan Haslam long tmp;
854c7a079a8SJonathan Haslam
855c7a079a8SJonathan Haslam /*
856c7a079a8SJonathan Haslam * If ddi_strtol() likes this event, use it as a raw
857c7a079a8SJonathan Haslam * event code.
858c7a079a8SJonathan Haslam */
859c7a079a8SJonathan Haslam if (ddi_strtol(event, NULL, 0, &tmp) != 0)
860c7a079a8SJonathan Haslam return (CPC_INVALID_EVENT);
861c7a079a8SJonathan Haslam
862c7a079a8SJonathan Haslam ev_raw.emask = tmp;
863c7a079a8SJonathan Haslam evp = &ev_raw;
864c7a079a8SJonathan Haslam }
8655d3a5ad8Srab }
8667c478bd9Sstevel@tonic-gate
86731725658Sksadhukh /*
868e850fb01SKuriakose Kuruvilla * Configuration of EventSelect register. While on some families
869e850fb01SKuriakose Kuruvilla * certain bits might not be supported (e.g. Guest/Host on family
870e850fb01SKuriakose Kuruvilla * 11h), setting these bits is harmless
87131725658Sksadhukh */
87231725658Sksadhukh
873e850fb01SKuriakose Kuruvilla /* Set GuestOnly bit to 0 and HostOnly bit to 1 */
874e850fb01SKuriakose Kuruvilla evsel &= ~OPT_PES_HOST;
875e850fb01SKuriakose Kuruvilla evsel &= ~OPT_PES_GUEST;
87631725658Sksadhukh
877e850fb01SKuriakose Kuruvilla /* Set bits [35:32] for extended part of Event Select field */
878e850fb01SKuriakose Kuruvilla evsel_tmp = evp->emask & 0x0f00;
879d0e58ef5SRobert Mustacchi evsel |= evsel_tmp << OPT_PES_EVSELHI_SHIFT;
88031725658Sksadhukh
88131725658Sksadhukh evsel |= evp->emask & 0x00ff;
882d0e58ef5SRobert Mustacchi evsel |= evp->unit << OPT_PES_UMASK_SHIFT;
8837c478bd9Sstevel@tonic-gate
8847c478bd9Sstevel@tonic-gate if (flags & CPC_COUNT_USER)
8857c478bd9Sstevel@tonic-gate evsel |= OPT_PES_USR;
8867c478bd9Sstevel@tonic-gate if (flags & CPC_COUNT_SYSTEM)
8877c478bd9Sstevel@tonic-gate evsel |= OPT_PES_OS;
8887c478bd9Sstevel@tonic-gate if (flags & CPC_OVF_NOTIFY_EMT)
8897c478bd9Sstevel@tonic-gate evsel |= OPT_PES_INT;
8907c478bd9Sstevel@tonic-gate
8917c478bd9Sstevel@tonic-gate for (i = 0; i < nattrs; i++) {
8927c478bd9Sstevel@tonic-gate if (strcmp(attrs[i].ka_name, "edge") == 0) {
8937c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0)
8947c478bd9Sstevel@tonic-gate evsel |= OPT_PES_EDGE;
8957c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "pc") == 0) {
8967c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0)
8977c478bd9Sstevel@tonic-gate evsel |= OPT_PES_PC;
8987c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "inv") == 0) {
8997c478bd9Sstevel@tonic-gate if (attrs[i].ka_val != 0)
9007c478bd9Sstevel@tonic-gate evsel |= OPT_PES_INV;
9017c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "cmask") == 0) {
9027c478bd9Sstevel@tonic-gate if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) !=
9037c478bd9Sstevel@tonic-gate OPT_PES_CMASK_MASK)
9047c478bd9Sstevel@tonic-gate return (CPC_ATTRIBUTE_OUT_OF_RANGE);
9057c478bd9Sstevel@tonic-gate evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT;
9067c478bd9Sstevel@tonic-gate } else if (strcmp(attrs[i].ka_name, "umask") == 0) {
907e850fb01SKuriakose Kuruvilla if ((attrs[i].ka_val | OPT_PES_UMASK_MASK) !=
908e850fb01SKuriakose Kuruvilla OPT_PES_UMASK_MASK)
9097c478bd9Sstevel@tonic-gate return (CPC_ATTRIBUTE_OUT_OF_RANGE);
9107c478bd9Sstevel@tonic-gate evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT;
9117c478bd9Sstevel@tonic-gate } else
9127c478bd9Sstevel@tonic-gate return (CPC_INVALID_ATTRIBUTE);
9137c478bd9Sstevel@tonic-gate }
9147c478bd9Sstevel@tonic-gate
9157c478bd9Sstevel@tonic-gate cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP);
9167c478bd9Sstevel@tonic-gate
9177c478bd9Sstevel@tonic-gate cfg->opt_picno = picnum;
9187c478bd9Sstevel@tonic-gate cfg->opt_evsel = evsel;
9197c478bd9Sstevel@tonic-gate cfg->opt_rawpic = preset & MASK48;
9207c478bd9Sstevel@tonic-gate
9217c478bd9Sstevel@tonic-gate *data = cfg;
9227c478bd9Sstevel@tonic-gate return (0);
9237c478bd9Sstevel@tonic-gate }
9247c478bd9Sstevel@tonic-gate
9257c478bd9Sstevel@tonic-gate static void
opt_pcbe_program(void * token)9267c478bd9Sstevel@tonic-gate opt_pcbe_program(void *token)
9277c478bd9Sstevel@tonic-gate {
928d0e58ef5SRobert Mustacchi opt_pcbe_config_t *cfgs[OPT_PCBE_EXT_NCOUNTERS] = { &nullcfgs[0],
929d0e58ef5SRobert Mustacchi &nullcfgs[1], &nullcfgs[2],
930d0e58ef5SRobert Mustacchi &nullcfgs[3], &nullcfgs[4],
931d0e58ef5SRobert Mustacchi &nullcfgs[5] };
9327c478bd9Sstevel@tonic-gate opt_pcbe_config_t *pcfg = NULL;
9337c478bd9Sstevel@tonic-gate int i;
934843e1988Sjohnlev ulong_t curcr4 = getcr4();
9357c478bd9Sstevel@tonic-gate
9367c478bd9Sstevel@tonic-gate /*
9377c478bd9Sstevel@tonic-gate * Allow nonprivileged code to read the performance counters if desired.
9387c478bd9Sstevel@tonic-gate */
9397c478bd9Sstevel@tonic-gate if (kcpc_allow_nonpriv(token))
9407c478bd9Sstevel@tonic-gate setcr4(curcr4 | CR4_PCE);
9417c478bd9Sstevel@tonic-gate else
9427c478bd9Sstevel@tonic-gate setcr4(curcr4 & ~CR4_PCE);
9437c478bd9Sstevel@tonic-gate
9447c478bd9Sstevel@tonic-gate /*
9457c478bd9Sstevel@tonic-gate * Query kernel for all configs which will be co-programmed.
9467c478bd9Sstevel@tonic-gate */
9477c478bd9Sstevel@tonic-gate do {
9487c478bd9Sstevel@tonic-gate pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL);
9497c478bd9Sstevel@tonic-gate
9507c478bd9Sstevel@tonic-gate if (pcfg != NULL) {
951d0e58ef5SRobert Mustacchi ASSERT(pcfg->opt_picno < opd.opd_ncounters);
9527c478bd9Sstevel@tonic-gate cfgs[pcfg->opt_picno] = pcfg;
9537c478bd9Sstevel@tonic-gate }
9547c478bd9Sstevel@tonic-gate } while (pcfg != NULL);
9557c478bd9Sstevel@tonic-gate
9567c478bd9Sstevel@tonic-gate /*
9577c478bd9Sstevel@tonic-gate * Program in two loops. The first configures and presets the counter,
9587c478bd9Sstevel@tonic-gate * and the second loop enables the counters. This ensures that the
9597c478bd9Sstevel@tonic-gate * counters are all enabled as closely together in time as possible.
9607c478bd9Sstevel@tonic-gate */
9617c478bd9Sstevel@tonic-gate
962d0e58ef5SRobert Mustacchi for (i = 0; i < opd.opd_ncounters; i++) {
963d0e58ef5SRobert Mustacchi wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel);
964d0e58ef5SRobert Mustacchi wrmsr(opd.opd_picf(i), cfgs[i]->opt_rawpic);
9657c478bd9Sstevel@tonic-gate }
9667c478bd9Sstevel@tonic-gate
967d0e58ef5SRobert Mustacchi for (i = 0; i < opd.opd_ncounters; i++) {
968d0e58ef5SRobert Mustacchi wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel |
9690ac7d7d8Skucharsk (uint64_t)(uintptr_t)OPT_PES_ENABLE);
9707c478bd9Sstevel@tonic-gate }
9717c478bd9Sstevel@tonic-gate }
9727c478bd9Sstevel@tonic-gate
9737c478bd9Sstevel@tonic-gate static void
opt_pcbe_allstop(void)9747c478bd9Sstevel@tonic-gate opt_pcbe_allstop(void)
9757c478bd9Sstevel@tonic-gate {
9767c478bd9Sstevel@tonic-gate int i;
9777c478bd9Sstevel@tonic-gate
978d0e58ef5SRobert Mustacchi for (i = 0; i < opd.opd_ncounters; i++)
979d0e58ef5SRobert Mustacchi wrmsr(opd.opd_pesf(i), 0ULL);
9807c478bd9Sstevel@tonic-gate
9817c478bd9Sstevel@tonic-gate /*
9827c478bd9Sstevel@tonic-gate * Disable non-privileged access to the counter registers.
9837c478bd9Sstevel@tonic-gate */
984843e1988Sjohnlev setcr4(getcr4() & ~CR4_PCE);
9857c478bd9Sstevel@tonic-gate }
9867c478bd9Sstevel@tonic-gate
9877c478bd9Sstevel@tonic-gate static void
opt_pcbe_sample(void * token)9887c478bd9Sstevel@tonic-gate opt_pcbe_sample(void *token)
9897c478bd9Sstevel@tonic-gate {
990d0e58ef5SRobert Mustacchi opt_pcbe_config_t *cfgs[OPT_PCBE_EXT_NCOUNTERS] = { NULL, NULL,
991d0e58ef5SRobert Mustacchi NULL, NULL, NULL, NULL };
9927c478bd9Sstevel@tonic-gate opt_pcbe_config_t *pcfg = NULL;
9937c478bd9Sstevel@tonic-gate int i;
994d0e58ef5SRobert Mustacchi uint64_t curpic[OPT_PCBE_EXT_NCOUNTERS];
995d0e58ef5SRobert Mustacchi uint64_t *addrs[OPT_PCBE_EXT_NCOUNTERS];
9967c478bd9Sstevel@tonic-gate uint64_t *tmp;
9977c478bd9Sstevel@tonic-gate int64_t diff;
9987c478bd9Sstevel@tonic-gate
999d0e58ef5SRobert Mustacchi for (i = 0; i < opd.opd_ncounters; i++)
1000d0e58ef5SRobert Mustacchi curpic[i] = rdmsr(opd.opd_picf(i));
10017c478bd9Sstevel@tonic-gate
10027c478bd9Sstevel@tonic-gate /*
10037c478bd9Sstevel@tonic-gate * Query kernel for all configs which are co-programmed.
10047c478bd9Sstevel@tonic-gate */
10057c478bd9Sstevel@tonic-gate do {
10067c478bd9Sstevel@tonic-gate pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp);
10077c478bd9Sstevel@tonic-gate
10087c478bd9Sstevel@tonic-gate if (pcfg != NULL) {
1009d0e58ef5SRobert Mustacchi ASSERT3U(pcfg->opt_picno, <, opd.opd_ncounters);
10107c478bd9Sstevel@tonic-gate cfgs[pcfg->opt_picno] = pcfg;
10117c478bd9Sstevel@tonic-gate addrs[pcfg->opt_picno] = tmp;
10127c478bd9Sstevel@tonic-gate }
10137c478bd9Sstevel@tonic-gate } while (pcfg != NULL);
10147c478bd9Sstevel@tonic-gate
1015d0e58ef5SRobert Mustacchi for (i = 0; i < opd.opd_ncounters; i++) {
10167c478bd9Sstevel@tonic-gate if (cfgs[i] == NULL)
10177c478bd9Sstevel@tonic-gate continue;
10187c478bd9Sstevel@tonic-gate
10197c478bd9Sstevel@tonic-gate diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48;
10207c478bd9Sstevel@tonic-gate *addrs[i] += diff;
10217c478bd9Sstevel@tonic-gate DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i],
10227c478bd9Sstevel@tonic-gate uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic);
10237c478bd9Sstevel@tonic-gate cfgs[i]->opt_rawpic = *addrs[i] & MASK48;
10247c478bd9Sstevel@tonic-gate }
10257c478bd9Sstevel@tonic-gate }
10267c478bd9Sstevel@tonic-gate
10277c478bd9Sstevel@tonic-gate static void
opt_pcbe_free(void * config)10287c478bd9Sstevel@tonic-gate opt_pcbe_free(void *config)
10297c478bd9Sstevel@tonic-gate {
10307c478bd9Sstevel@tonic-gate kmem_free(config, sizeof (opt_pcbe_config_t));
10317c478bd9Sstevel@tonic-gate }
10327c478bd9Sstevel@tonic-gate
10337c478bd9Sstevel@tonic-gate
10347c478bd9Sstevel@tonic-gate static struct modlpcbe modlpcbe = {
10357c478bd9Sstevel@tonic-gate &mod_pcbeops,
1036820c9f58Skk "AMD Performance Counters",
10377c478bd9Sstevel@tonic-gate &opt_pcbe_ops
10387c478bd9Sstevel@tonic-gate };
10397c478bd9Sstevel@tonic-gate
10407c478bd9Sstevel@tonic-gate static struct modlinkage modl = {
10417c478bd9Sstevel@tonic-gate MODREV_1,
10427c478bd9Sstevel@tonic-gate &modlpcbe,
10437c478bd9Sstevel@tonic-gate };
10447c478bd9Sstevel@tonic-gate
10457c478bd9Sstevel@tonic-gate int
_init(void)10467c478bd9Sstevel@tonic-gate _init(void)
10477c478bd9Sstevel@tonic-gate {
10487c478bd9Sstevel@tonic-gate int ret;
10497c478bd9Sstevel@tonic-gate
10507c478bd9Sstevel@tonic-gate if (opt_pcbe_init() != 0)
10517c478bd9Sstevel@tonic-gate return (ENOTSUP);
10527c478bd9Sstevel@tonic-gate
10537c478bd9Sstevel@tonic-gate if ((ret = mod_install(&modl)) != 0)
10547c478bd9Sstevel@tonic-gate kmem_free(evlist, evlist_sz + 1);
10557c478bd9Sstevel@tonic-gate
10567c478bd9Sstevel@tonic-gate return (ret);
10577c478bd9Sstevel@tonic-gate }
10587c478bd9Sstevel@tonic-gate
10597c478bd9Sstevel@tonic-gate int
_fini(void)10607c478bd9Sstevel@tonic-gate _fini(void)
10617c478bd9Sstevel@tonic-gate {
10627c478bd9Sstevel@tonic-gate int ret;
10637c478bd9Sstevel@tonic-gate
10647c478bd9Sstevel@tonic-gate if ((ret = mod_remove(&modl)) == 0)
10657c478bd9Sstevel@tonic-gate kmem_free(evlist, evlist_sz + 1);
10667c478bd9Sstevel@tonic-gate return (ret);
10677c478bd9Sstevel@tonic-gate }
10687c478bd9Sstevel@tonic-gate
10697c478bd9Sstevel@tonic-gate int
_info(struct modinfo * mi)10707c478bd9Sstevel@tonic-gate _info(struct modinfo *mi)
10717c478bd9Sstevel@tonic-gate {
10727c478bd9Sstevel@tonic-gate return (mod_info(&modl, mi));
10737c478bd9Sstevel@tonic-gate }
1074