1*62dadd65SYuri Pankov /* 2*62dadd65SYuri Pankov * Copyright (C) 2007 VMware, Inc. All rights reserved. 3*62dadd65SYuri Pankov * 4*62dadd65SYuri Pankov * The contents of this file are subject to the terms of the Common 5*62dadd65SYuri Pankov * Development and Distribution License (the "License") version 1.0 6*62dadd65SYuri Pankov * and no later version. You may not use this file except in 7*62dadd65SYuri Pankov * compliance with the License. 8*62dadd65SYuri Pankov * 9*62dadd65SYuri Pankov * You can obtain a copy of the License at 10*62dadd65SYuri Pankov * http://www.opensource.org/licenses/cddl1.php 11*62dadd65SYuri Pankov * 12*62dadd65SYuri Pankov * See the License for the specific language governing permissions 13*62dadd65SYuri Pankov * and limitations under the License. 14*62dadd65SYuri Pankov */ 15*62dadd65SYuri Pankov 16*62dadd65SYuri Pankov /* 17*62dadd65SYuri Pankov * vmxnet3_defs.h -- 18*62dadd65SYuri Pankov * 19*62dadd65SYuri Pankov * Definitions shared by device emulation and guest drivers for 20*62dadd65SYuri Pankov * VMXNET3 NIC 21*62dadd65SYuri Pankov */ 22*62dadd65SYuri Pankov 23*62dadd65SYuri Pankov #ifndef _VMXNET3_DEFS_H_ 24*62dadd65SYuri Pankov #define _VMXNET3_DEFS_H_ 25*62dadd65SYuri Pankov 26*62dadd65SYuri Pankov #include <upt1_defs.h> 27*62dadd65SYuri Pankov 28*62dadd65SYuri Pankov /* all registers are 32 bit wide */ 29*62dadd65SYuri Pankov /* BAR 1 */ 30*62dadd65SYuri Pankov #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */ 31*62dadd65SYuri Pankov #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */ 32*62dadd65SYuri Pankov #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */ 33*62dadd65SYuri Pankov #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */ 34*62dadd65SYuri Pankov #define VMXNET3_REG_CMD 0x20 /* Command */ 35*62dadd65SYuri Pankov #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */ 36*62dadd65SYuri Pankov #define VMXNET3_REG_MACH 0x30 /* MAC Address High */ 37*62dadd65SYuri Pankov #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */ 38*62dadd65SYuri Pankov #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */ 39*62dadd65SYuri Pankov 40*62dadd65SYuri Pankov #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */ 41*62dadd65SYuri Pankov #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */ 42*62dadd65SYuri Pankov #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */ 43*62dadd65SYuri Pankov 44*62dadd65SYuri Pankov /* BAR 0 */ 45*62dadd65SYuri Pankov #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */ 46*62dadd65SYuri Pankov #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */ 47*62dadd65SYuri Pankov #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */ 48*62dadd65SYuri Pankov #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */ 49*62dadd65SYuri Pankov 50*62dadd65SYuri Pankov #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 51*62dadd65SYuri Pankov #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 52*62dadd65SYuri Pankov 53*62dadd65SYuri Pankov /* 54*62dadd65SYuri Pankov * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at 55*62dadd65SYuri Pankov * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region: 56*62dadd65SYuri Pankov * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE--> 57*62dadd65SYuri Pankov * ------------------------------------------------------------------------- 58*62dadd65SYuri Pankov * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table | 59*62dadd65SYuri Pankov * ------------------------------------------------------------------------- 60*62dadd65SYuri Pankov * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h" 61*62dadd65SYuri Pankov */ 62*62dadd65SYuri Pankov #define VMXNET3_PHYSMEM_PAGES 4 63*62dadd65SYuri Pankov 64*62dadd65SYuri Pankov #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 65*62dadd65SYuri Pankov #define VMXNET3_REG_ALIGN_MASK 0x7 66*62dadd65SYuri Pankov 67*62dadd65SYuri Pankov /* I/O Mapped access to registers */ 68*62dadd65SYuri Pankov #define VMXNET3_IO_TYPE_PT 0 69*62dadd65SYuri Pankov #define VMXNET3_IO_TYPE_VD 1 70*62dadd65SYuri Pankov #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 71*62dadd65SYuri Pankov #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 72*62dadd65SYuri Pankov #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 73*62dadd65SYuri Pankov 74*62dadd65SYuri Pankov /* 75*62dadd65SYuri Pankov * The Sun Studio compiler complains if enums overflow INT_MAX, so we can only 76*62dadd65SYuri Pankov * use an enum with gcc. We keep this here for the convenience of merging 77*62dadd65SYuri Pankov * from upstream. 78*62dadd65SYuri Pankov */ 79*62dadd65SYuri Pankov #ifdef __GNUC__ 80*62dadd65SYuri Pankov 81*62dadd65SYuri Pankov typedef enum { 82*62dadd65SYuri Pankov VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 83*62dadd65SYuri Pankov VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 84*62dadd65SYuri Pankov VMXNET3_CMD_QUIESCE_DEV, 85*62dadd65SYuri Pankov VMXNET3_CMD_RESET_DEV, 86*62dadd65SYuri Pankov VMXNET3_CMD_UPDATE_RX_MODE, 87*62dadd65SYuri Pankov VMXNET3_CMD_UPDATE_MAC_FILTERS, 88*62dadd65SYuri Pankov VMXNET3_CMD_UPDATE_VLAN_FILTERS, 89*62dadd65SYuri Pankov VMXNET3_CMD_UPDATE_RSSIDT, 90*62dadd65SYuri Pankov VMXNET3_CMD_UPDATE_IML, 91*62dadd65SYuri Pankov VMXNET3_CMD_UPDATE_PMCFG, 92*62dadd65SYuri Pankov VMXNET3_CMD_UPDATE_FEATURE, 93*62dadd65SYuri Pankov VMXNET3_CMD_STOP_EMULATION, 94*62dadd65SYuri Pankov VMXNET3_CMD_LOAD_PLUGIN, 95*62dadd65SYuri Pankov VMXNET3_CMD_ACTIVATE_VF, 96*62dadd65SYuri Pankov 97*62dadd65SYuri Pankov VMXNET3_CMD_FIRST_GET = 0xF00D0000, 98*62dadd65SYuri Pankov VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 99*62dadd65SYuri Pankov VMXNET3_CMD_GET_STATS, 100*62dadd65SYuri Pankov VMXNET3_CMD_GET_LINK, 101*62dadd65SYuri Pankov VMXNET3_CMD_GET_PERM_MAC_LO, 102*62dadd65SYuri Pankov VMXNET3_CMD_GET_PERM_MAC_HI, 103*62dadd65SYuri Pankov VMXNET3_CMD_GET_DID_LO, 104*62dadd65SYuri Pankov VMXNET3_CMD_GET_DID_HI, 105*62dadd65SYuri Pankov VMXNET3_CMD_GET_DEV_EXTRA_INFO, 106*62dadd65SYuri Pankov VMXNET3_CMD_GET_CONF_INTR, 107*62dadd65SYuri Pankov VMXNET3_CMD_GET_ADAPTIVE_RING_INFO 108*62dadd65SYuri Pankov } Vmxnet3_Cmd; 109*62dadd65SYuri Pankov 110*62dadd65SYuri Pankov #else 111*62dadd65SYuri Pankov 112*62dadd65SYuri Pankov #define VMXNET3_CMD_FIRST_SET 0xCAFE0000U 113*62dadd65SYuri Pankov #define VMXNET3_CMD_ACTIVATE_DEV VMXNET3_CMD_FIRST_SET 114*62dadd65SYuri Pankov #define VMXNET3_CMD_QUIESCE_DEV (VMXNET3_CMD_FIRST_SET + 1) 115*62dadd65SYuri Pankov #define VMXNET3_CMD_RESET_DEV (VMXNET3_CMD_FIRST_SET + 2) 116*62dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_RX_MODE (VMXNET3_CMD_FIRST_SET + 3) 117*62dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_MAC_FILTERS (VMXNET3_CMD_FIRST_SET + 4) 118*62dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_VLAN_FILTERS (VMXNET3_CMD_FIRST_SET + 5) 119*62dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_RSSIDT (VMXNET3_CMD_FIRST_SET + 6) 120*62dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_IML (VMXNET3_CMD_FIRST_SET + 7) 121*62dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_PMCFG (VMXNET3_CMD_FIRST_SET + 8) 122*62dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_FEATURE (VMXNET3_CMD_FIRST_SET + 9) 123*62dadd65SYuri Pankov #define VMXNET3_CMD_STOP_EMULATION (VMXNET3_CMD_FIRST_SET + 10) 124*62dadd65SYuri Pankov #define VMXNET3_CMD_LOAD_PLUGIN (VMXNET3_CMD_FIRST_SET + 11) 125*62dadd65SYuri Pankov #define VMXNET3_CMD_ACTIVATE_VF (VMXNET3_CMD_FIRST_SET + 12) 126*62dadd65SYuri Pankov 127*62dadd65SYuri Pankov #define VMXNET3_CMD_FIRST_GET 0xF00D0000U 128*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_QUEUE_STATUS VMXNET3_CMD_FIRST_GET 129*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_STATS (VMXNET3_CMD_FIRST_GET + 1) 130*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_LINK (VMXNET3_CMD_FIRST_GET + 2) 131*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_PERM_MAC_LO (VMXNET3_CMD_FIRST_GET + 3) 132*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_PERM_MAC_HI (VMXNET3_CMD_FIRST_GET + 4) 133*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_DID_LO (VMXNET3_CMD_FIRST_GET + 5) 134*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_DID_HI (VMXNET3_CMD_FIRST_GET + 6) 135*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_DEV_EXTRA_INFO (VMXNET3_CMD_FIRST_GET + 7) 136*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_CONF_INTR (VMXNET3_CMD_FIRST_GET + 8) 137*62dadd65SYuri Pankov #define VMXNET3_CMD_GET_ADAPTIVE_RING_INFO (VMXNET3_CMD_FIRST_GET + 9) 138*62dadd65SYuri Pankov 139*62dadd65SYuri Pankov #endif 140*62dadd65SYuri Pankov 141*62dadd65SYuri Pankov /* Adaptive Ring Info Flags */ 142*62dadd65SYuri Pankov #define VMXNET3_DISABLE_ADAPTIVE_RING 1 143*62dadd65SYuri Pankov 144*62dadd65SYuri Pankov #pragma pack(1) 145*62dadd65SYuri Pankov typedef struct Vmxnet3_TxDesc { 146*62dadd65SYuri Pankov uint64_t addr; 147*62dadd65SYuri Pankov uint32_t len:14; 148*62dadd65SYuri Pankov uint32_t gen:1; /* generation bit */ 149*62dadd65SYuri Pankov uint32_t rsvd:1; 150*62dadd65SYuri Pankov uint32_t dtype:1; /* descriptor type */ 151*62dadd65SYuri Pankov uint32_t ext1:1; 152*62dadd65SYuri Pankov uint32_t msscof:14; /* MSS, checksum offset, flags */ 153*62dadd65SYuri Pankov uint32_t hlen:10; /* header len */ 154*62dadd65SYuri Pankov uint32_t om:2; /* offload mode */ 155*62dadd65SYuri Pankov uint32_t eop:1; /* End Of Packet */ 156*62dadd65SYuri Pankov uint32_t cq:1; /* completion request */ 157*62dadd65SYuri Pankov uint32_t ext2:1; 158*62dadd65SYuri Pankov uint32_t ti:1; /* VLAN Tag Insertion */ 159*62dadd65SYuri Pankov uint32_t tci:16; /* Tag to Insert */ 160*62dadd65SYuri Pankov } Vmxnet3_TxDesc; 161*62dadd65SYuri Pankov #pragma pack() 162*62dadd65SYuri Pankov 163*62dadd65SYuri Pankov /* TxDesc.OM values */ 164*62dadd65SYuri Pankov #define VMXNET3_OM_NONE 0 165*62dadd65SYuri Pankov #define VMXNET3_OM_CSUM 2 166*62dadd65SYuri Pankov #define VMXNET3_OM_TSO 3 167*62dadd65SYuri Pankov 168*62dadd65SYuri Pankov /* fields in TxDesc we access w/o using bit fields */ 169*62dadd65SYuri Pankov #define VMXNET3_TXD_EOP_SHIFT 12 170*62dadd65SYuri Pankov #define VMXNET3_TXD_CQ_SHIFT 13 171*62dadd65SYuri Pankov #define VMXNET3_TXD_GEN_SHIFT 14 172*62dadd65SYuri Pankov #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 173*62dadd65SYuri Pankov #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 174*62dadd65SYuri Pankov 175*62dadd65SYuri Pankov #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 176*62dadd65SYuri Pankov #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 177*62dadd65SYuri Pankov #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 178*62dadd65SYuri Pankov 179*62dadd65SYuri Pankov #define VMXNET3_TXD_GEN_SIZE 1 180*62dadd65SYuri Pankov #define VMXNET3_TXD_EOP_SIZE 1 181*62dadd65SYuri Pankov 182*62dadd65SYuri Pankov #define VMXNET3_HDR_COPY_SIZE 128 183*62dadd65SYuri Pankov 184*62dadd65SYuri Pankov #pragma pack(1) 185*62dadd65SYuri Pankov typedef struct Vmxnet3_TxDataDesc { 186*62dadd65SYuri Pankov uint8_t data[VMXNET3_HDR_COPY_SIZE]; 187*62dadd65SYuri Pankov } Vmxnet3_TxDataDesc; 188*62dadd65SYuri Pankov #pragma pack() 189*62dadd65SYuri Pankov 190*62dadd65SYuri Pankov #define VMXNET3_TCD_GEN_SHIFT 31 191*62dadd65SYuri Pankov #define VMXNET3_TCD_GEN_SIZE 1 192*62dadd65SYuri Pankov #define VMXNET3_TCD_TXIDX_SHIFT 0 193*62dadd65SYuri Pankov #define VMXNET3_TCD_TXIDX_SIZE 12 194*62dadd65SYuri Pankov #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 195*62dadd65SYuri Pankov 196*62dadd65SYuri Pankov #pragma pack(1) 197*62dadd65SYuri Pankov typedef struct Vmxnet3_TxCompDesc { 198*62dadd65SYuri Pankov uint32_t txdIdx:12; /* Index of the EOP TxDesc */ 199*62dadd65SYuri Pankov uint32_t ext1:20; 200*62dadd65SYuri Pankov 201*62dadd65SYuri Pankov uint32_t ext2; 202*62dadd65SYuri Pankov uint32_t ext3; 203*62dadd65SYuri Pankov 204*62dadd65SYuri Pankov uint32_t rsvd:24; 205*62dadd65SYuri Pankov uint32_t type:7; /* completion type */ 206*62dadd65SYuri Pankov uint32_t gen:1; /* generation bit */ 207*62dadd65SYuri Pankov } Vmxnet3_TxCompDesc; 208*62dadd65SYuri Pankov #pragma pack() 209*62dadd65SYuri Pankov 210*62dadd65SYuri Pankov #pragma pack(1) 211*62dadd65SYuri Pankov typedef struct Vmxnet3_RxDesc { 212*62dadd65SYuri Pankov uint64_t addr; 213*62dadd65SYuri Pankov uint32_t len:14; 214*62dadd65SYuri Pankov uint32_t btype:1; /* Buffer Type */ 215*62dadd65SYuri Pankov uint32_t dtype:1; /* Descriptor type */ 216*62dadd65SYuri Pankov uint32_t rsvd:15; 217*62dadd65SYuri Pankov uint32_t gen:1; /* Generation bit */ 218*62dadd65SYuri Pankov uint32_t ext1; 219*62dadd65SYuri Pankov } Vmxnet3_RxDesc; 220*62dadd65SYuri Pankov #pragma pack() 221*62dadd65SYuri Pankov 222*62dadd65SYuri Pankov /* values of RXD.BTYPE */ 223*62dadd65SYuri Pankov #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 224*62dadd65SYuri Pankov #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 225*62dadd65SYuri Pankov 226*62dadd65SYuri Pankov /* fields in RxDesc we access w/o using bit fields */ 227*62dadd65SYuri Pankov #define VMXNET3_RXD_BTYPE_SHIFT 14 228*62dadd65SYuri Pankov #define VMXNET3_RXD_GEN_SHIFT 31 229*62dadd65SYuri Pankov 230*62dadd65SYuri Pankov #pragma pack(1) 231*62dadd65SYuri Pankov typedef struct Vmxnet3_RxCompDesc { 232*62dadd65SYuri Pankov uint32_t rxdIdx:12; /* Index of the RxDesc */ 233*62dadd65SYuri Pankov uint32_t ext1:2; 234*62dadd65SYuri Pankov uint32_t eop:1; /* End of Packet */ 235*62dadd65SYuri Pankov uint32_t sop:1; /* Start of Packet */ 236*62dadd65SYuri Pankov uint32_t rqID:10; /* rx queue/ring ID */ 237*62dadd65SYuri Pankov uint32_t rssType:4; /* RSS hash type used */ 238*62dadd65SYuri Pankov uint32_t cnc:1; /* Checksum Not Calculated */ 239*62dadd65SYuri Pankov uint32_t ext2:1; 240*62dadd65SYuri Pankov uint32_t rssHash; /* RSS hash value */ 241*62dadd65SYuri Pankov uint32_t len:14; /* data length */ 242*62dadd65SYuri Pankov uint32_t err:1; /* Error */ 243*62dadd65SYuri Pankov uint32_t ts:1; /* Tag is stripped */ 244*62dadd65SYuri Pankov uint32_t tci:16; /* Tag stripped */ 245*62dadd65SYuri Pankov uint32_t csum:16; 246*62dadd65SYuri Pankov uint32_t tuc:1; /* TCP/UDP Checksum Correct */ 247*62dadd65SYuri Pankov uint32_t udp:1; /* UDP packet */ 248*62dadd65SYuri Pankov uint32_t tcp:1; /* TCP packet */ 249*62dadd65SYuri Pankov uint32_t ipc:1; /* IP Checksum Correct */ 250*62dadd65SYuri Pankov uint32_t v6:1; /* IPv6 */ 251*62dadd65SYuri Pankov uint32_t v4:1; /* IPv4 */ 252*62dadd65SYuri Pankov uint32_t frg:1; /* IP Fragment */ 253*62dadd65SYuri Pankov uint32_t fcs:1; /* Frame CRC correct */ 254*62dadd65SYuri Pankov uint32_t type:7; /* completion type */ 255*62dadd65SYuri Pankov uint32_t gen:1; /* generation bit */ 256*62dadd65SYuri Pankov } Vmxnet3_RxCompDesc; 257*62dadd65SYuri Pankov #pragma pack() 258*62dadd65SYuri Pankov 259*62dadd65SYuri Pankov /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 260*62dadd65SYuri Pankov #define VMXNET3_RCD_TUC_SHIFT 16 261*62dadd65SYuri Pankov #define VMXNET3_RCD_IPC_SHIFT 19 262*62dadd65SYuri Pankov 263*62dadd65SYuri Pankov /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 264*62dadd65SYuri Pankov #define VMXNET3_RCD_TYPE_SHIFT 56 265*62dadd65SYuri Pankov #define VMXNET3_RCD_GEN_SHIFT 63 266*62dadd65SYuri Pankov 267*62dadd65SYuri Pankov /* csum OK for TCP/UDP pkts over IP */ 268*62dadd65SYuri Pankov #define VMXNET3_RCD_CSUM_OK \ 269*62dadd65SYuri Pankov (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT) 270*62dadd65SYuri Pankov 271*62dadd65SYuri Pankov /* value of RxCompDesc.rssType */ 272*62dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_NONE 0 273*62dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_IPV4 1 274*62dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2 275*62dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_IPV6 3 276*62dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4 277*62dadd65SYuri Pankov 278*62dadd65SYuri Pankov /* a union for accessing all cmd/completion descriptors */ 279*62dadd65SYuri Pankov typedef union Vmxnet3_GenericDesc { 280*62dadd65SYuri Pankov uint64_t qword[2]; 281*62dadd65SYuri Pankov uint32_t dword[4]; 282*62dadd65SYuri Pankov uint16_t word[8]; 283*62dadd65SYuri Pankov Vmxnet3_TxDesc txd; 284*62dadd65SYuri Pankov Vmxnet3_RxDesc rxd; 285*62dadd65SYuri Pankov Vmxnet3_TxCompDesc tcd; 286*62dadd65SYuri Pankov Vmxnet3_RxCompDesc rcd; 287*62dadd65SYuri Pankov } Vmxnet3_GenericDesc; 288*62dadd65SYuri Pankov 289*62dadd65SYuri Pankov #define VMXNET3_INIT_GEN 1 290*62dadd65SYuri Pankov 291*62dadd65SYuri Pankov /* Max size of a single tx buffer */ 292*62dadd65SYuri Pankov #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 293*62dadd65SYuri Pankov 294*62dadd65SYuri Pankov /* # of tx desc needed for a tx buffer size */ 295*62dadd65SYuri Pankov #define VMXNET3_TXD_NEEDED(size) \ 296*62dadd65SYuri Pankov (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE) 297*62dadd65SYuri Pankov 298*62dadd65SYuri Pankov /* max # of tx descs for a non-tso pkt */ 299*62dadd65SYuri Pankov #define VMXNET3_MAX_TXD_PER_PKT 16 300*62dadd65SYuri Pankov 301*62dadd65SYuri Pankov /* Max size of a single rx buffer */ 302*62dadd65SYuri Pankov #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 303*62dadd65SYuri Pankov /* Minimum size of a type 0 buffer */ 304*62dadd65SYuri Pankov #define VMXNET3_MIN_T0_BUF_SIZE 128 305*62dadd65SYuri Pankov #define VMXNET3_MAX_CSUM_OFFSET 1024 306*62dadd65SYuri Pankov 307*62dadd65SYuri Pankov /* Ring base address alignment */ 308*62dadd65SYuri Pankov #define VMXNET3_RING_BA_ALIGN 512 309*62dadd65SYuri Pankov #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 310*62dadd65SYuri Pankov 311*62dadd65SYuri Pankov /* Ring size must be a multiple of 32 */ 312*62dadd65SYuri Pankov #define VMXNET3_RING_SIZE_ALIGN 32 313*62dadd65SYuri Pankov #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 314*62dadd65SYuri Pankov 315*62dadd65SYuri Pankov /* Max ring size */ 316*62dadd65SYuri Pankov #define VMXNET3_TX_RING_MAX_SIZE 4096 317*62dadd65SYuri Pankov #define VMXNET3_TC_RING_MAX_SIZE 4096 318*62dadd65SYuri Pankov #define VMXNET3_RX_RING_MAX_SIZE 4096 319*62dadd65SYuri Pankov #define VMXNET3_RC_RING_MAX_SIZE 8192 320*62dadd65SYuri Pankov 321*62dadd65SYuri Pankov /* a list of reasons for queue stop */ 322*62dadd65SYuri Pankov 323*62dadd65SYuri Pankov #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the */ 324*62dadd65SYuri Pankov /* EOP desc of a pkt */ 325*62dadd65SYuri Pankov #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx */ 326*62dadd65SYuri Pankov /* completion */ 327*62dadd65SYuri Pankov #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */ 328*62dadd65SYuri Pankov #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not */ 329*62dadd65SYuri Pankov /* supported */ 330*62dadd65SYuri Pankov #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */ 331*62dadd65SYuri Pankov #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing */ 332*62dadd65SYuri Pankov /* in vmkernel */ 333*62dadd65SYuri Pankov #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */ 334*62dadd65SYuri Pankov #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */ 335*62dadd65SYuri Pankov 336*62dadd65SYuri Pankov /* completion descriptor types */ 337*62dadd65SYuri Pankov #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 338*62dadd65SYuri Pankov #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 339*62dadd65SYuri Pankov 340*62dadd65SYuri Pankov #define VMXNET3_GOS_BITS_UNK 0 /* unknown */ 341*62dadd65SYuri Pankov #define VMXNET3_GOS_BITS_32 1 342*62dadd65SYuri Pankov #define VMXNET3_GOS_BITS_64 2 343*62dadd65SYuri Pankov 344*62dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */ 345*62dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_LINUX 1 346*62dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_WIN 2 347*62dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_SOLARIS 3 348*62dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_FREEBSD 4 349*62dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_PXE 5 350*62dadd65SYuri Pankov 351*62dadd65SYuri Pankov /* All structures in DriverShared are padded to multiples of 8 bytes */ 352*62dadd65SYuri Pankov 353*62dadd65SYuri Pankov #pragma pack(1) 354*62dadd65SYuri Pankov typedef struct Vmxnet3_GOSInfo { 355*62dadd65SYuri Pankov uint32_t gosBits: 2; /* 32-bit or 64-bit? */ 356*62dadd65SYuri Pankov uint32_t gosType: 4; /* which guest */ 357*62dadd65SYuri Pankov uint32_t gosVer: 16; /* gos version */ 358*62dadd65SYuri Pankov uint32_t gosMisc: 10; /* other info about gos */ 359*62dadd65SYuri Pankov } Vmxnet3_GOSInfo; 360*62dadd65SYuri Pankov #pragma pack() 361*62dadd65SYuri Pankov 362*62dadd65SYuri Pankov #pragma pack(1) 363*62dadd65SYuri Pankov typedef struct Vmxnet3_DriverInfo { 364*62dadd65SYuri Pankov uint32_t version; /* driver version */ 365*62dadd65SYuri Pankov Vmxnet3_GOSInfo gos; 366*62dadd65SYuri Pankov uint32_t vmxnet3RevSpt; /* vmxnet3 revision supported */ 367*62dadd65SYuri Pankov uint32_t uptVerSpt; /* upt version supported */ 368*62dadd65SYuri Pankov } Vmxnet3_DriverInfo; 369*62dadd65SYuri Pankov #pragma pack() 370*62dadd65SYuri Pankov 371*62dadd65SYuri Pankov #define VMXNET3_REV1_MAGIC 0xbabefee1 372*62dadd65SYuri Pankov 373*62dadd65SYuri Pankov /* 374*62dadd65SYuri Pankov * QueueDescPA must be 128 bytes aligned. It points to an array of 375*62dadd65SYuri Pankov * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 376*62dadd65SYuri Pankov * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 377*62dadd65SYuri Pankov * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 378*62dadd65SYuri Pankov */ 379*62dadd65SYuri Pankov #define VMXNET3_QUEUE_DESC_ALIGN 128 380*62dadd65SYuri Pankov 381*62dadd65SYuri Pankov #pragma pack(1) 382*62dadd65SYuri Pankov typedef struct Vmxnet3_MiscConf { 383*62dadd65SYuri Pankov Vmxnet3_DriverInfo driverInfo; 384*62dadd65SYuri Pankov uint64_t uptFeatures; 385*62dadd65SYuri Pankov uint64_t ddPA; /* driver data PA */ 386*62dadd65SYuri Pankov uint64_t queueDescPA; /* queue descriptor table PA */ 387*62dadd65SYuri Pankov uint32_t ddLen; /* driver data len */ 388*62dadd65SYuri Pankov uint32_t queueDescLen; /* queue descriptor table len, bytes */ 389*62dadd65SYuri Pankov uint32_t mtu; 390*62dadd65SYuri Pankov uint16_t maxNumRxSG; 391*62dadd65SYuri Pankov uint8_t numTxQueues; 392*62dadd65SYuri Pankov uint8_t numRxQueues; 393*62dadd65SYuri Pankov uint32_t reserved[4]; 394*62dadd65SYuri Pankov } Vmxnet3_MiscConf; 395*62dadd65SYuri Pankov #pragma pack() 396*62dadd65SYuri Pankov 397*62dadd65SYuri Pankov #pragma pack(1) 398*62dadd65SYuri Pankov typedef struct Vmxnet3_TxQueueConf { 399*62dadd65SYuri Pankov uint64_t txRingBasePA; 400*62dadd65SYuri Pankov uint64_t dataRingBasePA; 401*62dadd65SYuri Pankov uint64_t compRingBasePA; 402*62dadd65SYuri Pankov uint64_t ddPA; /* driver data */ 403*62dadd65SYuri Pankov uint64_t reserved; 404*62dadd65SYuri Pankov uint32_t txRingSize; /* # of tx desc */ 405*62dadd65SYuri Pankov uint32_t dataRingSize; /* # of data desc */ 406*62dadd65SYuri Pankov uint32_t compRingSize; /* # of comp desc */ 407*62dadd65SYuri Pankov uint32_t ddLen; /* size of driver data */ 408*62dadd65SYuri Pankov uint8_t intrIdx; 409*62dadd65SYuri Pankov uint8_t _pad[7]; 410*62dadd65SYuri Pankov } Vmxnet3_TxQueueConf; 411*62dadd65SYuri Pankov #pragma pack() 412*62dadd65SYuri Pankov 413*62dadd65SYuri Pankov #pragma pack(1) 414*62dadd65SYuri Pankov typedef struct Vmxnet3_RxQueueConf { 415*62dadd65SYuri Pankov uint64_t rxRingBasePA[2]; 416*62dadd65SYuri Pankov uint64_t compRingBasePA; 417*62dadd65SYuri Pankov uint64_t ddPA; /* driver data */ 418*62dadd65SYuri Pankov uint64_t reserved; 419*62dadd65SYuri Pankov uint32_t rxRingSize[2]; /* # of rx desc */ 420*62dadd65SYuri Pankov uint32_t compRingSize; /* # of rx comp desc */ 421*62dadd65SYuri Pankov uint32_t ddLen; /* size of driver data */ 422*62dadd65SYuri Pankov uint8_t intrIdx; 423*62dadd65SYuri Pankov uint8_t _pad[7]; 424*62dadd65SYuri Pankov } Vmxnet3_RxQueueConf; 425*62dadd65SYuri Pankov #pragma pack() 426*62dadd65SYuri Pankov 427*62dadd65SYuri Pankov enum vmxnet3_intr_mask_mode { 428*62dadd65SYuri Pankov VMXNET3_IMM_AUTO = 0, 429*62dadd65SYuri Pankov VMXNET3_IMM_ACTIVE = 1, 430*62dadd65SYuri Pankov VMXNET3_IMM_LAZY = 2 431*62dadd65SYuri Pankov }; 432*62dadd65SYuri Pankov 433*62dadd65SYuri Pankov enum vmxnet3_intr_type { 434*62dadd65SYuri Pankov VMXNET3_IT_AUTO = 0, 435*62dadd65SYuri Pankov VMXNET3_IT_INTX = 1, 436*62dadd65SYuri Pankov VMXNET3_IT_MSI = 2, 437*62dadd65SYuri Pankov VMXNET3_IT_MSIX = 3 438*62dadd65SYuri Pankov }; 439*62dadd65SYuri Pankov 440*62dadd65SYuri Pankov #define VMXNET3_MAX_TX_QUEUES 8 441*62dadd65SYuri Pankov #define VMXNET3_MAX_RX_QUEUES 16 442*62dadd65SYuri Pankov /* addition 1 for events */ 443*62dadd65SYuri Pankov #define VMXNET3_MAX_INTRS 25 444*62dadd65SYuri Pankov 445*62dadd65SYuri Pankov /* value of intrCtrl */ 446*62dadd65SYuri Pankov #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 447*62dadd65SYuri Pankov 448*62dadd65SYuri Pankov #pragma pack(1) 449*62dadd65SYuri Pankov typedef struct Vmxnet3_IntrConf { 450*62dadd65SYuri Pankov char autoMask; 451*62dadd65SYuri Pankov uint8_t numIntrs; /* # of interrupts */ 452*62dadd65SYuri Pankov uint8_t eventIntrIdx; 453*62dadd65SYuri Pankov uint8_t modLevels[VMXNET3_MAX_INTRS]; /* moderation level */ 454*62dadd65SYuri Pankov /* for each intr */ 455*62dadd65SYuri Pankov uint32_t intrCtrl; 456*62dadd65SYuri Pankov uint32_t reserved[2]; 457*62dadd65SYuri Pankov } Vmxnet3_IntrConf; 458*62dadd65SYuri Pankov #pragma pack() 459*62dadd65SYuri Pankov 460*62dadd65SYuri Pankov /* one bit per VLAN ID, the size is in the units of uint32_t */ 461*62dadd65SYuri Pankov #define VMXNET3_VFT_SIZE (4096 / (sizeof (uint32_t) * 8)) 462*62dadd65SYuri Pankov 463*62dadd65SYuri Pankov #pragma pack(1) 464*62dadd65SYuri Pankov typedef struct Vmxnet3_QueueStatus { 465*62dadd65SYuri Pankov char stopped; 466*62dadd65SYuri Pankov uint8_t _pad[3]; 467*62dadd65SYuri Pankov uint32_t error; 468*62dadd65SYuri Pankov } Vmxnet3_QueueStatus; 469*62dadd65SYuri Pankov #pragma pack() 470*62dadd65SYuri Pankov 471*62dadd65SYuri Pankov #pragma pack(1) 472*62dadd65SYuri Pankov typedef struct Vmxnet3_TxQueueCtrl { 473*62dadd65SYuri Pankov uint32_t txNumDeferred; 474*62dadd65SYuri Pankov uint32_t txThreshold; 475*62dadd65SYuri Pankov uint64_t reserved; 476*62dadd65SYuri Pankov } Vmxnet3_TxQueueCtrl; 477*62dadd65SYuri Pankov #pragma pack() 478*62dadd65SYuri Pankov 479*62dadd65SYuri Pankov #pragma pack(1) 480*62dadd65SYuri Pankov typedef struct Vmxnet3_RxQueueCtrl { 481*62dadd65SYuri Pankov char updateRxProd; 482*62dadd65SYuri Pankov uint8_t _pad[7]; 483*62dadd65SYuri Pankov uint64_t reserved; 484*62dadd65SYuri Pankov } Vmxnet3_RxQueueCtrl; 485*62dadd65SYuri Pankov #pragma pack() 486*62dadd65SYuri Pankov 487*62dadd65SYuri Pankov #define VMXNET3_RXM_UCAST 0x01 /* unicast only */ 488*62dadd65SYuri Pankov #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */ 489*62dadd65SYuri Pankov #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */ 490*62dadd65SYuri Pankov #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */ 491*62dadd65SYuri Pankov #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */ 492*62dadd65SYuri Pankov 493*62dadd65SYuri Pankov #pragma pack(1) 494*62dadd65SYuri Pankov typedef struct Vmxnet3_RxFilterConf { 495*62dadd65SYuri Pankov uint32_t rxMode; /* VMXNET3_RXM_xxx */ 496*62dadd65SYuri Pankov uint16_t mfTableLen; /* size of the multicast filter table */ 497*62dadd65SYuri Pankov uint16_t _pad1; 498*62dadd65SYuri Pankov uint64_t mfTablePA; /* PA of the multicast filters table */ 499*62dadd65SYuri Pankov uint32_t vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 500*62dadd65SYuri Pankov } Vmxnet3_RxFilterConf; 501*62dadd65SYuri Pankov #pragma pack() 502*62dadd65SYuri Pankov 503*62dadd65SYuri Pankov #define VMXNET3_PM_MAX_FILTERS 6 504*62dadd65SYuri Pankov #define VMXNET3_PM_MAX_PATTERN_SIZE 128 505*62dadd65SYuri Pankov #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 506*62dadd65SYuri Pankov 507*62dadd65SYuri Pankov #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */ 508*62dadd65SYuri Pankov #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching */ 509*62dadd65SYuri Pankov /* filters */ 510*62dadd65SYuri Pankov 511*62dadd65SYuri Pankov #pragma pack(1) 512*62dadd65SYuri Pankov typedef struct Vmxnet3_PM_PktFilter { 513*62dadd65SYuri Pankov uint8_t maskSize; 514*62dadd65SYuri Pankov uint8_t patternSize; 515*62dadd65SYuri Pankov uint8_t mask[VMXNET3_PM_MAX_MASK_SIZE]; 516*62dadd65SYuri Pankov uint8_t pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 517*62dadd65SYuri Pankov uint8_t pad[6]; 518*62dadd65SYuri Pankov } Vmxnet3_PM_PktFilter; 519*62dadd65SYuri Pankov #pragma pack() 520*62dadd65SYuri Pankov 521*62dadd65SYuri Pankov #pragma pack(1) 522*62dadd65SYuri Pankov typedef struct Vmxnet3_PMConf { 523*62dadd65SYuri Pankov uint16_t wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 524*62dadd65SYuri Pankov uint8_t numFilters; 525*62dadd65SYuri Pankov uint8_t pad[5]; 526*62dadd65SYuri Pankov Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 527*62dadd65SYuri Pankov } Vmxnet3_PMConf; 528*62dadd65SYuri Pankov #pragma pack() 529*62dadd65SYuri Pankov 530*62dadd65SYuri Pankov #pragma pack(1) 531*62dadd65SYuri Pankov typedef struct Vmxnet3_VariableLenConfDesc { 532*62dadd65SYuri Pankov uint32_t confVer; 533*62dadd65SYuri Pankov uint32_t confLen; 534*62dadd65SYuri Pankov uint64_t confPA; 535*62dadd65SYuri Pankov } Vmxnet3_VariableLenConfDesc; 536*62dadd65SYuri Pankov #pragma pack() 537*62dadd65SYuri Pankov 538*62dadd65SYuri Pankov #pragma pack(1) 539*62dadd65SYuri Pankov typedef struct Vmxnet3_DSDevRead { 540*62dadd65SYuri Pankov /* read-only region for device, read by dev in response to a SET cmd */ 541*62dadd65SYuri Pankov Vmxnet3_MiscConf misc; 542*62dadd65SYuri Pankov Vmxnet3_IntrConf intrConf; 543*62dadd65SYuri Pankov Vmxnet3_RxFilterConf rxFilterConf; 544*62dadd65SYuri Pankov Vmxnet3_VariableLenConfDesc rssConfDesc; 545*62dadd65SYuri Pankov Vmxnet3_VariableLenConfDesc pmConfDesc; 546*62dadd65SYuri Pankov Vmxnet3_VariableLenConfDesc pluginConfDesc; 547*62dadd65SYuri Pankov } Vmxnet3_DSDevRead; 548*62dadd65SYuri Pankov #pragma pack() 549*62dadd65SYuri Pankov 550*62dadd65SYuri Pankov #pragma pack(1) 551*62dadd65SYuri Pankov typedef struct Vmxnet3_TxQueueDesc { 552*62dadd65SYuri Pankov Vmxnet3_TxQueueCtrl ctrl; 553*62dadd65SYuri Pankov Vmxnet3_TxQueueConf conf; 554*62dadd65SYuri Pankov /* Driver read after a GET command */ 555*62dadd65SYuri Pankov Vmxnet3_QueueStatus status; 556*62dadd65SYuri Pankov UPT1_TxStats stats; 557*62dadd65SYuri Pankov uint8_t _pad[88]; /* 128 aligned */ 558*62dadd65SYuri Pankov } Vmxnet3_TxQueueDesc; 559*62dadd65SYuri Pankov #pragma pack() 560*62dadd65SYuri Pankov 561*62dadd65SYuri Pankov #pragma pack(1) 562*62dadd65SYuri Pankov typedef struct Vmxnet3_RxQueueDesc { 563*62dadd65SYuri Pankov Vmxnet3_RxQueueCtrl ctrl; 564*62dadd65SYuri Pankov Vmxnet3_RxQueueConf conf; 565*62dadd65SYuri Pankov /* Driver read after a GET command */ 566*62dadd65SYuri Pankov Vmxnet3_QueueStatus status; 567*62dadd65SYuri Pankov UPT1_RxStats stats; 568*62dadd65SYuri Pankov uint8_t _pad[88]; /* 128 aligned */ 569*62dadd65SYuri Pankov } Vmxnet3_RxQueueDesc; 570*62dadd65SYuri Pankov #pragma pack() 571*62dadd65SYuri Pankov 572*62dadd65SYuri Pankov #pragma pack(1) 573*62dadd65SYuri Pankov typedef struct Vmxnet3_DriverShared { 574*62dadd65SYuri Pankov uint32_t magic; 575*62dadd65SYuri Pankov uint32_t pad; /* make devRead start at */ 576*62dadd65SYuri Pankov /* 64-bit boundaries */ 577*62dadd65SYuri Pankov Vmxnet3_DSDevRead devRead; 578*62dadd65SYuri Pankov uint32_t ecr; 579*62dadd65SYuri Pankov uint32_t reserved[5]; 580*62dadd65SYuri Pankov } Vmxnet3_DriverShared; 581*62dadd65SYuri Pankov #pragma pack() 582*62dadd65SYuri Pankov 583*62dadd65SYuri Pankov #define VMXNET3_ECR_RQERR (1 << 0) 584*62dadd65SYuri Pankov #define VMXNET3_ECR_TQERR (1 << 1) 585*62dadd65SYuri Pankov #define VMXNET3_ECR_LINK (1 << 2) 586*62dadd65SYuri Pankov #define VMXNET3_ECR_DIC (1 << 3) 587*62dadd65SYuri Pankov #define VMXNET3_ECR_DEBUG (1 << 4) 588*62dadd65SYuri Pankov 589*62dadd65SYuri Pankov /* flip the gen bit of a ring */ 590*62dadd65SYuri Pankov #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 591*62dadd65SYuri Pankov 592*62dadd65SYuri Pankov /* only use this if moving the idx won't affect the gen bit */ 593*62dadd65SYuri Pankov #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) { \ 594*62dadd65SYuri Pankov (idx)++; \ 595*62dadd65SYuri Pankov if (UNLIKELY((idx) == (ring_size))) { \ 596*62dadd65SYuri Pankov (idx) = 0; \ 597*62dadd65SYuri Pankov } \ 598*62dadd65SYuri Pankov } 599*62dadd65SYuri Pankov 600*62dadd65SYuri Pankov #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 601*62dadd65SYuri Pankov vfTable[vid >> 5] |= (1 << (vid & 31)) 602*62dadd65SYuri Pankov #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 603*62dadd65SYuri Pankov vfTable[vid >> 5] &= ~(1 << (vid & 31)) 604*62dadd65SYuri Pankov 605*62dadd65SYuri Pankov #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 606*62dadd65SYuri Pankov ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 607*62dadd65SYuri Pankov 608*62dadd65SYuri Pankov #define VMXNET3_MAX_MTU 9000 609*62dadd65SYuri Pankov #define VMXNET3_MIN_MTU 60 610*62dadd65SYuri Pankov 611*62dadd65SYuri Pankov #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 612*62dadd65SYuri Pankov #define VMXNET3_LINK_DOWN 0 613*62dadd65SYuri Pankov 614*62dadd65SYuri Pankov #define VMXWIFI_DRIVER_SHARED_LEN 8192 615*62dadd65SYuri Pankov 616*62dadd65SYuri Pankov #define VMXNET3_DID_PASSTHRU 0xFFFF 617*62dadd65SYuri Pankov 618*62dadd65SYuri Pankov #endif /* _VMXNET3_DEFS_H_ */ 619