162dadd65SYuri Pankov /* 262dadd65SYuri Pankov * Copyright (C) 2007 VMware, Inc. All rights reserved. 362dadd65SYuri Pankov * 462dadd65SYuri Pankov * The contents of this file are subject to the terms of the Common 562dadd65SYuri Pankov * Development and Distribution License (the "License") version 1.0 662dadd65SYuri Pankov * and no later version. You may not use this file except in 762dadd65SYuri Pankov * compliance with the License. 862dadd65SYuri Pankov * 962dadd65SYuri Pankov * You can obtain a copy of the License at 1062dadd65SYuri Pankov * http://www.opensource.org/licenses/cddl1.php 1162dadd65SYuri Pankov * 1262dadd65SYuri Pankov * See the License for the specific language governing permissions 1362dadd65SYuri Pankov * and limitations under the License. 1462dadd65SYuri Pankov */ 1562dadd65SYuri Pankov 1662dadd65SYuri Pankov /* 1762dadd65SYuri Pankov * vmxnet3_defs.h -- 1862dadd65SYuri Pankov * 1962dadd65SYuri Pankov * Definitions shared by device emulation and guest drivers for 2062dadd65SYuri Pankov * VMXNET3 NIC 2162dadd65SYuri Pankov */ 2262dadd65SYuri Pankov 2362dadd65SYuri Pankov #ifndef _VMXNET3_DEFS_H_ 2462dadd65SYuri Pankov #define _VMXNET3_DEFS_H_ 2562dadd65SYuri Pankov 2662dadd65SYuri Pankov #include <upt1_defs.h> 2762dadd65SYuri Pankov 2862dadd65SYuri Pankov /* all registers are 32 bit wide */ 2962dadd65SYuri Pankov /* BAR 1 */ 3062dadd65SYuri Pankov #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */ 3162dadd65SYuri Pankov #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */ 3262dadd65SYuri Pankov #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */ 3362dadd65SYuri Pankov #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */ 34*ca5345b6SSebastien Roy #define VMXNET3_REG_CMD 0x20 /* Command */ 3562dadd65SYuri Pankov #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */ 3662dadd65SYuri Pankov #define VMXNET3_REG_MACH 0x30 /* MAC Address High */ 3762dadd65SYuri Pankov #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */ 3862dadd65SYuri Pankov #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */ 3962dadd65SYuri Pankov 4062dadd65SYuri Pankov #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */ 4162dadd65SYuri Pankov #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */ 4262dadd65SYuri Pankov #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */ 4362dadd65SYuri Pankov 4462dadd65SYuri Pankov /* BAR 0 */ 4562dadd65SYuri Pankov #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */ 4662dadd65SYuri Pankov #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */ 4762dadd65SYuri Pankov #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */ 4862dadd65SYuri Pankov #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */ 4962dadd65SYuri Pankov 5062dadd65SYuri Pankov #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 5162dadd65SYuri Pankov #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 5262dadd65SYuri Pankov 5362dadd65SYuri Pankov /* 5462dadd65SYuri Pankov * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at 5562dadd65SYuri Pankov * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region: 5662dadd65SYuri Pankov * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE--> 5762dadd65SYuri Pankov * ------------------------------------------------------------------------- 5862dadd65SYuri Pankov * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table | 5962dadd65SYuri Pankov * ------------------------------------------------------------------------- 6062dadd65SYuri Pankov * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h" 6162dadd65SYuri Pankov */ 6262dadd65SYuri Pankov #define VMXNET3_PHYSMEM_PAGES 4 6362dadd65SYuri Pankov 6462dadd65SYuri Pankov #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 6562dadd65SYuri Pankov #define VMXNET3_REG_ALIGN_MASK 0x7 6662dadd65SYuri Pankov 6762dadd65SYuri Pankov /* I/O Mapped access to registers */ 6862dadd65SYuri Pankov #define VMXNET3_IO_TYPE_PT 0 6962dadd65SYuri Pankov #define VMXNET3_IO_TYPE_VD 1 7062dadd65SYuri Pankov #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 7162dadd65SYuri Pankov #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 7262dadd65SYuri Pankov #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 7362dadd65SYuri Pankov 7462dadd65SYuri Pankov /* 7562dadd65SYuri Pankov * The Sun Studio compiler complains if enums overflow INT_MAX, so we can only 7662dadd65SYuri Pankov * use an enum with gcc. We keep this here for the convenience of merging 7762dadd65SYuri Pankov * from upstream. 7862dadd65SYuri Pankov */ 7962dadd65SYuri Pankov #ifdef __GNUC__ 8062dadd65SYuri Pankov 8162dadd65SYuri Pankov typedef enum { 8262dadd65SYuri Pankov VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 8362dadd65SYuri Pankov VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 8462dadd65SYuri Pankov VMXNET3_CMD_QUIESCE_DEV, 8562dadd65SYuri Pankov VMXNET3_CMD_RESET_DEV, 8662dadd65SYuri Pankov VMXNET3_CMD_UPDATE_RX_MODE, 8762dadd65SYuri Pankov VMXNET3_CMD_UPDATE_MAC_FILTERS, 8862dadd65SYuri Pankov VMXNET3_CMD_UPDATE_VLAN_FILTERS, 8962dadd65SYuri Pankov VMXNET3_CMD_UPDATE_RSSIDT, 9062dadd65SYuri Pankov VMXNET3_CMD_UPDATE_IML, 9162dadd65SYuri Pankov VMXNET3_CMD_UPDATE_PMCFG, 9262dadd65SYuri Pankov VMXNET3_CMD_UPDATE_FEATURE, 9362dadd65SYuri Pankov VMXNET3_CMD_STOP_EMULATION, 9462dadd65SYuri Pankov VMXNET3_CMD_LOAD_PLUGIN, 9562dadd65SYuri Pankov VMXNET3_CMD_ACTIVATE_VF, 9662dadd65SYuri Pankov 9762dadd65SYuri Pankov VMXNET3_CMD_FIRST_GET = 0xF00D0000, 9862dadd65SYuri Pankov VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 9962dadd65SYuri Pankov VMXNET3_CMD_GET_STATS, 10062dadd65SYuri Pankov VMXNET3_CMD_GET_LINK, 10162dadd65SYuri Pankov VMXNET3_CMD_GET_PERM_MAC_LO, 10262dadd65SYuri Pankov VMXNET3_CMD_GET_PERM_MAC_HI, 10362dadd65SYuri Pankov VMXNET3_CMD_GET_DID_LO, 10462dadd65SYuri Pankov VMXNET3_CMD_GET_DID_HI, 10562dadd65SYuri Pankov VMXNET3_CMD_GET_DEV_EXTRA_INFO, 10662dadd65SYuri Pankov VMXNET3_CMD_GET_CONF_INTR, 10762dadd65SYuri Pankov VMXNET3_CMD_GET_ADAPTIVE_RING_INFO 10862dadd65SYuri Pankov } Vmxnet3_Cmd; 10962dadd65SYuri Pankov 11062dadd65SYuri Pankov #else 11162dadd65SYuri Pankov 11262dadd65SYuri Pankov #define VMXNET3_CMD_FIRST_SET 0xCAFE0000U 11362dadd65SYuri Pankov #define VMXNET3_CMD_ACTIVATE_DEV VMXNET3_CMD_FIRST_SET 11462dadd65SYuri Pankov #define VMXNET3_CMD_QUIESCE_DEV (VMXNET3_CMD_FIRST_SET + 1) 11562dadd65SYuri Pankov #define VMXNET3_CMD_RESET_DEV (VMXNET3_CMD_FIRST_SET + 2) 11662dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_RX_MODE (VMXNET3_CMD_FIRST_SET + 3) 11762dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_MAC_FILTERS (VMXNET3_CMD_FIRST_SET + 4) 11862dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_VLAN_FILTERS (VMXNET3_CMD_FIRST_SET + 5) 11962dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_RSSIDT (VMXNET3_CMD_FIRST_SET + 6) 12062dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_IML (VMXNET3_CMD_FIRST_SET + 7) 12162dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_PMCFG (VMXNET3_CMD_FIRST_SET + 8) 12262dadd65SYuri Pankov #define VMXNET3_CMD_UPDATE_FEATURE (VMXNET3_CMD_FIRST_SET + 9) 12362dadd65SYuri Pankov #define VMXNET3_CMD_STOP_EMULATION (VMXNET3_CMD_FIRST_SET + 10) 12462dadd65SYuri Pankov #define VMXNET3_CMD_LOAD_PLUGIN (VMXNET3_CMD_FIRST_SET + 11) 12562dadd65SYuri Pankov #define VMXNET3_CMD_ACTIVATE_VF (VMXNET3_CMD_FIRST_SET + 12) 12662dadd65SYuri Pankov 12762dadd65SYuri Pankov #define VMXNET3_CMD_FIRST_GET 0xF00D0000U 12862dadd65SYuri Pankov #define VMXNET3_CMD_GET_QUEUE_STATUS VMXNET3_CMD_FIRST_GET 12962dadd65SYuri Pankov #define VMXNET3_CMD_GET_STATS (VMXNET3_CMD_FIRST_GET + 1) 13062dadd65SYuri Pankov #define VMXNET3_CMD_GET_LINK (VMXNET3_CMD_FIRST_GET + 2) 13162dadd65SYuri Pankov #define VMXNET3_CMD_GET_PERM_MAC_LO (VMXNET3_CMD_FIRST_GET + 3) 13262dadd65SYuri Pankov #define VMXNET3_CMD_GET_PERM_MAC_HI (VMXNET3_CMD_FIRST_GET + 4) 13362dadd65SYuri Pankov #define VMXNET3_CMD_GET_DID_LO (VMXNET3_CMD_FIRST_GET + 5) 13462dadd65SYuri Pankov #define VMXNET3_CMD_GET_DID_HI (VMXNET3_CMD_FIRST_GET + 6) 13562dadd65SYuri Pankov #define VMXNET3_CMD_GET_DEV_EXTRA_INFO (VMXNET3_CMD_FIRST_GET + 7) 13662dadd65SYuri Pankov #define VMXNET3_CMD_GET_CONF_INTR (VMXNET3_CMD_FIRST_GET + 8) 13762dadd65SYuri Pankov #define VMXNET3_CMD_GET_ADAPTIVE_RING_INFO (VMXNET3_CMD_FIRST_GET + 9) 13862dadd65SYuri Pankov 13962dadd65SYuri Pankov #endif 14062dadd65SYuri Pankov 14162dadd65SYuri Pankov /* Adaptive Ring Info Flags */ 14262dadd65SYuri Pankov #define VMXNET3_DISABLE_ADAPTIVE_RING 1 14362dadd65SYuri Pankov 14462dadd65SYuri Pankov #pragma pack(1) 14562dadd65SYuri Pankov typedef struct Vmxnet3_TxDesc { 14662dadd65SYuri Pankov uint64_t addr; 14762dadd65SYuri Pankov uint32_t len:14; 14862dadd65SYuri Pankov uint32_t gen:1; /* generation bit */ 14962dadd65SYuri Pankov uint32_t rsvd:1; 15062dadd65SYuri Pankov uint32_t dtype:1; /* descriptor type */ 15162dadd65SYuri Pankov uint32_t ext1:1; 15262dadd65SYuri Pankov uint32_t msscof:14; /* MSS, checksum offset, flags */ 15362dadd65SYuri Pankov uint32_t hlen:10; /* header len */ 15462dadd65SYuri Pankov uint32_t om:2; /* offload mode */ 15562dadd65SYuri Pankov uint32_t eop:1; /* End Of Packet */ 15662dadd65SYuri Pankov uint32_t cq:1; /* completion request */ 15762dadd65SYuri Pankov uint32_t ext2:1; 15862dadd65SYuri Pankov uint32_t ti:1; /* VLAN Tag Insertion */ 15962dadd65SYuri Pankov uint32_t tci:16; /* Tag to Insert */ 16062dadd65SYuri Pankov } Vmxnet3_TxDesc; 16162dadd65SYuri Pankov #pragma pack() 16262dadd65SYuri Pankov 16362dadd65SYuri Pankov /* TxDesc.OM values */ 16462dadd65SYuri Pankov #define VMXNET3_OM_NONE 0 16562dadd65SYuri Pankov #define VMXNET3_OM_CSUM 2 16662dadd65SYuri Pankov #define VMXNET3_OM_TSO 3 16762dadd65SYuri Pankov 16862dadd65SYuri Pankov /* fields in TxDesc we access w/o using bit fields */ 16962dadd65SYuri Pankov #define VMXNET3_TXD_EOP_SHIFT 12 17062dadd65SYuri Pankov #define VMXNET3_TXD_CQ_SHIFT 13 17162dadd65SYuri Pankov #define VMXNET3_TXD_GEN_SHIFT 14 17262dadd65SYuri Pankov #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 17362dadd65SYuri Pankov #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 17462dadd65SYuri Pankov 17562dadd65SYuri Pankov #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 17662dadd65SYuri Pankov #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 17762dadd65SYuri Pankov #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 17862dadd65SYuri Pankov 17962dadd65SYuri Pankov #define VMXNET3_TXD_GEN_SIZE 1 18062dadd65SYuri Pankov #define VMXNET3_TXD_EOP_SIZE 1 18162dadd65SYuri Pankov 18262dadd65SYuri Pankov #define VMXNET3_HDR_COPY_SIZE 128 18362dadd65SYuri Pankov 18462dadd65SYuri Pankov #pragma pack(1) 18562dadd65SYuri Pankov typedef struct Vmxnet3_TxDataDesc { 18662dadd65SYuri Pankov uint8_t data[VMXNET3_HDR_COPY_SIZE]; 18762dadd65SYuri Pankov } Vmxnet3_TxDataDesc; 18862dadd65SYuri Pankov #pragma pack() 18962dadd65SYuri Pankov 19062dadd65SYuri Pankov #define VMXNET3_TCD_GEN_SHIFT 31 19162dadd65SYuri Pankov #define VMXNET3_TCD_GEN_SIZE 1 19262dadd65SYuri Pankov #define VMXNET3_TCD_TXIDX_SHIFT 0 19362dadd65SYuri Pankov #define VMXNET3_TCD_TXIDX_SIZE 12 19462dadd65SYuri Pankov #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 19562dadd65SYuri Pankov 19662dadd65SYuri Pankov #pragma pack(1) 19762dadd65SYuri Pankov typedef struct Vmxnet3_TxCompDesc { 19862dadd65SYuri Pankov uint32_t txdIdx:12; /* Index of the EOP TxDesc */ 19962dadd65SYuri Pankov uint32_t ext1:20; 20062dadd65SYuri Pankov 20162dadd65SYuri Pankov uint32_t ext2; 20262dadd65SYuri Pankov uint32_t ext3; 20362dadd65SYuri Pankov 20462dadd65SYuri Pankov uint32_t rsvd:24; 20562dadd65SYuri Pankov uint32_t type:7; /* completion type */ 20662dadd65SYuri Pankov uint32_t gen:1; /* generation bit */ 20762dadd65SYuri Pankov } Vmxnet3_TxCompDesc; 20862dadd65SYuri Pankov #pragma pack() 20962dadd65SYuri Pankov 21062dadd65SYuri Pankov #pragma pack(1) 21162dadd65SYuri Pankov typedef struct Vmxnet3_RxDesc { 21262dadd65SYuri Pankov uint64_t addr; 21362dadd65SYuri Pankov uint32_t len:14; 21462dadd65SYuri Pankov uint32_t btype:1; /* Buffer Type */ 21562dadd65SYuri Pankov uint32_t dtype:1; /* Descriptor type */ 21662dadd65SYuri Pankov uint32_t rsvd:15; 21762dadd65SYuri Pankov uint32_t gen:1; /* Generation bit */ 21862dadd65SYuri Pankov uint32_t ext1; 21962dadd65SYuri Pankov } Vmxnet3_RxDesc; 22062dadd65SYuri Pankov #pragma pack() 22162dadd65SYuri Pankov 22262dadd65SYuri Pankov /* values of RXD.BTYPE */ 22362dadd65SYuri Pankov #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 22462dadd65SYuri Pankov #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 22562dadd65SYuri Pankov 22662dadd65SYuri Pankov /* fields in RxDesc we access w/o using bit fields */ 22762dadd65SYuri Pankov #define VMXNET3_RXD_BTYPE_SHIFT 14 22862dadd65SYuri Pankov #define VMXNET3_RXD_GEN_SHIFT 31 22962dadd65SYuri Pankov 23062dadd65SYuri Pankov #pragma pack(1) 23162dadd65SYuri Pankov typedef struct Vmxnet3_RxCompDesc { 23262dadd65SYuri Pankov uint32_t rxdIdx:12; /* Index of the RxDesc */ 23362dadd65SYuri Pankov uint32_t ext1:2; 23462dadd65SYuri Pankov uint32_t eop:1; /* End of Packet */ 23562dadd65SYuri Pankov uint32_t sop:1; /* Start of Packet */ 23662dadd65SYuri Pankov uint32_t rqID:10; /* rx queue/ring ID */ 23762dadd65SYuri Pankov uint32_t rssType:4; /* RSS hash type used */ 23862dadd65SYuri Pankov uint32_t cnc:1; /* Checksum Not Calculated */ 23962dadd65SYuri Pankov uint32_t ext2:1; 24062dadd65SYuri Pankov uint32_t rssHash; /* RSS hash value */ 24162dadd65SYuri Pankov uint32_t len:14; /* data length */ 24262dadd65SYuri Pankov uint32_t err:1; /* Error */ 24362dadd65SYuri Pankov uint32_t ts:1; /* Tag is stripped */ 24462dadd65SYuri Pankov uint32_t tci:16; /* Tag stripped */ 24562dadd65SYuri Pankov uint32_t csum:16; 24662dadd65SYuri Pankov uint32_t tuc:1; /* TCP/UDP Checksum Correct */ 24762dadd65SYuri Pankov uint32_t udp:1; /* UDP packet */ 24862dadd65SYuri Pankov uint32_t tcp:1; /* TCP packet */ 24962dadd65SYuri Pankov uint32_t ipc:1; /* IP Checksum Correct */ 25062dadd65SYuri Pankov uint32_t v6:1; /* IPv6 */ 25162dadd65SYuri Pankov uint32_t v4:1; /* IPv4 */ 25262dadd65SYuri Pankov uint32_t frg:1; /* IP Fragment */ 25362dadd65SYuri Pankov uint32_t fcs:1; /* Frame CRC correct */ 25462dadd65SYuri Pankov uint32_t type:7; /* completion type */ 25562dadd65SYuri Pankov uint32_t gen:1; /* generation bit */ 25662dadd65SYuri Pankov } Vmxnet3_RxCompDesc; 25762dadd65SYuri Pankov #pragma pack() 25862dadd65SYuri Pankov 25962dadd65SYuri Pankov /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 26062dadd65SYuri Pankov #define VMXNET3_RCD_TUC_SHIFT 16 26162dadd65SYuri Pankov #define VMXNET3_RCD_IPC_SHIFT 19 26262dadd65SYuri Pankov 26362dadd65SYuri Pankov /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 26462dadd65SYuri Pankov #define VMXNET3_RCD_TYPE_SHIFT 56 26562dadd65SYuri Pankov #define VMXNET3_RCD_GEN_SHIFT 63 26662dadd65SYuri Pankov 26762dadd65SYuri Pankov /* csum OK for TCP/UDP pkts over IP */ 26862dadd65SYuri Pankov #define VMXNET3_RCD_CSUM_OK \ 26962dadd65SYuri Pankov (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT) 27062dadd65SYuri Pankov 27162dadd65SYuri Pankov /* value of RxCompDesc.rssType */ 27262dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_NONE 0 27362dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_IPV4 1 27462dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2 27562dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_IPV6 3 27662dadd65SYuri Pankov #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4 27762dadd65SYuri Pankov 27862dadd65SYuri Pankov /* a union for accessing all cmd/completion descriptors */ 27962dadd65SYuri Pankov typedef union Vmxnet3_GenericDesc { 28062dadd65SYuri Pankov uint64_t qword[2]; 28162dadd65SYuri Pankov uint32_t dword[4]; 28262dadd65SYuri Pankov uint16_t word[8]; 28362dadd65SYuri Pankov Vmxnet3_TxDesc txd; 28462dadd65SYuri Pankov Vmxnet3_RxDesc rxd; 28562dadd65SYuri Pankov Vmxnet3_TxCompDesc tcd; 28662dadd65SYuri Pankov Vmxnet3_RxCompDesc rcd; 28762dadd65SYuri Pankov } Vmxnet3_GenericDesc; 28862dadd65SYuri Pankov 28962dadd65SYuri Pankov #define VMXNET3_INIT_GEN 1 29062dadd65SYuri Pankov 29162dadd65SYuri Pankov /* Max size of a single tx buffer */ 29262dadd65SYuri Pankov #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 29362dadd65SYuri Pankov 29462dadd65SYuri Pankov /* # of tx desc needed for a tx buffer size */ 29562dadd65SYuri Pankov #define VMXNET3_TXD_NEEDED(size) \ 29662dadd65SYuri Pankov (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE) 29762dadd65SYuri Pankov 29862dadd65SYuri Pankov /* max # of tx descs for a non-tso pkt */ 29962dadd65SYuri Pankov #define VMXNET3_MAX_TXD_PER_PKT 16 30062dadd65SYuri Pankov 30162dadd65SYuri Pankov /* Max size of a single rx buffer */ 30262dadd65SYuri Pankov #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 30362dadd65SYuri Pankov /* Minimum size of a type 0 buffer */ 30462dadd65SYuri Pankov #define VMXNET3_MIN_T0_BUF_SIZE 128 30562dadd65SYuri Pankov #define VMXNET3_MAX_CSUM_OFFSET 1024 30662dadd65SYuri Pankov 30762dadd65SYuri Pankov /* Ring base address alignment */ 30862dadd65SYuri Pankov #define VMXNET3_RING_BA_ALIGN 512 30962dadd65SYuri Pankov #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 31062dadd65SYuri Pankov 31162dadd65SYuri Pankov /* Ring size must be a multiple of 32 */ 31262dadd65SYuri Pankov #define VMXNET3_RING_SIZE_ALIGN 32 31362dadd65SYuri Pankov #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 31462dadd65SYuri Pankov 31562dadd65SYuri Pankov /* Max ring size */ 31662dadd65SYuri Pankov #define VMXNET3_TX_RING_MAX_SIZE 4096 31762dadd65SYuri Pankov #define VMXNET3_TC_RING_MAX_SIZE 4096 31862dadd65SYuri Pankov #define VMXNET3_RX_RING_MAX_SIZE 4096 31962dadd65SYuri Pankov #define VMXNET3_RC_RING_MAX_SIZE 8192 32062dadd65SYuri Pankov 32162dadd65SYuri Pankov /* a list of reasons for queue stop */ 32262dadd65SYuri Pankov 32362dadd65SYuri Pankov #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the */ 32462dadd65SYuri Pankov /* EOP desc of a pkt */ 32562dadd65SYuri Pankov #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx */ 32662dadd65SYuri Pankov /* completion */ 32762dadd65SYuri Pankov #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */ 32862dadd65SYuri Pankov #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not */ 32962dadd65SYuri Pankov /* supported */ 33062dadd65SYuri Pankov #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */ 33162dadd65SYuri Pankov #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing */ 33262dadd65SYuri Pankov /* in vmkernel */ 33362dadd65SYuri Pankov #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */ 33462dadd65SYuri Pankov #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */ 33562dadd65SYuri Pankov 33662dadd65SYuri Pankov /* completion descriptor types */ 33762dadd65SYuri Pankov #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 33862dadd65SYuri Pankov #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 33962dadd65SYuri Pankov 34062dadd65SYuri Pankov #define VMXNET3_GOS_BITS_UNK 0 /* unknown */ 34162dadd65SYuri Pankov #define VMXNET3_GOS_BITS_32 1 34262dadd65SYuri Pankov #define VMXNET3_GOS_BITS_64 2 34362dadd65SYuri Pankov 34462dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */ 34562dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_LINUX 1 34662dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_WIN 2 34762dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_SOLARIS 3 34862dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_FREEBSD 4 34962dadd65SYuri Pankov #define VMXNET3_GOS_TYPE_PXE 5 35062dadd65SYuri Pankov 35162dadd65SYuri Pankov /* All structures in DriverShared are padded to multiples of 8 bytes */ 35262dadd65SYuri Pankov 35362dadd65SYuri Pankov #pragma pack(1) 35462dadd65SYuri Pankov typedef struct Vmxnet3_GOSInfo { 35562dadd65SYuri Pankov uint32_t gosBits: 2; /* 32-bit or 64-bit? */ 35662dadd65SYuri Pankov uint32_t gosType: 4; /* which guest */ 35762dadd65SYuri Pankov uint32_t gosVer: 16; /* gos version */ 35862dadd65SYuri Pankov uint32_t gosMisc: 10; /* other info about gos */ 35962dadd65SYuri Pankov } Vmxnet3_GOSInfo; 36062dadd65SYuri Pankov #pragma pack() 36162dadd65SYuri Pankov 36262dadd65SYuri Pankov #pragma pack(1) 36362dadd65SYuri Pankov typedef struct Vmxnet3_DriverInfo { 36462dadd65SYuri Pankov uint32_t version; /* driver version */ 36562dadd65SYuri Pankov Vmxnet3_GOSInfo gos; 36662dadd65SYuri Pankov uint32_t vmxnet3RevSpt; /* vmxnet3 revision supported */ 36762dadd65SYuri Pankov uint32_t uptVerSpt; /* upt version supported */ 36862dadd65SYuri Pankov } Vmxnet3_DriverInfo; 36962dadd65SYuri Pankov #pragma pack() 37062dadd65SYuri Pankov 37162dadd65SYuri Pankov #define VMXNET3_REV1_MAGIC 0xbabefee1 37262dadd65SYuri Pankov 37362dadd65SYuri Pankov /* 37462dadd65SYuri Pankov * QueueDescPA must be 128 bytes aligned. It points to an array of 37562dadd65SYuri Pankov * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 37662dadd65SYuri Pankov * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 37762dadd65SYuri Pankov * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 37862dadd65SYuri Pankov */ 37962dadd65SYuri Pankov #define VMXNET3_QUEUE_DESC_ALIGN 128 38062dadd65SYuri Pankov 38162dadd65SYuri Pankov #pragma pack(1) 38262dadd65SYuri Pankov typedef struct Vmxnet3_MiscConf { 38362dadd65SYuri Pankov Vmxnet3_DriverInfo driverInfo; 38462dadd65SYuri Pankov uint64_t uptFeatures; 38562dadd65SYuri Pankov uint64_t ddPA; /* driver data PA */ 38662dadd65SYuri Pankov uint64_t queueDescPA; /* queue descriptor table PA */ 38762dadd65SYuri Pankov uint32_t ddLen; /* driver data len */ 38862dadd65SYuri Pankov uint32_t queueDescLen; /* queue descriptor table len, bytes */ 38962dadd65SYuri Pankov uint32_t mtu; 39062dadd65SYuri Pankov uint16_t maxNumRxSG; 39162dadd65SYuri Pankov uint8_t numTxQueues; 39262dadd65SYuri Pankov uint8_t numRxQueues; 39362dadd65SYuri Pankov uint32_t reserved[4]; 39462dadd65SYuri Pankov } Vmxnet3_MiscConf; 39562dadd65SYuri Pankov #pragma pack() 39662dadd65SYuri Pankov 39762dadd65SYuri Pankov #pragma pack(1) 39862dadd65SYuri Pankov typedef struct Vmxnet3_TxQueueConf { 39962dadd65SYuri Pankov uint64_t txRingBasePA; 40062dadd65SYuri Pankov uint64_t dataRingBasePA; 40162dadd65SYuri Pankov uint64_t compRingBasePA; 40262dadd65SYuri Pankov uint64_t ddPA; /* driver data */ 40362dadd65SYuri Pankov uint64_t reserved; 40462dadd65SYuri Pankov uint32_t txRingSize; /* # of tx desc */ 40562dadd65SYuri Pankov uint32_t dataRingSize; /* # of data desc */ 40662dadd65SYuri Pankov uint32_t compRingSize; /* # of comp desc */ 40762dadd65SYuri Pankov uint32_t ddLen; /* size of driver data */ 40862dadd65SYuri Pankov uint8_t intrIdx; 40962dadd65SYuri Pankov uint8_t _pad[7]; 41062dadd65SYuri Pankov } Vmxnet3_TxQueueConf; 41162dadd65SYuri Pankov #pragma pack() 41262dadd65SYuri Pankov 41362dadd65SYuri Pankov #pragma pack(1) 41462dadd65SYuri Pankov typedef struct Vmxnet3_RxQueueConf { 41562dadd65SYuri Pankov uint64_t rxRingBasePA[2]; 41662dadd65SYuri Pankov uint64_t compRingBasePA; 41762dadd65SYuri Pankov uint64_t ddPA; /* driver data */ 41862dadd65SYuri Pankov uint64_t reserved; 41962dadd65SYuri Pankov uint32_t rxRingSize[2]; /* # of rx desc */ 42062dadd65SYuri Pankov uint32_t compRingSize; /* # of rx comp desc */ 42162dadd65SYuri Pankov uint32_t ddLen; /* size of driver data */ 42262dadd65SYuri Pankov uint8_t intrIdx; 42362dadd65SYuri Pankov uint8_t _pad[7]; 42462dadd65SYuri Pankov } Vmxnet3_RxQueueConf; 42562dadd65SYuri Pankov #pragma pack() 42662dadd65SYuri Pankov 42762dadd65SYuri Pankov enum vmxnet3_intr_mask_mode { 42862dadd65SYuri Pankov VMXNET3_IMM_AUTO = 0, 42962dadd65SYuri Pankov VMXNET3_IMM_ACTIVE = 1, 43062dadd65SYuri Pankov VMXNET3_IMM_LAZY = 2 43162dadd65SYuri Pankov }; 43262dadd65SYuri Pankov 43362dadd65SYuri Pankov enum vmxnet3_intr_type { 43462dadd65SYuri Pankov VMXNET3_IT_AUTO = 0, 43562dadd65SYuri Pankov VMXNET3_IT_INTX = 1, 43662dadd65SYuri Pankov VMXNET3_IT_MSI = 2, 43762dadd65SYuri Pankov VMXNET3_IT_MSIX = 3 43862dadd65SYuri Pankov }; 43962dadd65SYuri Pankov 44062dadd65SYuri Pankov #define VMXNET3_MAX_TX_QUEUES 8 44162dadd65SYuri Pankov #define VMXNET3_MAX_RX_QUEUES 16 44262dadd65SYuri Pankov /* addition 1 for events */ 44362dadd65SYuri Pankov #define VMXNET3_MAX_INTRS 25 44462dadd65SYuri Pankov 44562dadd65SYuri Pankov /* value of intrCtrl */ 44662dadd65SYuri Pankov #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 44762dadd65SYuri Pankov 44862dadd65SYuri Pankov #pragma pack(1) 44962dadd65SYuri Pankov typedef struct Vmxnet3_IntrConf { 45062dadd65SYuri Pankov char autoMask; 45162dadd65SYuri Pankov uint8_t numIntrs; /* # of interrupts */ 45262dadd65SYuri Pankov uint8_t eventIntrIdx; 45362dadd65SYuri Pankov uint8_t modLevels[VMXNET3_MAX_INTRS]; /* moderation level */ 45462dadd65SYuri Pankov /* for each intr */ 45562dadd65SYuri Pankov uint32_t intrCtrl; 45662dadd65SYuri Pankov uint32_t reserved[2]; 45762dadd65SYuri Pankov } Vmxnet3_IntrConf; 45862dadd65SYuri Pankov #pragma pack() 45962dadd65SYuri Pankov 46062dadd65SYuri Pankov /* one bit per VLAN ID, the size is in the units of uint32_t */ 46162dadd65SYuri Pankov #define VMXNET3_VFT_SIZE (4096 / (sizeof (uint32_t) * 8)) 46262dadd65SYuri Pankov 46362dadd65SYuri Pankov #pragma pack(1) 46462dadd65SYuri Pankov typedef struct Vmxnet3_QueueStatus { 46562dadd65SYuri Pankov char stopped; 46662dadd65SYuri Pankov uint8_t _pad[3]; 46762dadd65SYuri Pankov uint32_t error; 46862dadd65SYuri Pankov } Vmxnet3_QueueStatus; 46962dadd65SYuri Pankov #pragma pack() 47062dadd65SYuri Pankov 47162dadd65SYuri Pankov #pragma pack(1) 47262dadd65SYuri Pankov typedef struct Vmxnet3_TxQueueCtrl { 47362dadd65SYuri Pankov uint32_t txNumDeferred; 47462dadd65SYuri Pankov uint32_t txThreshold; 47562dadd65SYuri Pankov uint64_t reserved; 47662dadd65SYuri Pankov } Vmxnet3_TxQueueCtrl; 47762dadd65SYuri Pankov #pragma pack() 47862dadd65SYuri Pankov 47962dadd65SYuri Pankov #pragma pack(1) 48062dadd65SYuri Pankov typedef struct Vmxnet3_RxQueueCtrl { 48162dadd65SYuri Pankov char updateRxProd; 48262dadd65SYuri Pankov uint8_t _pad[7]; 48362dadd65SYuri Pankov uint64_t reserved; 48462dadd65SYuri Pankov } Vmxnet3_RxQueueCtrl; 48562dadd65SYuri Pankov #pragma pack() 48662dadd65SYuri Pankov 48762dadd65SYuri Pankov #define VMXNET3_RXM_UCAST 0x01 /* unicast only */ 48862dadd65SYuri Pankov #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */ 48962dadd65SYuri Pankov #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */ 49062dadd65SYuri Pankov #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */ 49162dadd65SYuri Pankov #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */ 49262dadd65SYuri Pankov 49362dadd65SYuri Pankov #pragma pack(1) 49462dadd65SYuri Pankov typedef struct Vmxnet3_RxFilterConf { 49562dadd65SYuri Pankov uint32_t rxMode; /* VMXNET3_RXM_xxx */ 49662dadd65SYuri Pankov uint16_t mfTableLen; /* size of the multicast filter table */ 49762dadd65SYuri Pankov uint16_t _pad1; 49862dadd65SYuri Pankov uint64_t mfTablePA; /* PA of the multicast filters table */ 49962dadd65SYuri Pankov uint32_t vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 50062dadd65SYuri Pankov } Vmxnet3_RxFilterConf; 50162dadd65SYuri Pankov #pragma pack() 50262dadd65SYuri Pankov 50362dadd65SYuri Pankov #define VMXNET3_PM_MAX_FILTERS 6 50462dadd65SYuri Pankov #define VMXNET3_PM_MAX_PATTERN_SIZE 128 50562dadd65SYuri Pankov #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 50662dadd65SYuri Pankov 50762dadd65SYuri Pankov #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */ 50862dadd65SYuri Pankov #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching */ 50962dadd65SYuri Pankov /* filters */ 51062dadd65SYuri Pankov 51162dadd65SYuri Pankov #pragma pack(1) 51262dadd65SYuri Pankov typedef struct Vmxnet3_PM_PktFilter { 51362dadd65SYuri Pankov uint8_t maskSize; 51462dadd65SYuri Pankov uint8_t patternSize; 51562dadd65SYuri Pankov uint8_t mask[VMXNET3_PM_MAX_MASK_SIZE]; 51662dadd65SYuri Pankov uint8_t pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 51762dadd65SYuri Pankov uint8_t pad[6]; 51862dadd65SYuri Pankov } Vmxnet3_PM_PktFilter; 51962dadd65SYuri Pankov #pragma pack() 52062dadd65SYuri Pankov 52162dadd65SYuri Pankov #pragma pack(1) 52262dadd65SYuri Pankov typedef struct Vmxnet3_PMConf { 52362dadd65SYuri Pankov uint16_t wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 52462dadd65SYuri Pankov uint8_t numFilters; 52562dadd65SYuri Pankov uint8_t pad[5]; 52662dadd65SYuri Pankov Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 52762dadd65SYuri Pankov } Vmxnet3_PMConf; 52862dadd65SYuri Pankov #pragma pack() 52962dadd65SYuri Pankov 53062dadd65SYuri Pankov #pragma pack(1) 53162dadd65SYuri Pankov typedef struct Vmxnet3_VariableLenConfDesc { 53262dadd65SYuri Pankov uint32_t confVer; 53362dadd65SYuri Pankov uint32_t confLen; 53462dadd65SYuri Pankov uint64_t confPA; 53562dadd65SYuri Pankov } Vmxnet3_VariableLenConfDesc; 53662dadd65SYuri Pankov #pragma pack() 53762dadd65SYuri Pankov 53862dadd65SYuri Pankov #pragma pack(1) 53962dadd65SYuri Pankov typedef struct Vmxnet3_DSDevRead { 54062dadd65SYuri Pankov /* read-only region for device, read by dev in response to a SET cmd */ 54162dadd65SYuri Pankov Vmxnet3_MiscConf misc; 54262dadd65SYuri Pankov Vmxnet3_IntrConf intrConf; 54362dadd65SYuri Pankov Vmxnet3_RxFilterConf rxFilterConf; 54462dadd65SYuri Pankov Vmxnet3_VariableLenConfDesc rssConfDesc; 54562dadd65SYuri Pankov Vmxnet3_VariableLenConfDesc pmConfDesc; 54662dadd65SYuri Pankov Vmxnet3_VariableLenConfDesc pluginConfDesc; 54762dadd65SYuri Pankov } Vmxnet3_DSDevRead; 54862dadd65SYuri Pankov #pragma pack() 54962dadd65SYuri Pankov 55062dadd65SYuri Pankov #pragma pack(1) 55162dadd65SYuri Pankov typedef struct Vmxnet3_TxQueueDesc { 55262dadd65SYuri Pankov Vmxnet3_TxQueueCtrl ctrl; 55362dadd65SYuri Pankov Vmxnet3_TxQueueConf conf; 55462dadd65SYuri Pankov /* Driver read after a GET command */ 55562dadd65SYuri Pankov Vmxnet3_QueueStatus status; 55662dadd65SYuri Pankov UPT1_TxStats stats; 55762dadd65SYuri Pankov uint8_t _pad[88]; /* 128 aligned */ 55862dadd65SYuri Pankov } Vmxnet3_TxQueueDesc; 55962dadd65SYuri Pankov #pragma pack() 56062dadd65SYuri Pankov 56162dadd65SYuri Pankov #pragma pack(1) 56262dadd65SYuri Pankov typedef struct Vmxnet3_RxQueueDesc { 56362dadd65SYuri Pankov Vmxnet3_RxQueueCtrl ctrl; 56462dadd65SYuri Pankov Vmxnet3_RxQueueConf conf; 56562dadd65SYuri Pankov /* Driver read after a GET command */ 56662dadd65SYuri Pankov Vmxnet3_QueueStatus status; 56762dadd65SYuri Pankov UPT1_RxStats stats; 56862dadd65SYuri Pankov uint8_t _pad[88]; /* 128 aligned */ 56962dadd65SYuri Pankov } Vmxnet3_RxQueueDesc; 57062dadd65SYuri Pankov #pragma pack() 57162dadd65SYuri Pankov 57262dadd65SYuri Pankov #pragma pack(1) 57362dadd65SYuri Pankov typedef struct Vmxnet3_DriverShared { 57462dadd65SYuri Pankov uint32_t magic; 57562dadd65SYuri Pankov uint32_t pad; /* make devRead start at */ 57662dadd65SYuri Pankov /* 64-bit boundaries */ 57762dadd65SYuri Pankov Vmxnet3_DSDevRead devRead; 57862dadd65SYuri Pankov uint32_t ecr; 57962dadd65SYuri Pankov uint32_t reserved[5]; 58062dadd65SYuri Pankov } Vmxnet3_DriverShared; 58162dadd65SYuri Pankov #pragma pack() 58262dadd65SYuri Pankov 58362dadd65SYuri Pankov #define VMXNET3_ECR_RQERR (1 << 0) 58462dadd65SYuri Pankov #define VMXNET3_ECR_TQERR (1 << 1) 58562dadd65SYuri Pankov #define VMXNET3_ECR_LINK (1 << 2) 58662dadd65SYuri Pankov #define VMXNET3_ECR_DIC (1 << 3) 58762dadd65SYuri Pankov #define VMXNET3_ECR_DEBUG (1 << 4) 58862dadd65SYuri Pankov 58962dadd65SYuri Pankov /* flip the gen bit of a ring */ 59062dadd65SYuri Pankov #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 59162dadd65SYuri Pankov 59262dadd65SYuri Pankov /* only use this if moving the idx won't affect the gen bit */ 59362dadd65SYuri Pankov #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) { \ 59462dadd65SYuri Pankov (idx)++; \ 59562dadd65SYuri Pankov if (UNLIKELY((idx) == (ring_size))) { \ 59662dadd65SYuri Pankov (idx) = 0; \ 59762dadd65SYuri Pankov } \ 59862dadd65SYuri Pankov } 59962dadd65SYuri Pankov 60062dadd65SYuri Pankov #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 60162dadd65SYuri Pankov vfTable[vid >> 5] |= (1 << (vid & 31)) 60262dadd65SYuri Pankov #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 60362dadd65SYuri Pankov vfTable[vid >> 5] &= ~(1 << (vid & 31)) 60462dadd65SYuri Pankov 60562dadd65SYuri Pankov #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 60662dadd65SYuri Pankov ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 60762dadd65SYuri Pankov 60862dadd65SYuri Pankov #define VMXNET3_MAX_MTU 9000 60962dadd65SYuri Pankov #define VMXNET3_MIN_MTU 60 61062dadd65SYuri Pankov 61162dadd65SYuri Pankov #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 61262dadd65SYuri Pankov #define VMXNET3_LINK_DOWN 0 61362dadd65SYuri Pankov 61462dadd65SYuri Pankov #define VMXWIFI_DRIVER_SHARED_LEN 8192 61562dadd65SYuri Pankov 61662dadd65SYuri Pankov #define VMXNET3_DID_PASSTHRU 0xFFFF 61762dadd65SYuri Pankov 61862dadd65SYuri Pankov #endif /* _VMXNET3_DEFS_H_ */ 619