1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 * Copyright 2020 Oxide Computer Company 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/pcpu.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/x86_archext.h> 53 54 #include <machine/clock.h> 55 #include <machine/cpufunc.h> 56 #include <machine/md_var.h> 57 #include <machine/segments.h> 58 #include <machine/specialreg.h> 59 60 #include <machine/vmm.h> 61 62 #include "vmm_host.h" 63 #include "vmm_ktr.h" 64 #include "vmm_util.h" 65 #include "x86.h" 66 67 SYSCTL_DECL(_hw_vmm); 68 69 #define CPUID_VM_HIGH 0x40000000 70 71 static const char bhyve_id[12] = "bhyve bhyve "; 72 73 /* Number of times an unknown cpuid leaf was accessed */ 74 static uint64_t bhyve_xcpuids; 75 76 static int cpuid_leaf_b = 1; 77 78 /* 79 * Force exposition of the invariant TSC capability, regardless of whether the 80 * host CPU reports having it. 81 */ 82 static int vmm_force_invariant_tsc = 0; 83 84 /* 85 * Round up to the next power of two, if necessary, and then take log2. 86 * Returns -1 if argument is zero. 87 */ 88 static __inline int 89 log2(uint_t x) 90 { 91 92 return (fls(x << (1 - powerof2(x))) - 1); 93 } 94 95 int 96 x86_emulate_cpuid(struct vm *vm, int vcpu_id, uint64_t *rax, uint64_t *rbx, 97 uint64_t *rcx, uint64_t *rdx) 98 { 99 const struct xsave_limits *limits; 100 uint64_t cr4; 101 int error, enable_invpcid, level, width = 0, x2apic_id = 0; 102 unsigned int func, regs[4], logical_cpus = 0, param; 103 enum x2apic_state x2apic_state; 104 uint16_t cores, maxcpus, sockets, threads; 105 106 /* 107 * The function of CPUID is controlled through the provided value of 108 * %eax (and secondarily %ecx, for certain leaf data). 109 */ 110 func = (uint32_t)*rax; 111 param = (uint32_t)*rcx; 112 113 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", func, param); 114 115 /* 116 * Requests for invalid CPUID levels should map to the highest 117 * available level instead. 118 */ 119 if (cpu_exthigh != 0 && func >= 0x80000000) { 120 if (func > cpu_exthigh) 121 func = cpu_exthigh; 122 } else if (func >= 0x40000000) { 123 if (func > CPUID_VM_HIGH) 124 func = CPUID_VM_HIGH; 125 } else if (func > cpu_high) { 126 func = cpu_high; 127 } 128 129 /* 130 * In general the approach used for CPU topology is to 131 * advertise a flat topology where all CPUs are packages with 132 * no multi-core or SMT. 133 */ 134 switch (func) { 135 /* 136 * Pass these through to the guest 137 */ 138 case CPUID_0000_0000: 139 case CPUID_0000_0002: 140 case CPUID_0000_0003: 141 case CPUID_8000_0000: 142 case CPUID_8000_0002: 143 case CPUID_8000_0003: 144 case CPUID_8000_0004: 145 case CPUID_8000_0006: 146 cpuid_count(func, param, regs); 147 break; 148 case CPUID_8000_0008: 149 cpuid_count(func, param, regs); 150 if (vmm_is_svm()) { 151 /* 152 * As on Intel (0000_0007:0, EDX), mask out 153 * unsupported or unsafe AMD extended features 154 * (8000_0008 EBX). 155 */ 156 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF | 157 AMDFEID_XSAVEERPTR); 158 159 vm_get_topology(vm, &sockets, &cores, &threads, 160 &maxcpus); 161 /* 162 * Here, width is ApicIdCoreIdSize, present on 163 * at least Family 15h and newer. It 164 * represents the "number of bits in the 165 * initial apicid that indicate thread id 166 * within a package." 167 * 168 * Our topo_probe_amd() uses it for 169 * pkg_id_shift and other OSes may rely on it. 170 */ 171 width = MIN(0xF, log2(threads * cores)); 172 if (width < 0x4) 173 width = 0; 174 logical_cpus = MIN(0xFF, threads * cores - 1); 175 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | 176 logical_cpus; 177 } 178 break; 179 180 case CPUID_8000_0001: 181 cpuid_count(func, param, regs); 182 183 /* 184 * Hide SVM from guest. 185 */ 186 regs[2] &= ~AMDID2_SVM; 187 188 /* 189 * Don't advertise extended performance counter MSRs 190 * to the guest. 191 */ 192 regs[2] &= ~AMDID2_PCXC; 193 regs[2] &= ~AMDID2_PNXC; 194 regs[2] &= ~AMDID2_PTSCEL2I; 195 196 /* 197 * Don't advertise Instruction Based Sampling feature. 198 */ 199 regs[2] &= ~AMDID2_IBS; 200 201 /* NodeID MSR not available */ 202 regs[2] &= ~AMDID2_NODE_ID; 203 204 /* Don't advertise the OS visible workaround feature */ 205 regs[2] &= ~AMDID2_OSVW; 206 207 /* Hide mwaitx/monitorx capability from the guest */ 208 regs[2] &= ~AMDID2_MWAITX; 209 210 #ifndef __FreeBSD__ 211 /* 212 * Detection routines for TCE and FFXSR are missing 213 * from our vm_cpuid_capability() detection logic 214 * today. Mask them out until that is remedied. 215 * They do not appear to be in common usage, so their 216 * absence should not cause undue trouble. 217 */ 218 regs[2] &= ~AMDID2_TCE; 219 regs[3] &= ~AMDID_FFXSR; 220 #endif 221 222 /* 223 * Hide rdtscp/ia32_tsc_aux until we know how 224 * to deal with them. 225 */ 226 regs[3] &= ~AMDID_RDTSCP; 227 break; 228 229 case CPUID_8000_0007: 230 cpuid_count(func, param, regs); 231 /* 232 * AMD uses this leaf to advertise the processor's 233 * power monitoring and RAS capabilities. These 234 * features are hardware-specific and exposing 235 * them to a guest doesn't make a lot of sense. 236 * 237 * Intel uses this leaf only to advertise the 238 * "Invariant TSC" feature with all other bits 239 * being reserved (set to zero). 240 */ 241 regs[0] = 0; 242 regs[1] = 0; 243 regs[2] = 0; 244 245 /* 246 * If the host system possesses an invariant TSC, then 247 * it is safe to expose to the guest. 248 * 249 * If there is measured skew between host TSCs, it will 250 * be properly offset so guests do not observe any 251 * change between CPU migrations. 252 */ 253 regs[3] &= AMDPM_TSC_INVARIANT; 254 255 /* 256 * Since illumos avoids deep C-states on CPUs which do 257 * not support an invariant TSC, it may be safe (and 258 * desired) to unconditionally expose that capability to 259 * the guest. 260 */ 261 if (vmm_force_invariant_tsc != 0) { 262 regs[3] |= AMDPM_TSC_INVARIANT; 263 } 264 break; 265 266 case CPUID_8000_001D: 267 /* AMD Cache topology, like 0000_0004 for Intel. */ 268 if (!vmm_is_svm()) 269 goto default_leaf; 270 271 /* 272 * Similar to Intel, generate a ficticious cache 273 * topology for the guest with L3 shared by the 274 * package, and L1 and L2 local to a core. 275 */ 276 vm_get_topology(vm, &sockets, &cores, &threads, 277 &maxcpus); 278 switch (param) { 279 case 0: 280 logical_cpus = threads; 281 level = 1; 282 func = 1; /* data cache */ 283 break; 284 case 1: 285 logical_cpus = threads; 286 level = 2; 287 func = 3; /* unified cache */ 288 break; 289 case 2: 290 logical_cpus = threads * cores; 291 level = 3; 292 func = 3; /* unified cache */ 293 break; 294 default: 295 logical_cpus = 0; 296 level = 0; 297 func = 0; 298 break; 299 } 300 301 logical_cpus = MIN(0xfff, logical_cpus - 1); 302 regs[0] = (logical_cpus << 14) | (1 << 8) | 303 (level << 5) | func; 304 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0; 305 regs[2] = 0; 306 regs[3] = 0; 307 break; 308 309 case CPUID_8000_001E: 310 /* 311 * AMD Family 16h+ and Hygon Family 18h additional 312 * identifiers. 313 */ 314 if (!vmm_is_svm() || CPUID_TO_FAMILY(cpu_id) < 0x16) 315 goto default_leaf; 316 317 vm_get_topology(vm, &sockets, &cores, &threads, 318 &maxcpus); 319 regs[0] = vcpu_id; 320 threads = MIN(0xFF, threads - 1); 321 regs[1] = (threads << 8) | 322 (vcpu_id >> log2(threads + 1)); 323 /* 324 * XXX Bhyve topology cannot yet represent >1 node per 325 * processor. 326 */ 327 regs[2] = 0; 328 regs[3] = 0; 329 break; 330 331 case CPUID_0000_0001: 332 do_cpuid(1, regs); 333 334 error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state); 335 if (error) { 336 panic("x86_emulate_cpuid: error %d " 337 "fetching x2apic state", error); 338 } 339 340 /* 341 * Override the APIC ID only in ebx 342 */ 343 regs[1] &= ~(CPUID_LOCAL_APIC_ID); 344 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT); 345 346 /* 347 * Don't expose VMX, SpeedStep, TME or SMX capability. 348 * Advertise x2APIC capability and Hypervisor guest. 349 */ 350 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2); 351 regs[2] &= ~(CPUID2_SMX); 352 353 regs[2] |= CPUID2_HV; 354 355 if (x2apic_state != X2APIC_DISABLED) 356 regs[2] |= CPUID2_X2APIC; 357 else 358 regs[2] &= ~CPUID2_X2APIC; 359 360 /* 361 * Only advertise CPUID2_XSAVE in the guest if 362 * the host is using XSAVE. 363 */ 364 if (!(regs[2] & CPUID2_OSXSAVE)) 365 regs[2] &= ~CPUID2_XSAVE; 366 367 /* 368 * If CPUID2_XSAVE is being advertised and the 369 * guest has set CR4_XSAVE, set 370 * CPUID2_OSXSAVE. 371 */ 372 regs[2] &= ~CPUID2_OSXSAVE; 373 if (regs[2] & CPUID2_XSAVE) { 374 error = vm_get_register(vm, vcpu_id, 375 VM_REG_GUEST_CR4, &cr4); 376 if (error) 377 panic("x86_emulate_cpuid: error %d " 378 "fetching %%cr4", error); 379 if (cr4 & CR4_XSAVE) 380 regs[2] |= CPUID2_OSXSAVE; 381 } 382 383 /* 384 * Hide monitor/mwait until we know how to deal with 385 * these instructions. 386 */ 387 regs[2] &= ~CPUID2_MON; 388 389 /* 390 * Hide the performance and debug features. 391 */ 392 regs[2] &= ~CPUID2_PDCM; 393 394 /* 395 * No TSC deadline support in the APIC yet 396 */ 397 regs[2] &= ~CPUID2_TSCDLT; 398 399 /* 400 * Hide thermal monitoring 401 */ 402 regs[3] &= ~(CPUID_ACPI | CPUID_TM); 403 404 /* 405 * Hide the debug store capability. 406 */ 407 regs[3] &= ~CPUID_DS; 408 409 /* 410 * Advertise the Machine Check and MTRR capability. 411 * 412 * Some guest OSes (e.g. Windows) will not boot if 413 * these features are absent. 414 */ 415 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR); 416 417 vm_get_topology(vm, &sockets, &cores, &threads, 418 &maxcpus); 419 logical_cpus = threads * cores; 420 regs[1] &= ~CPUID_HTT_CORES; 421 regs[1] |= (logical_cpus & 0xff) << 16; 422 regs[3] |= CPUID_HTT; 423 break; 424 425 case CPUID_0000_0004: 426 cpuid_count(func, param, regs); 427 428 if (regs[0] || regs[1] || regs[2] || regs[3]) { 429 vm_get_topology(vm, &sockets, &cores, &threads, 430 &maxcpus); 431 regs[0] &= 0x3ff; 432 regs[0] |= (cores - 1) << 26; 433 /* 434 * Cache topology: 435 * - L1 and L2 are shared only by the logical 436 * processors in a single core. 437 * - L3 and above are shared by all logical 438 * processors in the package. 439 */ 440 logical_cpus = threads; 441 level = (regs[0] >> 5) & 0x7; 442 if (level >= 3) 443 logical_cpus *= cores; 444 regs[0] |= (logical_cpus - 1) << 14; 445 } 446 break; 447 448 case CPUID_0000_0007: 449 regs[0] = 0; 450 regs[1] = 0; 451 regs[2] = 0; 452 regs[3] = 0; 453 454 /* leaf 0 */ 455 if (param == 0) { 456 cpuid_count(func, param, regs); 457 458 /* Only leaf 0 is supported */ 459 regs[0] = 0; 460 461 /* 462 * Expose known-safe features. 463 */ 464 regs[1] &= (CPUID_STDEXT_FSGSBASE | 465 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE | 466 CPUID_STDEXT_AVX2 | CPUID_STDEXT_SMEP | 467 CPUID_STDEXT_BMI2 | 468 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM | 469 CPUID_STDEXT_AVX512F | 470 CPUID_STDEXT_RDSEED | 471 CPUID_STDEXT_SMAP | 472 CPUID_STDEXT_AVX512PF | 473 CPUID_STDEXT_AVX512ER | 474 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA); 475 regs[2] = 0; 476 regs[3] &= CPUID_STDEXT3_MD_CLEAR; 477 478 /* Advertise INVPCID if it is enabled. */ 479 error = vm_get_capability(vm, vcpu_id, 480 VM_CAP_ENABLE_INVPCID, &enable_invpcid); 481 if (error == 0 && enable_invpcid) 482 regs[1] |= CPUID_STDEXT_INVPCID; 483 } 484 break; 485 486 case CPUID_0000_0006: 487 regs[0] = CPUTPM1_ARAT; 488 regs[1] = 0; 489 regs[2] = 0; 490 regs[3] = 0; 491 break; 492 493 case CPUID_0000_000A: 494 /* 495 * Handle the access, but report 0 for 496 * all options 497 */ 498 regs[0] = 0; 499 regs[1] = 0; 500 regs[2] = 0; 501 regs[3] = 0; 502 break; 503 504 case CPUID_0000_000B: 505 /* 506 * Intel processor topology enumeration 507 */ 508 if (vmm_is_intel()) { 509 vm_get_topology(vm, &sockets, &cores, &threads, 510 &maxcpus); 511 if (param == 0) { 512 logical_cpus = threads; 513 width = log2(logical_cpus); 514 level = CPUID_TYPE_SMT; 515 x2apic_id = vcpu_id; 516 } 517 518 if (param == 1) { 519 logical_cpus = threads * cores; 520 width = log2(logical_cpus); 521 level = CPUID_TYPE_CORE; 522 x2apic_id = vcpu_id; 523 } 524 525 if (!cpuid_leaf_b || param >= 2) { 526 width = 0; 527 logical_cpus = 0; 528 level = 0; 529 x2apic_id = 0; 530 } 531 532 regs[0] = width & 0x1f; 533 regs[1] = logical_cpus & 0xffff; 534 regs[2] = (level << 8) | (param & 0xff); 535 regs[3] = x2apic_id; 536 } else { 537 regs[0] = 0; 538 regs[1] = 0; 539 regs[2] = 0; 540 regs[3] = 0; 541 } 542 break; 543 544 case CPUID_0000_000D: 545 limits = vmm_get_xsave_limits(); 546 if (!limits->xsave_enabled) { 547 regs[0] = 0; 548 regs[1] = 0; 549 regs[2] = 0; 550 regs[3] = 0; 551 break; 552 } 553 554 cpuid_count(func, param, regs); 555 switch (param) { 556 case 0: 557 /* 558 * Only permit the guest to use bits 559 * that are active in the host in 560 * %xcr0. Also, claim that the 561 * maximum save area size is 562 * equivalent to the host's current 563 * save area size. Since this runs 564 * "inside" of vmrun(), it runs with 565 * the guest's xcr0, so the current 566 * save area size is correct as-is. 567 */ 568 regs[0] &= limits->xcr0_allowed; 569 regs[2] = limits->xsave_max_size; 570 regs[3] &= (limits->xcr0_allowed >> 32); 571 break; 572 case 1: 573 /* Only permit XSAVEOPT. */ 574 regs[0] &= CPUID_EXTSTATE_XSAVEOPT; 575 regs[1] = 0; 576 regs[2] = 0; 577 regs[3] = 0; 578 break; 579 default: 580 /* 581 * If the leaf is for a permitted feature, 582 * pass through as-is, otherwise return 583 * all zeroes. 584 */ 585 if (!(limits->xcr0_allowed & (1ul << param))) { 586 regs[0] = 0; 587 regs[1] = 0; 588 regs[2] = 0; 589 regs[3] = 0; 590 } 591 break; 592 } 593 break; 594 595 case CPUID_0000_000F: 596 case CPUID_0000_0010: 597 /* 598 * Do not report any Resource Director Technology 599 * capabilities. Exposing control of cache or memory 600 * controller resource partitioning to the guest is not 601 * at all sensible. 602 * 603 * This is already hidden at a high level by masking of 604 * leaf 0x7. Even still, a guest may look here for 605 * detailed capability information. 606 */ 607 regs[0] = 0; 608 regs[1] = 0; 609 regs[2] = 0; 610 regs[3] = 0; 611 break; 612 613 case CPUID_0000_0015: 614 /* 615 * Don't report CPU TSC/Crystal ratio and clock 616 * values since guests may use these to derive the 617 * local APIC frequency.. 618 */ 619 regs[0] = 0; 620 regs[1] = 0; 621 regs[2] = 0; 622 regs[3] = 0; 623 break; 624 625 case 0x40000000: 626 regs[0] = CPUID_VM_HIGH; 627 bcopy(bhyve_id, ®s[1], 4); 628 bcopy(bhyve_id + 4, ®s[2], 4); 629 bcopy(bhyve_id + 8, ®s[3], 4); 630 break; 631 632 default: 633 default_leaf: 634 /* 635 * The leaf value has already been clamped so 636 * simply pass this through, keeping count of 637 * how many unhandled leaf values have been seen. 638 */ 639 atomic_add_long(&bhyve_xcpuids, 1); 640 cpuid_count(func, param, regs); 641 break; 642 } 643 644 /* 645 * CPUID clears the upper 32-bits of the long-mode registers. 646 */ 647 *rax = regs[0]; 648 *rbx = regs[1]; 649 *rcx = regs[2]; 650 *rdx = regs[3]; 651 652 return (1); 653 } 654 655 bool 656 vm_cpuid_capability(struct vm *vm, int vcpuid, enum vm_cpuid_capability cap) 657 { 658 bool rv; 659 660 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d", 661 __func__, cap)); 662 663 /* 664 * Simply passthrough the capabilities of the host cpu for now. 665 */ 666 rv = false; 667 switch (cap) { 668 #ifdef __FreeBSD__ 669 case VCC_NO_EXECUTE: 670 if (amd_feature & AMDID_NX) 671 rv = true; 672 break; 673 case VCC_FFXSR: 674 if (amd_feature & AMDID_FFXSR) 675 rv = true; 676 break; 677 case VCC_TCE: 678 if (amd_feature2 & AMDID2_TCE) 679 rv = true; 680 break; 681 #else 682 case VCC_NO_EXECUTE: 683 if (is_x86_feature(x86_featureset, X86FSET_NX)) 684 rv = true; 685 break; 686 /* XXXJOY: No kernel detection for FFXR or TCE at present, so ignore */ 687 case VCC_FFXSR: 688 case VCC_TCE: 689 break; 690 #endif 691 default: 692 panic("%s: unknown vm_cpu_capability %d", __func__, cap); 693 } 694 return (rv); 695 } 696