1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/param.h> 48 #include <sys/pcpu.h> 49 #include <sys/systm.h> 50 #include <sys/sysctl.h> 51 #include <sys/x86_archext.h> 52 53 #include <machine/clock.h> 54 #include <machine/cpufunc.h> 55 #include <machine/md_var.h> 56 #include <machine/segments.h> 57 #include <machine/specialreg.h> 58 59 #include <machine/vmm.h> 60 61 #include "vmm_host.h" 62 #include "vmm_ktr.h" 63 #include "vmm_util.h" 64 #include "x86.h" 65 66 SYSCTL_DECL(_hw_vmm); 67 SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD, 0, NULL); 68 69 #define CPUID_VM_HIGH 0x40000000 70 71 static const char bhyve_id[12] = "bhyve bhyve "; 72 73 static uint64_t bhyve_xcpuids; 74 SYSCTL_ULONG(_hw_vmm, OID_AUTO, bhyve_xcpuids, CTLFLAG_RW, &bhyve_xcpuids, 0, 75 "Number of times an unknown cpuid leaf was accessed"); 76 77 static int cpuid_leaf_b = 1; 78 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN, 79 &cpuid_leaf_b, 0, NULL); 80 81 /* 82 * Round up to the next power of two, if necessary, and then take log2. 83 * Returns -1 if argument is zero. 84 */ 85 static __inline int 86 log2(u_int x) 87 { 88 89 return (fls(x << (1 - powerof2(x))) - 1); 90 } 91 92 int 93 x86_emulate_cpuid(struct vm *vm, int vcpu_id, 94 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 95 { 96 const struct xsave_limits *limits; 97 uint64_t cr4; 98 int error, enable_invpcid, level, width = 0, x2apic_id = 0; 99 unsigned int func, regs[4], logical_cpus = 0; 100 enum x2apic_state x2apic_state; 101 uint16_t cores, maxcpus, sockets, threads; 102 103 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", *eax, *ecx); 104 105 /* 106 * Requests for invalid CPUID levels should map to the highest 107 * available level instead. 108 */ 109 if (cpu_exthigh != 0 && *eax >= 0x80000000) { 110 if (*eax > cpu_exthigh) 111 *eax = cpu_exthigh; 112 } else if (*eax >= 0x40000000) { 113 if (*eax > CPUID_VM_HIGH) 114 *eax = CPUID_VM_HIGH; 115 } else if (*eax > cpu_high) { 116 *eax = cpu_high; 117 } 118 119 func = *eax; 120 121 /* 122 * In general the approach used for CPU topology is to 123 * advertise a flat topology where all CPUs are packages with 124 * no multi-core or SMT. 125 */ 126 switch (func) { 127 /* 128 * Pass these through to the guest 129 */ 130 case CPUID_0000_0000: 131 case CPUID_0000_0002: 132 case CPUID_0000_0003: 133 case CPUID_8000_0000: 134 case CPUID_8000_0002: 135 case CPUID_8000_0003: 136 case CPUID_8000_0004: 137 case CPUID_8000_0006: 138 cpuid_count(*eax, *ecx, regs); 139 break; 140 case CPUID_8000_0008: 141 cpuid_count(*eax, *ecx, regs); 142 if (vmm_is_amd()) { 143 /* 144 * As on Intel (0000_0007:0, EDX), mask out 145 * unsupported or unsafe AMD extended features 146 * (8000_0008 EBX). 147 */ 148 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF | 149 AMDFEID_XSAVEERPTR); 150 151 vm_get_topology(vm, &sockets, &cores, &threads, 152 &maxcpus); 153 /* 154 * Here, width is ApicIdCoreIdSize, present on 155 * at least Family 15h and newer. It 156 * represents the "number of bits in the 157 * initial apicid that indicate thread id 158 * within a package." 159 * 160 * Our topo_probe_amd() uses it for 161 * pkg_id_shift and other OSes may rely on it. 162 */ 163 width = MIN(0xF, log2(threads * cores)); 164 if (width < 0x4) 165 width = 0; 166 logical_cpus = MIN(0xFF, threads * cores - 1); 167 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | logical_cpus; 168 } 169 break; 170 171 case CPUID_8000_0001: 172 cpuid_count(*eax, *ecx, regs); 173 174 /* 175 * Hide SVM from guest. 176 */ 177 regs[2] &= ~AMDID2_SVM; 178 179 /* 180 * Don't advertise extended performance counter MSRs 181 * to the guest. 182 */ 183 regs[2] &= ~AMDID2_PCXC; 184 regs[2] &= ~AMDID2_PNXC; 185 regs[2] &= ~AMDID2_PTSCEL2I; 186 187 /* 188 * Don't advertise Instruction Based Sampling feature. 189 */ 190 regs[2] &= ~AMDID2_IBS; 191 192 /* NodeID MSR not available */ 193 regs[2] &= ~AMDID2_NODE_ID; 194 195 /* Don't advertise the OS visible workaround feature */ 196 regs[2] &= ~AMDID2_OSVW; 197 198 /* Hide mwaitx/monitorx capability from the guest */ 199 regs[2] &= ~AMDID2_MWAITX; 200 201 #ifndef __FreeBSD__ 202 /* 203 * Detection routines for TCE and FFXSR are missing 204 * from our vm_cpuid_capability() detection logic 205 * today. Mask them out until that is remedied. 206 * They do not appear to be in common usage, so their 207 * absence should not cause undue trouble. 208 */ 209 regs[2] &= ~AMDID2_TCE; 210 regs[3] &= ~AMDID_FFXSR; 211 #endif 212 213 /* 214 * Hide rdtscp/ia32_tsc_aux until we know how 215 * to deal with them. 216 */ 217 regs[3] &= ~AMDID_RDTSCP; 218 break; 219 220 case CPUID_8000_0007: 221 /* 222 * AMD uses this leaf to advertise the processor's 223 * power monitoring and RAS capabilities. These 224 * features are hardware-specific and exposing 225 * them to a guest doesn't make a lot of sense. 226 * 227 * Intel uses this leaf only to advertise the 228 * "Invariant TSC" feature with all other bits 229 * being reserved (set to zero). 230 */ 231 regs[0] = 0; 232 regs[1] = 0; 233 regs[2] = 0; 234 regs[3] = 0; 235 236 /* 237 * "Invariant TSC" can be advertised to the guest if: 238 * - host TSC frequency is invariant 239 * - host TSCs are synchronized across physical cpus 240 * 241 * XXX This still falls short because the vcpu 242 * can observe the TSC moving backwards as it 243 * migrates across physical cpus. But at least 244 * it should discourage the guest from using the 245 * TSC to keep track of time. 246 */ 247 #ifdef __FreeBSD__ 248 /* XXXJOY: Wire up with our own TSC logic */ 249 if (tsc_is_invariant && smp_tsc) 250 regs[3] |= AMDPM_TSC_INVARIANT; 251 #endif /* __FreeBSD__ */ 252 break; 253 254 case CPUID_8000_001D: 255 /* AMD Cache topology, like 0000_0004 for Intel. */ 256 if (!vmm_is_amd()) 257 goto default_leaf; 258 259 /* 260 * Similar to Intel, generate a ficticious cache 261 * topology for the guest with L3 shared by the 262 * package, and L1 and L2 local to a core. 263 */ 264 vm_get_topology(vm, &sockets, &cores, &threads, 265 &maxcpus); 266 switch (*ecx) { 267 case 0: 268 logical_cpus = threads; 269 level = 1; 270 func = 1; /* data cache */ 271 break; 272 case 1: 273 logical_cpus = threads; 274 level = 2; 275 func = 3; /* unified cache */ 276 break; 277 case 2: 278 logical_cpus = threads * cores; 279 level = 3; 280 func = 3; /* unified cache */ 281 break; 282 default: 283 logical_cpus = 0; 284 level = 0; 285 func = 0; 286 break; 287 } 288 289 logical_cpus = MIN(0xfff, logical_cpus - 1); 290 regs[0] = (logical_cpus << 14) | (1 << 8) | 291 (level << 5) | func; 292 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0; 293 regs[2] = 0; 294 regs[3] = 0; 295 break; 296 297 case CPUID_8000_001E: 298 /* AMD Family 16h+ additional identifiers */ 299 if (!vmm_is_amd() || CPUID_TO_FAMILY(cpu_id) < 0x16) 300 goto default_leaf; 301 302 vm_get_topology(vm, &sockets, &cores, &threads, 303 &maxcpus); 304 regs[0] = vcpu_id; 305 threads = MIN(0xFF, threads - 1); 306 regs[1] = (threads << 8) | 307 (vcpu_id >> log2(threads + 1)); 308 /* 309 * XXX Bhyve topology cannot yet represent >1 node per 310 * processor. 311 */ 312 regs[2] = 0; 313 regs[3] = 0; 314 break; 315 316 case CPUID_0000_0001: 317 do_cpuid(1, regs); 318 319 error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state); 320 if (error) { 321 panic("x86_emulate_cpuid: error %d " 322 "fetching x2apic state", error); 323 } 324 325 /* 326 * Override the APIC ID only in ebx 327 */ 328 regs[1] &= ~(CPUID_LOCAL_APIC_ID); 329 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT); 330 331 /* 332 * Don't expose VMX, SpeedStep, TME or SMX capability. 333 * Advertise x2APIC capability and Hypervisor guest. 334 */ 335 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2); 336 regs[2] &= ~(CPUID2_SMX); 337 338 regs[2] |= CPUID2_HV; 339 340 if (x2apic_state != X2APIC_DISABLED) 341 regs[2] |= CPUID2_X2APIC; 342 else 343 regs[2] &= ~CPUID2_X2APIC; 344 345 /* 346 * Only advertise CPUID2_XSAVE in the guest if 347 * the host is using XSAVE. 348 */ 349 if (!(regs[2] & CPUID2_OSXSAVE)) 350 regs[2] &= ~CPUID2_XSAVE; 351 352 /* 353 * If CPUID2_XSAVE is being advertised and the 354 * guest has set CR4_XSAVE, set 355 * CPUID2_OSXSAVE. 356 */ 357 regs[2] &= ~CPUID2_OSXSAVE; 358 if (regs[2] & CPUID2_XSAVE) { 359 error = vm_get_register(vm, vcpu_id, 360 VM_REG_GUEST_CR4, &cr4); 361 if (error) 362 panic("x86_emulate_cpuid: error %d " 363 "fetching %%cr4", error); 364 if (cr4 & CR4_XSAVE) 365 regs[2] |= CPUID2_OSXSAVE; 366 } 367 368 /* 369 * Hide monitor/mwait until we know how to deal with 370 * these instructions. 371 */ 372 regs[2] &= ~CPUID2_MON; 373 374 /* 375 * Hide the performance and debug features. 376 */ 377 regs[2] &= ~CPUID2_PDCM; 378 379 /* 380 * No TSC deadline support in the APIC yet 381 */ 382 regs[2] &= ~CPUID2_TSCDLT; 383 384 /* 385 * Hide thermal monitoring 386 */ 387 regs[3] &= ~(CPUID_ACPI | CPUID_TM); 388 389 /* 390 * Hide the debug store capability. 391 */ 392 regs[3] &= ~CPUID_DS; 393 394 /* 395 * Advertise the Machine Check and MTRR capability. 396 * 397 * Some guest OSes (e.g. Windows) will not boot if 398 * these features are absent. 399 */ 400 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR); 401 402 vm_get_topology(vm, &sockets, &cores, &threads, 403 &maxcpus); 404 logical_cpus = threads * cores; 405 regs[1] &= ~CPUID_HTT_CORES; 406 regs[1] |= (logical_cpus & 0xff) << 16; 407 regs[3] |= CPUID_HTT; 408 break; 409 410 case CPUID_0000_0004: 411 cpuid_count(*eax, *ecx, regs); 412 413 if (regs[0] || regs[1] || regs[2] || regs[3]) { 414 vm_get_topology(vm, &sockets, &cores, &threads, 415 &maxcpus); 416 regs[0] &= 0x3ff; 417 regs[0] |= (cores - 1) << 26; 418 /* 419 * Cache topology: 420 * - L1 and L2 are shared only by the logical 421 * processors in a single core. 422 * - L3 and above are shared by all logical 423 * processors in the package. 424 */ 425 logical_cpus = threads; 426 level = (regs[0] >> 5) & 0x7; 427 if (level >= 3) 428 logical_cpus *= cores; 429 regs[0] |= (logical_cpus - 1) << 14; 430 } 431 break; 432 433 case CPUID_0000_0007: 434 regs[0] = 0; 435 regs[1] = 0; 436 regs[2] = 0; 437 regs[3] = 0; 438 439 /* leaf 0 */ 440 if (*ecx == 0) { 441 cpuid_count(*eax, *ecx, regs); 442 443 /* Only leaf 0 is supported */ 444 regs[0] = 0; 445 446 /* 447 * Expose known-safe features. 448 */ 449 regs[1] &= (CPUID_STDEXT_FSGSBASE | 450 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE | 451 CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 | 452 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM | 453 CPUID_STDEXT_AVX512F | 454 CPUID_STDEXT_RDSEED | 455 CPUID_STDEXT_AVX512PF | 456 CPUID_STDEXT_AVX512ER | 457 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA); 458 regs[2] = 0; 459 regs[3] &= CPUID_STDEXT3_MD_CLEAR; 460 461 /* Advertise INVPCID if it is enabled. */ 462 error = vm_get_capability(vm, vcpu_id, 463 VM_CAP_ENABLE_INVPCID, &enable_invpcid); 464 if (error == 0 && enable_invpcid) 465 regs[1] |= CPUID_STDEXT_INVPCID; 466 } 467 break; 468 469 case CPUID_0000_0006: 470 regs[0] = CPUTPM1_ARAT; 471 regs[1] = 0; 472 regs[2] = 0; 473 regs[3] = 0; 474 break; 475 476 case CPUID_0000_000A: 477 /* 478 * Handle the access, but report 0 for 479 * all options 480 */ 481 regs[0] = 0; 482 regs[1] = 0; 483 regs[2] = 0; 484 regs[3] = 0; 485 break; 486 487 case CPUID_0000_000B: 488 /* 489 * Intel processor topology enumeration 490 */ 491 if (vmm_is_intel()) { 492 vm_get_topology(vm, &sockets, &cores, &threads, 493 &maxcpus); 494 if (*ecx == 0) { 495 logical_cpus = threads; 496 width = log2(logical_cpus); 497 level = CPUID_TYPE_SMT; 498 x2apic_id = vcpu_id; 499 } 500 501 if (*ecx == 1) { 502 logical_cpus = threads * cores; 503 width = log2(logical_cpus); 504 level = CPUID_TYPE_CORE; 505 x2apic_id = vcpu_id; 506 } 507 508 if (!cpuid_leaf_b || *ecx >= 2) { 509 width = 0; 510 logical_cpus = 0; 511 level = 0; 512 x2apic_id = 0; 513 } 514 515 regs[0] = width & 0x1f; 516 regs[1] = logical_cpus & 0xffff; 517 regs[2] = (level << 8) | (*ecx & 0xff); 518 regs[3] = x2apic_id; 519 } else { 520 regs[0] = 0; 521 regs[1] = 0; 522 regs[2] = 0; 523 regs[3] = 0; 524 } 525 break; 526 527 case CPUID_0000_000D: 528 limits = vmm_get_xsave_limits(); 529 if (!limits->xsave_enabled) { 530 regs[0] = 0; 531 regs[1] = 0; 532 regs[2] = 0; 533 regs[3] = 0; 534 break; 535 } 536 537 cpuid_count(*eax, *ecx, regs); 538 switch (*ecx) { 539 case 0: 540 /* 541 * Only permit the guest to use bits 542 * that are active in the host in 543 * %xcr0. Also, claim that the 544 * maximum save area size is 545 * equivalent to the host's current 546 * save area size. Since this runs 547 * "inside" of vmrun(), it runs with 548 * the guest's xcr0, so the current 549 * save area size is correct as-is. 550 */ 551 regs[0] &= limits->xcr0_allowed; 552 regs[2] = limits->xsave_max_size; 553 regs[3] &= (limits->xcr0_allowed >> 32); 554 break; 555 case 1: 556 /* Only permit XSAVEOPT. */ 557 regs[0] &= CPUID_EXTSTATE_XSAVEOPT; 558 regs[1] = 0; 559 regs[2] = 0; 560 regs[3] = 0; 561 break; 562 default: 563 /* 564 * If the leaf is for a permitted feature, 565 * pass through as-is, otherwise return 566 * all zeroes. 567 */ 568 if (!(limits->xcr0_allowed & (1ul << *ecx))) { 569 regs[0] = 0; 570 regs[1] = 0; 571 regs[2] = 0; 572 regs[3] = 0; 573 } 574 break; 575 } 576 break; 577 578 case 0x40000000: 579 regs[0] = CPUID_VM_HIGH; 580 bcopy(bhyve_id, ®s[1], 4); 581 bcopy(bhyve_id + 4, ®s[2], 4); 582 bcopy(bhyve_id + 8, ®s[3], 4); 583 break; 584 585 default: 586 default_leaf: 587 /* 588 * The leaf value has already been clamped so 589 * simply pass this through, keeping count of 590 * how many unhandled leaf values have been seen. 591 */ 592 atomic_add_long(&bhyve_xcpuids, 1); 593 cpuid_count(*eax, *ecx, regs); 594 break; 595 } 596 597 *eax = regs[0]; 598 *ebx = regs[1]; 599 *ecx = regs[2]; 600 *edx = regs[3]; 601 602 return (1); 603 } 604 605 bool 606 vm_cpuid_capability(struct vm *vm, int vcpuid, enum vm_cpuid_capability cap) 607 { 608 bool rv; 609 610 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d", 611 __func__, cap)); 612 613 /* 614 * Simply passthrough the capabilities of the host cpu for now. 615 */ 616 rv = false; 617 switch (cap) { 618 #ifdef __FreeBSD__ 619 case VCC_NO_EXECUTE: 620 if (amd_feature & AMDID_NX) 621 rv = true; 622 break; 623 case VCC_FFXSR: 624 if (amd_feature & AMDID_FFXSR) 625 rv = true; 626 break; 627 case VCC_TCE: 628 if (amd_feature2 & AMDID2_TCE) 629 rv = true; 630 break; 631 #else 632 case VCC_NO_EXECUTE: 633 if (is_x86_feature(x86_featureset, X86FSET_NX)) 634 rv = true; 635 break; 636 /* XXXJOY: No kernel detection for FFXR or TCE at present, so ignore */ 637 case VCC_FFXSR: 638 case VCC_TCE: 639 break; 640 #endif 641 default: 642 panic("%s: unknown vm_cpu_capability %d", __func__, cap); 643 } 644 return (rv); 645 } 646