1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 * Copyright 2020 Oxide Computer Company 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/pcpu.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/x86_archext.h> 53 54 #include <machine/clock.h> 55 #include <machine/cpufunc.h> 56 #include <machine/md_var.h> 57 #include <machine/segments.h> 58 #include <machine/specialreg.h> 59 60 #include <machine/vmm.h> 61 62 #include "vmm_host.h" 63 #include "vmm_ktr.h" 64 #include "vmm_util.h" 65 #include "x86.h" 66 67 SYSCTL_DECL(_hw_vmm); 68 SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD, 0, NULL); 69 70 #define CPUID_VM_HIGH 0x40000000 71 72 static const char bhyve_id[12] = "bhyve bhyve "; 73 74 static uint64_t bhyve_xcpuids; 75 SYSCTL_ULONG(_hw_vmm, OID_AUTO, bhyve_xcpuids, CTLFLAG_RW, &bhyve_xcpuids, 0, 76 "Number of times an unknown cpuid leaf was accessed"); 77 78 static int cpuid_leaf_b = 1; 79 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN, 80 &cpuid_leaf_b, 0, NULL); 81 82 /* 83 * Round up to the next power of two, if necessary, and then take log2. 84 * Returns -1 if argument is zero. 85 */ 86 static __inline int 87 log2(u_int x) 88 { 89 90 return (fls(x << (1 - powerof2(x))) - 1); 91 } 92 93 int 94 x86_emulate_cpuid(struct vm *vm, int vcpu_id, uint64_t *rax, uint64_t *rbx, 95 uint64_t *rcx, uint64_t *rdx) 96 { 97 const struct xsave_limits *limits; 98 uint64_t cr4; 99 int error, enable_invpcid, level, width = 0, x2apic_id = 0; 100 unsigned int func, regs[4], logical_cpus = 0, param; 101 enum x2apic_state x2apic_state; 102 uint16_t cores, maxcpus, sockets, threads; 103 104 /* 105 * The function of CPUID is controlled through the provided value of 106 * %eax (and secondarily %ecx, for certain leaf data). 107 */ 108 func = (uint32_t)*rax; 109 param = (uint32_t)*rcx; 110 111 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", func, param); 112 113 /* 114 * Requests for invalid CPUID levels should map to the highest 115 * available level instead. 116 */ 117 if (cpu_exthigh != 0 && func >= 0x80000000) { 118 if (func > cpu_exthigh) 119 func = cpu_exthigh; 120 } else if (func >= 0x40000000) { 121 if (func > CPUID_VM_HIGH) 122 func = CPUID_VM_HIGH; 123 } else if (func > cpu_high) { 124 func = cpu_high; 125 } 126 127 /* 128 * In general the approach used for CPU topology is to 129 * advertise a flat topology where all CPUs are packages with 130 * no multi-core or SMT. 131 */ 132 switch (func) { 133 /* 134 * Pass these through to the guest 135 */ 136 case CPUID_0000_0000: 137 case CPUID_0000_0002: 138 case CPUID_0000_0003: 139 case CPUID_8000_0000: 140 case CPUID_8000_0002: 141 case CPUID_8000_0003: 142 case CPUID_8000_0004: 143 case CPUID_8000_0006: 144 cpuid_count(func, param, regs); 145 break; 146 case CPUID_8000_0008: 147 cpuid_count(func, param, regs); 148 if (vmm_is_amd()) { 149 /* 150 * As on Intel (0000_0007:0, EDX), mask out 151 * unsupported or unsafe AMD extended features 152 * (8000_0008 EBX). 153 */ 154 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF | 155 AMDFEID_XSAVEERPTR); 156 157 vm_get_topology(vm, &sockets, &cores, &threads, 158 &maxcpus); 159 /* 160 * Here, width is ApicIdCoreIdSize, present on 161 * at least Family 15h and newer. It 162 * represents the "number of bits in the 163 * initial apicid that indicate thread id 164 * within a package." 165 * 166 * Our topo_probe_amd() uses it for 167 * pkg_id_shift and other OSes may rely on it. 168 */ 169 width = MIN(0xF, log2(threads * cores)); 170 if (width < 0x4) 171 width = 0; 172 logical_cpus = MIN(0xFF, threads * cores - 1); 173 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | logical_cpus; 174 } 175 break; 176 177 case CPUID_8000_0001: 178 cpuid_count(func, param, regs); 179 180 /* 181 * Hide SVM from guest. 182 */ 183 regs[2] &= ~AMDID2_SVM; 184 185 /* 186 * Don't advertise extended performance counter MSRs 187 * to the guest. 188 */ 189 regs[2] &= ~AMDID2_PCXC; 190 regs[2] &= ~AMDID2_PNXC; 191 regs[2] &= ~AMDID2_PTSCEL2I; 192 193 /* 194 * Don't advertise Instruction Based Sampling feature. 195 */ 196 regs[2] &= ~AMDID2_IBS; 197 198 /* NodeID MSR not available */ 199 regs[2] &= ~AMDID2_NODE_ID; 200 201 /* Don't advertise the OS visible workaround feature */ 202 regs[2] &= ~AMDID2_OSVW; 203 204 /* Hide mwaitx/monitorx capability from the guest */ 205 regs[2] &= ~AMDID2_MWAITX; 206 207 #ifndef __FreeBSD__ 208 /* 209 * Detection routines for TCE and FFXSR are missing 210 * from our vm_cpuid_capability() detection logic 211 * today. Mask them out until that is remedied. 212 * They do not appear to be in common usage, so their 213 * absence should not cause undue trouble. 214 */ 215 regs[2] &= ~AMDID2_TCE; 216 regs[3] &= ~AMDID_FFXSR; 217 #endif 218 219 /* 220 * Hide rdtscp/ia32_tsc_aux until we know how 221 * to deal with them. 222 */ 223 regs[3] &= ~AMDID_RDTSCP; 224 break; 225 226 case CPUID_8000_0007: 227 /* 228 * AMD uses this leaf to advertise the processor's 229 * power monitoring and RAS capabilities. These 230 * features are hardware-specific and exposing 231 * them to a guest doesn't make a lot of sense. 232 * 233 * Intel uses this leaf only to advertise the 234 * "Invariant TSC" feature with all other bits 235 * being reserved (set to zero). 236 */ 237 regs[0] = 0; 238 regs[1] = 0; 239 regs[2] = 0; 240 regs[3] = 0; 241 242 /* 243 * "Invariant TSC" can be advertised to the guest if: 244 * - host TSC frequency is invariant 245 * - host TSCs are synchronized across physical cpus 246 * 247 * XXX This still falls short because the vcpu 248 * can observe the TSC moving backwards as it 249 * migrates across physical cpus. But at least 250 * it should discourage the guest from using the 251 * TSC to keep track of time. 252 */ 253 #ifdef __FreeBSD__ 254 /* XXXJOY: Wire up with our own TSC logic */ 255 if (tsc_is_invariant && smp_tsc) 256 regs[3] |= AMDPM_TSC_INVARIANT; 257 #endif /* __FreeBSD__ */ 258 break; 259 260 case CPUID_8000_001D: 261 /* AMD Cache topology, like 0000_0004 for Intel. */ 262 if (!vmm_is_amd()) 263 goto default_leaf; 264 265 /* 266 * Similar to Intel, generate a ficticious cache 267 * topology for the guest with L3 shared by the 268 * package, and L1 and L2 local to a core. 269 */ 270 vm_get_topology(vm, &sockets, &cores, &threads, 271 &maxcpus); 272 switch (param) { 273 case 0: 274 logical_cpus = threads; 275 level = 1; 276 func = 1; /* data cache */ 277 break; 278 case 1: 279 logical_cpus = threads; 280 level = 2; 281 func = 3; /* unified cache */ 282 break; 283 case 2: 284 logical_cpus = threads * cores; 285 level = 3; 286 func = 3; /* unified cache */ 287 break; 288 default: 289 logical_cpus = 0; 290 level = 0; 291 func = 0; 292 break; 293 } 294 295 logical_cpus = MIN(0xfff, logical_cpus - 1); 296 regs[0] = (logical_cpus << 14) | (1 << 8) | 297 (level << 5) | func; 298 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0; 299 regs[2] = 0; 300 regs[3] = 0; 301 break; 302 303 case CPUID_8000_001E: 304 /* AMD Family 16h+ additional identifiers */ 305 if (!vmm_is_amd() || CPUID_TO_FAMILY(cpu_id) < 0x16) 306 goto default_leaf; 307 308 vm_get_topology(vm, &sockets, &cores, &threads, 309 &maxcpus); 310 regs[0] = vcpu_id; 311 threads = MIN(0xFF, threads - 1); 312 regs[1] = (threads << 8) | 313 (vcpu_id >> log2(threads + 1)); 314 /* 315 * XXX Bhyve topology cannot yet represent >1 node per 316 * processor. 317 */ 318 regs[2] = 0; 319 regs[3] = 0; 320 break; 321 322 case CPUID_0000_0001: 323 do_cpuid(1, regs); 324 325 error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state); 326 if (error) { 327 panic("x86_emulate_cpuid: error %d " 328 "fetching x2apic state", error); 329 } 330 331 /* 332 * Override the APIC ID only in ebx 333 */ 334 regs[1] &= ~(CPUID_LOCAL_APIC_ID); 335 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT); 336 337 /* 338 * Don't expose VMX, SpeedStep, TME or SMX capability. 339 * Advertise x2APIC capability and Hypervisor guest. 340 */ 341 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2); 342 regs[2] &= ~(CPUID2_SMX); 343 344 regs[2] |= CPUID2_HV; 345 346 if (x2apic_state != X2APIC_DISABLED) 347 regs[2] |= CPUID2_X2APIC; 348 else 349 regs[2] &= ~CPUID2_X2APIC; 350 351 /* 352 * Only advertise CPUID2_XSAVE in the guest if 353 * the host is using XSAVE. 354 */ 355 if (!(regs[2] & CPUID2_OSXSAVE)) 356 regs[2] &= ~CPUID2_XSAVE; 357 358 /* 359 * If CPUID2_XSAVE is being advertised and the 360 * guest has set CR4_XSAVE, set 361 * CPUID2_OSXSAVE. 362 */ 363 regs[2] &= ~CPUID2_OSXSAVE; 364 if (regs[2] & CPUID2_XSAVE) { 365 error = vm_get_register(vm, vcpu_id, 366 VM_REG_GUEST_CR4, &cr4); 367 if (error) 368 panic("x86_emulate_cpuid: error %d " 369 "fetching %%cr4", error); 370 if (cr4 & CR4_XSAVE) 371 regs[2] |= CPUID2_OSXSAVE; 372 } 373 374 /* 375 * Hide monitor/mwait until we know how to deal with 376 * these instructions. 377 */ 378 regs[2] &= ~CPUID2_MON; 379 380 /* 381 * Hide the performance and debug features. 382 */ 383 regs[2] &= ~CPUID2_PDCM; 384 385 /* 386 * No TSC deadline support in the APIC yet 387 */ 388 regs[2] &= ~CPUID2_TSCDLT; 389 390 /* 391 * Hide thermal monitoring 392 */ 393 regs[3] &= ~(CPUID_ACPI | CPUID_TM); 394 395 /* 396 * Hide the debug store capability. 397 */ 398 regs[3] &= ~CPUID_DS; 399 400 /* 401 * Advertise the Machine Check and MTRR capability. 402 * 403 * Some guest OSes (e.g. Windows) will not boot if 404 * these features are absent. 405 */ 406 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR); 407 408 vm_get_topology(vm, &sockets, &cores, &threads, 409 &maxcpus); 410 logical_cpus = threads * cores; 411 regs[1] &= ~CPUID_HTT_CORES; 412 regs[1] |= (logical_cpus & 0xff) << 16; 413 regs[3] |= CPUID_HTT; 414 break; 415 416 case CPUID_0000_0004: 417 cpuid_count(func, param, regs); 418 419 if (regs[0] || regs[1] || regs[2] || regs[3]) { 420 vm_get_topology(vm, &sockets, &cores, &threads, 421 &maxcpus); 422 regs[0] &= 0x3ff; 423 regs[0] |= (cores - 1) << 26; 424 /* 425 * Cache topology: 426 * - L1 and L2 are shared only by the logical 427 * processors in a single core. 428 * - L3 and above are shared by all logical 429 * processors in the package. 430 */ 431 logical_cpus = threads; 432 level = (regs[0] >> 5) & 0x7; 433 if (level >= 3) 434 logical_cpus *= cores; 435 regs[0] |= (logical_cpus - 1) << 14; 436 } 437 break; 438 439 case CPUID_0000_0007: 440 regs[0] = 0; 441 regs[1] = 0; 442 regs[2] = 0; 443 regs[3] = 0; 444 445 /* leaf 0 */ 446 if (param == 0) { 447 cpuid_count(func, param, regs); 448 449 /* Only leaf 0 is supported */ 450 regs[0] = 0; 451 452 /* 453 * Expose known-safe features. 454 */ 455 regs[1] &= (CPUID_STDEXT_FSGSBASE | 456 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE | 457 CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 | 458 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM | 459 CPUID_STDEXT_AVX512F | 460 CPUID_STDEXT_RDSEED | 461 CPUID_STDEXT_AVX512PF | 462 CPUID_STDEXT_AVX512ER | 463 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA); 464 regs[2] = 0; 465 regs[3] &= CPUID_STDEXT3_MD_CLEAR; 466 467 /* Advertise INVPCID if it is enabled. */ 468 error = vm_get_capability(vm, vcpu_id, 469 VM_CAP_ENABLE_INVPCID, &enable_invpcid); 470 if (error == 0 && enable_invpcid) 471 regs[1] |= CPUID_STDEXT_INVPCID; 472 } 473 break; 474 475 case CPUID_0000_0006: 476 regs[0] = CPUTPM1_ARAT; 477 regs[1] = 0; 478 regs[2] = 0; 479 regs[3] = 0; 480 break; 481 482 case CPUID_0000_000A: 483 /* 484 * Handle the access, but report 0 for 485 * all options 486 */ 487 regs[0] = 0; 488 regs[1] = 0; 489 regs[2] = 0; 490 regs[3] = 0; 491 break; 492 493 case CPUID_0000_000B: 494 /* 495 * Intel processor topology enumeration 496 */ 497 if (vmm_is_intel()) { 498 vm_get_topology(vm, &sockets, &cores, &threads, 499 &maxcpus); 500 if (param == 0) { 501 logical_cpus = threads; 502 width = log2(logical_cpus); 503 level = CPUID_TYPE_SMT; 504 x2apic_id = vcpu_id; 505 } 506 507 if (param == 1) { 508 logical_cpus = threads * cores; 509 width = log2(logical_cpus); 510 level = CPUID_TYPE_CORE; 511 x2apic_id = vcpu_id; 512 } 513 514 if (!cpuid_leaf_b || param >= 2) { 515 width = 0; 516 logical_cpus = 0; 517 level = 0; 518 x2apic_id = 0; 519 } 520 521 regs[0] = width & 0x1f; 522 regs[1] = logical_cpus & 0xffff; 523 regs[2] = (level << 8) | (param & 0xff); 524 regs[3] = x2apic_id; 525 } else { 526 regs[0] = 0; 527 regs[1] = 0; 528 regs[2] = 0; 529 regs[3] = 0; 530 } 531 break; 532 533 case CPUID_0000_000D: 534 limits = vmm_get_xsave_limits(); 535 if (!limits->xsave_enabled) { 536 regs[0] = 0; 537 regs[1] = 0; 538 regs[2] = 0; 539 regs[3] = 0; 540 break; 541 } 542 543 cpuid_count(func, param, regs); 544 switch (param) { 545 case 0: 546 /* 547 * Only permit the guest to use bits 548 * that are active in the host in 549 * %xcr0. Also, claim that the 550 * maximum save area size is 551 * equivalent to the host's current 552 * save area size. Since this runs 553 * "inside" of vmrun(), it runs with 554 * the guest's xcr0, so the current 555 * save area size is correct as-is. 556 */ 557 regs[0] &= limits->xcr0_allowed; 558 regs[2] = limits->xsave_max_size; 559 regs[3] &= (limits->xcr0_allowed >> 32); 560 break; 561 case 1: 562 /* Only permit XSAVEOPT. */ 563 regs[0] &= CPUID_EXTSTATE_XSAVEOPT; 564 regs[1] = 0; 565 regs[2] = 0; 566 regs[3] = 0; 567 break; 568 default: 569 /* 570 * If the leaf is for a permitted feature, 571 * pass through as-is, otherwise return 572 * all zeroes. 573 */ 574 if (!(limits->xcr0_allowed & (1ul << param))) { 575 regs[0] = 0; 576 regs[1] = 0; 577 regs[2] = 0; 578 regs[3] = 0; 579 } 580 break; 581 } 582 break; 583 584 case 0x40000000: 585 regs[0] = CPUID_VM_HIGH; 586 bcopy(bhyve_id, ®s[1], 4); 587 bcopy(bhyve_id + 4, ®s[2], 4); 588 bcopy(bhyve_id + 8, ®s[3], 4); 589 break; 590 591 default: 592 default_leaf: 593 /* 594 * The leaf value has already been clamped so 595 * simply pass this through, keeping count of 596 * how many unhandled leaf values have been seen. 597 */ 598 atomic_add_long(&bhyve_xcpuids, 1); 599 cpuid_count(func, param, regs); 600 break; 601 } 602 603 /* 604 * CPUID clears the upper 32-bits of the long-mode registers. 605 */ 606 *rax = regs[0]; 607 *rbx = regs[1]; 608 *rcx = regs[2]; 609 *rdx = regs[3]; 610 611 return (1); 612 } 613 614 bool 615 vm_cpuid_capability(struct vm *vm, int vcpuid, enum vm_cpuid_capability cap) 616 { 617 bool rv; 618 619 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d", 620 __func__, cap)); 621 622 /* 623 * Simply passthrough the capabilities of the host cpu for now. 624 */ 625 rv = false; 626 switch (cap) { 627 #ifdef __FreeBSD__ 628 case VCC_NO_EXECUTE: 629 if (amd_feature & AMDID_NX) 630 rv = true; 631 break; 632 case VCC_FFXSR: 633 if (amd_feature & AMDID_FFXSR) 634 rv = true; 635 break; 636 case VCC_TCE: 637 if (amd_feature2 & AMDID2_TCE) 638 rv = true; 639 break; 640 #else 641 case VCC_NO_EXECUTE: 642 if (is_x86_feature(x86_featureset, X86FSET_NX)) 643 rv = true; 644 break; 645 /* XXXJOY: No kernel detection for FFXR or TCE at present, so ignore */ 646 case VCC_FFXSR: 647 case VCC_TCE: 648 break; 649 #endif 650 default: 651 panic("%s: unknown vm_cpu_capability %d", __func__, cap); 652 } 653 return (rv); 654 } 655