1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 * Copyright 2020 Oxide Computer Company 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/pcpu.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/x86_archext.h> 53 54 #include <machine/clock.h> 55 #include <machine/cpufunc.h> 56 #include <machine/md_var.h> 57 #include <machine/segments.h> 58 #include <machine/specialreg.h> 59 60 #include <machine/vmm.h> 61 62 #include "vmm_host.h" 63 #include "vmm_ktr.h" 64 #include "vmm_util.h" 65 #include "x86.h" 66 67 SYSCTL_DECL(_hw_vmm); 68 #ifdef __FreeBSD__ 69 static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 70 NULL); 71 #endif 72 73 #define CPUID_VM_HIGH 0x40000000 74 75 static const char bhyve_id[12] = "bhyve bhyve "; 76 77 /* Number of times an unknown cpuid leaf was accessed */ 78 static uint64_t bhyve_xcpuids; 79 80 static int cpuid_leaf_b = 1; 81 82 /* 83 * Round up to the next power of two, if necessary, and then take log2. 84 * Returns -1 if argument is zero. 85 */ 86 static __inline int 87 log2(uint_t x) 88 { 89 90 return (fls(x << (1 - powerof2(x))) - 1); 91 } 92 93 int 94 x86_emulate_cpuid(struct vm *vm, int vcpu_id, uint64_t *rax, uint64_t *rbx, 95 uint64_t *rcx, uint64_t *rdx) 96 { 97 const struct xsave_limits *limits; 98 uint64_t cr4; 99 int error, enable_invpcid, level, width = 0, x2apic_id = 0; 100 unsigned int func, regs[4], logical_cpus = 0, param; 101 enum x2apic_state x2apic_state; 102 uint16_t cores, maxcpus, sockets, threads; 103 104 /* 105 * The function of CPUID is controlled through the provided value of 106 * %eax (and secondarily %ecx, for certain leaf data). 107 */ 108 func = (uint32_t)*rax; 109 param = (uint32_t)*rcx; 110 111 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", func, param); 112 113 /* 114 * Requests for invalid CPUID levels should map to the highest 115 * available level instead. 116 */ 117 if (cpu_exthigh != 0 && func >= 0x80000000) { 118 if (func > cpu_exthigh) 119 func = cpu_exthigh; 120 } else if (func >= 0x40000000) { 121 if (func > CPUID_VM_HIGH) 122 func = CPUID_VM_HIGH; 123 } else if (func > cpu_high) { 124 func = cpu_high; 125 } 126 127 /* 128 * In general the approach used for CPU topology is to 129 * advertise a flat topology where all CPUs are packages with 130 * no multi-core or SMT. 131 */ 132 switch (func) { 133 /* 134 * Pass these through to the guest 135 */ 136 case CPUID_0000_0000: 137 case CPUID_0000_0002: 138 case CPUID_0000_0003: 139 case CPUID_8000_0000: 140 case CPUID_8000_0002: 141 case CPUID_8000_0003: 142 case CPUID_8000_0004: 143 case CPUID_8000_0006: 144 cpuid_count(func, param, regs); 145 break; 146 case CPUID_8000_0008: 147 cpuid_count(func, param, regs); 148 if (vmm_is_svm()) { 149 /* 150 * As on Intel (0000_0007:0, EDX), mask out 151 * unsupported or unsafe AMD extended features 152 * (8000_0008 EBX). 153 */ 154 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF | 155 AMDFEID_XSAVEERPTR); 156 157 vm_get_topology(vm, &sockets, &cores, &threads, 158 &maxcpus); 159 /* 160 * Here, width is ApicIdCoreIdSize, present on 161 * at least Family 15h and newer. It 162 * represents the "number of bits in the 163 * initial apicid that indicate thread id 164 * within a package." 165 * 166 * Our topo_probe_amd() uses it for 167 * pkg_id_shift and other OSes may rely on it. 168 */ 169 width = MIN(0xF, log2(threads * cores)); 170 if (width < 0x4) 171 width = 0; 172 logical_cpus = MIN(0xFF, threads * cores - 1); 173 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | 174 logical_cpus; 175 } 176 break; 177 178 case CPUID_8000_0001: 179 cpuid_count(func, param, regs); 180 181 /* 182 * Hide SVM from guest. 183 */ 184 regs[2] &= ~AMDID2_SVM; 185 186 /* 187 * Don't advertise extended performance counter MSRs 188 * to the guest. 189 */ 190 regs[2] &= ~AMDID2_PCXC; 191 regs[2] &= ~AMDID2_PNXC; 192 regs[2] &= ~AMDID2_PTSCEL2I; 193 194 /* 195 * Don't advertise Instruction Based Sampling feature. 196 */ 197 regs[2] &= ~AMDID2_IBS; 198 199 /* NodeID MSR not available */ 200 regs[2] &= ~AMDID2_NODE_ID; 201 202 /* Don't advertise the OS visible workaround feature */ 203 regs[2] &= ~AMDID2_OSVW; 204 205 /* Hide mwaitx/monitorx capability from the guest */ 206 regs[2] &= ~AMDID2_MWAITX; 207 208 #ifndef __FreeBSD__ 209 /* 210 * Detection routines for TCE and FFXSR are missing 211 * from our vm_cpuid_capability() detection logic 212 * today. Mask them out until that is remedied. 213 * They do not appear to be in common usage, so their 214 * absence should not cause undue trouble. 215 */ 216 regs[2] &= ~AMDID2_TCE; 217 regs[3] &= ~AMDID_FFXSR; 218 #endif 219 220 /* 221 * Hide rdtscp/ia32_tsc_aux until we know how 222 * to deal with them. 223 */ 224 regs[3] &= ~AMDID_RDTSCP; 225 break; 226 227 case CPUID_8000_0007: 228 /* 229 * AMD uses this leaf to advertise the processor's 230 * power monitoring and RAS capabilities. These 231 * features are hardware-specific and exposing 232 * them to a guest doesn't make a lot of sense. 233 * 234 * Intel uses this leaf only to advertise the 235 * "Invariant TSC" feature with all other bits 236 * being reserved (set to zero). 237 */ 238 regs[0] = 0; 239 regs[1] = 0; 240 regs[2] = 0; 241 regs[3] = 0; 242 243 /* 244 * "Invariant TSC" can be advertised to the guest if: 245 * - host TSC frequency is invariant 246 * - host TSCs are synchronized across physical cpus 247 * 248 * XXX This still falls short because the vcpu 249 * can observe the TSC moving backwards as it 250 * migrates across physical cpus. But at least 251 * it should discourage the guest from using the 252 * TSC to keep track of time. 253 */ 254 #ifdef __FreeBSD__ 255 /* XXXJOY: Wire up with our own TSC logic */ 256 if (tsc_is_invariant && smp_tsc) 257 regs[3] |= AMDPM_TSC_INVARIANT; 258 #endif /* __FreeBSD__ */ 259 break; 260 261 case CPUID_8000_001D: 262 /* AMD Cache topology, like 0000_0004 for Intel. */ 263 if (!vmm_is_svm()) 264 goto default_leaf; 265 266 /* 267 * Similar to Intel, generate a ficticious cache 268 * topology for the guest with L3 shared by the 269 * package, and L1 and L2 local to a core. 270 */ 271 vm_get_topology(vm, &sockets, &cores, &threads, 272 &maxcpus); 273 switch (param) { 274 case 0: 275 logical_cpus = threads; 276 level = 1; 277 func = 1; /* data cache */ 278 break; 279 case 1: 280 logical_cpus = threads; 281 level = 2; 282 func = 3; /* unified cache */ 283 break; 284 case 2: 285 logical_cpus = threads * cores; 286 level = 3; 287 func = 3; /* unified cache */ 288 break; 289 default: 290 logical_cpus = 0; 291 level = 0; 292 func = 0; 293 break; 294 } 295 296 logical_cpus = MIN(0xfff, logical_cpus - 1); 297 regs[0] = (logical_cpus << 14) | (1 << 8) | 298 (level << 5) | func; 299 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0; 300 regs[2] = 0; 301 regs[3] = 0; 302 break; 303 304 case CPUID_8000_001E: 305 /* 306 * AMD Family 16h+ and Hygon Family 18h additional 307 * identifiers. 308 */ 309 if (!vmm_is_svm() || CPUID_TO_FAMILY(cpu_id) < 0x16) 310 goto default_leaf; 311 312 vm_get_topology(vm, &sockets, &cores, &threads, 313 &maxcpus); 314 regs[0] = vcpu_id; 315 threads = MIN(0xFF, threads - 1); 316 regs[1] = (threads << 8) | 317 (vcpu_id >> log2(threads + 1)); 318 /* 319 * XXX Bhyve topology cannot yet represent >1 node per 320 * processor. 321 */ 322 regs[2] = 0; 323 regs[3] = 0; 324 break; 325 326 case CPUID_0000_0001: 327 do_cpuid(1, regs); 328 329 error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state); 330 if (error) { 331 panic("x86_emulate_cpuid: error %d " 332 "fetching x2apic state", error); 333 } 334 335 /* 336 * Override the APIC ID only in ebx 337 */ 338 regs[1] &= ~(CPUID_LOCAL_APIC_ID); 339 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT); 340 341 /* 342 * Don't expose VMX, SpeedStep, TME or SMX capability. 343 * Advertise x2APIC capability and Hypervisor guest. 344 */ 345 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2); 346 regs[2] &= ~(CPUID2_SMX); 347 348 regs[2] |= CPUID2_HV; 349 350 if (x2apic_state != X2APIC_DISABLED) 351 regs[2] |= CPUID2_X2APIC; 352 else 353 regs[2] &= ~CPUID2_X2APIC; 354 355 /* 356 * Only advertise CPUID2_XSAVE in the guest if 357 * the host is using XSAVE. 358 */ 359 if (!(regs[2] & CPUID2_OSXSAVE)) 360 regs[2] &= ~CPUID2_XSAVE; 361 362 /* 363 * If CPUID2_XSAVE is being advertised and the 364 * guest has set CR4_XSAVE, set 365 * CPUID2_OSXSAVE. 366 */ 367 regs[2] &= ~CPUID2_OSXSAVE; 368 if (regs[2] & CPUID2_XSAVE) { 369 error = vm_get_register(vm, vcpu_id, 370 VM_REG_GUEST_CR4, &cr4); 371 if (error) 372 panic("x86_emulate_cpuid: error %d " 373 "fetching %%cr4", error); 374 if (cr4 & CR4_XSAVE) 375 regs[2] |= CPUID2_OSXSAVE; 376 } 377 378 /* 379 * Hide monitor/mwait until we know how to deal with 380 * these instructions. 381 */ 382 regs[2] &= ~CPUID2_MON; 383 384 /* 385 * Hide the performance and debug features. 386 */ 387 regs[2] &= ~CPUID2_PDCM; 388 389 /* 390 * No TSC deadline support in the APIC yet 391 */ 392 regs[2] &= ~CPUID2_TSCDLT; 393 394 /* 395 * Hide thermal monitoring 396 */ 397 regs[3] &= ~(CPUID_ACPI | CPUID_TM); 398 399 /* 400 * Hide the debug store capability. 401 */ 402 regs[3] &= ~CPUID_DS; 403 404 /* 405 * Advertise the Machine Check and MTRR capability. 406 * 407 * Some guest OSes (e.g. Windows) will not boot if 408 * these features are absent. 409 */ 410 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR); 411 412 vm_get_topology(vm, &sockets, &cores, &threads, 413 &maxcpus); 414 logical_cpus = threads * cores; 415 regs[1] &= ~CPUID_HTT_CORES; 416 regs[1] |= (logical_cpus & 0xff) << 16; 417 regs[3] |= CPUID_HTT; 418 break; 419 420 case CPUID_0000_0004: 421 cpuid_count(func, param, regs); 422 423 if (regs[0] || regs[1] || regs[2] || regs[3]) { 424 vm_get_topology(vm, &sockets, &cores, &threads, 425 &maxcpus); 426 regs[0] &= 0x3ff; 427 regs[0] |= (cores - 1) << 26; 428 /* 429 * Cache topology: 430 * - L1 and L2 are shared only by the logical 431 * processors in a single core. 432 * - L3 and above are shared by all logical 433 * processors in the package. 434 */ 435 logical_cpus = threads; 436 level = (regs[0] >> 5) & 0x7; 437 if (level >= 3) 438 logical_cpus *= cores; 439 regs[0] |= (logical_cpus - 1) << 14; 440 } 441 break; 442 443 case CPUID_0000_0007: 444 regs[0] = 0; 445 regs[1] = 0; 446 regs[2] = 0; 447 regs[3] = 0; 448 449 /* leaf 0 */ 450 if (param == 0) { 451 cpuid_count(func, param, regs); 452 453 /* Only leaf 0 is supported */ 454 regs[0] = 0; 455 456 /* 457 * Expose known-safe features. 458 */ 459 regs[1] &= (CPUID_STDEXT_FSGSBASE | 460 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE | 461 CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 | 462 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM | 463 CPUID_STDEXT_AVX512F | 464 CPUID_STDEXT_RDSEED | 465 CPUID_STDEXT_AVX512PF | 466 CPUID_STDEXT_AVX512ER | 467 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA); 468 regs[2] = 0; 469 regs[3] &= CPUID_STDEXT3_MD_CLEAR; 470 471 /* Advertise INVPCID if it is enabled. */ 472 error = vm_get_capability(vm, vcpu_id, 473 VM_CAP_ENABLE_INVPCID, &enable_invpcid); 474 if (error == 0 && enable_invpcid) 475 regs[1] |= CPUID_STDEXT_INVPCID; 476 } 477 break; 478 479 case CPUID_0000_0006: 480 regs[0] = CPUTPM1_ARAT; 481 regs[1] = 0; 482 regs[2] = 0; 483 regs[3] = 0; 484 break; 485 486 case CPUID_0000_000A: 487 /* 488 * Handle the access, but report 0 for 489 * all options 490 */ 491 regs[0] = 0; 492 regs[1] = 0; 493 regs[2] = 0; 494 regs[3] = 0; 495 break; 496 497 case CPUID_0000_000B: 498 /* 499 * Intel processor topology enumeration 500 */ 501 if (vmm_is_intel()) { 502 vm_get_topology(vm, &sockets, &cores, &threads, 503 &maxcpus); 504 if (param == 0) { 505 logical_cpus = threads; 506 width = log2(logical_cpus); 507 level = CPUID_TYPE_SMT; 508 x2apic_id = vcpu_id; 509 } 510 511 if (param == 1) { 512 logical_cpus = threads * cores; 513 width = log2(logical_cpus); 514 level = CPUID_TYPE_CORE; 515 x2apic_id = vcpu_id; 516 } 517 518 if (!cpuid_leaf_b || param >= 2) { 519 width = 0; 520 logical_cpus = 0; 521 level = 0; 522 x2apic_id = 0; 523 } 524 525 regs[0] = width & 0x1f; 526 regs[1] = logical_cpus & 0xffff; 527 regs[2] = (level << 8) | (param & 0xff); 528 regs[3] = x2apic_id; 529 } else { 530 regs[0] = 0; 531 regs[1] = 0; 532 regs[2] = 0; 533 regs[3] = 0; 534 } 535 break; 536 537 case CPUID_0000_000D: 538 limits = vmm_get_xsave_limits(); 539 if (!limits->xsave_enabled) { 540 regs[0] = 0; 541 regs[1] = 0; 542 regs[2] = 0; 543 regs[3] = 0; 544 break; 545 } 546 547 cpuid_count(func, param, regs); 548 switch (param) { 549 case 0: 550 /* 551 * Only permit the guest to use bits 552 * that are active in the host in 553 * %xcr0. Also, claim that the 554 * maximum save area size is 555 * equivalent to the host's current 556 * save area size. Since this runs 557 * "inside" of vmrun(), it runs with 558 * the guest's xcr0, so the current 559 * save area size is correct as-is. 560 */ 561 regs[0] &= limits->xcr0_allowed; 562 regs[2] = limits->xsave_max_size; 563 regs[3] &= (limits->xcr0_allowed >> 32); 564 break; 565 case 1: 566 /* Only permit XSAVEOPT. */ 567 regs[0] &= CPUID_EXTSTATE_XSAVEOPT; 568 regs[1] = 0; 569 regs[2] = 0; 570 regs[3] = 0; 571 break; 572 default: 573 /* 574 * If the leaf is for a permitted feature, 575 * pass through as-is, otherwise return 576 * all zeroes. 577 */ 578 if (!(limits->xcr0_allowed & (1ul << param))) { 579 regs[0] = 0; 580 regs[1] = 0; 581 regs[2] = 0; 582 regs[3] = 0; 583 } 584 break; 585 } 586 break; 587 588 case CPUID_0000_000F: 589 case CPUID_0000_0010: 590 /* 591 * Do not report any Resource Director Technology 592 * capabilities. Exposing control of cache or memory 593 * controller resource partitioning to the guest is not 594 * at all sensible. 595 * 596 * This is already hidden at a high level by masking of 597 * leaf 0x7. Even still, a guest may look here for 598 * detailed capability information. 599 */ 600 regs[0] = 0; 601 regs[1] = 0; 602 regs[2] = 0; 603 regs[3] = 0; 604 break; 605 606 case CPUID_0000_0015: 607 /* 608 * Don't report CPU TSC/Crystal ratio and clock 609 * values since guests may use these to derive the 610 * local APIC frequency.. 611 */ 612 regs[0] = 0; 613 regs[1] = 0; 614 regs[2] = 0; 615 regs[3] = 0; 616 break; 617 618 case 0x40000000: 619 regs[0] = CPUID_VM_HIGH; 620 bcopy(bhyve_id, ®s[1], 4); 621 bcopy(bhyve_id + 4, ®s[2], 4); 622 bcopy(bhyve_id + 8, ®s[3], 4); 623 break; 624 625 default: 626 default_leaf: 627 /* 628 * The leaf value has already been clamped so 629 * simply pass this through, keeping count of 630 * how many unhandled leaf values have been seen. 631 */ 632 atomic_add_long(&bhyve_xcpuids, 1); 633 cpuid_count(func, param, regs); 634 break; 635 } 636 637 /* 638 * CPUID clears the upper 32-bits of the long-mode registers. 639 */ 640 *rax = regs[0]; 641 *rbx = regs[1]; 642 *rcx = regs[2]; 643 *rdx = regs[3]; 644 645 return (1); 646 } 647 648 bool 649 vm_cpuid_capability(struct vm *vm, int vcpuid, enum vm_cpuid_capability cap) 650 { 651 bool rv; 652 653 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d", 654 __func__, cap)); 655 656 /* 657 * Simply passthrough the capabilities of the host cpu for now. 658 */ 659 rv = false; 660 switch (cap) { 661 #ifdef __FreeBSD__ 662 case VCC_NO_EXECUTE: 663 if (amd_feature & AMDID_NX) 664 rv = true; 665 break; 666 case VCC_FFXSR: 667 if (amd_feature & AMDID_FFXSR) 668 rv = true; 669 break; 670 case VCC_TCE: 671 if (amd_feature2 & AMDID2_TCE) 672 rv = true; 673 break; 674 #else 675 case VCC_NO_EXECUTE: 676 if (is_x86_feature(x86_featureset, X86FSET_NX)) 677 rv = true; 678 break; 679 /* XXXJOY: No kernel detection for FFXR or TCE at present, so ignore */ 680 case VCC_FFXSR: 681 case VCC_TCE: 682 break; 683 #endif 684 default: 685 panic("%s: unknown vm_cpu_capability %d", __func__, cap); 686 } 687 return (rv); 688 } 689