1bf21cd93STycho Nightingale /*- 2*32640292SAndy Fiddaman * SPDX-License-Identifier: BSD-2-Clause 34c87aefeSPatrick Mooney * 4bf21cd93STycho Nightingale * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5bf21cd93STycho Nightingale * All rights reserved. 6bf21cd93STycho Nightingale * 7bf21cd93STycho Nightingale * Redistribution and use in source and binary forms, with or without 8bf21cd93STycho Nightingale * modification, are permitted provided that the following conditions 9bf21cd93STycho Nightingale * are met: 10bf21cd93STycho Nightingale * 1. Redistributions of source code must retain the above copyright 11bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer. 12bf21cd93STycho Nightingale * 2. Redistributions in binary form must reproduce the above copyright 13bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer in the 14bf21cd93STycho Nightingale * documentation and/or other materials provided with the distribution. 15bf21cd93STycho Nightingale * 16bf21cd93STycho Nightingale * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17bf21cd93STycho Nightingale * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18bf21cd93STycho Nightingale * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19bf21cd93STycho Nightingale * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20bf21cd93STycho Nightingale * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21bf21cd93STycho Nightingale * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22bf21cd93STycho Nightingale * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23bf21cd93STycho Nightingale * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24bf21cd93STycho Nightingale * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25bf21cd93STycho Nightingale * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26bf21cd93STycho Nightingale * SUCH DAMAGE. 27bf21cd93STycho Nightingale */ 285365b8a5SPatrick Mooney /* 295365b8a5SPatrick Mooney * This file and its contents are supplied under the terms of the 305365b8a5SPatrick Mooney * Common Development and Distribution License ("CDDL"), version 1.0. 315365b8a5SPatrick Mooney * You may only use this file in accordance with the terms of version 325365b8a5SPatrick Mooney * 1.0 of the CDDL. 335365b8a5SPatrick Mooney * 345365b8a5SPatrick Mooney * A full copy of the text of the CDDL should have accompanied this 355365b8a5SPatrick Mooney * source. A copy of the CDDL is also available via the Internet at 365365b8a5SPatrick Mooney * http://www.illumos.org/license/CDDL. 375365b8a5SPatrick Mooney * 3862ac5a8aSPatrick Mooney * Copyright 2023 Oxide Computer Company 395365b8a5SPatrick Mooney */ 40bf21cd93STycho Nightingale 41bf21cd93STycho Nightingale #ifndef _VLAPIC_PRIV_H_ 42bf21cd93STycho Nightingale #define _VLAPIC_PRIV_H_ 43bf21cd93STycho Nightingale 44bf21cd93STycho Nightingale #include <x86/apicreg.h> 45bf21cd93STycho Nightingale 46bf21cd93STycho Nightingale /* 47bf21cd93STycho Nightingale * APIC Register: Offset Description 48bf21cd93STycho Nightingale */ 492699b94cSPatrick Mooney #define APIC_OFFSET_ID 0x20 /* Local APIC ID */ 502699b94cSPatrick Mooney #define APIC_OFFSET_VER 0x30 /* Local APIC Version */ 512699b94cSPatrick Mooney #define APIC_OFFSET_TPR 0x80 /* Task Priority Register */ 522699b94cSPatrick Mooney #define APIC_OFFSET_APR 0x90 /* Arbitration Priority */ 532699b94cSPatrick Mooney #define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */ 542699b94cSPatrick Mooney #define APIC_OFFSET_EOI 0xB0 /* EOI Register */ 552699b94cSPatrick Mooney #define APIC_OFFSET_RRR 0xC0 /* Remote read */ 562699b94cSPatrick Mooney #define APIC_OFFSET_LDR 0xD0 /* Logical Destination */ 572699b94cSPatrick Mooney #define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */ 582699b94cSPatrick Mooney #define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */ 592699b94cSPatrick Mooney #define APIC_OFFSET_ISR0 0x100 /* In Service Register */ 602699b94cSPatrick Mooney #define APIC_OFFSET_ISR1 0x110 612699b94cSPatrick Mooney #define APIC_OFFSET_ISR2 0x120 622699b94cSPatrick Mooney #define APIC_OFFSET_ISR3 0x130 632699b94cSPatrick Mooney #define APIC_OFFSET_ISR4 0x140 642699b94cSPatrick Mooney #define APIC_OFFSET_ISR5 0x150 652699b94cSPatrick Mooney #define APIC_OFFSET_ISR6 0x160 662699b94cSPatrick Mooney #define APIC_OFFSET_ISR7 0x170 672699b94cSPatrick Mooney #define APIC_OFFSET_TMR0 0x180 /* Trigger Mode Register */ 682699b94cSPatrick Mooney #define APIC_OFFSET_TMR1 0x190 692699b94cSPatrick Mooney #define APIC_OFFSET_TMR2 0x1A0 702699b94cSPatrick Mooney #define APIC_OFFSET_TMR3 0x1B0 712699b94cSPatrick Mooney #define APIC_OFFSET_TMR4 0x1C0 722699b94cSPatrick Mooney #define APIC_OFFSET_TMR5 0x1D0 732699b94cSPatrick Mooney #define APIC_OFFSET_TMR6 0x1E0 742699b94cSPatrick Mooney #define APIC_OFFSET_TMR7 0x1F0 752699b94cSPatrick Mooney #define APIC_OFFSET_IRR0 0x200 /* Interrupt Request Register */ 762699b94cSPatrick Mooney #define APIC_OFFSET_IRR1 0x210 772699b94cSPatrick Mooney #define APIC_OFFSET_IRR2 0x220 782699b94cSPatrick Mooney #define APIC_OFFSET_IRR3 0x230 792699b94cSPatrick Mooney #define APIC_OFFSET_IRR4 0x240 802699b94cSPatrick Mooney #define APIC_OFFSET_IRR5 0x250 812699b94cSPatrick Mooney #define APIC_OFFSET_IRR6 0x260 822699b94cSPatrick Mooney #define APIC_OFFSET_IRR7 0x270 832699b94cSPatrick Mooney #define APIC_OFFSET_ESR 0x280 /* Error Status Register */ 842699b94cSPatrick Mooney #define APIC_OFFSET_CMCI_LVT 0x2F0 /* Local Vector Table (CMCI) */ 852699b94cSPatrick Mooney #define APIC_OFFSET_ICR_LOW 0x300 /* Interrupt Command Register */ 862699b94cSPatrick Mooney #define APIC_OFFSET_ICR_HI 0x310 872699b94cSPatrick Mooney #define APIC_OFFSET_TIMER_LVT 0x320 /* Local Vector Table (Timer) */ 882699b94cSPatrick Mooney #define APIC_OFFSET_THERM_LVT 0x330 /* Local Vector Table (Thermal) */ 892699b94cSPatrick Mooney #define APIC_OFFSET_PERF_LVT 0x340 /* Local Vector Table (PMC) */ 902699b94cSPatrick Mooney #define APIC_OFFSET_LINT0_LVT 0x350 /* Local Vector Table (LINT0) */ 912699b94cSPatrick Mooney #define APIC_OFFSET_LINT1_LVT 0x360 /* Local Vector Table (LINT1) */ 922699b94cSPatrick Mooney #define APIC_OFFSET_ERROR_LVT 0x370 /* Local Vector Table (ERROR) */ 932699b94cSPatrick Mooney #define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */ 942699b94cSPatrick Mooney #define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */ 952699b94cSPatrick Mooney #define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */ 96bf21cd93STycho Nightingale #define APIC_OFFSET_SELF_IPI 0x3F0 /* Self IPI register */ 97bf21cd93STycho Nightingale 98bf21cd93STycho Nightingale /* 99bf21cd93STycho Nightingale * 16 priority levels with at most one vector injected per level. 100bf21cd93STycho Nightingale */ 101bf21cd93STycho Nightingale #define ISRVEC_STK_SIZE (16 + 1) 102bf21cd93STycho Nightingale 1032699b94cSPatrick Mooney #define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI 104bf21cd93STycho Nightingale 1052699b94cSPatrick Mooney #define VLAPIC_TMR_CNT 8 1064c87aefeSPatrick Mooney 107bf21cd93STycho Nightingale struct vlapic; 108bf21cd93STycho Nightingale 109bf21cd93STycho Nightingale struct vlapic_ops { 110c74a40a5SPatrick Mooney vcpu_notify_t (*set_intr_ready)(struct vlapic *vlapic, int vector, 111c74a40a5SPatrick Mooney bool level); 112c74a40a5SPatrick Mooney void (*sync_state)(struct vlapic *vlapic); 113bf21cd93STycho Nightingale void (*intr_accepted)(struct vlapic *vlapic, int vector); 114bf21cd93STycho Nightingale void (*post_intr)(struct vlapic *vlapic, int hostcpu); 115bf21cd93STycho Nightingale void (*enable_x2apic_mode)(struct vlapic *vlapic); 116bf21cd93STycho Nightingale }; 117bf21cd93STycho Nightingale 11862ac5a8aSPatrick Mooney struct vlapic_stats { 11962ac5a8aSPatrick Mooney /* Result of a CCR read was clamped due to being > ICR */ 12062ac5a8aSPatrick Mooney uint64_t vs_clamp_ccr; 12162ac5a8aSPatrick Mooney /* Imported timer expiration further in future than ICR equiv */ 12262ac5a8aSPatrick Mooney uint64_t vs_import_timer_overage; 12362ac5a8aSPatrick Mooney }; 12462ac5a8aSPatrick Mooney 125bf21cd93STycho Nightingale struct vlapic { 126bf21cd93STycho Nightingale struct vm *vm; 127bf21cd93STycho Nightingale int vcpuid; 128bf21cd93STycho Nightingale struct LAPIC *apic_page; 129bf21cd93STycho Nightingale struct vlapic_ops ops; 130bf21cd93STycho Nightingale 131bf21cd93STycho Nightingale uint32_t esr_pending; 132bf21cd93STycho Nightingale 133bf21cd93STycho Nightingale struct callout callout; /* vlapic timer */ 1345103e761SPatrick Mooney hrtime_t timer_fire_when; 1355103e761SPatrick Mooney hrtime_t timer_period; 1365103e761SPatrick Mooney uint32_t timer_cur_freq; 1375103e761SPatrick Mooney 138fb29dee0SPatrick Mooney kmutex_t timer_lock; 139bf21cd93STycho Nightingale 140bf21cd93STycho Nightingale uint64_t msr_apicbase; 141bf21cd93STycho Nightingale 142bf21cd93STycho Nightingale /* 143bf21cd93STycho Nightingale * Copies of some registers in the virtual APIC page. We do this for 144bf21cd93STycho Nightingale * a couple of different reasons: 145bf21cd93STycho Nightingale * - to be able to detect what changed (e.g. svr_last) 146bf21cd93STycho Nightingale * - to maintain a coherent snapshot of the register (e.g. lvt_last) 147bf21cd93STycho Nightingale */ 148bf21cd93STycho Nightingale uint32_t svr_last; 149bf21cd93STycho Nightingale uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1]; 15062ac5a8aSPatrick Mooney 15162ac5a8aSPatrick Mooney /* Occurrences of unusual events are tracked in this stats struct. */ 15262ac5a8aSPatrick Mooney struct vlapic_stats stats; 153bf21cd93STycho Nightingale }; 154bf21cd93STycho Nightingale 155bf21cd93STycho Nightingale void vlapic_init(struct vlapic *vlapic); 156bf21cd93STycho Nightingale void vlapic_cleanup(struct vlapic *vlapic); 157bf21cd93STycho Nightingale 158bf21cd93STycho Nightingale #endif /* _VLAPIC_PRIV_H_ */ 159