xref: /illumos-gate/usr/src/uts/intel/io/vmm/intel/vmx.h (revision 7c8c0b82)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 /*
32  * This file and its contents are supplied under the terms of the
33  * Common Development and Distribution License ("CDDL"), version 1.0.
34  * You may only use this file in accordance with the terms of version
35  * 1.0 of the CDDL.
36  *
37  * A full copy of the text of the CDDL should have accompanied this
38  * source.  A copy of the CDDL is also available via the Internet at
39  * http://www.illumos.org/license/CDDL.
40  *
41  * Copyright 2018 Joyent, Inc.
42  * Copyright 2021 Oxide Computer Company
43  */
44 
45 #ifndef _VMX_H_
46 #define	_VMX_H_
47 
48 #include "vmcs.h"
49 
50 struct vmxctx {
51 	uint64_t	guest_rdi;		/* Guest state */
52 	uint64_t	guest_rsi;
53 	uint64_t	guest_rdx;
54 	uint64_t	guest_rcx;
55 	uint64_t	guest_r8;
56 	uint64_t	guest_r9;
57 	uint64_t	guest_rax;
58 	uint64_t	guest_rbx;
59 	uint64_t	guest_rbp;
60 	uint64_t	guest_r10;
61 	uint64_t	guest_r11;
62 	uint64_t	guest_r12;
63 	uint64_t	guest_r13;
64 	uint64_t	guest_r14;
65 	uint64_t	guest_r15;
66 	uint64_t	guest_cr2;
67 	uint64_t	guest_dr0;
68 	uint64_t	guest_dr1;
69 	uint64_t	guest_dr2;
70 	uint64_t	guest_dr3;
71 	uint64_t	guest_dr6;
72 
73 	uint64_t	host_dr0;
74 	uint64_t	host_dr1;
75 	uint64_t	host_dr2;
76 	uint64_t	host_dr3;
77 	uint64_t	host_dr6;
78 	uint64_t	host_dr7;
79 	uint64_t	host_debugctl;
80 	int		host_tf;
81 
82 	int		inst_fail_status;
83 };
84 
85 struct vmxcap {
86 	int	set;
87 	uint32_t proc_ctls;
88 	uint32_t proc_ctls2;
89 	uint32_t exc_bitmap;
90 };
91 
92 struct vmxstate {
93 	uint64_t nextrip;	/* next instruction to be executed by guest */
94 	int	lastcpu;	/* host cpu that this 'vcpu' last ran on */
95 	uint16_t vpid;
96 };
97 
98 struct apic_page {
99 	uint32_t reg[PAGE_SIZE / 4];
100 };
101 CTASSERT(sizeof (struct apic_page) == PAGE_SIZE);
102 
103 /* Posted Interrupt Descriptor (described in section 29.6 of the Intel SDM) */
104 struct pir_desc {
105 	uint32_t	pir[8];
106 	uint64_t	pending;
107 	uint64_t	unused[3];
108 } __aligned(64);
109 CTASSERT(sizeof (struct pir_desc) == 64);
110 
111 /* Index into the 'guest_msrs[]' array */
112 enum {
113 	IDX_MSR_LSTAR,
114 	IDX_MSR_CSTAR,
115 	IDX_MSR_STAR,
116 	IDX_MSR_SF_MASK,
117 	IDX_MSR_KGSBASE,
118 	IDX_MSR_PAT,
119 	GUEST_MSR_NUM		/* must be the last enumeration */
120 };
121 
122 typedef enum {
123 	VS_NONE		= 0x0,
124 	VS_LAUNCHED	= 0x1,
125 	VS_LOADED	= 0x2
126 } vmcs_state_t;
127 
128 /* virtual machine softc */
129 struct vmx {
130 	struct vmcs	vmcs[VM_MAXCPU];	/* one vmcs per virtual cpu */
131 	struct apic_page apic_page[VM_MAXCPU];	/* one apic page per vcpu */
132 	uint8_t		*msr_bitmap[VM_MAXCPU];	/* one MSR bitmap per vCPU */
133 	struct pir_desc	pir_desc[VM_MAXCPU];
134 	uint64_t	guest_msrs[VM_MAXCPU][GUEST_MSR_NUM];
135 	uint64_t	host_msrs[VM_MAXCPU][GUEST_MSR_NUM];
136 	uint64_t	tsc_offset_active[VM_MAXCPU];
137 	vmcs_state_t	vmcs_state[VM_MAXCPU];
138 	uintptr_t	vmcs_pa[VM_MAXCPU];
139 	void		*apic_access_page;
140 	struct vmxctx	ctx[VM_MAXCPU];
141 	struct vmxcap	cap[VM_MAXCPU];
142 	struct vmxstate	state[VM_MAXCPU];
143 	uint64_t	eptp;
144 	enum vmx_caps	vmx_caps;
145 	struct vm	*vm;
146 	/*
147 	 * Track the latest vmspace generation as it is run on a given host CPU.
148 	 * This allows us to react to modifications to the vmspace (such as
149 	 * unmap or changed protection) which necessitate flushing any
150 	 * guest-physical TLB entries tagged for this guest via 'invept'.
151 	 */
152 	uint64_t	eptgen[MAXCPU];
153 };
154 CTASSERT((offsetof(struct vmx, vmcs) & PAGE_MASK) == 0);
155 CTASSERT((offsetof(struct vmx, msr_bitmap) & PAGE_MASK) == 0);
156 CTASSERT((offsetof(struct vmx, pir_desc[0]) & 63) == 0);
157 
158 static __inline bool
vmx_cap_en(const struct vmx * vmx,enum vmx_caps cap)159 vmx_cap_en(const struct vmx *vmx, enum vmx_caps cap)
160 {
161 	return ((vmx->vmx_caps & cap) == cap);
162 }
163 
164 
165 /*
166  * Section 5.2 "Conventions" from Intel Architecture Manual 2B.
167  *
168  *			error
169  * VMsucceed		  0
170  * VMFailInvalid	  1
171  * VMFailValid		  2	see also VMCS VM-Instruction Error Field
172  */
173 #define	VM_SUCCESS		0
174 #define	VM_FAIL_INVALID		1
175 #define	VM_FAIL_VALID		2
176 #define	VMX_SET_ERROR_CODE_ASM \
177 	"	jnc 1f;"						\
178 	"	mov $1, %[error];"	/* CF: error = 1 */		\
179 	"	jmp 3f;"						\
180 	"1:	jnz 2f;"						\
181 	"	mov $2, %[error];"	/* ZF: error = 2 */		\
182 	"	jmp 3f;"						\
183 	"2:	mov $0, %[error];"					\
184 	"3:"
185 
186 
187 #define	VMX_GUEST_VMEXIT	0
188 #define	VMX_VMRESUME_ERROR	1
189 #define	VMX_VMLAUNCH_ERROR	2
190 #define	VMX_INVEPT_ERROR	3
191 #define	VMX_VMWRITE_ERROR	4
192 
193 int	vmx_enter_guest(struct vmxctx *ctx, struct vmx *vmx, int launched);
194 void	vmx_call_isr(uintptr_t entry);
195 
196 int	vmx_set_tsc_offset(struct vmx *vmx, int vcpu, uint64_t offset);
197 
198 extern char	vmx_exit_guest[];
199 extern char	vmx_exit_guest_flush_rsb[];
200 
201 #endif
202