1508aff1aSJames C. McPherson /* 2508aff1aSJames C. McPherson * 3508aff1aSJames C. McPherson * O.S : Solaris 4508aff1aSJames C. McPherson * FILE NAME : arcmsr.h 5508aff1aSJames C. McPherson * BY : Erich Chen 6508aff1aSJames C. McPherson * Description: SCSI RAID Device Driver for 7508aff1aSJames C. McPherson * ARECA RAID Host adapter 882beb602SGarrett D'Amore * 9508aff1aSJames C. McPherson * Copyright (C) 2002,2007 Areca Technology Corporation All rights reserved. 10508aff1aSJames C. McPherson * Copyright (C) 2002,2007 Erich Chen 11508aff1aSJames C. McPherson * Web site: www.areca.com.tw 12508aff1aSJames C. McPherson * E-mail: erich@areca.com.tw 1382beb602SGarrett D'Amore * 14508aff1aSJames C. McPherson * Redistribution and use in source and binary forms, with or without 15508aff1aSJames C. McPherson * modification, are permitted provided that the following conditions 16508aff1aSJames C. McPherson * are met: 17508aff1aSJames C. McPherson * 1. Redistributions of source code must retain the above copyright 18508aff1aSJames C. McPherson * notice, this list of conditions and the following disclaimer. 19508aff1aSJames C. McPherson * 2. Redistributions in binary form must reproduce the above copyright 20508aff1aSJames C. McPherson * notice, this list of conditions and the following disclaimer in the 21508aff1aSJames C. McPherson * documentation and/or other materials provided with the distribution. 22508aff1aSJames C. McPherson * 3. The party using or redistributing the source code and binary forms 23508aff1aSJames C. McPherson * agrees to the disclaimer below and the terms and conditions set forth 24508aff1aSJames C. McPherson * herein. 25508aff1aSJames C. McPherson * 26508aff1aSJames C. McPherson * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27508aff1aSJames C. McPherson * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28508aff1aSJames C. McPherson * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29508aff1aSJames C. McPherson * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 30508aff1aSJames C. McPherson * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31508aff1aSJames C. McPherson * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32508aff1aSJames C. McPherson * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33508aff1aSJames C. McPherson * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34508aff1aSJames C. McPherson * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35508aff1aSJames C. McPherson * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36508aff1aSJames C. McPherson * SUCH DAMAGE. 3782beb602SGarrett D'Amore * 38508aff1aSJames C. McPherson */ 39508aff1aSJames C. McPherson /* 40508aff1aSJames C. McPherson * CDDL HEADER START 41508aff1aSJames C. McPherson * 42508aff1aSJames C. McPherson * The contents of this file are subject to the terms of the 43508aff1aSJames C. McPherson * Common Development and Distribution License (the "License"). 44508aff1aSJames C. McPherson * You may not use this file except in compliance with the License. 45508aff1aSJames C. McPherson * 46508aff1aSJames C. McPherson * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 47508aff1aSJames C. McPherson * or http://www.opensolaris.org/os/licensing. 48508aff1aSJames C. McPherson * See the License for the specific language governing permissions 49508aff1aSJames C. McPherson * and limitations under the License. 50508aff1aSJames C. McPherson * 51508aff1aSJames C. McPherson * When distributing Covered Code, include this CDDL HEADER in each 52508aff1aSJames C. McPherson * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 53508aff1aSJames C. McPherson * If applicable, add the following below this CDDL HEADER, with the 54508aff1aSJames C. McPherson * fields enclosed by brackets "[]" replaced with your own identifying 55508aff1aSJames C. McPherson * information: Portions Copyright [yyyy] [name of copyright owner] 56508aff1aSJames C. McPherson * 57508aff1aSJames C. McPherson * CDDL HEADER END 58508aff1aSJames C. McPherson */ 59508aff1aSJames C. McPherson /* 60ed632624SColin Yi * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 61508aff1aSJames C. McPherson * Use is subject to license terms. 62508aff1aSJames C. McPherson */ 6382beb602SGarrett D'Amore /* 6482beb602SGarrett D'Amore * Copyright 2011 Nexenta Systems, Inc. All rights reserved. 6582beb602SGarrett D'Amore */ 66508aff1aSJames C. McPherson 67508aff1aSJames C. McPherson #ifndef _SYS_SCSI_ADAPTERS_ARCMSR_H 68508aff1aSJames C. McPherson #define _SYS_SCSI_ADAPTERS_ARCMSR_H 69508aff1aSJames C. McPherson 70508aff1aSJames C. McPherson #ifdef __cplusplus 71508aff1aSJames C. McPherson extern "C" { 72508aff1aSJames C. McPherson #endif 73508aff1aSJames C. McPherson 74508aff1aSJames C. McPherson #include <sys/sysmacros.h> 75508aff1aSJames C. McPherson 76508aff1aSJames C. McPherson #ifndef TRUE 77508aff1aSJames C. McPherson #define TRUE 1 78508aff1aSJames C. McPherson #define FALSE 0 79508aff1aSJames C. McPherson #endif 80508aff1aSJames C. McPherson 81508aff1aSJames C. McPherson 8282beb602SGarrett D'Amore typedef struct CCB *PCCB; 8382beb602SGarrett D'Amore typedef struct ACB *PACB; 84508aff1aSJames C. McPherson 85508aff1aSJames C. McPherson #define ARCMSR_SCSI_INITIATOR_ID 255 86508aff1aSJames C. McPherson #define ARCMSR_DEV_SECTOR_SIZE 512 87508aff1aSJames C. McPherson #define ARCMSR_MAX_XFER_SECTORS 256 8882beb602SGarrett D'Amore #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38 */ 89508aff1aSJames C. McPherson #define ARCMSR_MAX_XFER_LEN 0x00200000 /* 2M */ 9082beb602SGarrett D'Amore #define ARCMSR_MAX_TARGETID 17 /* 0-16 */ 9182beb602SGarrett D'Amore #define ARCMSR_MAX_TARGETLUN 8 /* 0-7 */ 9282beb602SGarrett D'Amore #define ARCMSR_MAX_DPC 16 /* defer procedure call */ 9382beb602SGarrett D'Amore #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 9482beb602SGarrett D'Amore #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* MAX_OUTSTANDING_CMD+8 */ 95508aff1aSJames C. McPherson 96508aff1aSJames C. McPherson #define ARCMSR_MAX_OUTSTANDING_CMD 256 9782beb602SGarrett D'Amore #define ARCMSR_MAX_FREECCB_NUM 384 9882beb602SGarrett D'Amore #define ARCMSR_TIMEOUT_WATCH 60 9982beb602SGarrett D'Amore #define ARCMSR_DEV_MAP_WATCH 5 10082beb602SGarrett D'Amore #define ARCMSR_CCB_EXPIRED_TIME 600 /* 10 min */ 101508aff1aSJames C. McPherson 102508aff1aSJames C. McPherson #define CHIP_REG_READ8(handle, a) \ 103508aff1aSJames C. McPherson (ddi_get8(handle, (uint8_t *)(a))) 104508aff1aSJames C. McPherson #define CHIP_REG_READ16(handle, a) \ 105508aff1aSJames C. McPherson (ddi_get16(handle, (uint16_t *)(a))) 106508aff1aSJames C. McPherson #define CHIP_REG_READ32(handle, a) \ 107508aff1aSJames C. McPherson (ddi_get32(handle, (uint32_t *)(a))) 108508aff1aSJames C. McPherson #define CHIP_REG_READ64(handle, a) \ 109508aff1aSJames C. McPherson (ddi_get64(handle, (uint64_t *)(a))) 110508aff1aSJames C. McPherson #define CHIP_REG_WRITE8(handle, a, d) \ 111508aff1aSJames C. McPherson ddi_put8(handle, (uint8_t *)(a), (uint8_t)(d)) 112508aff1aSJames C. McPherson #define CHIP_REG_WRITE16(handle, a, d) \ 113508aff1aSJames C. McPherson ddi_put16(handle, (uint16_t *)(a), (uint16_t)(d)) 114508aff1aSJames C. McPherson #define CHIP_REG_WRITE32(handle, a, d) \ 115508aff1aSJames C. McPherson ddi_put32(handle, (uint32_t *)(a), (uint32_t)(d)) 116508aff1aSJames C. McPherson #define CHIP_REG_WRITE64(handle, a, d) \ 117508aff1aSJames C. McPherson ddi_put64(handle, (uint64_t *)(a), (uint64_t)(d)) 118508aff1aSJames C. McPherson 119508aff1aSJames C. McPherson 12082beb602SGarrett D'Amore /* NOTE: GETG4ADDRTL(cdbp) is int32_t */ 12182beb602SGarrett D'Amore #define ARCMSR_GETGXADDR(cmdlen, cdbp) \ 12282beb602SGarrett D'Amore ((cmdlen == 6) ? GETG0ADDR(cdbp) : \ 12382beb602SGarrett D'Amore (cmdlen == 10) ? (uint32_t)GETG1ADDR(cdbp) : \ 12482beb602SGarrett D'Amore ((uint64_t)GETG4ADDR(cdbp) << 32) | (uint32_t)GETG4ADDRTL(cdbp)) 125508aff1aSJames C. McPherson 126508aff1aSJames C. McPherson #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 127508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 128508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 129508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 130508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 131508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 132508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 133508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 134508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 13582beb602SGarrett D'Amore #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 136508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 13782beb602SGarrett D'Amore #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 138508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 139508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 14082beb602SGarrett D'Amore #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 14182beb602SGarrett D'Amore #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 142508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 143508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 144508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 145508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 146508aff1aSJames C. McPherson #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 14782beb602SGarrett D'Amore #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 148*7d14b8f2SRobert Mustacchi #define PCI_DEVICE_ID_ARECA_1882 0x1882 /* Device ID */ 149508aff1aSJames C. McPherson 150508aff1aSJames C. McPherson #define dma_addr_hi32(addr) (uint32_t)((addr>>16)>>16) 151508aff1aSJames C. McPherson #define dma_addr_lo32(addr) (uint32_t)(addr & 0xffffffff) 152508aff1aSJames C. McPherson 153508aff1aSJames C. McPherson /* 154508aff1aSJames C. McPherson * IOCTL CONTROL CODE 155508aff1aSJames C. McPherson */ 156508aff1aSJames C. McPherson struct CMD_MESSAGE { 157508aff1aSJames C. McPherson uint32_t HeaderLength; 158508aff1aSJames C. McPherson uint8_t Signature[8]; 159508aff1aSJames C. McPherson uint32_t Timeout; 160508aff1aSJames C. McPherson uint32_t ControlCode; 161508aff1aSJames C. McPherson uint32_t ReturnCode; 162508aff1aSJames C. McPherson uint32_t Length; 163508aff1aSJames C. McPherson }; 164508aff1aSJames C. McPherson 165508aff1aSJames C. McPherson 16682beb602SGarrett D'Amore #define MSGDATABUFLEN 1031 167508aff1aSJames C. McPherson struct CMD_MESSAGE_FIELD { 168508aff1aSJames C. McPherson struct CMD_MESSAGE cmdmessage; /* 28 byte ioctl header */ 16982beb602SGarrett D'Amore uint8_t messagedatabuffer[MSGDATABUFLEN]; /* 1032 */ 170508aff1aSJames C. McPherson /* areca gui program does not accept more than 1031 byte */ 171508aff1aSJames C. McPherson }; 172508aff1aSJames C. McPherson 173508aff1aSJames C. McPherson /* IOP message transfer */ 174508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_FAIL 0x0001 175508aff1aSJames C. McPherson 176508aff1aSJames C. McPherson /* error code for StorPortLogError,ScsiPortLogError */ 177508aff1aSJames C. McPherson #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 178508aff1aSJames C. McPherson #define ARCMSR_IOP_ERROR_VENDORID 0x0002 179508aff1aSJames C. McPherson #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 180508aff1aSJames C. McPherson #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 181508aff1aSJames C. McPherson #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 182508aff1aSJames C. McPherson #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 183508aff1aSJames C. McPherson #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 184508aff1aSJames C. McPherson #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 185508aff1aSJames C. McPherson #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 186508aff1aSJames C. McPherson #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 187508aff1aSJames C. McPherson #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 188508aff1aSJames C. McPherson /* DeviceType */ 189d8e8ff11SColin Yi #define ARECA_SATA_RAID 0x90000000 190508aff1aSJames C. McPherson /* FunctionCode */ 191508aff1aSJames C. McPherson #define FUNCTION_READ_RQBUFFER 0x0801 192508aff1aSJames C. McPherson #define FUNCTION_WRITE_WQBUFFER 0x0802 193508aff1aSJames C. McPherson #define FUNCTION_CLEAR_RQBUFFER 0x0803 194508aff1aSJames C. McPherson #define FUNCTION_CLEAR_WQBUFFER 0x0804 195508aff1aSJames C. McPherson #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 196508aff1aSJames C. McPherson #define FUNCTION_REQUEST_RETURN_CODE_3F 0x0806 197508aff1aSJames C. McPherson #define FUNCTION_SAY_HELLO 0x0807 198508aff1aSJames C. McPherson #define FUNCTION_SAY_GOODBYE 0x0808 199508aff1aSJames C. McPherson #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 200508aff1aSJames C. McPherson 201508aff1aSJames C. McPherson /* ARECA IO CONTROL CODE */ 20282beb602SGarrett D'Amore #define ARCMSR_MESSAGE_READ_RQBUFFER \ 203508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 204508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 205508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 206508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 207508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 208508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 209508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 21082beb602SGarrett D'Amore #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 211508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 21282beb602SGarrett D'Amore #define ARCMSR_MESSAGE_REQUEST_RETURN_CODE_3F \ 213508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_REQUEST_RETURN_CODE_3F 21482beb602SGarrett D'Amore #define ARCMSR_MESSAGE_SAY_HELLO \ 215508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_SAY_HELLO 21682beb602SGarrett D'Amore #define ARCMSR_MESSAGE_SAY_GOODBYE \ 217508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 21882beb602SGarrett D'Amore #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 219508aff1aSJames C. McPherson ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 220508aff1aSJames C. McPherson 221508aff1aSJames C. McPherson /* ARECA IOCTL ReturnCode */ 222508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 223508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 224508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 225508aff1aSJames C. McPherson 226508aff1aSJames C. McPherson /* 227508aff1aSJames C. McPherson * SPEC. for Areca HBB adapter 228508aff1aSJames C. McPherson */ 229508aff1aSJames C. McPherson /* ARECA HBB COMMAND for its FIRMWARE */ 230508aff1aSJames C. McPherson /* window of "instruction flags" from driver to iop */ 231508aff1aSJames C. McPherson #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 232508aff1aSJames C. McPherson #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 233508aff1aSJames C. McPherson /* window of "instruction flags" from iop to driver */ 234508aff1aSJames C. McPherson #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 235508aff1aSJames C. McPherson #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 236508aff1aSJames C. McPherson 237508aff1aSJames C. McPherson 238508aff1aSJames C. McPherson /* ARECA FLAG LANGUAGE */ 239508aff1aSJames C. McPherson #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl xfer */ 240508aff1aSJames C. McPherson #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl xfer */ 241508aff1aSJames C. McPherson #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 242508aff1aSJames C. McPherson #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 243508aff1aSJames C. McPherson 244508aff1aSJames C. McPherson #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 245508aff1aSJames C. McPherson #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 246508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 247508aff1aSJames C. McPherson 248508aff1aSJames C. McPherson /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 249508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 250508aff1aSJames C. McPherson /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 251508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 252508aff1aSJames C. McPherson /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 253508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 254508aff1aSJames C. McPherson /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 255508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 256508aff1aSJames C. McPherson /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 257508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 258508aff1aSJames C. McPherson /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 259508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_START_BGRB 0x00060008 260508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 261508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 262508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 263508aff1aSJames C. McPherson /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 264508aff1aSJames C. McPherson #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 265508aff1aSJames C. McPherson 266508aff1aSJames C. McPherson #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl xfer */ 267508aff1aSJames C. McPherson #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl xfer */ 268508aff1aSJames C. McPherson #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 269508aff1aSJames C. McPherson #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 270508aff1aSJames C. McPherson #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 271508aff1aSJames C. McPherson 27282beb602SGarrett D'Amore #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 27382beb602SGarrett D'Amore #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 27482beb602SGarrett D'Amore /* Host Interrupt Mask */ 27582beb602SGarrett D'Amore #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 27682beb602SGarrett D'Amore #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 27782beb602SGarrett D'Amore #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 27882beb602SGarrett D'Amore #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D 27982beb602SGarrett D'Amore 28082beb602SGarrett D'Amore /* Host Interrupt Status */ 28182beb602SGarrett D'Amore #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 28282beb602SGarrett D'Amore /* 28382beb602SGarrett D'Amore * Set when the Utility_A Interrupt bit is set in the Outbound 28482beb602SGarrett D'Amore * Doorbell Register. It clears by writing a 1 to the 28582beb602SGarrett D'Amore * Utility_A bit in the Outbound Doorbell Clear Register or 28682beb602SGarrett D'Amore * through automatic clearing (if enabled). 28782beb602SGarrett D'Amore */ 28882beb602SGarrett D'Amore #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 28982beb602SGarrett D'Amore /* 29082beb602SGarrett D'Amore * Set if Outbound Doorbell register bits 30:1 have a non-zero 29182beb602SGarrett D'Amore * value. This bit clears only when Outbound Doorbell bits 29282beb602SGarrett D'Amore * 30:1 are ALL clear. Only a write to the Outbound Doorbell 29382beb602SGarrett D'Amore * Clear register clears bits in the Outbound Doorbell 29482beb602SGarrett D'Amore * register. 29582beb602SGarrett D'Amore */ 29682beb602SGarrett D'Amore #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 29782beb602SGarrett D'Amore /* 29882beb602SGarrett D'Amore * Set whenever the Outbound Post List Producer/Consumer 29982beb602SGarrett D'Amore * Register (FIFO) is not empty. It clears when the Outbound 30082beb602SGarrett D'Amore * Post List FIFO is empty. 30182beb602SGarrett D'Amore */ 30282beb602SGarrett D'Amore #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 30382beb602SGarrett D'Amore /* 30482beb602SGarrett D'Amore * This bit indicates a SAS interrupt from a source external to 30582beb602SGarrett D'Amore * the PCIe core. This bit is not maskable. 30682beb602SGarrett D'Amore */ 30782beb602SGarrett D'Amore /* DoorBell */ 30882beb602SGarrett D'Amore #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002 30982beb602SGarrett D'Amore #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004 31082beb602SGarrett D'Amore #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 31182beb602SGarrett D'Amore #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010 31282beb602SGarrett D'Amore #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002 31382beb602SGarrett D'Amore #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002 31482beb602SGarrett D'Amore #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004 31582beb602SGarrett D'Amore #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004 31682beb602SGarrett D'Amore #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 31782beb602SGarrett D'Amore #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008 31882beb602SGarrett D'Amore #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000 31982beb602SGarrett D'Amore 320508aff1aSJames C. McPherson /* data tunnel buffer between user space program and its firmware */ 321508aff1aSJames C. McPherson /* iop msgcode_rwbuffer for message command */ 322508aff1aSJames C. McPherson #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 323508aff1aSJames C. McPherson /* user space data to iop 128bytes */ 324508aff1aSJames C. McPherson #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 325508aff1aSJames C. McPherson /* iop data to user space 128bytes */ 326508aff1aSJames C. McPherson #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 327508aff1aSJames C. McPherson #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 328508aff1aSJames C. McPherson #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 329508aff1aSJames C. McPherson #define ARCMSR_HBB_BASE0_LEN 0x00021000 330508aff1aSJames C. McPherson #define ARCMSR_HBB_BASE1_LEN 0x00010000 331508aff1aSJames C. McPherson 332508aff1aSJames C. McPherson /* 333508aff1aSJames C. McPherson * structure for holding DMA address data 334508aff1aSJames C. McPherson */ 335508aff1aSJames C. McPherson #define IS_SG64_ADDR 0x01000000 /* bit24 */ 336508aff1aSJames C. McPherson 337508aff1aSJames C. McPherson /* 32bit Scatter-Gather list */ 338508aff1aSJames C. McPherson struct SG32ENTRY { 339508aff1aSJames C. McPherson /* bit 24 = 0, high 8 bit = flag, low 24 bit = length */ 340508aff1aSJames C. McPherson uint32_t length; 341508aff1aSJames C. McPherson uint32_t address; 342508aff1aSJames C. McPherson }; 343508aff1aSJames C. McPherson 344508aff1aSJames C. McPherson /* 64bit Scatter-Gather list */ 345508aff1aSJames C. McPherson struct SG64ENTRY { 346508aff1aSJames C. McPherson /* bit 24 = 1, high 8 bit = flag, low 24 bit = length */ 347508aff1aSJames C. McPherson uint32_t length; 348508aff1aSJames C. McPherson uint32_t address; 349508aff1aSJames C. McPherson uint32_t addresshigh; 350508aff1aSJames C. McPherson }; 351508aff1aSJames C. McPherson 352508aff1aSJames C. McPherson 353508aff1aSJames C. McPherson struct QBUFFER { 354508aff1aSJames C. McPherson uint32_t data_len; 355508aff1aSJames C. McPherson uint8_t data[124]; 356508aff1aSJames C. McPherson }; 357508aff1aSJames C. McPherson 35882beb602SGarrett D'Amore struct list_head { 35982beb602SGarrett D'Amore struct list_head *next, *prev; 36082beb602SGarrett D'Amore }; 36182beb602SGarrett D'Amore 362508aff1aSJames C. McPherson /* 363508aff1aSJames C. McPherson * FIRMWARE INFO 364508aff1aSJames C. McPherson */ 365508aff1aSJames C. McPherson #define ARCMSR_FW_MODEL_OFFSET 0x0f 366508aff1aSJames C. McPherson #define ARCMSR_FW_VERS_OFFSET 0x11 367ed632624SColin Yi #define ARCMSR_FW_MAP_OFFSET 0x15 368508aff1aSJames C. McPherson 369508aff1aSJames C. McPherson struct FIRMWARE_INFO { 370508aff1aSJames C. McPherson uint32_t signature; 371508aff1aSJames C. McPherson uint32_t request_len; 372508aff1aSJames C. McPherson uint32_t numbers_queue; 373508aff1aSJames C. McPherson uint32_t sdram_size; 374508aff1aSJames C. McPherson uint32_t ide_channels; 375508aff1aSJames C. McPherson char vendor[40]; 376508aff1aSJames C. McPherson char model[8]; 377508aff1aSJames C. McPherson char firmware_ver[16]; 378508aff1aSJames C. McPherson char device_map[16]; 379508aff1aSJames C. McPherson }; 380508aff1aSJames C. McPherson 381508aff1aSJames C. McPherson /* 382508aff1aSJames C. McPherson * ARECA FIRMWARE SPEC 383508aff1aSJames C. McPherson * 384508aff1aSJames C. McPherson * Usage of IOP331 adapter 385508aff1aSJames C. McPherson * 386508aff1aSJames C. McPherson * (All In/Out is in IOP331's view) 387508aff1aSJames C. McPherson * 1. Message 0 --> InitThread message and retrun code 388508aff1aSJames C. McPherson * 2. Doorbell is used for RS-232 emulation 389508aff1aSJames C. McPherson * InDoorBell : 390508aff1aSJames C. McPherson * bit0 -- data in ready (DRIVER DATA WRITE OK) 391508aff1aSJames C. McPherson * bit1 -- data out has been read 392508aff1aSJames C. McPherson * (DRIVER DATA READ OK) 393508aff1aSJames C. McPherson * outDoorBell: 394508aff1aSJames C. McPherson * bit0 -- data out ready (IOP331 DATA WRITE OK) 395508aff1aSJames C. McPherson * bit1 -- data in has been read 396508aff1aSJames C. McPherson * (IOP331 DATA READ OK) 397508aff1aSJames C. McPherson * 3. Index Memory Usage 398508aff1aSJames C. McPherson * offset 0xf00 : for RS232 out (request buffer) 399508aff1aSJames C. McPherson * offset 0xe00 : for RS232 in (scratch buffer) 400508aff1aSJames C. McPherson * offset 0xa00 : for inbound message code msgcode_rwbuffer 401508aff1aSJames C. McPherson * (driver send to IOP331) 402508aff1aSJames C. McPherson * offset 0xa00 : for outbound message code msgcode_rwbuffer 403508aff1aSJames C. McPherson * (IOP331 send to driver) 404508aff1aSJames C. McPherson * 4. RS-232 emulation 405508aff1aSJames C. McPherson * Currently 128 byte buffer is used: 406508aff1aSJames C. McPherson * 1st uint32_t : Data length (1--124) 407508aff1aSJames C. McPherson * Byte 4--127 : Max 124 bytes of data 408508aff1aSJames C. McPherson * 5. PostQ 409508aff1aSJames C. McPherson * All SCSI Command must be sent through postQ: 410508aff1aSJames C. McPherson * (inbound queue port) Request frame must be 32 bytes aligned 411508aff1aSJames C. McPherson * # bits 31:27 => flag for post ccb 412508aff1aSJames C. McPherson * # bits 26:00 => real address (bit 31:27) of post arcmsr_cdb 413508aff1aSJames C. McPherson * bit31 : 0 : 256 bytes frame 414508aff1aSJames C. McPherson * 1 : 512 bytes frame 415508aff1aSJames C. McPherson * bit30 : 0 : normal request 416508aff1aSJames C. McPherson * 1 : BIOS request 417508aff1aSJames C. McPherson * bit29 : reserved 418508aff1aSJames C. McPherson * bit28 : reserved 419508aff1aSJames C. McPherson * bit27 : reserved 420508aff1aSJames C. McPherson * ----------------------------------------------------------------------- 421508aff1aSJames C. McPherson * (outbount queue port) Request reply 422508aff1aSJames C. McPherson * # bits 31:27 => flag for reply 423508aff1aSJames C. McPherson * # bits 26:00 => real address (bits 31:27) of reply arcmsr_cdb 424508aff1aSJames C. McPherson * # bit31 : must be 0 (for this type of reply) 425508aff1aSJames C. McPherson * # bit30 : reserved for BIOS handshake 426508aff1aSJames C. McPherson * # bit29 : reserved 427508aff1aSJames C. McPherson * # bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 428508aff1aSJames C. McPherson * 1 : Error, see in AdapStatus/DevStatus/SenseData 429508aff1aSJames C. McPherson * # bit27 : reserved 430508aff1aSJames C. McPherson * 6. BIOS request 431508aff1aSJames C. McPherson * All BIOS request is the same with request from PostQ 432508aff1aSJames C. McPherson * Except : 433508aff1aSJames C. McPherson * Request frame is sent from configuration space 434508aff1aSJames C. McPherson * offset: 0x78 : Request Frame (bit30 == 1) 435508aff1aSJames C. McPherson * offset: 0x18 : writeonly to generate IRQ to IOP331 436508aff1aSJames C. McPherson * Completion of request: 437508aff1aSJames C. McPherson * (bit30 == 0, bit28==err flag) 438508aff1aSJames C. McPherson * 7. Definition of SGL entry (structure) 439508aff1aSJames C. McPherson * 8. Message1 Out - Diag Status Code (????) 440508aff1aSJames C. McPherson * 9. Message0 message code : 441508aff1aSJames C. McPherson * 0x00 : NOP 442508aff1aSJames C. McPherson * 0x01 : Get Config ->offset 0xa00 443508aff1aSJames C. McPherson * : for outbound message code msgcode_rwbuffer 444508aff1aSJames C. McPherson * (IOP331 send to driver) 445508aff1aSJames C. McPherson * Signature 0x87974060(4) 446508aff1aSJames C. McPherson * Request len 0x00000200(4) 447508aff1aSJames C. McPherson * numbers of queue 0x00000100(4) 448508aff1aSJames C. McPherson * SDRAM Size 0x00000100(4)-->256 MB 449508aff1aSJames C. McPherson * IDE Channels 0x00000008(4) 450508aff1aSJames C. McPherson * vendor 40 bytes char 451508aff1aSJames C. McPherson * model 8 bytes char 452508aff1aSJames C. McPherson * FirmVer 16 bytes char 453508aff1aSJames C. McPherson * Device Map 16 bytes char 454508aff1aSJames C. McPherson * 455508aff1aSJames C. McPherson * FirmwareVersion DWORD 456508aff1aSJames C. McPherson * <== Added for checking of new firmware capability 457508aff1aSJames C. McPherson * 0x02 : Set Config ->offset 0xa00 458508aff1aSJames C. McPherson * :for inbound message code msgcode_rwbuffer 459508aff1aSJames C. McPherson * (driver send to IOP331) 460508aff1aSJames C. McPherson * Signature 0x87974063(4) 461508aff1aSJames C. McPherson * UPPER32 of Request Frame (4)-->Driver Only 462508aff1aSJames C. McPherson * 0x03 : Reset (Abort all queued Command) 463508aff1aSJames C. McPherson * 0x04 : Stop Background Activity 464508aff1aSJames C. McPherson * 0x05 : Flush Cache 465508aff1aSJames C. McPherson * 0x06 : Start Background Activity 466508aff1aSJames C. McPherson * (re-start if background is halted) 467508aff1aSJames C. McPherson * 0x07 : Check If Host Command Pending 468508aff1aSJames C. McPherson * (Novell May Need This Function) 469508aff1aSJames C. McPherson * 0x08 : Set controller time ->offset 0xa00 (driver to IOP331) 470508aff1aSJames C. McPherson * : for inbound message code msgcode_rwbuffer 471508aff1aSJames C. McPherson * byte 0 : 0xaa <-- signature 472508aff1aSJames C. McPherson * byte 1 : 0x55 <-- signature 473508aff1aSJames C. McPherson * byte 2 : year (04) 474508aff1aSJames C. McPherson * byte 3 : month (1..12) 475508aff1aSJames C. McPherson * byte 4 : date (1..31) 476508aff1aSJames C. McPherson * byte 5 : hour (0..23) 477508aff1aSJames C. McPherson * byte 6 : minute (0..59) 478508aff1aSJames C. McPherson * byte 7 : second (0..59) 479508aff1aSJames C. McPherson * 480508aff1aSJames C. McPherson */ 481508aff1aSJames C. McPherson 482508aff1aSJames C. McPherson 483508aff1aSJames C. McPherson /* signature of set and get firmware config */ 484508aff1aSJames C. McPherson #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 485508aff1aSJames C. McPherson #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 486508aff1aSJames C. McPherson 487508aff1aSJames C. McPherson 488508aff1aSJames C. McPherson /* message code of inbound message register */ 489508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 490508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 491508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 492508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 493508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 494508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 495508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 496508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 497508aff1aSJames C. McPherson #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 498508aff1aSJames C. McPherson /* doorbell interrupt generator */ 499508aff1aSJames C. McPherson #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 500508aff1aSJames C. McPherson #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 501508aff1aSJames C. McPherson #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 502508aff1aSJames C. McPherson #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 50382beb602SGarrett D'Amore /* ccb areca ccb flag */ 504508aff1aSJames C. McPherson #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 505508aff1aSJames C. McPherson #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 506508aff1aSJames C. McPherson #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 507508aff1aSJames C. McPherson #define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 50882beb602SGarrett D'Amore #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000 50982beb602SGarrett D'Amore #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001 510508aff1aSJames C. McPherson /* outbound firmware ok */ 511508aff1aSJames C. McPherson #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 512508aff1aSJames C. McPherson 51382beb602SGarrett D'Amore /* dma burst sizes */ 514508aff1aSJames C. McPherson #ifndef BURSTSIZE 515508aff1aSJames C. McPherson #define BURSTSIZE 516508aff1aSJames C. McPherson #define BURST1 0x01 517508aff1aSJames C. McPherson #define BURST2 0x02 518508aff1aSJames C. McPherson #define BURST4 0x04 519508aff1aSJames C. McPherson #define BURST8 0x08 520508aff1aSJames C. McPherson #define BURST16 0x10 521508aff1aSJames C. McPherson #define BURST32 0x20 522508aff1aSJames C. McPherson #define BURST64 0x40 523508aff1aSJames C. McPherson #define BURSTSIZE_MASK 0x7f 524508aff1aSJames C. McPherson #define DEFAULT_BURSTSIZE BURST16|BURST8|BURST4|BURST2|BURST1 525508aff1aSJames C. McPherson #endif /* BURSTSIZE */ 526508aff1aSJames C. McPherson 52782beb602SGarrett D'Amore #define PtrToNum(p) (uintptr_t)((void *)p) 52882beb602SGarrett D'Amore #define NumToPtr(ul) (void *)((uintptr_t)ul) 529508aff1aSJames C. McPherson 530508aff1aSJames C. McPherson /* 531508aff1aSJames C. McPherson * 532508aff1aSJames C. McPherson */ 533508aff1aSJames C. McPherson struct ARCMSR_CDB { 53482beb602SGarrett D'Amore uint8_t Bus; /* should be 0 */ 53582beb602SGarrett D'Amore uint8_t TargetID; /* should be 0..15 */ 53682beb602SGarrett D'Amore uint8_t LUN; /* should be 0..7 */ 53782beb602SGarrett D'Amore uint8_t Function; /* should be 1 */ 538508aff1aSJames C. McPherson 53982beb602SGarrett D'Amore uint8_t CdbLength; /* set in arcmsr_tran_init_pkt */ 54082beb602SGarrett D'Amore uint8_t sgcount; 54182beb602SGarrett D'Amore uint8_t Flags; 542508aff1aSJames C. McPherson 543508aff1aSJames C. McPherson /* bit 0: 0(256) / 1(512) bytes */ 544508aff1aSJames C. McPherson #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 545508aff1aSJames C. McPherson /* bit 1: 0(from driver) / 1(from BIOS) */ 546508aff1aSJames C. McPherson #define ARCMSR_CDB_FLAG_BIOS 0x02 547508aff1aSJames C. McPherson /* bit 2: 0(Data in) / 1(Data out) */ 548508aff1aSJames C. McPherson #define ARCMSR_CDB_FLAG_WRITE 0x04 549508aff1aSJames C. McPherson /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 550508aff1aSJames C. McPherson #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 551508aff1aSJames C. McPherson #define ARCMSR_CDB_FLAG_HEADQ 0x08 552508aff1aSJames C. McPherson #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 553508aff1aSJames C. McPherson 55482beb602SGarrett D'Amore uint8_t Reserved1; 555508aff1aSJames C. McPherson 556508aff1aSJames C. McPherson uint32_t Context; /* Address of this request */ 557508aff1aSJames C. McPherson uint32_t DataLength; /* currently unused */ 558508aff1aSJames C. McPherson 559508aff1aSJames C. McPherson uint8_t Cdb[16]; /* SCSI CDB */ 560508aff1aSJames C. McPherson /* 561508aff1aSJames C. McPherson * Device Status : the same from SCSI bus if error occur 562508aff1aSJames C. McPherson * SCSI bus status codes. 563508aff1aSJames C. McPherson */ 564508aff1aSJames C. McPherson uint8_t DeviceStatus; 565508aff1aSJames C. McPherson 566508aff1aSJames C. McPherson #define SCSISTAT_GOOD 0x00 567508aff1aSJames C. McPherson #define SCSISTAT_CHECK_CONDITION 0x02 568508aff1aSJames C. McPherson #define SCSISTAT_CONDITION_MET 0x04 569508aff1aSJames C. McPherson #define SCSISTAT_BUSY 0x08 570508aff1aSJames C. McPherson #define SCSISTAT_INTERMEDIATE 0x10 571508aff1aSJames C. McPherson #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 572508aff1aSJames C. McPherson #define SCSISTAT_RESERVATION_CONFLICT 0x18 573508aff1aSJames C. McPherson #define SCSISTAT_COMMAND_TERMINATED 0x22 574508aff1aSJames C. McPherson #define SCSISTAT_QUEUE_FULL 0x28 57582beb602SGarrett D'Amore 576508aff1aSJames C. McPherson #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 577508aff1aSJames C. McPherson #define ARCMSR_DEV_ABORTED 0xF1 578508aff1aSJames C. McPherson #define ARCMSR_DEV_INIT_FAIL 0xF2 579508aff1aSJames C. McPherson 580508aff1aSJames C. McPherson uint8_t SenseData[15]; 581508aff1aSJames C. McPherson 582508aff1aSJames C. McPherson /* Scatter gather address */ 583508aff1aSJames C. McPherson union { 584508aff1aSJames C. McPherson struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; 585508aff1aSJames C. McPherson struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; 586508aff1aSJames C. McPherson } sgu; 587508aff1aSJames C. McPherson }; 588508aff1aSJames C. McPherson 589508aff1aSJames C. McPherson 590508aff1aSJames C. McPherson struct HBA_msgUnit { 591508aff1aSJames C. McPherson uint32_t resrved0[4]; 592508aff1aSJames C. McPherson uint32_t inbound_msgaddr0; 593508aff1aSJames C. McPherson uint32_t inbound_msgaddr1; 594508aff1aSJames C. McPherson uint32_t outbound_msgaddr0; 595508aff1aSJames C. McPherson uint32_t outbound_msgaddr1; 596508aff1aSJames C. McPherson uint32_t inbound_doorbell; 597508aff1aSJames C. McPherson uint32_t inbound_intstatus; 598508aff1aSJames C. McPherson uint32_t inbound_intmask; 599508aff1aSJames C. McPherson uint32_t outbound_doorbell; 600508aff1aSJames C. McPherson uint32_t outbound_intstatus; 601508aff1aSJames C. McPherson uint32_t outbound_intmask; 602508aff1aSJames C. McPherson uint32_t reserved1[2]; 603508aff1aSJames C. McPherson uint32_t inbound_queueport; 604508aff1aSJames C. McPherson uint32_t outbound_queueport; 605508aff1aSJames C. McPherson uint32_t reserved2[2]; 606508aff1aSJames C. McPherson /* ......local_buffer */ 607508aff1aSJames C. McPherson uint32_t reserved3[492]; 608508aff1aSJames C. McPherson uint32_t reserved4[128]; 609508aff1aSJames C. McPherson uint32_t msgcode_rwbuffer[256]; 610508aff1aSJames C. McPherson uint32_t message_wbuffer[32]; 611508aff1aSJames C. McPherson uint32_t reserved5[32]; 612508aff1aSJames C. McPherson uint32_t message_rbuffer[32]; 613508aff1aSJames C. McPherson uint32_t reserved6[32]; 614508aff1aSJames C. McPherson }; 615508aff1aSJames C. McPherson 616508aff1aSJames C. McPherson 617508aff1aSJames C. McPherson struct HBB_DOORBELL { 618508aff1aSJames C. McPherson uint8_t doorbell_reserved[132096]; 619508aff1aSJames C. McPherson /* 620508aff1aSJames C. McPherson * offset 0x00020400:00,01,02,03: window of "instruction flags" 621508aff1aSJames C. McPherson * from driver to iop 622508aff1aSJames C. McPherson */ 623508aff1aSJames C. McPherson uint32_t drv2iop_doorbell; 624508aff1aSJames C. McPherson /* 04,05,06,07: doorbell mask */ 625508aff1aSJames C. McPherson uint32_t drv2iop_doorbell_mask; 626508aff1aSJames C. McPherson /* 08,09,10,11: window of "instruction flags" from iop to driver */ 627508aff1aSJames C. McPherson uint32_t iop2drv_doorbell; 628508aff1aSJames C. McPherson /* 12,13,14,15: doorbell mask */ 629508aff1aSJames C. McPherson uint32_t iop2drv_doorbell_mask; 630508aff1aSJames C. McPherson }; 631508aff1aSJames C. McPherson 632508aff1aSJames C. McPherson 633508aff1aSJames C. McPherson struct HBB_RWBUFFER { 634508aff1aSJames C. McPherson uint8_t message_reserved0[64000]; 635508aff1aSJames C. McPherson /* offset 0x0000fa00: 0..1023: message code read write 1024bytes */ 636508aff1aSJames C. McPherson uint32_t msgcode_rwbuffer[256]; 637508aff1aSJames C. McPherson /* offset 0x0000fe00:1024...1151: user space data to iop 128bytes */ 638508aff1aSJames C. McPherson uint32_t message_wbuffer[32]; 639508aff1aSJames C. McPherson /* 1152...1279: message reserved */ 640508aff1aSJames C. McPherson uint32_t message_reserved1[32]; 641508aff1aSJames C. McPherson /* offset 0x0000ff00:1280...1407: iop data to user space 128bytes */ 642508aff1aSJames C. McPherson uint32_t message_rbuffer[32]; 643508aff1aSJames C. McPherson }; 644508aff1aSJames C. McPherson 645508aff1aSJames C. McPherson struct HBB_msgUnit { 64682beb602SGarrett D'Amore uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 64782beb602SGarrett D'Amore uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 648508aff1aSJames C. McPherson 64982beb602SGarrett D'Amore int32_t postq_index; /* post queue index */ 65082beb602SGarrett D'Amore int32_t doneq_index; /* done queue index */ 651508aff1aSJames C. McPherson struct HBB_DOORBELL *hbb_doorbell; 652508aff1aSJames C. McPherson struct HBB_RWBUFFER *hbb_rwbuffer; 653508aff1aSJames C. McPherson }; 654508aff1aSJames C. McPherson 65582beb602SGarrett D'Amore struct HBC_msgUnit { 65682beb602SGarrett D'Amore uint32_t message_unit_status; /* 0000 0003 */ 65782beb602SGarrett D'Amore uint32_t slave_error_attribute; /* 0004 0007 */ 65882beb602SGarrett D'Amore uint32_t slave_error_address; /* 0008 000B */ 65982beb602SGarrett D'Amore uint32_t posted_outbound_doorbell; /* 000C 000F */ 66082beb602SGarrett D'Amore uint32_t master_error_attribute; /* 0010 0013 */ 66182beb602SGarrett D'Amore uint32_t master_error_address_low; /* 0014 0017 */ 66282beb602SGarrett D'Amore uint32_t master_error_address_high; /* 0018 001B */ 66382beb602SGarrett D'Amore uint32_t hcb_size; /* 001C 001F */ 66482beb602SGarrett D'Amore uint32_t inbound_doorbell; /* 0020 0023 */ 66582beb602SGarrett D'Amore uint32_t diagnostic_rw_data; /* 0024 0027 */ 66682beb602SGarrett D'Amore uint32_t diagnostic_rw_address_low; /* 0028 002B */ 66782beb602SGarrett D'Amore uint32_t diagnostic_rw_address_high; /* 002C 002F */ 66882beb602SGarrett D'Amore uint32_t host_int_status; /* 0030 0033 */ 66982beb602SGarrett D'Amore uint32_t host_int_mask; /* 0034 0037 */ 67082beb602SGarrett D'Amore uint32_t dcr_data; /* 0038 003B */ 67182beb602SGarrett D'Amore uint32_t dcr_address; /* 003C 003F */ 67282beb602SGarrett D'Amore uint32_t inbound_queueport; /* 0040 0043 */ 67382beb602SGarrett D'Amore uint32_t outbound_queueport; /* 0044 0047 */ 67482beb602SGarrett D'Amore uint32_t hcb_pci_address_low; /* 0048 004B */ 67582beb602SGarrett D'Amore uint32_t hcb_pci_address_high; /* 004C 004F */ 67682beb602SGarrett D'Amore uint32_t iop_int_status; /* 0050 0053 */ 67782beb602SGarrett D'Amore uint32_t iop_int_mask; /* 0054 0057 */ 67882beb602SGarrett D'Amore uint32_t iop_inbound_queue_port; /* 0058 005B */ 67982beb602SGarrett D'Amore uint32_t iop_outbound_queue_port; /* 005C 005F */ 68082beb602SGarrett D'Amore uint32_t inbound_free_list_index; /* 0060 0063 */ 68182beb602SGarrett D'Amore uint32_t inbound_post_list_index; /* 0064 0067 */ 68282beb602SGarrett D'Amore uint32_t outbound_free_list_index; /* 0068 006B */ 68382beb602SGarrett D'Amore uint32_t outbound_post_list_index; /* 006C 006F */ 68482beb602SGarrett D'Amore uint32_t inbound_doorbell_clear; /* 0070 0073 */ 68582beb602SGarrett D'Amore uint32_t i2o_message_unit_control; /* 0074 0077 */ 68682beb602SGarrett D'Amore uint32_t last_used_message_source_address_low; /* 0078 007B */ 68782beb602SGarrett D'Amore uint32_t last_used_message_source_address_high; /* 007C 007F */ 68882beb602SGarrett D'Amore uint32_t pull_mode_data_byte_count[4]; /* 0080 008F */ 68982beb602SGarrett D'Amore uint32_t message_dest_address_index; /* 0090 0093 */ 69082beb602SGarrett D'Amore uint32_t done_queue_not_empty_int_counter_timer; /* 0094 0097 */ 69182beb602SGarrett D'Amore uint32_t utility_A_int_counter_timer; /* 0098 009B */ 69282beb602SGarrett D'Amore uint32_t outbound_doorbell; /* 009C 009F */ 69382beb602SGarrett D'Amore uint32_t outbound_doorbell_clear; /* 00A0 00A3 */ 69482beb602SGarrett D'Amore uint32_t message_source_address_index; /* 00A4 00A7 */ 69582beb602SGarrett D'Amore uint32_t message_done_queue_index; /* 00A8 00AB */ 69682beb602SGarrett D'Amore uint32_t reserved0; /* 00AC 00AF */ 69782beb602SGarrett D'Amore uint32_t inbound_msgaddr0; /* 00B0 00B3 */ 69882beb602SGarrett D'Amore uint32_t inbound_msgaddr1; /* 00B4 00B7 */ 69982beb602SGarrett D'Amore uint32_t outbound_msgaddr0; /* 00B8 00BB */ 70082beb602SGarrett D'Amore uint32_t outbound_msgaddr1; /* 00BC 00BF */ 70182beb602SGarrett D'Amore uint32_t inbound_queueport_low; /* 00C0 00C3 */ 70282beb602SGarrett D'Amore uint32_t inbound_queueport_high; /* 00C4 00C7 */ 70382beb602SGarrett D'Amore uint32_t outbound_queueport_low; /* 00C8 00CB */ 70482beb602SGarrett D'Amore uint32_t outbound_queueport_high; /* 00CC 00CF */ 70582beb602SGarrett D'Amore uint32_t iop_inbound_queue_port_low; /* 00D0 00D3 */ 70682beb602SGarrett D'Amore uint32_t iop_inbound_queue_port_high; /* 00D4 00D7 */ 70782beb602SGarrett D'Amore uint32_t iop_outbound_queue_port_low; /* 00D8 00DB */ 70882beb602SGarrett D'Amore uint32_t iop_outbound_queue_port_high; /* 00DC 00DF */ 70982beb602SGarrett D'Amore uint32_t message_dest_queue_port_low; /* 00E0 00E3 */ 71082beb602SGarrett D'Amore uint32_t message_dest_queue_port_high; /* 00E4 00E7 */ 71182beb602SGarrett D'Amore uint32_t last_used_message_dest_address_low; /* 00E8 00EB */ 71282beb602SGarrett D'Amore uint32_t last_used_message_dest_address_high; /* 00EC 00EF */ 71382beb602SGarrett D'Amore uint32_t message_done_queue_base_address_low; /* 00F0 00F3 */ 71482beb602SGarrett D'Amore uint32_t message_done_queue_base_address_high; /* 00F4 00F7 */ 71582beb602SGarrett D'Amore uint32_t host_diagnostic; /* 00F8 00FB */ 71682beb602SGarrett D'Amore uint32_t write_sequence; /* 00FC 00FF */ 71782beb602SGarrett D'Amore uint32_t reserved1[34]; /* 0100 0187 */ 71882beb602SGarrett D'Amore uint32_t reserved2[1950]; /* 0188 1FFF */ 71982beb602SGarrett D'Amore uint32_t message_wbuffer[32]; /* 2000 207F */ 72082beb602SGarrett D'Amore uint32_t reserved3[32]; /* 2080 20FF */ 72182beb602SGarrett D'Amore uint32_t message_rbuffer[32]; /* 2100 217F */ 72282beb602SGarrett D'Amore uint32_t reserved4[32]; /* 2180 21FF */ 72382beb602SGarrett D'Amore uint32_t msgcode_rwbuffer[256]; /* 2200 23FF */ 72482beb602SGarrett D'Amore }; 72582beb602SGarrett D'Amore 726508aff1aSJames C. McPherson struct msgUnit { 727508aff1aSJames C. McPherson union { 728508aff1aSJames C. McPherson struct HBA_msgUnit hbamu; 729508aff1aSJames C. McPherson struct HBB_msgUnit hbbmu; 73082beb602SGarrett D'Amore struct HBC_msgUnit hbcmu; 731508aff1aSJames C. McPherson } muu; 732508aff1aSJames C. McPherson }; 733508aff1aSJames C. McPherson 734508aff1aSJames C. McPherson 735508aff1aSJames C. McPherson /* 736508aff1aSJames C. McPherson * Adapter Control Block 737508aff1aSJames C. McPherson */ 738508aff1aSJames C. McPherson struct ACB { 739508aff1aSJames C. McPherson uint32_t adapter_type; /* A/B/C/D */ 740508aff1aSJames C. McPherson 741508aff1aSJames C. McPherson #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba (Intel) IOP */ 742508aff1aSJames C. McPherson #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb (Marvell) IOP */ 74382beb602SGarrett D'Amore #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc (Lsi) IOP */ 744508aff1aSJames C. McPherson #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 745508aff1aSJames C. McPherson 746508aff1aSJames C. McPherson scsi_hba_tran_t *scsi_hba_transport; 747508aff1aSJames C. McPherson dev_info_t *dev_info; 748508aff1aSJames C. McPherson ddi_acc_handle_t reg_mu_acc_handle0; 749508aff1aSJames C. McPherson ddi_acc_handle_t reg_mu_acc_handle1; 750508aff1aSJames C. McPherson ddi_acc_handle_t ccbs_acc_handle; 751508aff1aSJames C. McPherson ddi_dma_handle_t ccbs_pool_handle; 752508aff1aSJames C. McPherson ddi_dma_cookie_t ccb_cookie; 753508aff1aSJames C. McPherson ddi_device_acc_attr_t dev_acc_attr; 75482beb602SGarrett D'Amore kmutex_t isr_mutex; 755508aff1aSJames C. McPherson kmutex_t acb_mutex; 756508aff1aSJames C. McPherson kmutex_t postq_mutex; 757508aff1aSJames C. McPherson kmutex_t workingQ_mutex; 758508aff1aSJames C. McPherson kmutex_t ioctl_mutex; 75982beb602SGarrett D'Amore kmutex_t ccb_complete_list_mutex; 760508aff1aSJames C. McPherson timeout_id_t timeout_id; 761ed632624SColin Yi timeout_id_t timeout_sc_id; 762ed632624SColin Yi ddi_taskq_t *taskq; 76382beb602SGarrett D'Amore ddi_intr_handle_t *phandle; 76482beb602SGarrett D'Amore uint_t intr_size; 76582beb602SGarrett D'Amore int intr_count; 76682beb602SGarrett D'Amore uint_t intr_pri; 76782beb602SGarrett D'Amore int intr_cap; 76882beb602SGarrett D'Amore 769508aff1aSJames C. McPherson /* Offset for arc cdb physical to virtual calculations */ 77082beb602SGarrett D'Amore uint64_t vir2phy_offset; 771508aff1aSJames C. McPherson uint32_t outbound_int_enable; 77282beb602SGarrett D'Amore uint32_t cdb_phyaddr_hi32; 773508aff1aSJames C. McPherson /* message unit ATU inbound base address0 virtual */ 77482beb602SGarrett D'Amore struct msgUnit *pmu; 77582beb602SGarrett D'Amore struct list_head ccb_complete_list; 776508aff1aSJames C. McPherson 777508aff1aSJames C. McPherson uint8_t adapter_index; 778508aff1aSJames C. McPherson uint16_t acb_flags; 779508aff1aSJames C. McPherson 78082beb602SGarrett D'Amore #define ACB_F_SCSISTOPADAPTER 0x0001 781508aff1aSJames C. McPherson /* stop RAID background rebuild */ 78282beb602SGarrett D'Amore #define ACB_F_MSG_STOP_BGRB 0x0002 783508aff1aSJames C. McPherson /* stop RAID background rebuild */ 78482beb602SGarrett D'Amore #define ACB_F_MSG_START_BGRB 0x0004 785508aff1aSJames C. McPherson /* iop ioctl data rqbuffer overflow */ 78682beb602SGarrett D'Amore #define ACB_F_IOPDATA_OVERFLOW 0x0008 787508aff1aSJames C. McPherson /* ioctl clear wqbuffer */ 78882beb602SGarrett D'Amore #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 789508aff1aSJames C. McPherson /* ioctl clear rqbuffer */ 79082beb602SGarrett D'Amore #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 791508aff1aSJames C. McPherson /* ioctl iop wqbuffer data readed */ 79282beb602SGarrett D'Amore #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 79382beb602SGarrett D'Amore #define ACB_F_BUS_RESET 0x0080 794508aff1aSJames C. McPherson /* iop init */ 79582beb602SGarrett D'Amore #define ACB_F_IOP_INITED 0x0100 79682beb602SGarrett D'Amore /* need hardware reset bus */ 79782beb602SGarrett D'Amore #define ACB_F_BUS_HANG_ON 0x0800 798508aff1aSJames C. McPherson 799508aff1aSJames C. McPherson /* serial ccb pointer array */ 80082beb602SGarrett D'Amore struct CCB *pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 801508aff1aSJames C. McPherson /* working ccb pointer array */ 80282beb602SGarrett D'Amore struct CCB *ccbworkingQ[ARCMSR_MAX_FREECCB_NUM]; 803508aff1aSJames C. McPherson /* done ccb array index */ 80482beb602SGarrett D'Amore int32_t ccb_put_index; 805508aff1aSJames C. McPherson /* start ccb array index */ 80682beb602SGarrett D'Amore int32_t ccb_get_index; 80782beb602SGarrett D'Amore volatile uint32_t ccboutstandingcount; 808508aff1aSJames C. McPherson 809508aff1aSJames C. McPherson /* data collection buffer for read from 80331 */ 810508aff1aSJames C. McPherson uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 811508aff1aSJames C. McPherson /* first of read buffer */ 812508aff1aSJames C. McPherson int32_t rqbuf_firstidx; 813508aff1aSJames C. McPherson /* last of read buffer */ 814508aff1aSJames C. McPherson int32_t rqbuf_lastidx; 815508aff1aSJames C. McPherson 816508aff1aSJames C. McPherson /* data collection buffer for write to 80331 */ 817508aff1aSJames C. McPherson uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 818508aff1aSJames C. McPherson /* first of write buffer */ 819508aff1aSJames C. McPherson int32_t wqbuf_firstidx; 820508aff1aSJames C. McPherson /* last of write buffer */ 821508aff1aSJames C. McPherson int32_t wqbuf_lastidx; 822508aff1aSJames C. McPherson /* id0 ..... id15,lun0...lun7 */ 823508aff1aSJames C. McPherson uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 824508aff1aSJames C. McPherson #define ARECA_RAID_GONE 0x55 825508aff1aSJames C. McPherson #define ARECA_RAID_GOOD 0xaa 826508aff1aSJames C. McPherson 827ed632624SColin Yi uint32_t timeout_count; 828508aff1aSJames C. McPherson uint32_t num_resets; 829508aff1aSJames C. McPherson uint32_t num_aborts; 830508aff1aSJames C. McPherson uint32_t firm_request_len; 831508aff1aSJames C. McPherson uint32_t firm_numbers_queue; 832508aff1aSJames C. McPherson uint32_t firm_sdram_size; 833508aff1aSJames C. McPherson uint32_t firm_ide_channels; 83482beb602SGarrett D'Amore uint32_t firm_cfg_version; 835508aff1aSJames C. McPherson char firm_model[12]; 836508aff1aSJames C. McPherson char firm_version[20]; 837ed632624SColin Yi char device_map[20]; /* 21,84-99 */ 838508aff1aSJames C. McPherson ddi_acc_handle_t pci_acc_handle; 839508aff1aSJames C. McPherson }; 840508aff1aSJames C. McPherson 841508aff1aSJames C. McPherson 842508aff1aSJames C. McPherson /* 843508aff1aSJames C. McPherson * Command Control Block (SrbExtension) 844508aff1aSJames C. McPherson * 845508aff1aSJames C. McPherson * CCB must be not cross page boundary,and the order from offset 0 846508aff1aSJames C. McPherson * structure describing an ATA disk request this CCB length must be 847508aff1aSJames C. McPherson * 32 bytes boundary 848508aff1aSJames C. McPherson * 849508aff1aSJames C. McPherson */ 850508aff1aSJames C. McPherson struct CCB 851508aff1aSJames C. McPherson { 852508aff1aSJames C. McPherson struct ARCMSR_CDB arcmsr_cdb; 85382beb602SGarrett D'Amore struct list_head complete_queue_pointer; 85482beb602SGarrett D'Amore uint32_t cdb_phyaddr_pattern; 85582beb602SGarrett D'Amore uint16_t ccb_flags; 85682beb602SGarrett D'Amore #define CCB_FLAG_READ 0x0000 85782beb602SGarrett D'Amore #define CCB_FLAG_WRITE 0x0001 85882beb602SGarrett D'Amore #define CCB_FLAG_ERROR 0x0002 85982beb602SGarrett D'Amore #define CCB_FLAG_FLUSHCACHE 0x0004 86082beb602SGarrett D'Amore #define CCB_FLAG_MASTER_ABORTED 0x0008 86182beb602SGarrett D'Amore #define CCB_FLAG_DMAVALID 0x0010 86282beb602SGarrett D'Amore #define CCB_FLAG_DMACONSISTENT 0x0020 86382beb602SGarrett D'Amore #define CCB_FLAG_DMAWRITE 0x0040 86482beb602SGarrett D'Amore #define CCB_FLAG_PKTBIND 0x0080 86582beb602SGarrett D'Amore uint16_t ccb_state; 86682beb602SGarrett D'Amore #define ARCMSR_CCB_FREE 0x0000 86782beb602SGarrett D'Amore #define ARCMSR_CCB_UNBUILD 0x0100 86882beb602SGarrett D'Amore #define ARCMSR_CCB_START 0x0001 86982beb602SGarrett D'Amore #define ARCMSR_CCB_RETRY 0x0002 87082beb602SGarrett D'Amore #define ARCMSR_CCB_TIMEOUT 0x0004 87182beb602SGarrett D'Amore #define ARCMSR_CCB_ABORTED 0x0008 87282beb602SGarrett D'Amore #define ARCMSR_CCB_RESET 0x0010 87382beb602SGarrett D'Amore #define ARCMSR_CCB_DONE 0x0020 87482beb602SGarrett D'Amore #define ARCMSR_CCB_WAIT4_FREE 0x0040 87582beb602SGarrett D'Amore #define ARCMSR_CCB_BACK 0x0080 87682beb602SGarrett D'Amore #define ARCMSR_CCB_ILLEGAL 0xFFFF 87782beb602SGarrett D'Amore #define ARCMSR_ABNORMAL_MASK \ 87882beb602SGarrett D'Amore (ARCMSR_CCB_TIMEOUT | ARCMSR_CCB_ABORTED | ARCMSR_CCB_RESET) 87982beb602SGarrett D'Amore #define ARCMSR_CCB_CAN_BE_FREE (ARCMSR_CCB_WAIT4_FREE | ARCMSR_CCB_BACK) 880508aff1aSJames C. McPherson struct scsi_pkt *pkt; 88182beb602SGarrett D'Amore struct ACB *acb; 88282beb602SGarrett D'Amore ddi_dma_cookie_t pkt_dmacookies[ARCMSR_MAX_SG_ENTRIES]; 88382beb602SGarrett D'Amore ddi_dma_handle_t pkt_dma_handle; 88482beb602SGarrett D'Amore uint_t pkt_cookie; 88582beb602SGarrett D'Amore uint_t pkt_ncookies; 88682beb602SGarrett D'Amore uint_t pkt_nwin; 88782beb602SGarrett D'Amore uint_t pkt_curwin; 88882beb602SGarrett D'Amore off_t pkt_dma_offset; 88982beb602SGarrett D'Amore size_t pkt_dma_len; 89082beb602SGarrett D'Amore size_t total_dmac_size; 89182beb602SGarrett D'Amore time_t ccb_time; 89282beb602SGarrett D'Amore struct buf *bp; 89382beb602SGarrett D'Amore ddi_dma_cookie_t resid_dmacookie; 89482beb602SGarrett D'Amore uint32_t arc_cdb_size; 895508aff1aSJames C. McPherson }; 896508aff1aSJames C. McPherson 897508aff1aSJames C. McPherson 898508aff1aSJames C. McPherson /* SenseData[15] */ 899508aff1aSJames C. McPherson struct SENSE_DATA { 900508aff1aSJames C. McPherson DECL_BITFIELD3( 901508aff1aSJames C. McPherson ErrorCode :4, /* Vendor Unique error code */ 902508aff1aSJames C. McPherson ErrorClass :3, /* Error Class- fixed at 0x7 */ 903508aff1aSJames C. McPherson Valid :1); /* sense data is valid */ 904508aff1aSJames C. McPherson 905508aff1aSJames C. McPherson uint8_t SegmentNumber; /* segment number: for COPY cmd */ 906508aff1aSJames C. McPherson 907508aff1aSJames C. McPherson DECL_BITFIELD5( 908508aff1aSJames C. McPherson SenseKey :4, /* Sense key (see below) */ 909508aff1aSJames C. McPherson Reserved :1, /* reserved */ 910508aff1aSJames C. McPherson IncorrectLength :1, /* Incorrect Length Indicator */ 911508aff1aSJames C. McPherson EndOfMedia :1, /* End of Media */ 912508aff1aSJames C. McPherson FileMark :1); /* File Mark Detected */ 913508aff1aSJames C. McPherson 914508aff1aSJames C. McPherson uint8_t Information[4]; 915508aff1aSJames C. McPherson uint8_t AdditionalSenseLength; 916508aff1aSJames C. McPherson uint8_t CommandSpecificInformation[4]; 917508aff1aSJames C. McPherson uint8_t AdditionalSenseCode; 918508aff1aSJames C. McPherson uint8_t AdditionalSenseCodeQualifier; 919508aff1aSJames C. McPherson uint8_t FieldReplaceableUnitCode; 920508aff1aSJames C. McPherson }; 921508aff1aSJames C. McPherson 922508aff1aSJames C. McPherson #define VIDLEN 8 923508aff1aSJames C. McPherson #define PIDLEN 16 924508aff1aSJames C. McPherson #define REVLEN 4 925508aff1aSJames C. McPherson struct SCSIInqData { 926508aff1aSJames C. McPherson uint8_t DevType; /* Periph Qualifier & Periph Dev Type */ 927508aff1aSJames C. McPherson uint8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 928508aff1aSJames C. McPherson uint8_t Vers; /* ISO, ECMA, & ANSI versions */ 929508aff1aSJames C. McPherson uint8_t RDF; /* AEN, TRMIOP, & response data format */ 930508aff1aSJames C. McPherson uint8_t AddLen; /* length of additional data */ 931508aff1aSJames C. McPherson uint8_t Res1; /* reserved */ 932508aff1aSJames C. McPherson uint8_t Res2; /* reserved */ 933508aff1aSJames C. McPherson uint8_t Flags; /* RelADr, Wbus32, Wbus16, Sync etc */ 93482beb602SGarrett D'Amore uint8_t VendorID[VIDLEN]; /* Vendor Identification */ 93582beb602SGarrett D'Amore uint8_t ProductID[PIDLEN]; /* Product Identification */ 93682beb602SGarrett D'Amore uint8_t ProductRev[REVLEN]; /* Product Revision */ 937508aff1aSJames C. McPherson }; 938508aff1aSJames C. McPherson 939508aff1aSJames C. McPherson 940508aff1aSJames C. McPherson 941508aff1aSJames C. McPherson /* 942508aff1aSJames C. McPherson * These definitions are the register offsets as defined in the Intel 943508aff1aSJames C. McPherson * IOP manuals. See (correct as of 18 January 2008) 944508aff1aSJames C. McPherson * http://developer.intel.com/design/iio/index.htm?iid=ncdcnav2+stor_ioproc 945508aff1aSJames C. McPherson * for more details 946508aff1aSJames C. McPherson */ 947508aff1aSJames C. McPherson 948508aff1aSJames C. McPherson 949508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 950508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 951508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 952508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C 953508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 954508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 955508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 956508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C 957508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 958508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 959508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 960508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 961508aff1aSJames C. McPherson 962508aff1aSJames C. McPherson 963508aff1aSJames C. McPherson 964508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 965508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 966508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 967508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 968508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 969508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 970508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 971508aff1aSJames C. McPherson 972508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 973508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 974508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 975508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 976508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 977508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 978508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 979508aff1aSJames C. McPherson 980508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 981508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 982508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 983508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 984508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 985508aff1aSJames C. McPherson 986508aff1aSJames C. McPherson 98782beb602SGarrett D'Amore #define ARCMSR_MU_OUTBOUND_HANDLE_INT ( \ 98882beb602SGarrett D'Amore ARCMSR_MU_OUTBOUND_MESSAGE0_INT| \ 98982beb602SGarrett D'Amore ARCMSR_MU_OUTBOUND_MESSAGE1_INT| \ 99082beb602SGarrett D'Amore ARCMSR_MU_OUTBOUND_DOORBELL_INT| \ 99182beb602SGarrett D'Amore ARCMSR_MU_OUTBOUND_POSTQUEUE_INT| \ 99282beb602SGarrett D'Amore ARCMSR_MU_OUTBOUND_PCI_INT) 993508aff1aSJames C. McPherson 994508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 995508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 996508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 997508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 998508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 999508aff1aSJames C. McPherson 1000508aff1aSJames C. McPherson #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 1001508aff1aSJames C. McPherson 1002508aff1aSJames C. McPherson #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 1003508aff1aSJames C. McPherson #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 1004508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 1005508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 1006508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 1007508aff1aSJames C. McPherson #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 1008508aff1aSJames C. McPherson #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 1009508aff1aSJames C. McPherson 1010508aff1aSJames C. McPherson #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 1011508aff1aSJames C. McPherson #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 1012508aff1aSJames C. McPherson #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 1013508aff1aSJames C. McPherson #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 1014508aff1aSJames C. McPherson #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 1015508aff1aSJames C. McPherson #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 1016508aff1aSJames C. McPherson 1017508aff1aSJames C. McPherson 1018508aff1aSJames C. McPherson 1019508aff1aSJames C. McPherson #ifdef __cplusplus 1020508aff1aSJames C. McPherson } 1021508aff1aSJames C. McPherson #endif 102282beb602SGarrett D'Amore 1023508aff1aSJames C. McPherson #endif /* _SYS_SCSI_ADAPTERS_ARCMSR_H */ 1024