xref: /illumos-gate/usr/src/uts/intel/io/pci/pci_boot.c (revision d4039345)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright 2019 Joyent, Inc.
24  * Copyright 2019 Western Digital Corporation
25  * Copyright 2020 OmniOS Community Edition (OmniOSce) Association.
26  * Copyright 2022 Oxide Computer Company
27  */
28 
29 /*
30  * PCI bus enumeration and device programming are done in several passes. The
31  * following is a high level overview of this process.
32  *
33  * pci_enumerate(reprogram=0)
34  *				The main entry point to PCI bus enumeration is
35  *				pci_enumerate(). This function is invoked
36  *				twice, once to set up the PCI portion of the
37  *				device tree, and then a second time to
38  *				reprogram any devices which were not set up by
39  *				the system firmware. On this first call, the
40  *				reprogram parameter is set to 0.
41  *   add_pci_fixes()
42  *	enumerate_bus_devs(CONFIG_FIX)
43  *	    <foreach bus>
44  *	        process_devfunc(CONFIG_FIX)
45  *				Some devices need a specific action taking in
46  *				order for subsequent enumeration to be
47  *				successful. add_pci_fixes() retrieves the
48  *				vendor and device IDs for each item on the bus
49  *				and applies fixes as required. It also creates
50  *				a list which is used by undo_pci_fixes() to
51  *				reverse the process later.
52  *   pci_setup_tree()
53  *	enumerate_bus_devs(CONFIG_INFO)
54  *	    <foreach bus>
55  *	        process_devfunc(CONFIG_INFO)
56  *	            <set up most device properties>
57  *				The next stage is to enumerate the bus and set
58  *				up the bulk of the properties for each device.
59  *				This is where the generic properties such as
60  *				'device-id' are created.
61  *		    <if PPB device>
62  *			add_ppb_props()
63  *				For a PCI-to-PCI bridge (ppb) device, any
64  *				memory ranges for IO, memory or pre-fetchable
65  *				memory that have been programmed by the system
66  *				firmware (BIOS/EFI) are retrieved and stored in
67  *				bus-specific lists (pci_bus_res[bus].io_avail,
68  *				mem_avail and pmem_avail). The contents of
69  *				these lists are used to set the initial 'ranges'
70  *				property on the ppb device. Later, as children
71  *				are found for this bridge, resources will be
72  *				removed from these avail lists as necessary.
73  *				This is an initial pass so the ppb devices can
74  *				still be reprogrammed later in fix_ppb_res().
75  *		    <else>
76  *			<add to list of non-PPB devices for the bus>
77  *				Any non-PPB device on the bus is recorded in a
78  *				bus-specific list, to be set up (and possibly
79  *				reprogrammed) later.
80  *		    add_reg_props(CONFIG_INFO)
81  *				The final step in this phase is to add the
82  *				initial 'reg' and 'assigned-addresses'
83  *				properties to all devices. At the same time,
84  *				any IO or memory ranges which have been
85  *				assigned to the bus are moved from the avail
86  *				list to the corresponding used one. If no
87  *				resources have been assigned to a device at
88  *				this stage, then it is flagged for subsequent
89  *				reprogramming.
90  *     undo_pci_fixes()
91  *				Any fixes which were applied in add_pci_fixes()
92  *				are now undone before returning, using the
93  *				undo list which was created earier.
94  *
95  * pci_enumerate(reprogram=1)
96  *				The second bus enumeration pass is to take care
97  *				of any devices that were not set up by the
98  *				system firmware. These devices were flagged
99  *				during the first pass. This pass is bracketed
100  *				by the same pci fix application and removal as
101  *				the first.
102  *   add_pci_fixes()
103  *				As for first pass.
104  *   pci_reprogram()
105  *	pci_prd_root_complex_iter()
106  *				The platform is asked to tell us of all root
107  *				complexes that it knows about (e.g. using the
108  *				_BBN method via ACPI). This will include buses
109  *				that we've already discovered and those that we
110  *				potentially haven't. Anything that has not been
111  *				previously discovered (or inferred to exist) is
112  *				then added to the system.
113  *	<foreach ROOT bus>
114  *	    populate_bus_res()
115  *				Find resources associated with this root bus
116  *				based on what the platform provideds through the
117  *				pci platform interfaces defined in
118  *				sys/plat/pci_prd.h. On i86pc this is driven by
119  *				ACPI and BIOS tables.
120  *	<foreach bus>
121  *	    fix_ppb_res()
122  *				Reprogram pci(e) bridges which have not already
123  *				had resources assigned, or which are under a
124  *				bus that has been flagged for reprogramming.
125  *				If the parent bus has not been flagged, then IO
126  *				space is reprogrammed only if there are no
127  *				assigned IO resources. Memory space is
128  *				reprogrammed only if there is both no assigned
129  *				ordinary memory AND no assigned pre-fetchable
130  *				memory. However, if memory reprogramming is
131  *				necessary then both ordinary and prefetch are
132  *				done together so that both memory ranges end up
133  *				in the avail lists for add_reg_props() to find
134  *				later.
135  *	    enumerate_bus_devs(CONFIG_NEW)
136  *		<foreach non-PPB device on the bus>
137  *		    add_reg_props(CONFIG_NEW)
138  *				Using the list of non-PPB devices on the bus
139  *				which was assembled during the first pass, add
140  *				or update the 'reg' and 'assigned-address'
141  *				properties for these devices. For devices which
142  *				have been flagged for reprogramming or have no
143  *				assigned resources, this is where resources are
144  *				finally assigned and programmed into the
145  *				device. This can result in these properties
146  *				changing from their previous values.
147  *	<foreach bus>
148  *	    add_bus_available_prop()
149  *				Finally, the 'available' properties is set on
150  *				each device, representing that device's final
151  *				unallocated (available) IO and memory ranges.
152  *   undo_pci_fixes()
153  *				As for first pass.
154  */
155 
156 #include <sys/types.h>
157 #include <sys/stat.h>
158 #include <sys/sysmacros.h>
159 #include <sys/sunndi.h>
160 #include <sys/pci.h>
161 #include <sys/pci_impl.h>
162 #include <sys/pcie_impl.h>
163 #include <sys/memlist.h>
164 #include <sys/bootconf.h>
165 #include <sys/pci_cfgacc.h>
166 #include <sys/pci_cfgspace.h>
167 #include <sys/pci_cfgspace_impl.h>
168 #include <sys/psw.h>
169 #include "../../../../common/pci/pci_strings.h"
170 #include <sys/apic.h>
171 #include <io/pciex/pcie_nvidia.h>
172 #include <sys/hotplug/pci/pciehpc_acpi.h>
173 #include <sys/acpi/acpi.h>
174 #include <sys/acpica.h>
175 #include <sys/iommulib.h>
176 #include <sys/devcache.h>
177 #include <sys/pci_cfgacc_x86.h>
178 #include <sys/plat/pci_prd.h>
179 
180 #define	pci_getb	(*pci_getb_func)
181 #define	pci_getw	(*pci_getw_func)
182 #define	pci_getl	(*pci_getl_func)
183 #define	pci_putb	(*pci_putb_func)
184 #define	pci_putw	(*pci_putw_func)
185 #define	pci_putl	(*pci_putl_func)
186 #define	dcmn_err	if (pci_boot_debug != 0) cmn_err
187 #define	bus_debug(bus)	(pci_boot_debug != 0 && pci_debug_bus_start != -1 && \
188 	    pci_debug_bus_end != -1 && (bus) >= pci_debug_bus_start && \
189 	    (bus) <= pci_debug_bus_end)
190 #define	dump_memlists(tag, bus) \
191 	if (bus_debug((bus))) dump_memlists_impl((tag), (bus))
192 
193 #define	CONFIG_INFO	0
194 #define	CONFIG_UPDATE	1
195 #define	CONFIG_NEW	2
196 #define	CONFIG_FIX	3
197 #define	COMPAT_BUFSIZE	512
198 
199 #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
200 #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
201 /* round down to nearest power of two */
202 #define	P2LE(align)					\
203 	{						\
204 		int i = 0;				\
205 		while (align >>= 1)			\
206 			i ++;				\
207 		align = 1 << i;				\
208 	}						\
209 
210 /* for is_vga and list_is_vga_only */
211 
212 enum io_mem {
213 	IO,
214 	MEM
215 };
216 
217 /* for get_parbus_res */
218 
219 enum parbus_mem {
220 	PB_IO,
221 	PB_MEM,
222 	PB_PMEM
223 };
224 
225 
226 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
227 #define	LPC_IO_CONTROL_REG_1	0x40
228 #define	AMD8111_ENABLENMI	(uint8_t)0x80
229 #define	DEVID_AMD8111_LPC	0x7468
230 
231 struct pci_fixundo {
232 	uint8_t			bus;
233 	uint8_t			dev;
234 	uint8_t			fn;
235 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
236 	struct pci_fixundo	*next;
237 };
238 
239 struct pci_devfunc {
240 	struct pci_devfunc *next;
241 	dev_info_t *dip;
242 	uchar_t dev;
243 	uchar_t func;
244 	boolean_t reprogram;	/* this device needs to be reprogrammed */
245 };
246 
247 extern int apic_nvidia_io_max;
248 extern int pseudo_isa;
249 static uchar_t max_dev_pci = 32;	/* PCI standard */
250 int pci_boot_maxbus;
251 int pci_boot_debug = 0;
252 int pci_debug_bus_start = -1;
253 int pci_debug_bus_end = -1;
254 static struct pci_fixundo *undolist = NULL;
255 static int num_root_bus = 0;	/* count of root buses */
256 extern void pci_cfgacc_add_workaround(uint16_t, uchar_t, uchar_t);
257 extern dev_info_t *pcie_get_rc_dip(dev_info_t *);
258 
259 /*
260  * Module prototypes
261  */
262 static void enumerate_bus_devs(uchar_t bus, int config_op);
263 static void create_root_bus_dip(uchar_t bus);
264 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
265     ushort_t, int);
266 static void add_compatible(dev_info_t *, ushort_t, ushort_t,
267     ushort_t, ushort_t, uchar_t, uint_t, int);
268 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
269 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int,
270     ushort_t);
271 static void add_model_prop(dev_info_t *, uint_t);
272 static void add_bus_range_prop(int);
273 static void add_ranges_prop(int, int);
274 static void add_bus_available_prop(int);
275 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
276 static void fix_ppb_res(uchar_t, boolean_t);
277 static void alloc_res_array(void);
278 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
279     ushort_t deviceid);
280 static void pciex_slot_names_prop(dev_info_t *, ushort_t);
281 static void populate_bus_res(uchar_t bus);
282 static void memlist_remove_list(struct memlist **list,
283     struct memlist *remove_list);
284 static void ck804_fix_aer_ptr(dev_info_t *, pcie_req_id_t);
285 
286 static int pci_unitaddr_cache_valid(void);
287 static int pci_bus_unitaddr(int);
288 static void pci_unitaddr_cache_create(void);
289 
290 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *);
291 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **);
292 static void pci_cache_free_list(nvf_handle_t);
293 
294 /* set non-zero to force PCI peer-bus renumbering */
295 int pci_bus_always_renumber = 0;
296 
297 /*
298  * used to register ISA resource usage which must not be made
299  * "available" from other PCI node' resource maps
300  */
301 static struct {
302 	struct memlist *io_used;
303 	struct memlist *mem_used;
304 } isa_res;
305 
306 /*
307  * PCI unit-address cache management
308  */
309 static nvf_ops_t pci_unitaddr_cache_ops = {
310 	"/etc/devices/pci_unitaddr_persistent",	/* path to cache */
311 	pci_cache_unpack_nvlist,		/* read in nvlist form */
312 	pci_cache_pack_nvlist,			/* convert to nvlist form */
313 	pci_cache_free_list,			/* free data list */
314 	NULL					/* write complete callback */
315 };
316 
317 typedef struct {
318 	list_node_t	pua_nodes;
319 	int		pua_index;
320 	int		pua_addr;
321 } pua_node_t;
322 
323 nvf_handle_t	puafd_handle;
324 int		pua_cache_valid = 0;
325 
326 dev_info_t *
pci_boot_bus_to_dip(uint32_t busno)327 pci_boot_bus_to_dip(uint32_t busno)
328 {
329 	ASSERT3U(busno, <=, pci_boot_maxbus);
330 	return (pci_bus_res[busno].dip);
331 }
332 
333 static void
dump_memlists_impl(const char * tag,int bus)334 dump_memlists_impl(const char *tag, int bus)
335 {
336 	printf("Memlist dump at %s - bus %x\n", tag, bus);
337 	if (pci_bus_res[bus].io_used != NULL) {
338 		printf("    io_used ");
339 		memlist_dump(pci_bus_res[bus].io_used);
340 	}
341 	if (pci_bus_res[bus].io_avail != NULL) {
342 		printf("    io_avail ");
343 		memlist_dump(pci_bus_res[bus].io_avail);
344 	}
345 	if (pci_bus_res[bus].mem_used != NULL) {
346 		printf("    mem_used ");
347 		memlist_dump(pci_bus_res[bus].mem_used);
348 	}
349 	if (pci_bus_res[bus].mem_avail != NULL) {
350 		printf("    mem_avail ");
351 		memlist_dump(pci_bus_res[bus].mem_avail);
352 	}
353 	if (pci_bus_res[bus].pmem_used != NULL) {
354 		printf("    pmem_used ");
355 		memlist_dump(pci_bus_res[bus].pmem_used);
356 	}
357 	if (pci_bus_res[bus].pmem_avail != NULL) {
358 		printf("    pmem_avail ");
359 		memlist_dump(pci_bus_res[bus].pmem_avail);
360 	}
361 }
362 
363 static boolean_t
pci_rc_scan_cb(uint32_t busno,void * arg)364 pci_rc_scan_cb(uint32_t busno, void *arg)
365 {
366 	if (busno > pci_boot_maxbus) {
367 		dcmn_err(CE_NOTE, "platform root complex scan returned bus "
368 		    "with invalid bus id: 0x%x", busno);
369 		return (B_TRUE);
370 	}
371 
372 	if (pci_bus_res[busno].par_bus == (uchar_t)-1 &&
373 	    pci_bus_res[busno].dip == NULL) {
374 		create_root_bus_dip((uchar_t)busno);
375 	}
376 
377 	return (B_TRUE);
378 }
379 
380 static void
pci_unitaddr_cache_init(void)381 pci_unitaddr_cache_init(void)
382 {
383 
384 	puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops);
385 	ASSERT(puafd_handle);
386 
387 	list_create(nvf_list(puafd_handle), sizeof (pua_node_t),
388 	    offsetof(pua_node_t, pua_nodes));
389 
390 	rw_enter(nvf_lock(puafd_handle), RW_WRITER);
391 	(void) nvf_read_file(puafd_handle);
392 	rw_exit(nvf_lock(puafd_handle));
393 }
394 
395 /*
396  * Format of /etc/devices/pci_unitaddr_persistent:
397  *
398  * The persistent record of unit-address assignments contains
399  * a list of name/value pairs, where name is a string representation
400  * of the "index value" of the PCI root-bus and the value is
401  * the assigned unit-address.
402  *
403  * The "index value" is simply the zero-based index of the PCI
404  * root-buses ordered by physical bus number; first PCI bus is 0,
405  * second is 1, and so on.
406  */
407 
408 /*ARGSUSED*/
409 static int
pci_cache_unpack_nvlist(nvf_handle_t hdl,nvlist_t * nvl,char * name)410 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name)
411 {
412 	long		index;
413 	int32_t		value;
414 	nvpair_t	*np;
415 	pua_node_t	*node;
416 
417 	np = NULL;
418 	while ((np = nvlist_next_nvpair(nvl, np)) != NULL) {
419 		/* name of nvpair is index value */
420 		if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0)
421 			continue;
422 
423 		if (nvpair_value_int32(np, &value) != 0)
424 			continue;
425 
426 		node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP);
427 		node->pua_index = index;
428 		node->pua_addr = value;
429 		list_insert_tail(nvf_list(hdl), node);
430 	}
431 
432 	pua_cache_valid = 1;
433 	return (DDI_SUCCESS);
434 }
435 
436 static int
pci_cache_pack_nvlist(nvf_handle_t hdl,nvlist_t ** ret_nvl)437 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl)
438 {
439 	int		rval;
440 	nvlist_t	*nvl, *sub_nvl;
441 	list_t		*listp;
442 	pua_node_t	*pua;
443 	char		buf[13];
444 
445 	ASSERT(RW_WRITE_HELD(nvf_lock(hdl)));
446 
447 	rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
448 	if (rval != DDI_SUCCESS) {
449 		nvf_error("%s: nvlist alloc error %d\n",
450 		    nvf_cache_name(hdl), rval);
451 		return (DDI_FAILURE);
452 	}
453 
454 	sub_nvl = NULL;
455 	rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP);
456 	if (rval != DDI_SUCCESS)
457 		goto error;
458 
459 	listp = nvf_list(hdl);
460 	for (pua = list_head(listp); pua != NULL;
461 	    pua = list_next(listp, pua)) {
462 		(void) snprintf(buf, sizeof (buf), "%d", pua->pua_index);
463 		rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr);
464 		if (rval != DDI_SUCCESS)
465 			goto error;
466 	}
467 
468 	rval = nvlist_add_nvlist(nvl, "table", sub_nvl);
469 	if (rval != DDI_SUCCESS)
470 		goto error;
471 	nvlist_free(sub_nvl);
472 
473 	*ret_nvl = nvl;
474 	return (DDI_SUCCESS);
475 
476 error:
477 	nvlist_free(sub_nvl);
478 	ASSERT(nvl);
479 	nvlist_free(nvl);
480 	*ret_nvl = NULL;
481 	return (DDI_FAILURE);
482 }
483 
484 static void
pci_cache_free_list(nvf_handle_t hdl)485 pci_cache_free_list(nvf_handle_t hdl)
486 {
487 	list_t		*listp;
488 	pua_node_t	*pua;
489 
490 	ASSERT(RW_WRITE_HELD(nvf_lock(hdl)));
491 
492 	listp = nvf_list(hdl);
493 	for (pua = list_head(listp); pua != NULL;
494 	    pua = list_next(listp, pua)) {
495 		list_remove(listp, pua);
496 		kmem_free(pua, sizeof (pua_node_t));
497 	}
498 }
499 
500 
501 static int
pci_unitaddr_cache_valid(void)502 pci_unitaddr_cache_valid(void)
503 {
504 
505 	/* read only, no need for rw lock */
506 	return (pua_cache_valid);
507 }
508 
509 
510 static int
pci_bus_unitaddr(int index)511 pci_bus_unitaddr(int index)
512 {
513 	pua_node_t	*pua;
514 	list_t		*listp;
515 	int		addr;
516 
517 	rw_enter(nvf_lock(puafd_handle), RW_READER);
518 
519 	addr = -1;	/* default return if no match */
520 	listp = nvf_list(puafd_handle);
521 	for (pua = list_head(listp); pua != NULL;
522 	    pua = list_next(listp, pua)) {
523 		if (pua->pua_index == index) {
524 			addr = pua->pua_addr;
525 			break;
526 		}
527 	}
528 
529 	rw_exit(nvf_lock(puafd_handle));
530 	return (addr);
531 }
532 
533 static void
pci_unitaddr_cache_create(void)534 pci_unitaddr_cache_create(void)
535 {
536 	int		i, index;
537 	pua_node_t	*node;
538 	list_t		*listp;
539 
540 	rw_enter(nvf_lock(puafd_handle), RW_WRITER);
541 
542 	index = 0;
543 	listp = nvf_list(puafd_handle);
544 	for (i = 0; i <= pci_boot_maxbus; i++) {
545 		/* skip non-root (peer) PCI busses */
546 		if ((pci_bus_res[i].par_bus != (uchar_t)-1) ||
547 		    (pci_bus_res[i].dip == NULL))
548 			continue;
549 		node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP);
550 		node->pua_index = index++;
551 		node->pua_addr = pci_bus_res[i].root_addr;
552 		list_insert_tail(listp, node);
553 	}
554 
555 	(void) nvf_mark_dirty(puafd_handle);
556 	rw_exit(nvf_lock(puafd_handle));
557 	nvf_wake_daemon();
558 }
559 
560 
561 /*
562  * Enumerate all PCI devices
563  */
564 void
pci_setup_tree(void)565 pci_setup_tree(void)
566 {
567 	uint_t i, root_bus_addr = 0;
568 
569 	alloc_res_array();
570 	for (i = 0; i <= pci_boot_maxbus; i++) {
571 		pci_bus_res[i].par_bus = (uchar_t)-1;
572 		pci_bus_res[i].root_addr = (uchar_t)-1;
573 		pci_bus_res[i].sub_bus = i;
574 	}
575 
576 	pci_bus_res[0].root_addr = root_bus_addr++;
577 	create_root_bus_dip(0);
578 	enumerate_bus_devs(0, CONFIG_INFO);
579 
580 	/*
581 	 * Now enumerate peer busses
582 	 *
583 	 * We loop till pci_boot_maxbus. On most systems, there is
584 	 * one more bus at the high end, which implements the ISA
585 	 * compatibility bus. We don't care about that.
586 	 *
587 	 * Note: In the old (bootconf) enumeration, the peer bus
588 	 *	address did not use the bus number, and there were
589 	 *	too many peer busses created. The root_bus_addr is
590 	 *	used to maintain the old peer bus address assignment.
591 	 *	However, we stop enumerating phantom peers with no
592 	 *	device below.
593 	 */
594 	for (i = 1; i <= pci_boot_maxbus; i++) {
595 		if (pci_bus_res[i].dip == NULL) {
596 			pci_bus_res[i].root_addr = root_bus_addr++;
597 		}
598 		enumerate_bus_devs(i, CONFIG_INFO);
599 	}
600 }
601 
602 void
pci_register_isa_resources(int type,uint32_t base,uint32_t size)603 pci_register_isa_resources(int type, uint32_t base, uint32_t size)
604 {
605 	(void) memlist_insert(
606 	    (type == 1) ?  &isa_res.io_used : &isa_res.mem_used,
607 	    base, size);
608 }
609 
610 /*
611  * Remove the resources which are already used by devices under a subtractive
612  * bridge from the bus's resources lists, because they're not available, and
613  * shouldn't be allocated to other buses.  This is necessary because tracking
614  * resources for subtractive bridges is not complete.  (Subtractive bridges only
615  * track some of their claimed resources, not "the rest of the address space" as
616  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
617  * need a fully-capable global resource allocator).
618  */
619 static void
remove_subtractive_res()620 remove_subtractive_res()
621 {
622 	int i, j;
623 	struct memlist *list;
624 
625 	for (i = 0; i <= pci_boot_maxbus; i++) {
626 		if (pci_bus_res[i].subtractive) {
627 			/* remove used io ports */
628 			list = pci_bus_res[i].io_used;
629 			while (list) {
630 				for (j = 0; j <= pci_boot_maxbus; j++)
631 					(void) memlist_remove(
632 					    &pci_bus_res[j].io_avail,
633 					    list->ml_address, list->ml_size);
634 				list = list->ml_next;
635 			}
636 			/* remove used mem resource */
637 			list = pci_bus_res[i].mem_used;
638 			while (list) {
639 				for (j = 0; j <= pci_boot_maxbus; j++) {
640 					(void) memlist_remove(
641 					    &pci_bus_res[j].mem_avail,
642 					    list->ml_address, list->ml_size);
643 					(void) memlist_remove(
644 					    &pci_bus_res[j].pmem_avail,
645 					    list->ml_address, list->ml_size);
646 				}
647 				list = list->ml_next;
648 			}
649 			/* remove used prefetchable mem resource */
650 			list = pci_bus_res[i].pmem_used;
651 			while (list) {
652 				for (j = 0; j <= pci_boot_maxbus; j++) {
653 					(void) memlist_remove(
654 					    &pci_bus_res[j].pmem_avail,
655 					    list->ml_address, list->ml_size);
656 					(void) memlist_remove(
657 					    &pci_bus_res[j].mem_avail,
658 					    list->ml_address, list->ml_size);
659 				}
660 				list = list->ml_next;
661 			}
662 		}
663 	}
664 }
665 
666 /*
667  * Set up (or complete the setup of) the bus_avail resource list
668  */
669 static void
setup_bus_res(int bus)670 setup_bus_res(int bus)
671 {
672 	uchar_t par_bus;
673 
674 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
675 		return;
676 
677 	/*
678 	 * Set up bus_avail if not already filled in by populate_bus_res()
679 	 */
680 	if (pci_bus_res[bus].bus_avail == NULL) {
681 		ASSERT(pci_bus_res[bus].sub_bus >= bus);
682 		memlist_insert(&pci_bus_res[bus].bus_avail, bus,
683 		    pci_bus_res[bus].sub_bus - bus + 1);
684 	}
685 
686 	ASSERT(pci_bus_res[bus].bus_avail != NULL);
687 
688 	/*
689 	 * Remove resources from parent bus node if this is not a
690 	 * root bus.
691 	 */
692 	par_bus = pci_bus_res[bus].par_bus;
693 	if (par_bus != (uchar_t)-1) {
694 		ASSERT(pci_bus_res[par_bus].bus_avail != NULL);
695 		memlist_remove_list(&pci_bus_res[par_bus].bus_avail,
696 		    pci_bus_res[bus].bus_avail);
697 	}
698 
699 	/* remove self from bus_avail */;
700 	(void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1);
701 }
702 
703 /*
704  * Allocate a resource from the parent bus
705  */
706 static uint64_t
get_parbus_res(uchar_t parbus,uchar_t bus,uint64_t size,uint64_t align,enum parbus_mem mem)707 get_parbus_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align,
708     enum parbus_mem mem)
709 {
710 	uint64_t addr = 0;
711 	uchar_t res_bus;
712 
713 	/*
714 	 * Skip root(peer) buses in multiple-root-bus systems when
715 	 * ACPI resource discovery was not successfully done; the
716 	 * initial resources set on each root bus might not be correctly
717 	 * accounted for in this case.
718 	 */
719 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
720 	    (num_root_bus > 1) && !pci_prd_multi_root_ok()) {
721 		return (0);
722 	}
723 
724 	/*
725 	 * Set res_bus to the bus from which resources should be allocated.
726 	 * A device under a subtractive PPB can allocate resources from its
727 	 * parent bus if there are no resources available on its own bus, so
728 	 * iterate up the chain until resources are found or the root is
729 	 * reached.
730 	 */
731 	res_bus = parbus;
732 	while (pci_bus_res[res_bus].subtractive) {
733 		if (mem == PB_IO && pci_bus_res[res_bus].io_avail != NULL)
734 			break;
735 		if (mem == PB_MEM && pci_bus_res[res_bus].mem_avail != NULL)
736 			break;
737 		if (mem == PB_PMEM && pci_bus_res[res_bus].pmem_avail != NULL)
738 			break;
739 		res_bus = pci_bus_res[res_bus].par_bus;
740 		/* Has the root bus been reached? */
741 		if (res_bus == (uchar_t)-1)
742 			break;
743 	}
744 
745 	switch (mem) {
746 	case PB_IO:
747 		if (pci_bus_res[res_bus].io_avail == NULL)
748 			break;
749 		addr = memlist_find(&pci_bus_res[res_bus].io_avail,
750 		    size, align);
751 		if (addr > 0) {
752 			memlist_insert(&pci_bus_res[res_bus].io_used,
753 			    addr, size);
754 
755 			/* free the old resource */
756 			memlist_free_all(&pci_bus_res[bus].io_avail);
757 			memlist_free_all(&pci_bus_res[bus].io_used);
758 
759 			/* add the new resource */
760 			memlist_insert(&pci_bus_res[bus].io_avail, addr, size);
761 		}
762 		break;
763 	case PB_MEM:
764 		if (pci_bus_res[res_bus].mem_avail == NULL)
765 			break;
766 		addr = memlist_find(&pci_bus_res[res_bus].mem_avail,
767 		    size, align);
768 		if (addr > 0) {
769 			memlist_insert(&pci_bus_res[res_bus].mem_used,
770 			    addr, size);
771 			(void) memlist_remove(&pci_bus_res[res_bus].pmem_avail,
772 			    addr, size);
773 
774 			/* free the old resource */
775 			memlist_free_all(&pci_bus_res[bus].mem_avail);
776 			memlist_free_all(&pci_bus_res[bus].mem_used);
777 
778 			/* add the new resource */
779 			memlist_insert(&pci_bus_res[bus].mem_avail, addr, size);
780 		}
781 		break;
782 	case PB_PMEM:
783 		if (pci_bus_res[res_bus].pmem_avail == NULL)
784 			break;
785 		addr = memlist_find(&pci_bus_res[res_bus].pmem_avail,
786 		    size, align);
787 		if (addr > 0) {
788 			memlist_insert(&pci_bus_res[res_bus].pmem_used,
789 			    addr, size);
790 			(void) memlist_remove(&pci_bus_res[res_bus].mem_avail,
791 			    addr, size);
792 
793 			/* free the old resource */
794 			memlist_free_all(&pci_bus_res[bus].pmem_avail);
795 			memlist_free_all(&pci_bus_res[bus].pmem_used);
796 
797 			/* add the new resource */
798 			memlist_insert(&pci_bus_res[bus].pmem_avail,
799 			    addr, size);
800 		}
801 		break;
802 	}
803 
804 	return (addr);
805 }
806 
807 /*
808  * given a cap_id, return its cap_id location in config space
809  */
810 static int
get_pci_cap(uchar_t bus,uchar_t dev,uchar_t func,uint8_t cap_id)811 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
812 {
813 	uint8_t curcap, cap_id_loc;
814 	uint16_t status;
815 	int location = -1;
816 
817 	/*
818 	 * Need to check the Status register for ECP support first.
819 	 * Also please note that for type 1 devices, the
820 	 * offset could change. Should support type 1 next.
821 	 */
822 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
823 	if (!(status & PCI_STAT_CAP)) {
824 		return (-1);
825 	}
826 	cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
827 
828 	/* Walk the list of capabilities */
829 	while (cap_id_loc && cap_id_loc != (uint8_t)-1) {
830 		curcap = pci_getb(bus, dev, func, cap_id_loc);
831 
832 		if (curcap == cap_id) {
833 			location = cap_id_loc;
834 			break;
835 		}
836 		cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
837 	}
838 	return (location);
839 }
840 
841 /*
842  * Does this resource element live in the legacy VGA range?
843  */
844 
845 static boolean_t
is_vga(struct memlist * elem,enum io_mem io)846 is_vga(struct memlist *elem, enum io_mem io)
847 {
848 	if (io == IO) {
849 		if ((elem->ml_address == 0x3b0 && elem->ml_size == 0xc) ||
850 		    (elem->ml_address == 0x3c0 && elem->ml_size == 0x20))
851 			return (B_TRUE);
852 	} else {
853 		if (elem->ml_address == 0xa0000 && elem->ml_size == 0x20000)
854 			return (B_TRUE);
855 	}
856 	return (B_FALSE);
857 }
858 
859 /*
860  * Does this entire resource list consist only of legacy VGA resources?
861  */
862 
863 static boolean_t
list_is_vga_only(struct memlist * l,enum io_mem io)864 list_is_vga_only(struct memlist *l, enum io_mem io)
865 {
866 	if (l == NULL) {
867 		return (B_FALSE);
868 	}
869 
870 	do {
871 		if (!is_vga(l, io))
872 			return (B_FALSE);
873 	} while ((l = l->ml_next) != NULL);
874 	return (B_TRUE);
875 }
876 
877 /*
878  * Find the start and end addresses that cover the range for all list entries,
879  * excluding legacy VGA addresses. Relies on the list being sorted.
880  */
881 static void
pci_memlist_range(struct memlist * list,enum io_mem iomem,uint64_t * basep,uint64_t * limitp)882 pci_memlist_range(struct memlist *list, enum io_mem iomem, uint64_t *basep,
883     uint64_t *limitp)
884 {
885 	*limitp = *basep = 0;
886 
887 	for (; list != NULL; list = list->ml_next) {
888 		if (is_vga(list, iomem))
889 			continue;
890 
891 		if (*basep == 0)
892 			*basep = list->ml_address;
893 
894 		if (list->ml_address + list->ml_size >= *limitp)
895 			*limitp = list->ml_address + list->ml_size - 1;
896 	}
897 }
898 
899 /*
900  * Assign valid resources to unconfigured pci(e) bridges. We are trying
901  * to reprogram the bridge when its
902  *		i)   SECBUS == SUBBUS	||
903  *		ii)  IOBASE > IOLIM	||
904  *		iii) MEMBASE > MEMLIM && PMEMBASE > PMEMLIM
905  * This must be done after one full pass through the PCI tree to collect
906  * all BIOS-configured resources, so that we know what resources are
907  * free and available to assign to the unconfigured PPBs.
908  */
909 static void
fix_ppb_res(uchar_t secbus,boolean_t prog_sub)910 fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
911 {
912 	uchar_t bus, dev, func;
913 	uchar_t parbus, subbus;
914 	uint_t io_base, io_limit, mem_base;
915 	uint_t io_size, io_align;
916 	uint64_t mem_size, mem_align, mem_limit;
917 	uint64_t pmem_size, pmem_base, pmem_limit;
918 	uint64_t addr = 0;
919 	int *regp = NULL;
920 	uint_t val, reglen;
921 	int rv, cap_ptr, physhi;
922 	dev_info_t *dip;
923 	uint16_t cmd_reg;
924 	struct memlist *scratch_list;
925 	boolean_t reprogram_mem;
926 
927 	/* skip root (peer) PCI busses */
928 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
929 		return;
930 
931 	/* skip subtractive PPB when prog_sub is not TRUE */
932 	if (pci_bus_res[secbus].subtractive && !prog_sub)
933 		return;
934 
935 	/* some entries may be empty due to discontiguous bus numbering */
936 	dip = pci_bus_res[secbus].dip;
937 	if (dip == NULL)
938 		return;
939 
940 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
941 	    "reg", &regp, &reglen);
942 	if (rv != DDI_PROP_SUCCESS || reglen == 0)
943 		return;
944 	physhi = regp[0];
945 	ddi_prop_free(regp);
946 
947 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
948 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
949 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
950 
951 	dump_memlists("fix_ppb_res start bus", bus);
952 	dump_memlists("fix_ppb_res start secbus", secbus);
953 
954 	/*
955 	 * If pcie bridge, check to see if link is enabled
956 	 */
957 	cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
958 	if (cap_ptr != -1) {
959 		cmd_reg = pci_getw(bus, dev, func,
960 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
961 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
962 			dcmn_err(CE_NOTE,
963 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.",
964 			    bus, dev, func);
965 			return;
966 		}
967 	}
968 
969 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
970 	parbus = pci_bus_res[secbus].par_bus;
971 	ASSERT(parbus == bus);
972 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
973 
974 	/*
975 	 * If we have a Cardbus bridge, but no bus space
976 	 */
977 	if (pci_bus_res[secbus].num_cbb != 0 &&
978 	    pci_bus_res[secbus].bus_avail == NULL) {
979 		uchar_t range;
980 
981 		/* normally there are 2 buses under a cardbus bridge */
982 		range = pci_bus_res[secbus].num_cbb * 2;
983 
984 		/*
985 		 * Try to find and allocate a bus-range starting at subbus+1
986 		 * from the parent of the PPB.
987 		 */
988 		for (; range != 0; range--) {
989 			if (memlist_find_with_startaddr(
990 			    &pci_bus_res[parbus].bus_avail,
991 			    subbus + 1, range, 1) != 0)
992 				break; /* find bus range resource at parent */
993 		}
994 		if (range != 0) {
995 			memlist_insert(&pci_bus_res[secbus].bus_avail,
996 			    subbus + 1, range);
997 			subbus = subbus + range;
998 			pci_bus_res[secbus].sub_bus = subbus;
999 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
1000 			add_bus_range_prop(secbus);
1001 
1002 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
1003 			    "[%x/%x/%x]: %x ~ %x", bus, dev, func,
1004 			    secbus, subbus);
1005 		}
1006 	}
1007 
1008 	/*
1009 	 * Calculate required IO size and alignment
1010 	 * If bus io_size is zero, we are going to assign 512 bytes per bus,
1011 	 * otherwise, we'll choose the maximum value of such calculation and
1012 	 * bus io_size. The size needs to be 4K aligned.
1013 	 *
1014 	 * We calculate alignment as the largest power of two less than the
1015 	 * the sum of all children's IO size requirements, because this will
1016 	 * align to the size of the largest child request within that size
1017 	 * (which is always a power of two).
1018 	 */
1019 	io_size = (subbus - secbus + 1) * 0x200;
1020 	if (io_size <  pci_bus_res[secbus].io_size)
1021 		io_size = pci_bus_res[secbus].io_size;
1022 	io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT);
1023 	io_align = io_size;
1024 	P2LE(io_align);
1025 
1026 	/*
1027 	 * Calculate required MEM size and alignment
1028 	 * If bus mem_size is zero, we are going to assign 1M bytes per bus,
1029 	 * otherwise, we'll choose the maximum value of such calculation and
1030 	 * bus mem_size. The size needs to be 1M aligned.
1031 	 *
1032 	 * For the alignment, refer to the I/O comment above.
1033 	 */
1034 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
1035 	if (mem_size < pci_bus_res[secbus].mem_size) {
1036 		mem_size = pci_bus_res[secbus].mem_size;
1037 		mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT);
1038 	}
1039 	mem_align = mem_size;
1040 	P2LE(mem_align);
1041 
1042 	/* Subtractive bridge */
1043 	if (pci_bus_res[secbus].subtractive && prog_sub) {
1044 		/*
1045 		 * We program an arbitrary amount of I/O and memory resource
1046 		 * for the subtractive bridge so that child dynamic-resource-
1047 		 * allocating devices (such as Cardbus bridges) have a chance
1048 		 * of success.  Until we have full-tree resource rebalancing,
1049 		 * dynamic resource allocation (thru busra) only looks at the
1050 		 * parent bridge, so all PPBs must have some allocatable
1051 		 * resource.  For non-subtractive bridges, the resources come
1052 		 * from the base/limit register "windows", but subtractive
1053 		 * bridges often don't program those (since they don't need to).
1054 		 * If we put all the remaining resources on the subtractive
1055 		 * bridge, then peer non-subtractive bridges can't allocate
1056 		 * more space (even though this is probably most correct).
1057 		 * If we put the resources only on the parent, then allocations
1058 		 * from children of subtractive bridges will fail without
1059 		 * special-case code for bypassing the subtractive bridge.
1060 		 * This solution is the middle-ground temporary solution until
1061 		 * we have fully-capable resource allocation.
1062 		 */
1063 
1064 		/*
1065 		 * Add an arbitrary I/O resource to the subtractive PPB
1066 		 */
1067 		if (pci_bus_res[secbus].io_avail == NULL) {
1068 			addr = get_parbus_res(parbus, secbus, io_size,
1069 			    io_align, PB_IO);
1070 			if (addr) {
1071 				add_ranges_prop(secbus, 1);
1072 				pci_bus_res[secbus].io_reprogram =
1073 				    pci_bus_res[parbus].io_reprogram;
1074 
1075 				cmn_err(CE_NOTE, "!add io-range on subtractive"
1076 				    " ppb[%x/%x/%x]: "
1077 				    "0x%"PRIx64" ~ 0x%"PRIx64"",
1078 				    bus, dev, func, addr, addr + io_size - 1);
1079 			}
1080 		}
1081 		/*
1082 		 * Add an arbitrary memory resource to the subtractive PPB
1083 		 */
1084 		if (pci_bus_res[secbus].mem_avail == NULL) {
1085 			addr = get_parbus_res(parbus, secbus, mem_size,
1086 			    mem_align, PB_MEM);
1087 			if (addr) {
1088 				add_ranges_prop(secbus, 1);
1089 				pci_bus_res[secbus].mem_reprogram =
1090 				    pci_bus_res[parbus].mem_reprogram;
1091 
1092 				cmn_err(CE_NOTE, "!add mem-range on "
1093 				    "subtractive ppb[%x/%x/%x]: "
1094 				    "0x%"PRIx64" ~ 0x%"PRIx64"",
1095 				    bus, dev, func,
1096 				    addr, addr + mem_size - 1);
1097 			}
1098 		}
1099 
1100 		goto cmd_enable;
1101 	}
1102 
1103 	/*
1104 	 * Check to see if we need to reprogram I/O space, either because the
1105 	 * parent bus needed reprogramming and so do we, or because I/O space is
1106 	 * disabled in base/limit or command register.
1107 	 */
1108 	val = io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
1109 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
1110 	io_base = (io_base & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT;
1111 	io_limit = ((io_limit & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 0xfff;
1112 	if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) {
1113 		uint16_t io_base_hi, io_limit_hi;
1114 		io_base_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI);
1115 		io_limit_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI);
1116 
1117 		io_base |= (uint_t)io_base_hi << 16;
1118 		io_limit |= (uint_t)io_limit_hi << 16;
1119 	}
1120 
1121 	/* Form list of all resources passed (avail + used) */
1122 	scratch_list = memlist_dup(pci_bus_res[secbus].io_avail);
1123 	memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list);
1124 
1125 	if ((pci_bus_res[parbus].io_reprogram ||
1126 	    (io_base > io_limit) ||
1127 	    (!(cmd_reg & PCI_COMM_IO))) &&
1128 	    !list_is_vga_only(scratch_list, IO)) {
1129 
1130 		if (pci_bus_res[secbus].io_used) {
1131 			memlist_subsume(&pci_bus_res[secbus].io_used,
1132 			    &pci_bus_res[secbus].io_avail);
1133 		}
1134 
1135 		if (pci_bus_res[secbus].io_avail &&
1136 		    !pci_bus_res[parbus].io_reprogram &&
1137 		    !pci_bus_res[parbus].subtractive) {
1138 			/* re-choose old io ports info */
1139 
1140 			uint64_t base, limit;
1141 
1142 			pci_memlist_range(pci_bus_res[secbus].io_avail,
1143 			    IO, &base, &limit);
1144 			io_base = (uint_t)base;
1145 			io_limit = (uint_t)limit;
1146 
1147 			/* 4K aligned */
1148 			io_base = P2ALIGN(base, PPB_IO_ALIGNMENT);
1149 			io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1;
1150 			io_size = io_limit - io_base + 1;
1151 			ASSERT(io_base <= io_limit);
1152 			memlist_free_all(&pci_bus_res[secbus].io_avail);
1153 			memlist_insert(&pci_bus_res[secbus].io_avail,
1154 			    io_base, io_size);
1155 			memlist_insert(&pci_bus_res[parbus].io_used,
1156 			    io_base, io_size);
1157 			(void) memlist_remove(&pci_bus_res[parbus].io_avail,
1158 			    io_base, io_size);
1159 			pci_bus_res[secbus].io_reprogram = B_TRUE;
1160 		} else {
1161 			/* get new io ports from parent bus */
1162 			addr = get_parbus_res(parbus, secbus, io_size,
1163 			    io_align, PB_IO);
1164 			if (addr) {
1165 				io_base = addr;
1166 				io_limit = addr + io_size - 1;
1167 				pci_bus_res[secbus].io_reprogram = B_TRUE;
1168 			}
1169 		}
1170 		if (pci_bus_res[secbus].io_reprogram) {
1171 			/* reprogram PPB regs */
1172 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
1173 			    (uchar_t)((io_base>>8) & 0xf0));
1174 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
1175 			    (uchar_t)((io_limit>>8) & 0xf0));
1176 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
1177 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
1178 			add_ranges_prop(secbus, 1);
1179 
1180 			cmn_err(CE_NOTE, "!reprogram io-range on"
1181 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x",
1182 			    bus, dev, func, io_base, io_limit);
1183 		}
1184 	}
1185 	memlist_free_all(&scratch_list);
1186 
1187 	/*
1188 	 * Check memory space as we did I/O space.
1189 	 */
1190 
1191 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
1192 	mem_base = (mem_base & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT;
1193 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
1194 	mem_limit = ((mem_limit & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT)
1195 	    | 0xfffff;
1196 
1197 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
1198 	pmem_limit = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) |
1199 	    0xfffff;
1200 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
1201 	pmem_base = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT);
1202 
1203 	if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) {
1204 		uint32_t pf_addr_hi, pf_limit_hi;
1205 
1206 		pf_addr_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH);
1207 		pf_limit_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH);
1208 		pmem_base |= (uint64_t)pf_addr_hi << 32;
1209 		pmem_limit |= (uint64_t)pf_limit_hi << 32;
1210 	}
1211 
1212 	/*
1213 	 * Reprogram memory if any of:
1214 	 *
1215 	 *	- The parent bus is flagged for reprogramming;
1216 	 *	- Mem space is currently disabled in the command register;
1217 	 *	- Both mem and pmem space are disabled via base/limit.
1218 	 *
1219 	 * Always reprogram both mem and pmem together since this leaves
1220 	 * resources in the 'avail' list for add_reg_props() to subsequently
1221 	 * find and assign.
1222 	 */
1223 	reprogram_mem = pci_bus_res[parbus].mem_reprogram ||
1224 	    !(cmd_reg & PCI_COMM_MAE) ||
1225 	    (mem_base > mem_limit && pmem_base > pmem_limit);
1226 
1227 	scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail);
1228 	memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list);
1229 
1230 	if (reprogram_mem && !list_is_vga_only(scratch_list, MEM)) {
1231 
1232 		if (pci_bus_res[secbus].mem_used) {
1233 			memlist_subsume(&pci_bus_res[secbus].mem_used,
1234 			    &pci_bus_res[secbus].mem_avail);
1235 		}
1236 
1237 		/*
1238 		 * At this point, if the parent bus has not been
1239 		 * reprogrammed and there is memory in this bus' available
1240 		 * pool, then it can just be re-used. Otherwise a new range
1241 		 * is requested from the parent bus - note that
1242 		 * get_parbus_res() also takes care of constructing new
1243 		 * avail and used lists for the bus.
1244 		 *
1245 		 * For a subtractive parent bus, always request a fresh
1246 		 * memory range.
1247 		 */
1248 		if (pci_bus_res[secbus].mem_avail &&
1249 		    !pci_bus_res[parbus].mem_reprogram &&
1250 		    !pci_bus_res[parbus].subtractive) {
1251 			/* re-choose old mem resource */
1252 
1253 			uint64_t base;
1254 
1255 			pci_memlist_range(pci_bus_res[secbus].mem_avail,
1256 			    MEM, &base, &mem_limit);
1257 			mem_base = (uint_t)base;
1258 
1259 			mem_base = P2ALIGN(mem_base, PPB_MEM_ALIGNMENT);
1260 			mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1;
1261 			mem_size = mem_limit + 1 - mem_base;
1262 			ASSERT(mem_base <= mem_limit);
1263 			memlist_free_all(&pci_bus_res[secbus].mem_avail);
1264 			memlist_insert(&pci_bus_res[secbus].mem_avail,
1265 			    mem_base, mem_size);
1266 			memlist_insert(&pci_bus_res[parbus].mem_used,
1267 			    mem_base, mem_size);
1268 			(void) memlist_remove(&pci_bus_res[parbus].mem_avail,
1269 			    mem_base, mem_size);
1270 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
1271 		} else {
1272 			/* get new mem resource from parent bus */
1273 			addr = get_parbus_res(parbus, secbus, mem_size,
1274 			    mem_align, PB_MEM);
1275 			if (addr) {
1276 				mem_base = addr;
1277 				mem_limit = addr + mem_size - 1;
1278 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
1279 			}
1280 		}
1281 	}
1282 	memlist_free_all(&scratch_list);
1283 
1284 	/* Prefetch memory */
1285 
1286 	scratch_list = memlist_dup(pci_bus_res[secbus].pmem_avail);
1287 	memlist_merge(&pci_bus_res[secbus].pmem_used, &scratch_list);
1288 
1289 	/*
1290 	 * Only reprogram prefetchable memory If the MEM access bit is
1291 	 * currently enabled. If it is not, then prefetchable memory will be
1292 	 * disabled anyway via base/limit below.
1293 	 */
1294 	if (reprogram_mem && !list_is_vga_only(scratch_list, MEM) &&
1295 	    (cmd_reg & PCI_COMM_MAE)) {
1296 
1297 		if (pci_bus_res[secbus].pmem_used) {
1298 			memlist_subsume(&pci_bus_res[secbus].pmem_used,
1299 			    &pci_bus_res[secbus].pmem_avail);
1300 		}
1301 
1302 		/* Same logic as for non-prefetch memory, see above */
1303 		if (pci_bus_res[secbus].pmem_avail &&
1304 		    !pci_bus_res[parbus].mem_reprogram &&
1305 		    !pci_bus_res[parbus].subtractive) {
1306 			/* re-choose old mem resource */
1307 
1308 			pci_memlist_range(pci_bus_res[secbus].pmem_avail,
1309 			    MEM, &pmem_base, &pmem_limit);
1310 
1311 			pmem_base = P2ALIGN(pmem_base, PPB_MEM_ALIGNMENT);
1312 			pmem_limit = P2ROUNDUP(pmem_limit,
1313 			    PPB_MEM_ALIGNMENT) - 1;
1314 			pmem_size = pmem_limit + 1 - pmem_base;
1315 			ASSERT(pmem_base <= pmem_limit);
1316 			memlist_free_all(&pci_bus_res[secbus].pmem_avail);
1317 			memlist_insert(&pci_bus_res[secbus].pmem_avail,
1318 			    pmem_base, pmem_size);
1319 			memlist_insert(&pci_bus_res[parbus].pmem_used,
1320 			    pmem_base, pmem_size);
1321 			(void) memlist_remove(&pci_bus_res[parbus].pmem_avail,
1322 			    pmem_base, pmem_size);
1323 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
1324 		} else {
1325 			/* get new mem resource from parent bus */
1326 			addr = get_parbus_res(parbus, secbus, mem_size,
1327 			    mem_align, PB_PMEM);
1328 			if (addr) {
1329 				pmem_base = addr;
1330 				pmem_limit = addr + mem_size - 1;
1331 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
1332 			}
1333 		}
1334 	}
1335 
1336 	memlist_free_all(&scratch_list);
1337 
1338 	if (pci_bus_res[secbus].mem_reprogram) {
1339 		/* reprogram PPB MEM regs */
1340 
1341 		pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
1342 		    (uint16_t)((mem_base >> PCI_BCNF_MEM_SHIFT) &
1343 		    PCI_BCNF_MEM_MASK));
1344 		pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
1345 		    (uint16_t)((mem_limit >> PCI_BCNF_MEM_SHIFT) &
1346 		    PCI_BCNF_MEM_MASK));
1347 
1348 		cmn_err(CE_NOTE, "!reprogram mem-range on"
1349 		    " ppb[%x/%x/%x]: 0x%x ~ 0x%"PRIx64"",
1350 		    bus, dev, func, mem_base, mem_limit);
1351 
1352 		if (!(cmd_reg & PCI_COMM_MAE)) {
1353 			/*
1354 			 * If the MEM access bit is initially disabled by BIOS,
1355 			 * we disable the PMEM window manually by setting PMEM
1356 			 * base > PMEM limit here, in case there are incorrect
1357 			 * values in them from BIOS, so that we won't get in
1358 			 * trouble once the MEM access bit is enabled at the
1359 			 * end of this function.
1360 			 */
1361 			pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 0xfff0);
1362 			pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 0x0);
1363 			pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH,
1364 			    0xffffffff);
1365 			pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 0x0);
1366 
1367 		} else {
1368 
1369 			pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW,
1370 			    ((pmem_base & 0xffffffff) >> PCI_BCNF_MEM_SHIFT) &
1371 			    PCI_BCNF_MEM_MASK);
1372 			pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH,
1373 			    pmem_base >> 32);
1374 
1375 			pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW,
1376 			    ((pmem_limit & 0xffffffff) >> PCI_BCNF_MEM_SHIFT) &
1377 			    PCI_BCNF_MEM_MASK);
1378 			pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH,
1379 			    pmem_limit >> 32);
1380 
1381 			cmn_err(CE_NOTE, "!reprogram pmem-range on"
1382 			    " ppb[%x/%x/%x]: 0x%"PRIx64" ~ 0x%"PRIx64"",
1383 			    bus, dev, func, pmem_base, pmem_limit);
1384 		}
1385 
1386 		add_ranges_prop(secbus, 1);
1387 	}
1388 
1389 cmd_enable:
1390 	dump_memlists("fix_ppb_res end bus", bus);
1391 	dump_memlists("fix_ppb_res end secbus", secbus);
1392 
1393 	if (pci_bus_res[secbus].io_avail)
1394 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
1395 	if (pci_bus_res[secbus].mem_avail)
1396 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
1397 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
1398 }
1399 
1400 void
pci_reprogram(void)1401 pci_reprogram(void)
1402 {
1403 	int i, pci_reconfig = 1;
1404 	char *onoff;
1405 	int bus;
1406 
1407 	/*
1408 	 * Ask platform code for all of the root complexes it knows about in
1409 	 * case we have missed anything in the scan. This is to ensure that we
1410 	 * have them show up in the devinfo tree. This scan should find any
1411 	 * existing entries as well. After this, go through each bus and
1412 	 * ask the platform if it wants to change the name of the slot.
1413 	 */
1414 	pci_prd_root_complex_iter(pci_rc_scan_cb, NULL);
1415 	for (bus = 0; bus <= pci_boot_maxbus; bus++) {
1416 		pci_prd_slot_name(bus, pci_bus_res[bus].dip);
1417 	}
1418 	pci_unitaddr_cache_init();
1419 
1420 	/*
1421 	 * Fix-up unit-address assignments if cache is available
1422 	 */
1423 	if (pci_unitaddr_cache_valid()) {
1424 		int pci_regs[] = {0, 0, 0};
1425 		int	new_addr;
1426 		int	index = 0;
1427 
1428 		for (bus = 0; bus <= pci_boot_maxbus; bus++) {
1429 			/* skip non-root (peer) PCI busses */
1430 			if ((pci_bus_res[bus].par_bus != (uchar_t)-1) ||
1431 			    (pci_bus_res[bus].dip == NULL))
1432 				continue;
1433 
1434 			new_addr = pci_bus_unitaddr(index);
1435 			if (pci_bus_res[bus].root_addr != new_addr) {
1436 				/* update reg property for node */
1437 				pci_regs[0] = pci_bus_res[bus].root_addr =
1438 				    new_addr;
1439 				(void) ndi_prop_update_int_array(
1440 				    DDI_DEV_T_NONE, pci_bus_res[bus].dip,
1441 				    "reg", (int *)pci_regs, 3);
1442 			}
1443 			index++;
1444 		}
1445 	} else {
1446 		/* perform legacy processing */
1447 		pci_unitaddr_cache_create();
1448 	}
1449 
1450 	/*
1451 	 * Do root-bus resource discovery
1452 	 */
1453 	for (bus = 0; bus <= pci_boot_maxbus; bus++) {
1454 		/* skip non-root (peer) PCI busses */
1455 		if (pci_bus_res[bus].par_bus != (uchar_t)-1)
1456 			continue;
1457 
1458 		/*
1459 		 * 1. find resources associated with this root bus
1460 		 */
1461 		populate_bus_res(bus);
1462 
1463 
1464 		/*
1465 		 * 2. Remove used PCI and ISA resources from bus resource map
1466 		 */
1467 
1468 		memlist_remove_list(&pci_bus_res[bus].io_avail,
1469 		    pci_bus_res[bus].io_used);
1470 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1471 		    pci_bus_res[bus].mem_used);
1472 		memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1473 		    pci_bus_res[bus].pmem_used);
1474 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1475 		    pci_bus_res[bus].pmem_used);
1476 		memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1477 		    pci_bus_res[bus].mem_used);
1478 
1479 		memlist_remove_list(&pci_bus_res[bus].io_avail,
1480 		    isa_res.io_used);
1481 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1482 		    isa_res.mem_used);
1483 
1484 		/*
1485 		 * 3. Exclude <1M address range here in case below reserved
1486 		 * ranges for BIOS data area, ROM area etc are wrongly reported
1487 		 * in ACPI resource producer entries for PCI root bus.
1488 		 *	00000000 - 000003FF	RAM
1489 		 *	00000400 - 000004FF	BIOS data area
1490 		 *	00000500 - 0009FFFF	RAM
1491 		 *	000A0000 - 000BFFFF	VGA RAM
1492 		 *	000C0000 - 000FFFFF	ROM area
1493 		 */
1494 		(void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000);
1495 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
1496 		    0, 0x100000);
1497 	}
1498 
1499 	memlist_free_all(&isa_res.io_used);
1500 	memlist_free_all(&isa_res.mem_used);
1501 
1502 	/* add bus-range property for root/peer bus nodes */
1503 	for (i = 0; i <= pci_boot_maxbus; i++) {
1504 		/* create bus-range property on root/peer buses */
1505 		if (pci_bus_res[i].par_bus == (uchar_t)-1)
1506 			add_bus_range_prop(i);
1507 
1508 		/* setup bus range resource on each bus */
1509 		setup_bus_res(i);
1510 	}
1511 
1512 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
1513 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
1514 		if (strcmp(onoff, "off") == 0) {
1515 			pci_reconfig = 0;
1516 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
1517 		}
1518 		ddi_prop_free(onoff);
1519 	}
1520 
1521 	remove_subtractive_res();
1522 
1523 	/* reprogram the non-subtractive PPB */
1524 	if (pci_reconfig)
1525 		for (i = 0; i <= pci_boot_maxbus; i++)
1526 			fix_ppb_res(i, B_FALSE);
1527 
1528 	for (i = 0; i <= pci_boot_maxbus; i++) {
1529 		/* configure devices not configured by BIOS */
1530 		if (pci_reconfig) {
1531 			/*
1532 			 * Reprogram the subtractive PPB. At this time, all its
1533 			 * siblings should have got their resources already.
1534 			 */
1535 			if (pci_bus_res[i].subtractive)
1536 				fix_ppb_res(i, B_TRUE);
1537 			enumerate_bus_devs(i, CONFIG_NEW);
1538 		}
1539 	}
1540 
1541 	/* All dev programmed, so we can create available prop */
1542 	for (i = 0; i <= pci_boot_maxbus; i++)
1543 		add_bus_available_prop(i);
1544 }
1545 
1546 /*
1547  * populate bus resources
1548  */
1549 static void
populate_bus_res(uchar_t bus)1550 populate_bus_res(uchar_t bus)
1551 {
1552 
1553 	/* scan BIOS structures */
1554 	pci_bus_res[bus].pmem_avail = pci_prd_find_resource(bus,
1555 	    PCI_PRD_R_PREFETCH);
1556 	pci_bus_res[bus].mem_avail = pci_prd_find_resource(bus, PCI_PRD_R_MMIO);
1557 	pci_bus_res[bus].io_avail = pci_prd_find_resource(bus, PCI_PRD_R_IO);
1558 	pci_bus_res[bus].bus_avail = pci_prd_find_resource(bus, PCI_PRD_R_BUS);
1559 
1560 	/*
1561 	 * attempt to initialize sub_bus from the largest range-end
1562 	 * in the bus_avail list
1563 	 */
1564 	if (pci_bus_res[bus].bus_avail != NULL) {
1565 		struct memlist *entry;
1566 		int current;
1567 
1568 		entry = pci_bus_res[bus].bus_avail;
1569 		while (entry != NULL) {
1570 			current = entry->ml_address + entry->ml_size - 1;
1571 			if (current > pci_bus_res[bus].sub_bus)
1572 				pci_bus_res[bus].sub_bus = current;
1573 			entry = entry->ml_next;
1574 		}
1575 	}
1576 
1577 	if (bus == 0) {
1578 		/*
1579 		 * Special treatment of bus 0:
1580 		 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy
1581 		 * pcimem from boot and make I/O space the entire range
1582 		 * starting at 0x100.
1583 		 */
1584 		if (pci_bus_res[0].mem_avail == NULL)
1585 			pci_bus_res[0].mem_avail =
1586 			    memlist_dup(bootops->boot_mem->pcimem);
1587 		/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
1588 		if (pci_bus_res[0].io_avail == NULL)
1589 			memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff);
1590 	}
1591 
1592 	/*
1593 	 * Create 'ranges' property here before any resources are
1594 	 * removed from the resource lists
1595 	 */
1596 	add_ranges_prop(bus, 0);
1597 }
1598 
1599 /*
1600  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
1601  */
1602 static void
create_root_bus_dip(uchar_t bus)1603 create_root_bus_dip(uchar_t bus)
1604 {
1605 	int pci_regs[] = {0, 0, 0};
1606 	dev_info_t *dip;
1607 
1608 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
1609 
1610 	num_root_bus++;
1611 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
1612 	    (pnode_t)DEVI_SID_NODEID, &dip);
1613 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1614 	    "#address-cells", 3);
1615 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1616 	    "#size-cells", 2);
1617 	pci_regs[0] = pci_bus_res[bus].root_addr;
1618 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1619 	    "reg", (int *)pci_regs, 3);
1620 
1621 	/*
1622 	 * If system has PCIe bus, then create different properties
1623 	 */
1624 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
1625 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1626 		    "device_type", "pci");
1627 
1628 	(void) ndi_devi_bind_driver(dip, 0);
1629 	pci_bus_res[bus].dip = dip;
1630 }
1631 
1632 /*
1633  * For any fixed configuration (often compatability) pci devices
1634  * and those with their own expansion rom, create device nodes
1635  * to hold the already configured device details.
1636  */
1637 void
enumerate_bus_devs(uchar_t bus,int config_op)1638 enumerate_bus_devs(uchar_t bus, int config_op)
1639 {
1640 	uchar_t dev, func, nfunc, header;
1641 	ushort_t venid;
1642 	struct pci_devfunc *devlist = NULL, *entry;
1643 
1644 	if (pci_debug_bus_start == -1 || bus_debug(bus)) {
1645 		if (config_op == CONFIG_NEW) {
1646 			dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1647 		} else if (config_op == CONFIG_FIX) {
1648 			dcmn_err(CE_NOTE,
1649 			    "fixing devices on pci bus 0x%x", bus);
1650 		} else {
1651 			dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1652 		}
1653 	}
1654 
1655 	if (config_op == CONFIG_NEW) {
1656 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1657 		while (devlist) {
1658 			entry = devlist;
1659 			devlist = entry->next;
1660 			if (entry->reprogram ||
1661 			    pci_bus_res[bus].io_reprogram ||
1662 			    pci_bus_res[bus].mem_reprogram) {
1663 				/* reprogram device(s) */
1664 				(void) add_reg_props(entry->dip, bus,
1665 				    entry->dev, entry->func, CONFIG_NEW, 0);
1666 			}
1667 			kmem_free(entry, sizeof (*entry));
1668 		}
1669 		pci_bus_res[bus].privdata = NULL;
1670 		return;
1671 	}
1672 
1673 	for (dev = 0; dev < max_dev_pci; dev++) {
1674 		nfunc = 1;
1675 		for (func = 0; func < nfunc; func++) {
1676 
1677 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1678 
1679 			if ((venid == 0xffff) || (venid == 0)) {
1680 				/* no function at this address */
1681 				continue;
1682 			}
1683 
1684 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1685 			if (header == 0xff) {
1686 				continue; /* illegal value */
1687 			}
1688 
1689 			/*
1690 			 * according to some mail from Microsoft posted
1691 			 * to the pci-drivers alias, their only requirement
1692 			 * for a multifunction device is for the 1st
1693 			 * function to have to PCI_HEADER_MULTI bit set.
1694 			 */
1695 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
1696 				nfunc = 8;
1697 			}
1698 
1699 			if (config_op == CONFIG_FIX ||
1700 			    config_op == CONFIG_INFO) {
1701 				/*
1702 				 * Create the node, unconditionally, on the
1703 				 * first pass only.  It may still need
1704 				 * resource assignment, which will be
1705 				 * done on the second, CONFIG_NEW, pass.
1706 				 */
1707 				process_devfunc(bus, dev, func, header,
1708 				    venid, config_op);
1709 
1710 			}
1711 		}
1712 	}
1713 
1714 	/* percolate bus used resources up through parents to root */
1715 	if (config_op == CONFIG_INFO) {
1716 		int	par_bus;
1717 
1718 		par_bus = pci_bus_res[bus].par_bus;
1719 		while (par_bus != (uchar_t)-1) {
1720 			pci_bus_res[par_bus].io_size +=
1721 			    pci_bus_res[bus].io_size;
1722 			pci_bus_res[par_bus].mem_size +=
1723 			    pci_bus_res[bus].mem_size;
1724 
1725 			if (pci_bus_res[bus].io_used)
1726 				memlist_merge(&pci_bus_res[bus].io_used,
1727 				    &pci_bus_res[par_bus].io_used);
1728 
1729 			if (pci_bus_res[bus].mem_used)
1730 				memlist_merge(&pci_bus_res[bus].mem_used,
1731 				    &pci_bus_res[par_bus].mem_used);
1732 
1733 			if (pci_bus_res[bus].pmem_used)
1734 				memlist_merge(&pci_bus_res[bus].pmem_used,
1735 				    &pci_bus_res[par_bus].pmem_used);
1736 
1737 			bus = par_bus;
1738 			par_bus = pci_bus_res[par_bus].par_bus;
1739 		}
1740 	}
1741 }
1742 
1743 /*
1744  * As a workaround for devices which is_pciide() (below, which see) would not
1745  * match due to device issues, check an undocumented device tree property
1746  * 'pci-ide', the value of which is a 1275 device identifier.
1747  *
1748  * Should a device matching this (in normal 'compatible' order) be found, and
1749  * the device not otherwise bound, it will be have its node name changed to
1750  * 'pci-ide' so the pci-ide driver will attach.
1751  *
1752  * This can be set via `eeprom pci-ide=pciXXXX,YYYY` (see eeprom(8)) or
1753  * otherwise added to bootenv.rc.
1754  */
1755 static int
check_pciide_prop(uchar_t revid,ushort_t venid,ushort_t devid,ushort_t subvenid,ushort_t subdevid)1756 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
1757     ushort_t subvenid, ushort_t subdevid)
1758 {
1759 	static int prop_exist = -1;
1760 	static char *pciide_str;
1761 	char compat[32];
1762 
1763 	if (prop_exist == -1) {
1764 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
1765 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
1766 		    &pciide_str) == DDI_SUCCESS);
1767 	}
1768 
1769 	if (!prop_exist)
1770 		return (0);
1771 
1772 	/* compare property value against various forms of compatible */
1773 	if (subvenid) {
1774 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
1775 		    venid, devid, subvenid, subdevid, revid);
1776 		if (strcmp(pciide_str, compat) == 0)
1777 			return (1);
1778 
1779 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
1780 		    venid, devid, subvenid, subdevid);
1781 		if (strcmp(pciide_str, compat) == 0)
1782 			return (1);
1783 
1784 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
1785 		    subvenid, subdevid);
1786 		if (strcmp(pciide_str, compat) == 0)
1787 			return (1);
1788 	}
1789 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
1790 	    venid, devid, revid);
1791 	if (strcmp(pciide_str, compat) == 0)
1792 		return (1);
1793 
1794 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
1795 	if (strcmp(pciide_str, compat) == 0)
1796 		return (1);
1797 
1798 	return (0);
1799 }
1800 
1801 static int
is_pciide(uchar_t basecl,uchar_t subcl,uchar_t revid,ushort_t venid,ushort_t devid,ushort_t subvenid,ushort_t subdevid)1802 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
1803     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
1804 {
1805 	struct ide_table {
1806 		ushort_t venid;
1807 		ushort_t devid;
1808 	} *entry;
1809 
1810 	/*
1811 	 * Devices which need to be matched specially as pci-ide because of
1812 	 * various device issues.  Commonly their specification as being
1813 	 * PCI_MASS_OTHER or PCI_MASS_SATA despite our using them in ATA mode.
1814 	 */
1815 	static struct ide_table ide_other[] = {
1816 		{0x1095, 0x3112}, /* Silicon Image 3112 SATALink/SATARaid */
1817 		{0x1095, 0x3114}, /* Silicon Image 3114 SATALink/SATARaid */
1818 		{0x1095, 0x3512}, /* Silicon Image 3512 SATALink/SATARaid */
1819 		{0x1095, 0x680},  /* Silicon Image PCI0680 Ultra ATA-133 */
1820 		{0x1283, 0x8211}, /* Integrated Technology Express 8211F */
1821 		{0, 0}
1822 	};
1823 
1824 	if (basecl != PCI_CLASS_MASS)
1825 		return (0);
1826 
1827 	if (subcl == PCI_MASS_IDE) {
1828 		return (1);
1829 	}
1830 
1831 	if (check_pciide_prop(revid, venid, devid, subvenid, subdevid))
1832 		return (1);
1833 
1834 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
1835 		return (0);
1836 	}
1837 
1838 	entry = &ide_other[0];
1839 	while (entry->venid != 0) {
1840 		if (entry->venid == venid && entry->devid == devid)
1841 			return (1);
1842 		entry++;
1843 	}
1844 	return (0);
1845 }
1846 
1847 static int
is_display(uint_t classcode)1848 is_display(uint_t classcode)
1849 {
1850 	static uint_t disp_classes[] = {
1851 		0x000100,	/* pre-class code VGA Compatible */
1852 		0x030000,	/* VGA Compatible */
1853 		0x030001	/* VGA+8514 Compatible */
1854 	};
1855 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
1856 
1857 	for (i = 0; i < nclasses; i++) {
1858 		if (classcode == disp_classes[i])
1859 			return (1);
1860 	}
1861 	return (0);
1862 }
1863 
1864 static void
add_undofix_entry(uint8_t bus,uint8_t dev,uint8_t fn,void (* undofn)(uint8_t,uint8_t,uint8_t))1865 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1866     void (*undofn)(uint8_t, uint8_t, uint8_t))
1867 {
1868 	struct pci_fixundo *newundo;
1869 
1870 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1871 
1872 	/*
1873 	 * Adding an item to this list means that we must turn its NMIENABLE
1874 	 * bit back on at a later time.
1875 	 */
1876 	newundo->bus = bus;
1877 	newundo->dev = dev;
1878 	newundo->fn = fn;
1879 	newundo->undofn = undofn;
1880 	newundo->next = undolist;
1881 
1882 	/* add to the undo list in LIFO order */
1883 	undolist = newundo;
1884 }
1885 
1886 void
add_pci_fixes(void)1887 add_pci_fixes(void)
1888 {
1889 	int i;
1890 
1891 	for (i = 0; i <= pci_boot_maxbus; i++) {
1892 		/*
1893 		 * For each bus, apply needed fixes to the appropriate devices.
1894 		 * This must be done before the main enumeration loop because
1895 		 * some fixes must be applied to devices normally encountered
1896 		 * later in the pci scan (e.g. if a fix to device 7 must be
1897 		 * applied before scanning device 6, applying fixes in the
1898 		 * normal enumeration loop would obviously be too late).
1899 		 */
1900 		enumerate_bus_devs(i, CONFIG_FIX);
1901 	}
1902 }
1903 
1904 void
undo_pci_fixes(void)1905 undo_pci_fixes(void)
1906 {
1907 	struct pci_fixundo *nextundo;
1908 	uint8_t bus, dev, fn;
1909 
1910 	/*
1911 	 * All fixes in the undo list are performed unconditionally.  Future
1912 	 * fixes may require selective undo.
1913 	 */
1914 	while (undolist != NULL) {
1915 
1916 		bus = undolist->bus;
1917 		dev = undolist->dev;
1918 		fn = undolist->fn;
1919 
1920 		(*(undolist->undofn))(bus, dev, fn);
1921 
1922 		nextundo = undolist->next;
1923 		kmem_free(undolist, sizeof (struct pci_fixundo));
1924 		undolist = nextundo;
1925 	}
1926 }
1927 
1928 static void
undo_amd8111_pci_fix(uint8_t bus,uint8_t dev,uint8_t fn)1929 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1930 {
1931 	uint8_t val8;
1932 
1933 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1934 	/*
1935 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1936 	 * to handle more critical PCI errors (e.g. PERR#).
1937 	 */
1938 	val8 |= AMD8111_ENABLENMI;
1939 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1940 }
1941 
1942 static void
pci_fix_amd8111(uint8_t bus,uint8_t dev,uint8_t fn)1943 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1944 {
1945 	uint8_t val8;
1946 
1947 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1948 
1949 	if ((val8 & AMD8111_ENABLENMI) == 0)
1950 		return;
1951 
1952 	/*
1953 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1954 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1955 	 * which sometimes prevents all devices from being enumerated.
1956 	 */
1957 	val8 &= ~AMD8111_ENABLENMI;
1958 
1959 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1960 
1961 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1962 }
1963 
1964 static void
set_devpm_d0(uchar_t bus,uchar_t dev,uchar_t func)1965 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1966 {
1967 	uint16_t status;
1968 	uint8_t header;
1969 	uint8_t cap_ptr;
1970 	uint8_t cap_id;
1971 	uint16_t pmcsr;
1972 
1973 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1974 	if (!(status & PCI_STAT_CAP))
1975 		return;	/* No capabilities list */
1976 
1977 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1978 	if (header == PCI_HEADER_CARDBUS)
1979 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR);
1980 	else
1981 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1982 	/*
1983 	 * Walk the capabilities list searching for a PM entry.
1984 	 */
1985 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1986 		cap_ptr &= PCI_CAP_PTR_MASK;
1987 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1988 		if (cap_id == PCI_CAP_ID_PM) {
1989 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1990 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1991 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1992 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1993 			break;
1994 		}
1995 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1996 	}
1997 
1998 }
1999 
2000 #define	is_isa(bc, sc)	\
2001 	(((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA))
2002 
2003 static void
process_devfunc(uchar_t bus,uchar_t dev,uchar_t func,uchar_t header,ushort_t vendorid,int config_op)2004 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
2005     ushort_t vendorid, int config_op)
2006 {
2007 	char nodename[32], unitaddr[5];
2008 	dev_info_t *dip;
2009 	uchar_t basecl, subcl, progcl, intr, revid;
2010 	ushort_t subvenid, subdevid, status;
2011 	ushort_t slot_num;
2012 	uint_t classcode, revclass;
2013 	int reprogram = 0, pciide = 0;
2014 	int power[2] = {1, 1};
2015 	int pciex = 0;
2016 	ushort_t is_pci_bridge = 0;
2017 	struct pci_devfunc *devlist = NULL, *entry = NULL;
2018 	boolean_t slot_valid;
2019 	gfx_entry_t *gfxp;
2020 	pcie_req_id_t bdf;
2021 
2022 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
2023 
2024 	switch (header & PCI_HEADER_TYPE_M) {
2025 	case PCI_HEADER_ZERO:
2026 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
2027 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
2028 		break;
2029 	case PCI_HEADER_CARDBUS:
2030 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
2031 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
2032 		/* Record the # of cardbus bridges found on the bus */
2033 		if (config_op == CONFIG_INFO)
2034 			pci_bus_res[bus].num_cbb++;
2035 		break;
2036 	default:
2037 		subvenid = 0;
2038 		subdevid = 0;
2039 		break;
2040 	}
2041 
2042 	if (config_op == CONFIG_FIX) {
2043 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
2044 			pci_fix_amd8111(bus, dev, func);
2045 		}
2046 		return;
2047 	}
2048 
2049 	/* XXX should be use generic names? derive from class? */
2050 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
2051 	classcode = revclass >> 8;
2052 	revid = revclass & 0xff;
2053 
2054 	/* figure out if this is pci-ide */
2055 	basecl = classcode >> 16;
2056 	subcl = (classcode >> 8) & 0xff;
2057 	progcl = classcode & 0xff;
2058 
2059 
2060 	if (is_display(classcode))
2061 		(void) snprintf(nodename, sizeof (nodename), "display");
2062 	else if (!pseudo_isa && is_isa(basecl, subcl))
2063 		(void) snprintf(nodename, sizeof (nodename), "isa");
2064 	else if (subvenid != 0)
2065 		(void) snprintf(nodename, sizeof (nodename),
2066 		    "pci%x,%x", subvenid, subdevid);
2067 	else
2068 		(void) snprintf(nodename, sizeof (nodename),
2069 		    "pci%x,%x", vendorid, deviceid);
2070 
2071 	/* make sure parent bus dip has been created */
2072 	if (pci_bus_res[bus].dip == NULL)
2073 		create_root_bus_dip(bus);
2074 
2075 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
2076 	    DEVI_SID_NODEID, &dip);
2077 
2078 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid,
2079 	    &slot_num, &is_pci_bridge) == B_TRUE)
2080 		pciex = 1;
2081 
2082 	bdf = PCI_GETBDF(bus, dev, func);
2083 	/*
2084 	 * Record BAD AMD bridges which don't support MMIO config access.
2085 	 */
2086 	if (IS_BAD_AMD_NTBRIDGE(vendorid, deviceid) ||
2087 	    IS_AMD_8132_CHIP(vendorid, deviceid)) {
2088 		uchar_t secbus = 0;
2089 		uchar_t subbus = 0;
2090 
2091 		if ((basecl == PCI_CLASS_BRIDGE) &&
2092 		    (subcl == PCI_BRIDGE_PCI)) {
2093 			secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2094 			subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2095 		}
2096 		pci_cfgacc_add_workaround(bdf, secbus, subbus);
2097 	}
2098 
2099 	/*
2100 	 * Only populate bus_t if this device is sitting under a PCIE root
2101 	 * complex.  Some particular machines have both a PCIE root complex and
2102 	 * a PCI hostbridge, in which case only devices under the PCIE root
2103 	 * complex will have their bus_t populated.
2104 	 */
2105 	if (pcie_get_rc_dip(dip) != NULL) {
2106 		ck804_fix_aer_ptr(dip, bdf);
2107 		(void) pcie_init_bus(dip, bdf, PCIE_BUS_INITIAL);
2108 	}
2109 
2110 	/* add properties */
2111 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
2112 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
2113 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
2114 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2115 	    "class-code", classcode);
2116 	if (func == 0)
2117 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
2118 	else
2119 		(void) snprintf(unitaddr, sizeof (unitaddr),
2120 		    "%x,%x", dev, func);
2121 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2122 	    "unit-address", unitaddr);
2123 
2124 	/* add device_type for display nodes */
2125 	if (is_display(classcode)) {
2126 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2127 		    "device_type", "display");
2128 	}
2129 	/* add special stuff for header type */
2130 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
2131 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
2132 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
2133 
2134 		if (subvenid != 0) {
2135 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2136 			    "subsystem-id", subdevid);
2137 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2138 			    "subsystem-vendor-id", subvenid);
2139 		}
2140 		if (!pciex)
2141 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2142 			    "min-grant", mingrant);
2143 		if (!pciex)
2144 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2145 			    "max-latency", maxlatency);
2146 	}
2147 
2148 	/* interrupt, record if not 0 */
2149 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
2150 	if (intr != 0)
2151 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2152 		    "interrupts", intr);
2153 
2154 	/*
2155 	 * Add support for 133 mhz pci eventually
2156 	 */
2157 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
2158 
2159 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2160 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
2161 	if (!pciex && (status & PCI_STAT_FBBC))
2162 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
2163 		    "fast-back-to-back");
2164 	if (!pciex && (status & PCI_STAT_66MHZ))
2165 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
2166 		    "66mhz-capable");
2167 	if (status & PCI_STAT_UDF)
2168 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
2169 		    "udf-supported");
2170 	if (pciex && slot_valid) {
2171 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2172 		    "physical-slot#", slot_num);
2173 		if (!is_pci_bridge)
2174 			pciex_slot_names_prop(dip, slot_num);
2175 	}
2176 
2177 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2178 	    "power-consumption", power, 2);
2179 
2180 	/* Set the device PM state to D0 */
2181 	set_devpm_d0(bus, dev, func);
2182 
2183 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
2184 		add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
2185 	else {
2186 		/*
2187 		 * Record the non-PPB devices on the bus for possible
2188 		 * reprogramming at 2nd bus enumeration.
2189 		 * Note: PPB reprogramming is done in fix_ppb_res()
2190 		 */
2191 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
2192 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
2193 		entry->dip = dip;
2194 		entry->dev = dev;
2195 		entry->func = func;
2196 		entry->next = devlist;
2197 		pci_bus_res[bus].privdata = entry;
2198 	}
2199 
2200 	if (IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
2201 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
2202 	}
2203 
2204 	/* check for NVIDIA CK8-04/MCP55 based LPC bridge */
2205 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
2206 	    (func == 0)) {
2207 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
2208 		/* each LPC bridge has an integrated IOAPIC */
2209 		apic_nvidia_io_max++;
2210 	}
2211 
2212 	if (pciex && is_pci_bridge)
2213 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2214 		    (char *)"PCIe-PCI bridge");
2215 	else
2216 		add_model_prop(dip, classcode);
2217 
2218 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
2219 	    revid, classcode, pciex);
2220 
2221 	/*
2222 	 * See if this device is a controller that advertises
2223 	 * itself to be a standard ATA task file controller, or one that
2224 	 * has been hard coded.
2225 	 *
2226 	 * If it is, check if any other higher precedence driver listed in
2227 	 * driver_aliases will claim the node by calling
2228 	 * ddi_compatible_driver_major.  If so, clear pciide and do not
2229 	 * create a pci-ide node or any other special handling.
2230 	 *
2231 	 * If another driver does not bind, set the node name to pci-ide
2232 	 * and then let the special pci-ide handling for registers and
2233 	 * child pci-ide nodes proceed below.
2234 	 */
2235 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
2236 	    subvenid, subdevid) == 1) {
2237 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
2238 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
2239 			pciide = 1;
2240 		}
2241 	}
2242 
2243 	DEVI_SET_PCI(dip);
2244 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
2245 	(void) ndi_devi_bind_driver(dip, 0);
2246 
2247 	/* special handling for pci-ide */
2248 	if (pciide) {
2249 		dev_info_t *cdip;
2250 
2251 		/*
2252 		 * Create properties specified by P1275 Working Group
2253 		 * Proposal #414 Version 1
2254 		 */
2255 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2256 		    "device_type", "pci-ide");
2257 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2258 		    "#address-cells", 1);
2259 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2260 		    "#size-cells", 0);
2261 
2262 		/* allocate two child nodes */
2263 		ndi_devi_alloc_sleep(dip, "ide",
2264 		    (pnode_t)DEVI_SID_NODEID, &cdip);
2265 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
2266 		    "reg", 0);
2267 		(void) ndi_devi_bind_driver(cdip, 0);
2268 		ndi_devi_alloc_sleep(dip, "ide",
2269 		    (pnode_t)DEVI_SID_NODEID, &cdip);
2270 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
2271 		    "reg", 1);
2272 		(void) ndi_devi_bind_driver(cdip, 0);
2273 
2274 		reprogram = 0;	/* don't reprogram pci-ide bridge */
2275 	}
2276 
2277 	if (is_display(classcode)) {
2278 		gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP);
2279 		gfxp->g_dip = dip;
2280 		gfxp->g_prev = NULL;
2281 		gfxp->g_next = gfx_devinfo_list;
2282 		gfx_devinfo_list = gfxp;
2283 		if (gfxp->g_next)
2284 			gfxp->g_next->g_prev = gfxp;
2285 	}
2286 
2287 	/* special handling for isa */
2288 	if (!pseudo_isa && is_isa(basecl, subcl)) {
2289 		/* add device_type */
2290 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2291 		    "device_type", "isa");
2292 	}
2293 
2294 	if (reprogram && (entry != NULL))
2295 		entry->reprogram = B_TRUE;
2296 
2297 }
2298 
2299 /*
2300  * Some vendors do not use unique subsystem IDs in their products, which
2301  * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate.
2302  * Allow for these compatible forms to be excluded on a per-device basis.
2303  */
2304 /*ARGSUSED*/
2305 static boolean_t
subsys_compat_exclude(ushort_t venid,ushort_t devid,ushort_t subvenid,ushort_t subdevid,uchar_t revid,uint_t classcode)2306 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid,
2307     ushort_t subdevid, uchar_t revid, uint_t classcode)
2308 {
2309 	/* Nvidia display adapters */
2310 	if ((venid == 0x10de) && (is_display(classcode)))
2311 		return (B_TRUE);
2312 
2313 	/*
2314 	 * 8086,166 is the Ivy Bridge built-in graphics controller on some
2315 	 * models. Unfortunately 8086,2044 is the Skylake Server processor
2316 	 * memory channel device. The Ivy Bridge device uses the Skylake
2317 	 * ID as its sub-device ID. The GPU is not a memory controller DIMM
2318 	 * channel.
2319 	 */
2320 	if (venid == 0x8086 && devid == 0x166 && subvenid == 0x8086 &&
2321 	    subdevid == 0x2044) {
2322 		return (B_TRUE);
2323 	}
2324 
2325 	return (B_FALSE);
2326 }
2327 
2328 /*
2329  * Set the compatible property to a value compliant with rev 2.1 of the IEEE1275
2330  * PCI binding. This is also used for PCI express devices and we have our own
2331  * minor additions.
2332  *
2333  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
2334  *   pciVVVV,DDDD.SSSS.ssss	(1)
2335  *   pciSSSS,ssss,s		(2+)
2336  *   pciSSSS,ssss		(2)
2337  *   pciVVVV,DDDD.RR		(3)
2338  *   pciVVVV,DDDD,p		(4+)
2339  *   pciVVVV,DDDD		(4)
2340  *   pciclass,CCSSPP		(5)
2341  *   pciclass,CCSS		(6)
2342  *
2343  * The Subsystem (SSSS) forms are not inserted if subsystem-vendor-id is 0 or if
2344  * it is a case where we know that the IDs overlap.
2345  *
2346  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above and
2347  * property 2 is not created as per "1275 bindings for PCI Express
2348  * Interconnect".
2349  *
2350  * Unlike on SPARC, we generate both the "pciex" and "pci" versions of the
2351  * above. The problem with property 2 is that it has an ambiguity with
2352  * property 4. To make sure that drivers can specify either form of 2 or 4
2353  * without ambiguity we add a suffix. The 'p' suffix represents the primary ID,
2354  * meaning that it is guaranteed to be form 4. The 's' suffix means that it is
2355  * sub-vendor and sub-device form, meaning it is guaranteed to be form 2.
2356  *
2357  * Set with setprop and \x00 between each to generate the encoded string array
2358  * form.
2359  */
2360 void
add_compatible(dev_info_t * dip,ushort_t subvenid,ushort_t subdevid,ushort_t vendorid,ushort_t deviceid,uchar_t revid,uint_t classcode,int pciex)2361 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
2362     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
2363     int pciex)
2364 {
2365 	int i = 0;
2366 	int size = COMPAT_BUFSIZE;
2367 	char *compat[15];
2368 	char *buf, *curr;
2369 
2370 	curr = buf = kmem_alloc(size, KM_SLEEP);
2371 
2372 	if (pciex) {
2373 		if (subvenid) {
2374 			compat[i++] = curr;	/* form 0 */
2375 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
2376 			    vendorid, deviceid, subvenid, subdevid, revid);
2377 			size -= strlen(curr) + 1;
2378 			curr += strlen(curr) + 1;
2379 
2380 			compat[i++] = curr;	/* form 1 */
2381 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
2382 			    vendorid, deviceid, subvenid, subdevid);
2383 			size -= strlen(curr) + 1;
2384 			curr += strlen(curr) + 1;
2385 
2386 		}
2387 		compat[i++] = curr;	/* form 3 */
2388 		(void) snprintf(curr, size, "pciex%x,%x.%x",
2389 		    vendorid, deviceid, revid);
2390 		size -= strlen(curr) + 1;
2391 		curr += strlen(curr) + 1;
2392 
2393 		compat[i++] = curr;	/* form 4 */
2394 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
2395 		size -= strlen(curr) + 1;
2396 		curr += strlen(curr) + 1;
2397 
2398 		compat[i++] = curr;	/* form 5 */
2399 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
2400 		size -= strlen(curr) + 1;
2401 		curr += strlen(curr) + 1;
2402 
2403 		compat[i++] = curr;	/* form 6 */
2404 		(void) snprintf(curr, size, "pciexclass,%04x",
2405 		    (classcode >> 8));
2406 		size -= strlen(curr) + 1;
2407 		curr += strlen(curr) + 1;
2408 	}
2409 
2410 	if (subvenid) {
2411 		compat[i++] = curr;	/* form 0 */
2412 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
2413 		    vendorid, deviceid, subvenid, subdevid, revid);
2414 		size -= strlen(curr) + 1;
2415 		curr += strlen(curr) + 1;
2416 
2417 		compat[i++] = curr;	/* form 1 */
2418 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
2419 		    vendorid, deviceid, subvenid, subdevid);
2420 		size -= strlen(curr) + 1;
2421 		curr += strlen(curr) + 1;
2422 
2423 		if (subsys_compat_exclude(vendorid, deviceid, subvenid,
2424 		    subdevid, revid, classcode) == B_FALSE) {
2425 			compat[i++] = curr;	/* form 2+ */
2426 			(void) snprintf(curr, size, "pci%x,%x,s", subvenid,
2427 			    subdevid);
2428 			size -= strlen(curr) + 1;
2429 			curr += strlen(curr) + 1;
2430 
2431 			compat[i++] = curr;	/* form 2 */
2432 			(void) snprintf(curr, size, "pci%x,%x", subvenid,
2433 			    subdevid);
2434 			size -= strlen(curr) + 1;
2435 			curr += strlen(curr) + 1;
2436 		}
2437 	}
2438 	compat[i++] = curr;	/* form 3 */
2439 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
2440 	size -= strlen(curr) + 1;
2441 	curr += strlen(curr) + 1;
2442 
2443 	compat[i++] = curr;	/* form 4+ */
2444 	(void) snprintf(curr, size, "pci%x,%x,p", vendorid, deviceid);
2445 	size -= strlen(curr) + 1;
2446 	curr += strlen(curr) + 1;
2447 
2448 	compat[i++] = curr;	/* form 4 */
2449 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
2450 	size -= strlen(curr) + 1;
2451 	curr += strlen(curr) + 1;
2452 
2453 	compat[i++] = curr;	/* form 5 */
2454 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
2455 	size -= strlen(curr) + 1;
2456 	curr += strlen(curr) + 1;
2457 
2458 	compat[i++] = curr;	/* form 6 */
2459 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
2460 	size -= strlen(curr) + 1;
2461 	curr += strlen(curr) + 1;
2462 
2463 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
2464 	    "compatible", compat, i);
2465 	kmem_free(buf, COMPAT_BUFSIZE);
2466 }
2467 
2468 /*
2469  * Adjust the reg properties for a dual channel PCI-IDE device.
2470  *
2471  * NOTE: don't do anything that changes the order of the hard-decodes
2472  * and programmed BARs. The kernel driver depends on these values
2473  * being in this order regardless of whether they're for a 'native'
2474  * mode BAR or not.
2475  */
2476 /*
2477  * config info for pci-ide devices
2478  */
2479 static struct {
2480 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
2481 	uchar_t  bar_offset;	/* offset for alt status register */
2482 	ushort_t addr;		/* compatibility mode base address */
2483 	ushort_t length;	/* number of ports for this BAR */
2484 } pciide_bar[] = {
2485 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
2486 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
2487 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
2488 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
2489 };
2490 
2491 static int
pciide_adjust_bar(uchar_t progcl,int index,uint_t * basep,uint_t * lenp)2492 pciide_adjust_bar(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
2493 {
2494 	int hard_decode = 0;
2495 
2496 	/*
2497 	 * Adjust the base and len for the BARs of the PCI-IDE
2498 	 * device's primary and secondary controllers. The first
2499 	 * two BARs are for the primary controller and the next
2500 	 * two BARs are for the secondary controller. The fifth
2501 	 * and sixth bars are never adjusted.
2502 	 */
2503 	if (index >= 0 && index <= 3) {
2504 		*lenp = pciide_bar[index].length;
2505 
2506 		if (progcl & pciide_bar[index].native_mask) {
2507 			*basep += pciide_bar[index].bar_offset;
2508 		} else {
2509 			*basep = pciide_bar[index].addr;
2510 			hard_decode = 1;
2511 		}
2512 	}
2513 
2514 	/*
2515 	 * if either base or len is zero make certain both are zero
2516 	 */
2517 	if (*basep == 0 || *lenp == 0) {
2518 		*basep = 0;
2519 		*lenp = 0;
2520 		hard_decode = 0;
2521 	}
2522 
2523 	return (hard_decode);
2524 }
2525 
2526 
2527 /*
2528  * Add the "reg" and "assigned-addresses" property
2529  */
2530 static int
add_reg_props(dev_info_t * dip,uchar_t bus,uchar_t dev,uchar_t func,int config_op,int pciide)2531 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2532     int config_op, int pciide)
2533 {
2534 	uchar_t baseclass, subclass, progclass, header;
2535 	ushort_t bar_sz;
2536 	uint64_t value = 0, fbase;
2537 	uint_t devloc;
2538 	uint_t base, base_hi, type;
2539 	ushort_t offset, end;
2540 	int max_basereg, j, reprogram = 0;
2541 	uint_t phys_hi;
2542 	struct memlist **io_avail, **io_used;
2543 	struct memlist **mem_avail, **mem_used;
2544 	struct memlist **pmem_avail, **pmem_used;
2545 	uchar_t res_bus;
2546 
2547 	pci_regspec_t regs[16] = {{0}};
2548 	pci_regspec_t assigned[15] = {{0}};
2549 	int nreg, nasgn;
2550 
2551 	io_avail = &pci_bus_res[bus].io_avail;
2552 	io_used = &pci_bus_res[bus].io_used;
2553 	mem_avail = &pci_bus_res[bus].mem_avail;
2554 	mem_used = &pci_bus_res[bus].mem_used;
2555 	pmem_avail = &pci_bus_res[bus].pmem_avail;
2556 	pmem_used = &pci_bus_res[bus].pmem_used;
2557 
2558 	dump_memlists("add_reg_props start", bus);
2559 
2560 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
2561 	regs[0].pci_phys_hi = devloc;
2562 	nreg = 1;	/* rest of regs[0] is all zero */
2563 	nasgn = 0;
2564 
2565 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
2566 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
2567 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2568 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
2569 
2570 	switch (header) {
2571 	case PCI_HEADER_ZERO:
2572 		max_basereg = PCI_BASE_NUM;
2573 		break;
2574 	case PCI_HEADER_PPB:
2575 		max_basereg = PCI_BCNF_BASE_NUM;
2576 		break;
2577 	case PCI_HEADER_CARDBUS:
2578 		max_basereg = PCI_CBUS_BASE_NUM;
2579 		reprogram = 1;
2580 		break;
2581 	default:
2582 		max_basereg = 0;
2583 		break;
2584 	}
2585 
2586 	/*
2587 	 * Create the register property by saving the current
2588 	 * value of the base register. Write 0xffffffff to the
2589 	 * base register.  Read the value back to determine the
2590 	 * required size of the address space.  Restore the base
2591 	 * register contents.
2592 	 *
2593 	 * Do not disable I/O and memory access for bridges; this
2594 	 * has the side-effect of making the bridge transparent to
2595 	 * secondary-bus activity (see sections 4.1-4.3 of the
2596 	 * PCI-PCI Bridge Spec V1.2).  For non-bridges, disable
2597 	 * I/O and memory access to avoid difficulty with USB
2598 	 * emulation (see OHCI spec1.0a appendix B
2599 	 * "Host Controller Mapping")
2600 	 */
2601 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
2602 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
2603 	    j++, offset += bar_sz) {
2604 		uint_t	command = 0;
2605 
2606 		/* determine the size of the address space */
2607 		base = pci_getl(bus, dev, func, offset);
2608 		if (baseclass != PCI_CLASS_BRIDGE) {
2609 			command = (uint_t)pci_getw(bus, dev, func,
2610 			    PCI_CONF_COMM);
2611 			pci_putw(bus, dev, func, PCI_CONF_COMM,
2612 			    command & ~(PCI_COMM_MAE | PCI_COMM_IO));
2613 		}
2614 		pci_putl(bus, dev, func, offset, 0xffffffff);
2615 		value = pci_getl(bus, dev, func, offset);
2616 		pci_putl(bus, dev, func, offset, base);
2617 		if (baseclass != PCI_CLASS_BRIDGE)
2618 			pci_putw(bus, dev, func, PCI_CONF_COMM, command);
2619 
2620 		/* construct phys hi,med.lo, size hi, lo */
2621 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
2622 			int hard_decode = 0;
2623 			uint_t len;
2624 
2625 			/* i/o space */
2626 			bar_sz = PCI_BAR_SZ_32;
2627 			value &= PCI_BASE_IO_ADDR_M;
2628 			len = ((value ^ (value-1)) + 1) >> 1;
2629 
2630 			/* XXX Adjust first 4 IDE registers */
2631 			if (pciide) {
2632 				if (subclass != PCI_MASS_IDE)
2633 					progclass = (PCI_IDE_IF_NATIVE_PRI |
2634 					    PCI_IDE_IF_NATIVE_SEC);
2635 				hard_decode = pciide_adjust_bar(progclass, j,
2636 				    &base, &len);
2637 			} else if (value == 0) {
2638 				/* skip base regs with size of 0 */
2639 				continue;
2640 			}
2641 
2642 			regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc |
2643 			    (hard_decode ? PCI_RELOCAT_B : offset);
2644 			regs[nreg].pci_phys_low = hard_decode ?
2645 			    base & PCI_BASE_IO_ADDR_M : 0;
2646 			assigned[nasgn].pci_phys_hi =
2647 			    PCI_RELOCAT_B | regs[nreg].pci_phys_hi;
2648 			regs[nreg].pci_size_low =
2649 			    assigned[nasgn].pci_size_low = len;
2650 			type = base & (~PCI_BASE_IO_ADDR_M);
2651 			base &= PCI_BASE_IO_ADDR_M;
2652 			/*
2653 			 * A device under a subtractive PPB can allocate
2654 			 * resources from its parent bus if there is no resource
2655 			 * available on its own bus.
2656 			 */
2657 			if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) {
2658 				res_bus = bus;
2659 				while (pci_bus_res[res_bus].subtractive) {
2660 					res_bus = pci_bus_res[res_bus].par_bus;
2661 					if (res_bus == (uchar_t)-1)
2662 						break; /* root bus already */
2663 					if (pci_bus_res[res_bus].io_avail) {
2664 						io_avail = &pci_bus_res
2665 						    [res_bus].io_avail;
2666 						break;
2667 					}
2668 				}
2669 			}
2670 
2671 			/*
2672 			 * first pass - gather what's there
2673 			 * update/second pass - adjust/allocate regions
2674 			 *	config - allocate regions
2675 			 */
2676 			if (config_op == CONFIG_INFO) {	/* first pass */
2677 				/* take out of the resource map of the bus */
2678 				if (base != 0) {
2679 					(void) memlist_remove(io_avail, base,
2680 					    len);
2681 					memlist_insert(io_used, base, len);
2682 				} else {
2683 					reprogram = 1;
2684 				}
2685 				pci_bus_res[bus].io_size += len;
2686 			} else if ((*io_avail && base == 0) ||
2687 			    pci_bus_res[bus].io_reprogram) {
2688 				base = (uint_t)memlist_find(io_avail, len, len);
2689 				if (base != 0) {
2690 					memlist_insert(io_used, base, len);
2691 					/* XXX need to worry about 64-bit? */
2692 					pci_putl(bus, dev, func, offset,
2693 					    base | type);
2694 					base = pci_getl(bus, dev, func, offset);
2695 					base &= PCI_BASE_IO_ADDR_M;
2696 				}
2697 				if (base == 0) {
2698 					cmn_err(CE_WARN, "failed to program"
2699 					    " IO space [%d/%d/%d] BAR@0x%x"
2700 					    " length 0x%x",
2701 					    bus, dev, func, offset, len);
2702 				}
2703 			}
2704 			assigned[nasgn].pci_phys_low = base;
2705 			nreg++, nasgn++;
2706 
2707 		} else {
2708 			uint64_t len;
2709 			/* memory space */
2710 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
2711 				bar_sz = PCI_BAR_SZ_64;
2712 				base_hi = pci_getl(bus, dev, func, offset + 4);
2713 				pci_putl(bus, dev, func, offset + 4,
2714 				    0xffffffff);
2715 				value |= (uint64_t)pci_getl(bus, dev, func,
2716 				    offset + 4) << 32;
2717 				pci_putl(bus, dev, func, offset + 4, base_hi);
2718 				phys_hi = PCI_ADDR_MEM64;
2719 				value &= PCI_BASE_M_ADDR64_M;
2720 			} else {
2721 				bar_sz = PCI_BAR_SZ_32;
2722 				base_hi = 0;
2723 				phys_hi = PCI_ADDR_MEM32;
2724 				value &= PCI_BASE_M_ADDR_M;
2725 			}
2726 
2727 			/* skip base regs with size of 0 */
2728 			if (value == 0)
2729 				continue;
2730 
2731 			len = ((value ^ (value-1)) + 1) >> 1;
2732 			regs[nreg].pci_size_low =
2733 			    assigned[nasgn].pci_size_low = len & 0xffffffff;
2734 			regs[nreg].pci_size_hi =
2735 			    assigned[nasgn].pci_size_hi = len >> 32;
2736 
2737 			phys_hi |= (devloc | offset);
2738 			if (base & PCI_BASE_PREF_M)
2739 				phys_hi |= PCI_PREFETCH_B;
2740 
2741 			/*
2742 			 * A device under a subtractive PPB can allocate
2743 			 * resources from its parent bus if there is no resource
2744 			 * available on its own bus.
2745 			 */
2746 			if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) {
2747 				res_bus = bus;
2748 				while (pci_bus_res[res_bus].subtractive) {
2749 					res_bus = pci_bus_res[res_bus].par_bus;
2750 					if (res_bus == (uchar_t)-1)
2751 						break; /* root bus already */
2752 					mem_avail =
2753 					    &pci_bus_res[res_bus].mem_avail;
2754 					pmem_avail =
2755 					    &pci_bus_res [res_bus].pmem_avail;
2756 					/*
2757 					 * Break out as long as at least
2758 					 * mem_avail is available
2759 					 */
2760 					if ((*pmem_avail &&
2761 					    (phys_hi & PCI_PREFETCH_B)) ||
2762 					    *mem_avail) {
2763 						break;
2764 					}
2765 				}
2766 			}
2767 
2768 			regs[nreg].pci_phys_hi =
2769 			    assigned[nasgn].pci_phys_hi = phys_hi;
2770 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2771 			type = base & ~PCI_BASE_M_ADDR_M;
2772 			base &= PCI_BASE_M_ADDR_M;
2773 
2774 			fbase = (((uint64_t)base_hi) << 32) | base;
2775 
2776 			if (config_op == CONFIG_INFO) {
2777 				/* take out of the resource map of the bus */
2778 				if (fbase != 0) {
2779 					/* remove from PMEM and MEM space */
2780 					(void) memlist_remove(mem_avail,
2781 					    fbase, len);
2782 					(void) memlist_remove(pmem_avail,
2783 					    fbase, len);
2784 					/* only note as used in correct map */
2785 					if (phys_hi & PCI_PREFETCH_B)
2786 						memlist_insert(pmem_used,
2787 						    fbase, len);
2788 					else
2789 						memlist_insert(mem_used,
2790 						    fbase, len);
2791 				} else {
2792 					reprogram = 1;
2793 				}
2794 				pci_bus_res[bus].mem_size += len;
2795 			} else if (pci_bus_res[bus].mem_reprogram ||
2796 			    (fbase == 0 &&
2797 			    (*mem_avail != NULL || *pmem_avail != NULL))) {
2798 
2799 				fbase = 0;
2800 
2801 				/*
2802 				 * When desired, attempt a prefetchable
2803 				 * allocation first
2804 				 */
2805 				if ((phys_hi & PCI_PREFETCH_B) &&
2806 				    *pmem_avail != NULL) {
2807 					fbase = memlist_find(pmem_avail,
2808 					    len, len);
2809 					if (fbase != 0) {
2810 						memlist_insert(pmem_used,
2811 						    fbase, len);
2812 						(void) memlist_remove(
2813 						    pmem_avail, fbase, len);
2814 						cmn_err(CE_NOTE, "!program "
2815 						    "[%x/%x/%x] BAR@0x%x"
2816 						    " 0x%lx length 0x%lx",
2817 						    bus, dev, func, offset,
2818 						    fbase, len);
2819 					}
2820 				}
2821 				/*
2822 				 * If prefetchable allocation was not
2823 				 * desired, or failed, attempt ordinary
2824 				 * memory allocation
2825 				 */
2826 				if (fbase == 0 && *mem_avail != NULL) {
2827 					fbase = memlist_find(mem_avail,
2828 					    len, len);
2829 					if (fbase != 0) {
2830 						memlist_insert(mem_used,
2831 						    fbase, len);
2832 						(void) memlist_remove(
2833 						    mem_avail, fbase, len);
2834 						cmn_err(CE_NOTE, "!program "
2835 						    "[%x/%x/%x] BAR@0x%x"
2836 						    " 0x%lx length 0x%lx",
2837 						    bus, dev, func, offset,
2838 						    fbase, len);
2839 					}
2840 				}
2841 
2842 				base_hi = fbase >> 32;
2843 				base = fbase & 0xffffffff;
2844 
2845 				if (fbase != 0) {
2846 					pci_putl(bus, dev, func, offset,
2847 					    base | type);
2848 					base = pci_getl(bus, dev, func, offset);
2849 
2850 					if (bar_sz == PCI_BAR_SZ_64) {
2851 						pci_putl(bus, dev, func,
2852 						    offset + 4, base_hi);
2853 						base_hi = pci_getl(bus, dev,
2854 						    func, offset + 4);
2855 					}
2856 
2857 					base &= PCI_BASE_M_ADDR_M;
2858 				} else {
2859 					cmn_err(CE_WARN, "failed to program "
2860 					    "mem space [%x/%x/%x] BAR@0x%x"
2861 					    " length 0x%"PRIx64,
2862 					    bus, dev, func, offset, len);
2863 				}
2864 			}
2865 
2866 			assigned[nasgn].pci_phys_mid = base_hi;
2867 			assigned[nasgn].pci_phys_low = base;
2868 
2869 			dcmn_err(CE_NOTE,
2870 			    "![%x/%x/%x] --- %08x.%x.%x.%x.%x",
2871 			    bus, dev, func,
2872 			    assigned[nasgn].pci_phys_hi,
2873 			    assigned[nasgn].pci_phys_mid,
2874 			    assigned[nasgn].pci_phys_low,
2875 			    assigned[nasgn].pci_size_hi,
2876 			    assigned[nasgn].pci_size_low);
2877 
2878 			nreg++, nasgn++;
2879 		}
2880 	}
2881 	switch (header) {
2882 	case PCI_HEADER_ZERO:
2883 		offset = PCI_CONF_ROM;
2884 		break;
2885 	case PCI_HEADER_PPB:
2886 		offset = PCI_BCNF_ROM;
2887 		break;
2888 	default: /* including PCI_HEADER_CARDBUS */
2889 		goto done;
2890 	}
2891 
2892 	/*
2893 	 * Add the expansion rom memory space
2894 	 * Determine the size of the ROM base reg; don't write reserved bits
2895 	 * ROM isn't in the PCI memory space.
2896 	 */
2897 	base = pci_getl(bus, dev, func, offset);
2898 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2899 	value = pci_getl(bus, dev, func, offset);
2900 	pci_putl(bus, dev, func, offset, base);
2901 	if (value & PCI_BASE_ROM_ENABLE)
2902 		value &= PCI_BASE_ROM_ADDR_M;
2903 	else
2904 		value = 0;
2905 
2906 	if (value != 0) {
2907 		uint_t len;
2908 
2909 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2910 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2911 		    PCI_ADDR_MEM32 | devloc) + offset;
2912 		base &= PCI_BASE_ROM_ADDR_M;
2913 		assigned[nasgn].pci_phys_low = base;
2914 		len = ((value ^ (value-1)) + 1) >> 1;
2915 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
2916 		nreg++, nasgn++;
2917 		/* take it out of the memory resource */
2918 		if (base != 0) {
2919 			(void) memlist_remove(mem_avail, base, len);
2920 			memlist_insert(mem_used, base, len);
2921 			pci_bus_res[bus].mem_size += len;
2922 		}
2923 	}
2924 
2925 	/*
2926 	 * Account for "legacy" (alias) video adapter resources
2927 	 */
2928 
2929 	/* add the three hard-decode, aliased address spaces for VGA */
2930 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
2931 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
2932 
2933 		/* VGA hard decode 0x3b0-0x3bb */
2934 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2935 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2936 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
2937 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
2938 		nreg++, nasgn++;
2939 		(void) memlist_remove(io_avail, 0x3b0, 0xc);
2940 		memlist_insert(io_used, 0x3b0, 0xc);
2941 		pci_bus_res[bus].io_size += 0xc;
2942 
2943 		/* VGA hard decode 0x3c0-0x3df */
2944 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2945 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2946 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
2947 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
2948 		nreg++, nasgn++;
2949 		(void) memlist_remove(io_avail, 0x3c0, 0x20);
2950 		memlist_insert(io_used, 0x3c0, 0x20);
2951 		pci_bus_res[bus].io_size += 0x20;
2952 
2953 		/* Video memory */
2954 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2955 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc);
2956 		regs[nreg].pci_phys_low =
2957 		    assigned[nasgn].pci_phys_low = 0xa0000;
2958 		regs[nreg].pci_size_low =
2959 		    assigned[nasgn].pci_size_low = 0x20000;
2960 		nreg++, nasgn++;
2961 		/* remove from MEM and PMEM space */
2962 		(void) memlist_remove(mem_avail, 0xa0000, 0x20000);
2963 		(void) memlist_remove(pmem_avail, 0xa0000, 0x20000);
2964 		memlist_insert(mem_used, 0xa0000, 0x20000);
2965 		pci_bus_res[bus].mem_size += 0x20000;
2966 	}
2967 
2968 	/* add the hard-decode, aliased address spaces for 8514 */
2969 	if ((baseclass == PCI_CLASS_DISPLAY) &&
2970 	    (subclass == PCI_DISPLAY_VGA) &&
2971 	    (progclass & PCI_DISPLAY_IF_8514)) {
2972 
2973 		/* hard decode 0x2e8 */
2974 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2975 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2976 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
2977 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
2978 		nreg++, nasgn++;
2979 		(void) memlist_remove(io_avail, 0x2e8, 0x1);
2980 		memlist_insert(io_used, 0x2e8, 0x1);
2981 		pci_bus_res[bus].io_size += 0x1;
2982 
2983 		/* hard decode 0x2ea-0x2ef */
2984 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2985 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2986 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
2987 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
2988 		nreg++, nasgn++;
2989 		(void) memlist_remove(io_avail, 0x2ea, 0x6);
2990 		memlist_insert(io_used, 0x2ea, 0x6);
2991 		pci_bus_res[bus].io_size += 0x6;
2992 	}
2993 
2994 done:
2995 	dump_memlists("add_reg_props end", bus);
2996 
2997 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
2998 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
2999 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
3000 	    "assigned-addresses",
3001 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
3002 
3003 	return (reprogram);
3004 }
3005 
3006 static void
add_ppb_props(dev_info_t * dip,uchar_t bus,uchar_t dev,uchar_t func,int pciex,ushort_t is_pci_bridge)3007 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
3008     int pciex, ushort_t is_pci_bridge)
3009 {
3010 	char *dev_type;
3011 	int i;
3012 	uint_t val;
3013 	uint64_t io_range[2], mem_range[2], pmem_range[2];
3014 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
3015 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
3016 	uchar_t progclass;
3017 
3018 	ASSERT(secbus <= subbus);
3019 
3020 	dump_memlists("add_ppb_props start bus", bus);
3021 	dump_memlists("add_ppb_props start secbus", secbus);
3022 
3023 	/*
3024 	 * Check if it's a subtractive PPB.
3025 	 */
3026 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
3027 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
3028 		pci_bus_res[secbus].subtractive = B_TRUE;
3029 
3030 	/*
3031 	 * Some BIOSes lie about max pci busses, we allow for
3032 	 * such mistakes here
3033 	 */
3034 	if (subbus > pci_boot_maxbus) {
3035 		pci_boot_maxbus = subbus;
3036 		alloc_res_array();
3037 	}
3038 
3039 	ASSERT(pci_bus_res[secbus].dip == NULL);
3040 	pci_bus_res[secbus].dip = dip;
3041 	pci_bus_res[secbus].par_bus = bus;
3042 
3043 	dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci";
3044 
3045 	/* setup bus number hierarchy */
3046 	pci_bus_res[secbus].sub_bus = subbus;
3047 	/*
3048 	 * Keep track of the largest subordinate bus number (this is essential
3049 	 * for peer busses because there is no other way of determining its
3050 	 * subordinate bus number).
3051 	 */
3052 	if (subbus > pci_bus_res[bus].sub_bus)
3053 		pci_bus_res[bus].sub_bus = subbus;
3054 	/*
3055 	 * Loop through subordinate busses, initializing their parent bus
3056 	 * field to this bridge's parent.  The subordinate busses' parent
3057 	 * fields may very well be further refined later, as child bridges
3058 	 * are enumerated.  (The value is to note that the subordinate busses
3059 	 * are not peer busses by changing their par_bus fields to anything
3060 	 * other than -1.)
3061 	 */
3062 	for (i = secbus + 1; i <= subbus; i++)
3063 		pci_bus_res[i].par_bus = bus;
3064 
3065 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
3066 	    "device_type", dev_type);
3067 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3068 	    "#address-cells", 3);
3069 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
3070 	    "#size-cells", 2);
3071 
3072 	/*
3073 	 * Collect bridge window specifications, and use them to populate
3074 	 * the "avail" resources for the bus.  Not all of those resources will
3075 	 * end up being available; this is done top-down, and so the initial
3076 	 * collection of windows populates the 'ranges' property for the
3077 	 * bus node.  Later, as children are found, resources are removed from
3078 	 * the 'avail' list, so that it becomes the freelist for
3079 	 * this point in the tree.  ranges may be set again after bridge
3080 	 * reprogramming in fix_ppb_res(), in which case it's set from
3081 	 * used + avail.
3082 	 *
3083 	 * According to PPB spec, the base register should be programmed
3084 	 * with a value bigger than the limit register when there are
3085 	 * no resources available. This applies to io, memory, and
3086 	 * prefetchable memory.
3087 	 */
3088 
3089 	/*
3090 	 * io range
3091 	 * We determine i/o windows that are left unconfigured by BIOS
3092 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
3093 	 * If it is unset, we disable i/o and mark it for reconfiguration in
3094 	 * later passes by setting the base > limit
3095 	 */
3096 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
3097 	if (val & PCI_COMM_IO) {
3098 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
3099 		io_range[1]  = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) |
3100 		    0xfff;
3101 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
3102 		io_range[0] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT);
3103 		if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) {
3104 			uint16_t io_base_hi, io_limit_hi;
3105 			io_base_hi = pci_getw(bus, dev, func,
3106 			    PCI_BCNF_IO_BASE_HI);
3107 			io_limit_hi = pci_getw(bus, dev, func,
3108 			    PCI_BCNF_IO_LIMIT_HI);
3109 
3110 			io_range[0] |= (uint32_t)io_base_hi << 16;
3111 			io_range[1] |= (uint32_t)io_limit_hi << 16;
3112 		}
3113 	} else {
3114 		io_range[0] = 0x9fff;
3115 		io_range[1] = 0x1000;
3116 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
3117 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
3118 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
3119 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
3120 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
3121 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
3122 	}
3123 
3124 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
3125 		memlist_insert(&pci_bus_res[secbus].io_avail,
3126 		    io_range[0], (io_range[1] - io_range[0] + 1));
3127 		memlist_insert(&pci_bus_res[bus].io_used,
3128 		    io_range[0], (io_range[1] - io_range[0] + 1));
3129 		if (pci_bus_res[bus].io_avail != NULL) {
3130 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
3131 			    io_range[0], (io_range[1] - io_range[0] + 1));
3132 		}
3133 		dcmn_err(CE_NOTE, "bus %x io-range: 0x%" PRIx64 "-%" PRIx64,
3134 		    secbus, io_range[0], io_range[1]);
3135 	}
3136 
3137 	/* mem range */
3138 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
3139 	mem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT);
3140 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
3141 	mem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) |
3142 	    0xfffff;
3143 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
3144 		memlist_insert(&pci_bus_res[secbus].mem_avail,
3145 		    mem_range[0], mem_range[1] - mem_range[0] + 1);
3146 		memlist_insert(&pci_bus_res[bus].mem_used,
3147 		    mem_range[0], mem_range[1] - mem_range[0] + 1);
3148 		/* remove from parent resource list */
3149 		(void) memlist_remove(&pci_bus_res[bus].mem_avail,
3150 		    mem_range[0], mem_range[1] - mem_range[0] + 1);
3151 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
3152 		    mem_range[0], mem_range[1] - mem_range[0] + 1);
3153 		dcmn_err(CE_NOTE, "bus %x mem-range: 0x%" PRIx64 "-%" PRIx64,
3154 		    secbus, mem_range[0], mem_range[1]);
3155 	}
3156 
3157 	/* prefetchable memory range */
3158 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
3159 	pmem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) |
3160 	    0xfffff;
3161 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
3162 	pmem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT);
3163 	if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) {
3164 		uint32_t pf_addr_hi, pf_limit_hi;
3165 		pf_addr_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH);
3166 		pf_limit_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH);
3167 		pmem_range[0] |= (uint64_t)pf_addr_hi << 32;
3168 		pmem_range[1] |= (uint64_t)pf_limit_hi << 32;
3169 	}
3170 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
3171 		memlist_insert(&pci_bus_res[secbus].pmem_avail,
3172 		    pmem_range[0], pmem_range[1] - pmem_range[0] + 1);
3173 		memlist_insert(&pci_bus_res[bus].pmem_used,
3174 		    pmem_range[0], pmem_range[1] - pmem_range[0] + 1);
3175 		/* remove from parent resource list */
3176 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
3177 		    pmem_range[0], pmem_range[1] - pmem_range[0] + 1);
3178 		(void) memlist_remove(&pci_bus_res[bus].mem_avail,
3179 		    pmem_range[0], pmem_range[1] - pmem_range[0] + 1);
3180 		dcmn_err(CE_NOTE, "bus %x pmem-range: 0x%" PRIx64 "-%" PRIx64,
3181 		    secbus, pmem_range[0], pmem_range[1]);
3182 	}
3183 
3184 	/*
3185 	 * Add VGA legacy resources to the bridge's pci_bus_res if it
3186 	 * has VGA_ENABLE set.  Note that we put them in 'avail',
3187 	 * because that's used to populate the ranges prop; they'll be
3188 	 * removed from there by the VGA device once it's found.  Also,
3189 	 * remove them from the parent's available list and note them as
3190 	 * used in the parent.
3191 	 */
3192 
3193 	if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) &
3194 	    PCI_BCNF_BCNTRL_VGA_ENABLE) {
3195 
3196 		memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc);
3197 
3198 		memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc);
3199 		if (pci_bus_res[bus].io_avail != NULL) {
3200 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
3201 			    0x3b0, 0xc);
3202 		}
3203 
3204 		memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20);
3205 
3206 		memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20);
3207 		if (pci_bus_res[bus].io_avail != NULL) {
3208 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
3209 			    0x3c0, 0x20);
3210 		}
3211 
3212 		memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000,
3213 		    0x20000);
3214 
3215 		memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000);
3216 		if (pci_bus_res[bus].mem_avail != NULL) {
3217 			(void) memlist_remove(&pci_bus_res[bus].mem_avail,
3218 			    0xa0000, 0x20000);
3219 		}
3220 	}
3221 	add_bus_range_prop(secbus);
3222 	add_ranges_prop(secbus, 1);
3223 
3224 	dump_memlists("add_ppb_props end bus", bus);
3225 	dump_memlists("add_ppb_props end secbus", secbus);
3226 }
3227 
3228 extern const struct pci_class_strings_s class_pci[];
3229 extern int class_pci_items;
3230 
3231 static void
add_model_prop(dev_info_t * dip,uint_t classcode)3232 add_model_prop(dev_info_t *dip, uint_t classcode)
3233 {
3234 	const char *desc;
3235 	int i;
3236 	uchar_t baseclass = classcode >> 16;
3237 	uchar_t subclass = (classcode >> 8) & 0xff;
3238 	uchar_t progclass = classcode & 0xff;
3239 
3240 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
3241 		desc = "IDE controller";
3242 	} else {
3243 		for (desc = 0, i = 0; i < class_pci_items; i++) {
3244 			if ((baseclass == class_pci[i].base_class) &&
3245 			    (subclass == class_pci[i].sub_class) &&
3246 			    (progclass == class_pci[i].prog_class)) {
3247 				desc = class_pci[i].actual_desc;
3248 				break;
3249 			}
3250 		}
3251 		if (i == class_pci_items)
3252 			desc = "Unknown class of pci/pnpbios device";
3253 	}
3254 
3255 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
3256 	    (char *)desc);
3257 }
3258