1*507c3241Smlf /* 2*507c3241Smlf * CDDL HEADER START 3*507c3241Smlf * 4*507c3241Smlf * The contents of this file are subject to the terms of the 5*507c3241Smlf * Common Development and Distribution License (the "License"). 6*507c3241Smlf * You may not use this file except in compliance with the License. 7*507c3241Smlf * 8*507c3241Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*507c3241Smlf * or http://www.opensolaris.org/os/licensing. 10*507c3241Smlf * See the License for the specific language governing permissions 11*507c3241Smlf * and limitations under the License. 12*507c3241Smlf * 13*507c3241Smlf * When distributing Covered Code, include this CDDL HEADER in each 14*507c3241Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*507c3241Smlf * If applicable, add the following below this CDDL HEADER, with the 16*507c3241Smlf * fields enclosed by brackets "[]" replaced with your own identifying 17*507c3241Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 18*507c3241Smlf * 19*507c3241Smlf * CDDL HEADER END 20*507c3241Smlf */ 21*507c3241Smlf 22*507c3241Smlf /* 23*507c3241Smlf * Copyright 1997 Sun Microsystems, Inc. All rights reserved. 24*507c3241Smlf * Use is subject to license terms. 25*507c3241Smlf */ 26*507c3241Smlf 27*507c3241Smlf #ifndef _ATA_FSM_H 28*507c3241Smlf #define _ATA_FSM_H 29*507c3241Smlf 30*507c3241Smlf #ifdef __cplusplus 31*507c3241Smlf extern "C" { 32*507c3241Smlf #endif 33*507c3241Smlf 34*507c3241Smlf 35*507c3241Smlf /* 36*507c3241Smlf * 37*507c3241Smlf * The interrupt reason can be interpreted from other bits as follows: 38*507c3241Smlf * 39*507c3241Smlf * IO CoD DRQ 40*507c3241Smlf * -- --- --- 41*507c3241Smlf * 0 0 1 == 1 Data to device 42*507c3241Smlf * 0 1 0 == 2 Idle 43*507c3241Smlf * 0 1 1 == 3 Send ATAPI CDB to device 44*507c3241Smlf * 1 0 1 == 5 Data from device 45*507c3241Smlf * 1 1 0 == 6 Status ready 46*507c3241Smlf * 1 1 1 == 7 Future use 47*507c3241Smlf * 48*507c3241Smlf */ 49*507c3241Smlf 50*507c3241Smlf /* 51*507c3241Smlf * This macro encodes the interrupt reason into a one byte 52*507c3241Smlf * event code which is used to index the FSM tables 53*507c3241Smlf */ 54*507c3241Smlf #define ATAPI_EVENT(drq, intr) \ 55*507c3241Smlf (((unsigned char)((drq) & ATS_DRQ) >> 3) \ 56*507c3241Smlf | (((intr) & (ATI_IO | ATI_COD)) << 1)) 57*507c3241Smlf 58*507c3241Smlf /* 59*507c3241Smlf * These are the names for the encoded ATAPI events 60*507c3241Smlf */ 61*507c3241Smlf #define ATAPI_EVENT_0 0 62*507c3241Smlf #define ATAPI_EVENT_IDLE ATAPI_EVENT(0, ATI_COD) 63*507c3241Smlf #define ATAPI_EVENT_2 2 64*507c3241Smlf #define ATAPI_EVENT_STATUS ATAPI_EVENT(0, ATI_IO | ATI_COD) 65*507c3241Smlf #define ATAPI_EVENT_PIO_OUT ATAPI_EVENT(ATS_DRQ, 0) 66*507c3241Smlf #define ATAPI_EVENT_CDB ATAPI_EVENT(ATS_DRQ, ATI_COD) 67*507c3241Smlf #define ATAPI_EVENT_PIO_IN ATAPI_EVENT(ATS_DRQ, ATI_IO) 68*507c3241Smlf #define ATAPI_EVENT_UNKNOWN ATAPI_EVENT(ATS_DRQ, (ATI_IO | ATI_COD)) 69*507c3241Smlf 70*507c3241Smlf #define ATAPI_NEVENTS 8 71*507c3241Smlf 72*507c3241Smlf /* 73*507c3241Smlf * Actions for the ATAPI PIO FSM 74*507c3241Smlf * 75*507c3241Smlf */ 76*507c3241Smlf 77*507c3241Smlf enum { 78*507c3241Smlf A_UNK, /* invalid event detected */ 79*507c3241Smlf A_NADA, /* do nothing */ 80*507c3241Smlf A_CDB, /* send the CDB */ 81*507c3241Smlf A_IN, /* transfer data out to the device */ 82*507c3241Smlf A_OUT, /* transfer data in from the device */ 83*507c3241Smlf A_IDLE, /* unexpected idle phase */ 84*507c3241Smlf A_RE, /* read the error code register */ 85*507c3241Smlf A_REX /* alternate read the error code register */ 86*507c3241Smlf }; 87*507c3241Smlf 88*507c3241Smlf /* 89*507c3241Smlf * States for the ATAPI PIO FSM 90*507c3241Smlf */ 91*507c3241Smlf 92*507c3241Smlf enum { 93*507c3241Smlf S_IDLE, /* idle or fatal error state */ 94*507c3241Smlf S_CMD, /* command byte sent */ 95*507c3241Smlf S_CDB, /* CDB sent */ 96*507c3241Smlf S_IN, /* transferring data in from device */ 97*507c3241Smlf S_OUT, /* transferring data out to device */ 98*507c3241Smlf S_DMA, /* dma transfer active */ 99*507c3241Smlf 100*507c3241Smlf ATAPI_NSTATES 101*507c3241Smlf }; 102*507c3241Smlf 103*507c3241Smlf #define S_X S_IDLE /* alias for idle */ 104*507c3241Smlf 105*507c3241Smlf /* 106*507c3241Smlf * controller and device functions 107*507c3241Smlf */ 108*507c3241Smlf enum { 109*507c3241Smlf ATA_FSM_START0, 110*507c3241Smlf ATA_FSM_START1, 111*507c3241Smlf ATA_FSM_INTR, 112*507c3241Smlf ATA_FSM_FINI, 113*507c3241Smlf ATA_FSM_RESET, 114*507c3241Smlf 115*507c3241Smlf ATA_CTLR_NFUNCS 116*507c3241Smlf }; 117*507c3241Smlf 118*507c3241Smlf 119*507c3241Smlf /* 120*507c3241Smlf * FSM return codes 121*507c3241Smlf */ 122*507c3241Smlf enum { 123*507c3241Smlf ATA_FSM_RC_OKAY, 124*507c3241Smlf ATA_FSM_RC_BUSY, 125*507c3241Smlf ATA_FSM_RC_INTR, 126*507c3241Smlf ATA_FSM_RC_FINI 127*507c3241Smlf }; 128*507c3241Smlf 129*507c3241Smlf /* 130*507c3241Smlf * states for the controller FSM 131*507c3241Smlf */ 132*507c3241Smlf enum { 133*507c3241Smlf AS_IDLE, 134*507c3241Smlf AS_ACTIVE0, 135*507c3241Smlf AS_ACTIVE1, 136*507c3241Smlf 137*507c3241Smlf ATA_CTLR_NSTATES 138*507c3241Smlf }; 139*507c3241Smlf 140*507c3241Smlf /* 141*507c3241Smlf * actions for the controller FSM 142*507c3241Smlf */ 143*507c3241Smlf enum { 144*507c3241Smlf AC_NADA, 145*507c3241Smlf AC_START, 146*507c3241Smlf AC_INTR, 147*507c3241Smlf AC_FINI, 148*507c3241Smlf AC_BUSY, 149*507c3241Smlf AC_RESET_I, 150*507c3241Smlf AC_RESET_A 151*507c3241Smlf }; 152*507c3241Smlf 153*507c3241Smlf #ifdef __cplusplus 154*507c3241Smlf } 155*507c3241Smlf #endif 156*507c3241Smlf 157*507c3241Smlf #endif /* _ATA_FSM_H */ 158