1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _ATA_COMMON_H 28 #define _ATA_COMMON_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/varargs.h> 37 38 #include <sys/scsi/scsi.h> 39 #include <sys/dktp/dadkio.h> 40 #include <sys/dktp/dadev.h> 41 #include <sys/dkio.h> 42 #include <sys/dktp/tgdk.h> 43 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 47 #include "ghd.h" 48 49 #include "pciide.h" 50 #include "ata_cmd.h" 51 #include "ata_fsm.h" 52 #include "ata_debug.h" 53 54 55 /* 56 * device types 57 */ 58 #define ATA_DEV_NONE 0 59 #define ATA_DEV_DISK 1 60 #define ATA_DEV_ATAPI 2 61 62 /* 63 * Largest sector allowed in 28 bit mode 64 */ 65 #define MAX_28BIT_CAPACITY 0xfffffff 66 67 /* 68 * Largest sector count allowed for device firmware file in one command. 69 */ 70 #define MAX_FWFILE_SIZE_ONECMD 0xffff 71 72 /* 73 * ata-options property configuration bits 74 */ 75 76 #define ATA_OPTIONS_DMA 0x01 77 78 #define ATAPRT(fmt) ghd_err fmt 79 80 /* ad_flags (per-drive) */ 81 82 #define AD_ATAPI 0x01 /* is an ATAPI drive */ 83 #define AD_DISK 0x02 84 #define AD_MUTEX_INIT 0x04 85 #define AD_NO_CDB_INTR 0x20 86 #define AD_1SECTOR 0x40 87 #define AD_INT13LBA 0x80 /* supports LBA at Int13 interface */ 88 #define AD_NORVRT 0x100 /* block revert-to-defaults */ 89 #define AD_EXT48 0x200 /* 48 bit (extended) LBA */ 90 #define ATAPIDRV(X) ((X)->ad_flags & AD_ATAPI) 91 92 93 /* max targets and luns */ 94 95 #define ATA_MAXTARG 2 96 #define ATA_MAXLUN 16 97 98 /* 99 * PCI-IDE Bus Mastering Scatter/Gather list size 100 */ 101 #define ATA_DMA_NSEGS 17 /* enough for at least 64K */ 102 103 /* 104 * Controller port address defaults 105 */ 106 #define ATA_BASE0 0x1f0 107 #define ATA_BASE1 0x170 108 109 /* 110 * port offsets from base address ioaddr1 111 */ 112 #define AT_DATA 0x00 /* data register */ 113 #define AT_ERROR 0x01 /* error register (read) */ 114 #define AT_FEATURE 0x01 /* features (write) */ 115 #define AT_COUNT 0x02 /* sector count */ 116 #define AT_SECT 0x03 /* sector number */ 117 #define AT_LCYL 0x04 /* cylinder low byte */ 118 #define AT_HCYL 0x05 /* cylinder high byte */ 119 #define AT_DRVHD 0x06 /* drive/head register */ 120 #define AT_STATUS 0x07 /* status/command register */ 121 #define AT_CMD 0x07 /* status/command register */ 122 123 /* 124 * port offsets from base address ioaddr2 125 */ 126 #define AT_ALTSTATUS 0x00 /* alternate status (read) */ 127 #define AT_DEVCTL 0x00 /* device control (write) */ 128 129 /* Device control register */ 130 #define ATDC_NIEN 0x02 /* disable interrupts */ 131 #define ATDC_SRST 0x04 /* controller reset */ 132 #define ATDC_D3 0x08 /* Mysterious bit, must be set */ 133 /* 134 * ATA-6 spec 135 * In 48-bit addressing, reading the LBA location and count 136 * registers when the high-order bit is set reads the "previous 137 * content" (LBA bits 47:24, count bits 15:8) instead of the 138 * "most recent" values (LBA bits 23:0, count bits 7:0). 139 */ 140 #define ATDC_HOB 0x80 /* High order bit */ 141 142 /* 143 * Status bits from AT_STATUS register 144 */ 145 #define ATS_BSY 0x80 /* controller busy */ 146 #define ATS_DRDY 0x40 /* drive ready */ 147 #define ATS_DF 0x20 /* device fault */ 148 #define ATS_DSC 0x10 /* seek operation complete */ 149 #define ATS_DRQ 0x08 /* data request */ 150 #define ATS_CORR 0x04 /* ECC correction applied */ 151 #define ATS_IDX 0x02 /* disk revolution index */ 152 #define ATS_ERR 0x01 /* error flag */ 153 154 /* 155 * Status bits from AT_ERROR register 156 */ 157 #define ATE_BBK_ICRC 0x80 /* bad block detected in ATA-1 */ 158 /* ICRC error in ATA-4 and newer */ 159 #define ATE_UNC 0x40 /* uncorrectable data error */ 160 #define ATE_MC 0x20 /* Media change */ 161 #define ATE_IDNF 0x10 /* ID not found */ 162 #define ATE_MCR 0x08 /* media change request */ 163 #define ATE_ABORT 0x04 /* aborted command */ 164 #define ATE_TKONF 0x02 /* track 0 not found */ 165 #define ATE_AMNF 0x01 /* address mark not found */ 166 167 #define ATE_NM 0x02 /* no media */ 168 169 /* 170 * Drive selectors for AT_DRVHD register 171 */ 172 #define ATDH_LBA 0x40 /* addressing in LBA mode not chs */ 173 #define ATDH_DRIVE0 0xa0 /* or into AT_DRVHD to select drive 0 */ 174 #define ATDH_DRIVE1 0xb0 /* or into AT_DRVHD to select drive 1 */ 175 176 /* 177 * Feature register bits 178 */ 179 #define ATF_ATAPI_DMA 0x01 /* ATAPI DMA enable bit */ 180 #define ATF_XFRMOD_UDMA 0x40 /* Ultra DMA mode */ 181 #define ATACM_UDMA_SEL(id) (((id)->ai_ultradma >> 8) & 0x7f) 182 183 /* 184 * Set feature register definitions. 185 */ 186 #define ATSF_SET_XFRMOD 0X03 /* Set transfer mode */ 187 #define ATSF_DIS_REVPOD 0x66 /* Disable reverting to power on defaults */ 188 #define ATSF_ENA_REVPOD 0xcc /* Enable reverting to power on defaults */ 189 190 /* 191 * common bits and options for set features (ATC_SET_FEAT) 192 */ 193 #define FC_WRITE_CACHE_ON 0x02 194 #define FC_WRITE_CACHE_OFF 0x82 195 196 /* Test which version of ATA is supported */ 197 #define IS_ATA_VERSION_SUPPORTED(idp, n) \ 198 ((idp->ai_majorversion != 0xffff) && \ 199 (idp->ai_majorversion & (1<<n))) 200 201 /* Test if supported version >= ATA-n */ 202 #define IS_ATA_VERSION_GE(idp, n) \ 203 ((idp->ai_majorversion != 0xffff) && \ 204 (idp->ai_majorversion != 0) && \ 205 (idp->ai_majorversion >= (1<<n))) 206 207 /* Test whether a device is a CD drive */ 208 #define IS_CDROM(dp) \ 209 ((dp->ad_flags & AD_ATAPI) && \ 210 ((dp->ad_id.ai_config >> 8) & DTYPE_MASK) == \ 211 DTYPE_RODIRECT) 212 213 /* macros from old common hba code */ 214 215 #define ATA_INTPROP(devi, pname, pval, plen) \ 216 (ddi_prop_op(DDI_DEV_T_ANY, (devi), PROP_LEN_AND_VAL_BUF, \ 217 DDI_PROP_DONTPASS, (pname), (caddr_t)(pval), (plen))) 218 219 #define ATA_LONGPROP(devi, pname, pval, plen) \ 220 (ddi_getlongprop(DDI_DEV_T_ANY, (devi), DDI_PROP_DONTPASS, \ 221 (pname), (caddr_t)(pval), (plen))) 222 223 /* 224 * 225 * per-controller soft-state data structure 226 * 227 */ 228 229 #define CTL2DRV(cp, t, l) (cp->ac_drvp[t][l]) 230 231 typedef struct ata_ctl { 232 233 dev_info_t *ac_dip; 234 uint_t ac_flags; 235 uint_t ac_timing_flags; 236 struct ata_drv *ac_drvp[ATA_MAXTARG][ATA_MAXLUN]; 237 int ac_max_transfer; /* max transfer in sectors */ 238 uint_t ac_standby_time; /* timer value seconds */ 239 240 ccc_t ac_ccc; /* for GHD module */ 241 struct ata_drv *ac_active_drvp; /* active drive, if any */ 242 struct ata_pkt *ac_active_pktp; /* active packet, if any */ 243 uchar_t ac_state; 244 245 scsi_hba_tran_t *ac_atapi_tran; /* for atapi module */ 246 247 /* 248 * port addresses associated with ioaddr1 249 */ 250 ddi_acc_handle_t ac_iohandle1; /* DDI I/O handle */ 251 caddr_t ac_ioaddr1; 252 ushort_t *ac_data; /* data register */ 253 uchar_t *ac_error; /* error register (read) */ 254 uchar_t *ac_feature; /* features (write) */ 255 uchar_t *ac_count; /* sector count */ 256 uchar_t *ac_sect; /* sector number */ 257 uchar_t *ac_lcyl; /* cylinder low byte */ 258 uchar_t *ac_hcyl; /* cylinder high byte */ 259 uchar_t *ac_drvhd; /* drive/head register */ 260 uchar_t *ac_status; /* status/command register */ 261 uchar_t *ac_cmd; /* status/command register */ 262 263 /* 264 * port addresses associated with ioaddr2 265 */ 266 ddi_acc_handle_t ac_iohandle2; /* DDI I/O handle */ 267 caddr_t ac_ioaddr2; 268 uchar_t *ac_altstatus; /* alternate status (read) */ 269 uchar_t *ac_devctl; /* device control (write) */ 270 271 /* 272 * handle and port addresss for PCI-IDE Bus Master controller 273 */ 274 ddi_acc_handle_t ac_bmhandle; /* DDI I/O handle */ 275 caddr_t ac_bmaddr; /* base addr of Bus Master Regs */ 276 uchar_t ac_pciide; /* PCI-IDE device */ 277 uchar_t ac_pciide_bm; /* Bus Mastering PCI-IDE device */ 278 279 /* 280 * Scatter/Gather list for PCI-IDE Bus Mastering controllers 281 */ 282 caddr_t ac_sg_list; /* virtual addr of S/G list */ 283 paddr_t ac_sg_paddr; /* phys addr of S/G list */ 284 ddi_acc_handle_t ac_sg_acc_handle; 285 ddi_dma_handle_t ac_sg_handle; 286 287 /* 288 * data for managing ARQ on ATAPI devices 289 */ 290 struct ata_pkt *ac_arq_pktp; /* pkt for performing ATAPI ARQ */ 291 struct ata_pkt *ac_fault_pktp; /* pkt that caused ARQ */ 292 uchar_t ac_arq_cdb[6]; 293 294 /* 295 * Power Management 296 */ 297 int ac_pm_support; 298 int ac_pm_level; 299 } ata_ctl_t; 300 301 /* ac_flags (per-controller) */ 302 303 #define AC_GHD_INIT 0x02 304 #define AC_ATAPI_INIT 0x04 305 #define AC_DISK_INIT 0x08 306 #define AC_ATTACHED 0x10 307 #define AC_SCSI_HBA_TRAN_ALLOC 0x1000 308 #define AC_SCSI_HBA_ATTACH 0x2000 309 310 #define AC_BMSTATREG_PIO_BROKEN 0x80000000 311 312 /* 313 * Bug 1256489: 314 * 315 * If AC_BSY_WAIT needs to be set for laptops that do 316 * suspend/resume but do not correctly wait for the busy bit to 317 * drop after a resume. 318 */ 319 320 /* ac_timing_flags (per-controller) */ 321 #define AC_BSY_WAIT 0x1 /* tweak timing in ata_start & atapi_start */ 322 323 324 325 /* Identify drive data */ 326 struct ata_id { 327 /* WORD */ 328 /* OFFSET COMMENT */ 329 ushort_t ai_config; /* 0 general configuration bits */ 330 ushort_t ai_fixcyls; /* 1 # of fixed cylinders */ 331 ushort_t ai_resv0; /* 2 # reserved */ 332 ushort_t ai_heads; /* 3 # of heads */ 333 ushort_t ai_trksiz; /* 4 # of unformatted bytes/track */ 334 ushort_t ai_secsiz; /* 5 # of unformatted bytes/sector */ 335 ushort_t ai_sectors; /* 6 # of sectors/track */ 336 ushort_t ai_resv1[3]; /* 7 "Vendor Unique" */ 337 char ai_drvser[20]; /* 10 Serial number */ 338 ushort_t ai_buftype; /* 20 Buffer type */ 339 ushort_t ai_bufsz; /* 21 Buffer size in 512 byte incr */ 340 ushort_t ai_ecc; /* 22 # of ecc bytes avail on rd/wr */ 341 char ai_fw[8]; /* 23 Firmware revision */ 342 char ai_model[40]; /* 27 Model # */ 343 ushort_t ai_mult1; /* 47 Multiple command flags */ 344 ushort_t ai_dwcap; /* 48 Doubleword capabilities */ 345 ushort_t ai_cap; /* 49 Capabilities */ 346 ushort_t ai_resv2; /* 50 Reserved */ 347 ushort_t ai_piomode; /* 51 PIO timing mode */ 348 ushort_t ai_dmamode; /* 52 DMA timing mode */ 349 ushort_t ai_validinfo; /* 53 bit0: wds 54-58, bit1: 64-70 */ 350 ushort_t ai_curcyls; /* 54 # of current cylinders */ 351 ushort_t ai_curheads; /* 55 # of current heads */ 352 ushort_t ai_cursectrk; /* 56 # of current sectors/track */ 353 ushort_t ai_cursccp[2]; /* 57 current sectors capacity */ 354 ushort_t ai_mult2; /* 59 multiple sectors info */ 355 ushort_t ai_addrsec[2]; /* 60 LBA only: no of addr secs */ 356 ushort_t ai_sworddma; /* 62 single word dma modes */ 357 ushort_t ai_dworddma; /* 63 double word dma modes */ 358 ushort_t ai_advpiomode; /* 64 advanced PIO modes supported */ 359 ushort_t ai_minmwdma; /* 65 min multi-word dma cycle info */ 360 ushort_t ai_recmwdma; /* 66 rec multi-word dma cycle info */ 361 ushort_t ai_minpio; /* 67 min PIO cycle info */ 362 ushort_t ai_minpioflow; /* 68 min PIO cycle info w/flow ctl */ 363 ushort_t ai_resv3[2]; /* 69,70 reserved */ 364 ushort_t ai_resv4[4]; /* 71-74 reserved */ 365 ushort_t ai_qdepth; /* 75 queue depth */ 366 ushort_t ai_resv5[4]; /* 76-79 reserved */ 367 ushort_t ai_majorversion; /* 80 major versions supported */ 368 ushort_t ai_minorversion; /* 81 minor version number supported */ 369 ushort_t ai_cmdset82; /* 82 command set supported */ 370 ushort_t ai_cmdset83; /* 83 more command sets supported */ 371 ushort_t ai_cmdset84; /* 84 more command sets supported */ 372 ushort_t ai_features85; /* 85 enabled features */ 373 ushort_t ai_features86; /* 86 enabled features */ 374 ushort_t ai_features87; /* 87 enabled features */ 375 ushort_t ai_ultradma; /* 88 Ultra DMA mode */ 376 ushort_t ai_erasetime; /* 89 security erase time */ 377 ushort_t ai_erasetimex; /* 90 enhanced security erase time */ 378 ushort_t ai_padding1[9]; /* pad through 99 */ 379 ushort_t ai_addrsecxt[4]; /* 100 extended max LBA sector */ 380 ushort_t ai_padding2[22]; /* pad to 126 */ 381 ushort_t ai_lastlun; /* 126 last LUN, as per SFF-8070i */ 382 ushort_t ai_resv6; /* 127 reserved */ 383 ushort_t ai_securestatus; /* 128 security status */ 384 ushort_t ai_vendor[31]; /* 129-159 vendor specific */ 385 ushort_t ai_padding3[16]; /* 160 pad to 176 */ 386 ushort_t ai_curmedser[30]; /* 176-205 current media serial number */ 387 ushort_t ai_padding4[49]; /* 206 pad to 255 */ 388 ushort_t ai_integrity; /* 255 integrity word */ 389 }; 390 391 /* Identify Drive: general config bits - word 0 */ 392 393 #define ATA_ID_REM_DRV 0x80 394 #define ATA_ID_COMPACT_FLASH 0x848a 395 #define ATA_ID_CF_TO_ATA 0x040a 396 #define ATA_ID_INCMPT 0x0004 397 398 /* Identify Drive: common capability bits - word 49 */ 399 400 #define ATAC_DMA_SUPPORT 0x0100 401 #define ATAC_LBA_SUPPORT 0x0200 402 #define ATAC_IORDY_DISABLE 0x0400 403 #define ATAC_IORDY_SUPPORT 0x0800 404 #define ATAC_RESERVED_IDPKT 0x1000 /* rsrvd for identify pkt dev */ 405 #define ATAC_STANDBYTIMER 0x2000 406 #define ATAC_ATA_TYPE_MASK 0x8001 407 #define ATAC_ATA_TYPE 0x0000 408 #define ATAC_ATAPI_TYPE_MASK 0xc000 409 #define ATAC_ATAPI_TYPE 0x8000 410 411 /* Identify Driver ai_validinfo (word 53) */ 412 413 #define ATAC_VALIDINFO_83 0x0004 /* word 83 supported fields valid */ 414 #define ATAC_VALIDINFO_70_64 0x0002 /* word 70:64 sup. fields valid */ 415 416 /* Identify Drive: ai_dworddma (word 63) */ 417 418 #define ATAC_MDMA_SEL_MASK 0x0700 /* Multiword DMA selected */ 419 #define ATAC_MDMA_2_SEL 0x0400 /* Multiword DMA mode 2 selected */ 420 #define ATAC_MDMA_1_SEL 0x0200 /* Multiword DMA mode 1 selected */ 421 #define ATAC_MDMA_0_SEL 0x0100 /* Multiword DMA mode 0 selected */ 422 #define ATAC_MDMA_2_SUP 0x0004 /* Multiword DMA mode 2 supported */ 423 #define ATAC_MDMA_1_SUP 0x0002 /* Multiword DMA mode 1 supported */ 424 #define ATAC_MDMA_0_SUP 0x0001 /* Multiword DMA mode 0 supported */ 425 426 /* Identify Drive: ai_advpiomode (word 64) */ 427 428 #define ATAC_ADVPIO_4_SUP 0x0002 /* PIO mode 4 supported */ 429 #define ATAC_ADVPIO_3_SUP 0x0001 /* PIO mode 3 supported */ 430 #define ATAC_ADVPIO_SERIAL 0x0003 /* Serial interface */ 431 432 /* Identify Drive: ai_majorversion (word 80) */ 433 434 #define ATAC_MAJVER_8 0x0100 /* ATA/ATAPI-8 version supported */ 435 #define ATAC_MAJVER_6 0x0040 /* ATA/ATAPI-6 version supported */ 436 #define ATAC_MAJVER_4 0x0010 /* ATA/ATAPI-4 version supported */ 437 438 /* Identify Drive: command set supported/enabled bits - words 83 and 86 */ 439 440 #define ATACS_EXT48 0x0400 /* 48 bit address feature */ 441 442 /* Identify Drive: ai_features85 (word 85) */ 443 #define ATAC_FEATURES85_WCE 0x0020 /* write cache enabled */ 444 445 /* per-drive data struct */ 446 447 typedef struct ata_drv { 448 ata_ctl_t *ad_ctlp; /* pointer back to ctlr */ 449 struct ata_id ad_id; /* IDENTIFY DRIVE data */ 450 451 uint_t ad_flags; 452 uchar_t ad_pciide_dma; /* PCIIDE DMA supported */ 453 uchar_t ad_targ; /* target */ 454 uchar_t ad_lun; /* lun */ 455 uchar_t ad_drive_bits; 456 457 /* Used by atapi side only */ 458 459 uchar_t ad_state; /* state of ATAPI FSM */ 460 uchar_t ad_cdb_len; /* Size of ATAPI CDBs */ 461 462 uchar_t ad_bogus_drq; 463 uchar_t ad_nec_bad_status; 464 465 /* Used by disk side only */ 466 467 struct scsi_device ad_device; 468 struct scsi_inquiry ad_inquiry; 469 struct ctl_obj ad_ctl_obj; 470 uchar_t ad_rd_cmd; 471 uchar_t ad_wr_cmd; 472 ushort_t ad_acyl; 473 474 /* 475 * Geometry note: The following three values are the geometry 476 * that the driver will use. They may differ from the 477 * geometry reported by the controller and/or BIOS. See note 478 * on ata_fix_large_disk_geometry in ata_disk.c for more 479 * details. 480 */ 481 uint32_t ad_drvrcyl; /* number of cyls */ 482 uint32_t ad_drvrhd; /* number of heads */ 483 uint32_t ad_drvrsec; /* number of sectors */ 484 ushort_t ad_phhd; /* number of phys heads */ 485 ushort_t ad_phsec; /* number of phys sectors */ 486 short ad_block_factor; 487 short ad_bytes_per_block; 488 489 /* 490 * Support for 48-bit LBA (ATA-6) 491 */ 492 uint64_t ad_capacity; /* Total sectors on disk */ 493 } ata_drv_t; 494 495 typedef struct ata_tgt { 496 ata_drv_t *at_drvp; 497 int at_arq; 498 ulong_t at_total_sectors; 499 ddi_dma_attr_t at_dma_attr; 500 } ata_tgt_t; 501 502 /* values for ad_pciide_dma */ 503 #define ATA_DMA_OFF 0x0 504 #define ATA_DMA_ON 0x1 505 506 /* 507 * (ata_pkt_t *) to (gcmd_t *) 508 */ 509 #define APKT2GCMD(apktp) (apktp->ap_gcmdp) 510 511 /* 512 * (gcmd_t *) to (ata_pkt_t *) 513 */ 514 #define GCMD2APKT(gcmdp) ((ata_pkt_t *)gcmdp->cmd_private) 515 516 /* 517 * (gtgt_t *) to (ata_ctl_t *) 518 */ 519 #define GTGTP2ATAP(gtgtp) ((ata_ctl_t *)GTGTP2HBA(gtgtp)) 520 521 /* 522 * (gtgt_t *) to (ata_tgt_t *) 523 */ 524 #define GTGTP2ATATGTP(gtgtp) ((ata_tgt_t *)GTGTP2TARGET(gtgtp)) 525 526 /* 527 * (gtgt_t *) to (ata_drv_t *) 528 */ 529 #define GTGTP2ATADRVP(gtgtp) (GTGTP2ATATGTP(gtgtp)->at_drvp) 530 531 /* 532 * (gcmd_t *) to (ata_tgt_t *) 533 */ 534 #define GCMD2TGT(gcmdp) GTGTP2ATATGTP(GCMDP2GTGTP(gcmdp)) 535 536 /* 537 * (gcmd_t *) to (ata_drv_t *) 538 */ 539 #define GCMD2DRV(gcmdp) GTGTP2ATADRVP(GCMDP2GTGTP(gcmdp)) 540 541 /* 542 * (ata_pkt_t *) to (ata_drv_t *) 543 */ 544 #define APKT2DRV(apktp) GCMD2DRV(APKT2GCMD(apktp)) 545 546 547 /* 548 * (struct hba_tran *) to (ata_ctl_t *) 549 */ 550 #define TRAN2ATAP(tranp) ((ata_ctl_t *)TRAN2HBA(tranp)) 551 552 553 /* 554 * ata common packet structure 555 */ 556 typedef struct ata_pkt { 557 558 gcmd_t *ap_gcmdp; /* GHD command struct */ 559 560 uint_t ap_flags; /* packet flags */ 561 562 caddr_t ap_baddr; /* I/O buffer base address */ 563 size_t ap_boffset; /* current offset into I/O buffer */ 564 size_t ap_bcount; /* # bytes in this request */ 565 566 caddr_t ap_v_addr; /* I/O buffer address */ 567 size_t ap_resid; /* # bytes left to read/write */ 568 569 uchar_t ap_pciide_dma; /* This pkt uses DMA transfer mode */ 570 prde_t ap_sg_list[ATA_DMA_NSEGS]; /* Scatter/Gather list */ 571 int ap_sg_cnt; /* number of entries in S/G list */ 572 573 /* command, starting sector number, sector count */ 574 575 daddr_t ap_startsec; /* starting sector number */ 576 ushort_t ap_count; /* sector count */ 577 uchar_t ap_sec; 578 uchar_t ap_lwcyl; 579 uchar_t ap_hicyl; 580 uchar_t ap_hd; 581 uchar_t ap_cmd; 582 583 /* saved status and error registers for error case */ 584 585 uchar_t ap_status; 586 uchar_t ap_error; 587 588 /* disk/atapi callback routines */ 589 590 int (*ap_start)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 591 struct ata_pkt *ata_pktp); 592 int (*ap_intr)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 593 struct ata_pkt *ata_pktp); 594 void (*ap_complete)(ata_drv_t *ata_drvp, 595 struct ata_pkt *ata_pktp, int do_callback); 596 597 /* Used by disk side */ 598 599 char ap_cdb; /* disk command */ 600 char ap_scb; /* status after disk cmd */ 601 uint_t ap_bytes_per_block; /* blk mode factor */ 602 uint_t ap_wrt_count; /* size of last write */ 603 caddr_t ap_v_addr_sav; /* Original I/O buffer address. */ 604 size_t ap_resid_sav; /* Original # of bytes */ 605 /* left to read/write. */ 606 607 /* Used by atapi side */ 608 609 uchar_t *ap_cdbp; /* ptr to SCSI CDB */ 610 uchar_t ap_cdb_len; /* length of SCSI CDB (in bytes) */ 611 uchar_t ap_cdb_pad; /* padding after SCSI CDB (in shorts) */ 612 613 struct scsi_arq_status *ap_scbp; /* ptr to SCSI status block */ 614 uchar_t ap_statuslen; /* length of SCSI status block */ 615 } ata_pkt_t; 616 617 618 /* 619 * defines for ap_flags 620 */ 621 #define AP_ATAPI 0x0001 /* device is atapi */ 622 #define AP_ERROR 0x0002 /* normal error */ 623 #define AP_TRAN_ERROR 0x0004 /* transport error */ 624 #define AP_READ 0x0008 /* read data */ 625 #define AP_WRITE 0x0010 /* write data */ 626 #define AP_ABORT 0x0020 /* packet aborted */ 627 #define AP_TIMEOUT 0x0040 /* packet timed out */ 628 #define AP_BUS_RESET 0x0080 /* bus reset */ 629 #define AP_DEV_RESET 0x0100 /* device reset */ 630 631 #define AP_SENT_CMD 0x0200 /* atapi: cdb sent */ 632 #define AP_XFERRED_DATA 0x0400 /* atapi: data transferred */ 633 #define AP_GOT_STATUS 0x0800 /* atapi: status received */ 634 #define AP_ARQ_ON_ERROR 0x1000 /* atapi: do ARQ on error */ 635 #define AP_ARQ_OKAY 0x2000 636 #define AP_ARQ_ERROR 0x4000 637 638 #define AP_FREE 0x80000000u /* packet is free! */ 639 640 641 /* 642 * public function prototypes 643 */ 644 645 int ata_check_drive_blacklist(struct ata_id *aidp, uint_t flags); 646 int ata_command(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, int expect_drdy, 647 int silent, uint_t busy_wait, uchar_t cmd, uchar_t feature, 648 uchar_t count, uchar_t sector, uchar_t head, uchar_t cyl_low, 649 uchar_t cyl_hi); 650 int ata_get_status_clear_intr(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp); 651 int ata_id_common(uchar_t id_cmd, int drdy_expected, 652 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 653 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 654 struct ata_id *ata_idp); 655 int ata_prop_create(dev_info_t *tgt_dip, ata_drv_t *ata_drvp, char *name); 656 int ata_queue_cmd(int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 657 void *arg, ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 658 gtgt_t *gtgtp); 659 int ata_set_feature(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 660 uchar_t feature, uchar_t value); 661 int ata_wait(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits, 662 uchar_t offbits, uint_t timeout_usec); 663 int ata_wait3(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits1, 664 uchar_t offbits1, uchar_t failure_onbits2, 665 uchar_t failure_offbits2, uchar_t failure_onbits3, 666 uchar_t failure_offbits3, uint_t timeout_usec); 667 int ata_test_lba_support(struct ata_id *aidp); 668 void ata_nsecwait(clock_t count); 669 670 671 /* 672 * PCIIDE DMA (Bus Mastering) functions and data in ata_dma.c 673 */ 674 extern ddi_dma_attr_t ata_pciide_dma_attr; 675 extern int ata_dma_disabled; 676 677 int ata_pciide_alloc(dev_info_t *dip, ata_ctl_t *ata_ctlp); 678 void ata_pciide_free(ata_ctl_t *ata_ctlp); 679 680 void ata_pciide_dma_sg_func(gcmd_t *gcmdp, ddi_dma_cookie_t *dmackp, 681 int single_segment, int seg_index); 682 void ata_pciide_dma_setup(ata_ctl_t *ata_ctlp, prde_t *srcp, int sg_cnt); 683 void ata_pciide_dma_start(ata_ctl_t *ata_ctlp, uchar_t direction); 684 void ata_pciide_dma_stop(ata_ctl_t *ata_ctlp); 685 int ata_pciide_status_clear(ata_ctl_t *ata_ctlp); 686 int ata_pciide_status_dmacheck_clear(ata_ctl_t *ata_ctlp); 687 int ata_pciide_status_pending(ata_ctl_t *ata_ctlp); 688 689 #ifdef __cplusplus 690 } 691 #endif 692 693 #endif /* _ATA_COMMON_H */ 694