1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 #include <sys/mutex.h>
27 #include <sys/types.h>
28 #include <sys/time.h>
29 #include <sys/clock.h>
30 #include <sys/machlock.h>
31 #include <sys/smp_impldefs.h>
32 #include <sys/uadmin.h>
33 #include <sys/promif.h>
34 #include <sys/psm.h>
35 #include <sys/psm_common.h>
36 #include <sys/atomic.h>
37 #include <sys/apic.h>
38 #include <sys/archsystm.h>
39 #include <sys/mach_intr.h>
40 #include <sys/modctl.h>
41 #include <sys/sysmacros.h>
42 #include <sys/pci_intr_lib.h>
43
44
45 /* Multiple vector support for MSI */
46 int apic_multi_msi_enable = 1;
47
48 /* Multiple vector support for MSI-X */
49 int apic_msix_enable = 1;
50
51 /*
52 * check whether the system supports MSI
53 *
54 * If PCI-E capability is found, then this must be a PCI-E system.
55 * Since MSI is required for PCI-E system, it returns PSM_SUCCESS
56 * to indicate this system supports MSI.
57 */
58 int
apic_check_msi_support()59 apic_check_msi_support()
60 {
61 dev_info_t *cdip;
62 char dev_type[16];
63 int dev_len;
64
65 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support:\n"));
66
67 /*
68 * check whether the first level children of root_node have
69 * PCI-E capability
70 */
71 for (cdip = ddi_get_child(ddi_root_node()); cdip != NULL;
72 cdip = ddi_get_next_sibling(cdip)) {
73
74 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support: cdip: 0x%p,"
75 " driver: %s, binding: %s, nodename: %s\n", (void *)cdip,
76 ddi_driver_name(cdip), ddi_binding_name(cdip),
77 ddi_node_name(cdip)));
78 dev_len = sizeof (dev_type);
79 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS,
80 "device_type", (caddr_t)dev_type, &dev_len)
81 != DDI_PROP_SUCCESS)
82 continue;
83 if (strcmp(dev_type, "pciex") == 0)
84 return (PSM_SUCCESS);
85 }
86
87 /* MSI is not supported on this system */
88 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support: no 'pciex' "
89 "device_type found\n"));
90 return (PSM_FAILURE);
91 }
92
93
94 /*
95 * It finds the apic_irq_t associates with the dip, ispec and type.
96 */
97 apic_irq_t *
apic_find_irq(dev_info_t * dip,struct intrspec * ispec,int type)98 apic_find_irq(dev_info_t *dip, struct intrspec *ispec, int type)
99 {
100 apic_irq_t *irqp;
101 int i;
102
103 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_irq: dip=0x%p vec=0x%x "
104 "ipl=0x%x type=0x%x\n", (void *)dip, ispec->intrspec_vec,
105 ispec->intrspec_pri, type));
106
107 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
108 for (irqp = apic_irq_table[i]; irqp; irqp = irqp->airq_next) {
109 if ((irqp->airq_dip == dip) &&
110 (irqp->airq_origirq == ispec->intrspec_vec) &&
111 (irqp->airq_ipl == ispec->intrspec_pri)) {
112 if (type == DDI_INTR_TYPE_MSI) {
113 if (irqp->airq_mps_intr_index ==
114 MSI_INDEX)
115 return (irqp);
116 } else if (type == DDI_INTR_TYPE_MSIX) {
117 if (irqp->airq_mps_intr_index ==
118 MSIX_INDEX)
119 return (irqp);
120 } else
121 return (irqp);
122 }
123 }
124 }
125 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_irq: return NULL\n"));
126 return (NULL);
127 }
128
129
130 int
apic_get_vector_intr_info(int vecirq,apic_get_intr_t * intr_params_p)131 apic_get_vector_intr_info(int vecirq, apic_get_intr_t *intr_params_p)
132 {
133 struct autovec *av_dev;
134 uchar_t irqno;
135 int i;
136 apic_irq_t *irq_p;
137
138 /* Sanity check the vector/irq argument. */
139 ASSERT((vecirq >= 0) || (vecirq <= APIC_MAX_VECTOR));
140
141 mutex_enter(&airq_mutex);
142
143 /*
144 * Convert the vecirq arg to an irq using vector_to_irq table
145 * if the arg is a vector. Pass thru if already an irq.
146 */
147 if ((intr_params_p->avgi_req_flags & PSMGI_INTRBY_FLAGS) ==
148 PSMGI_INTRBY_VEC)
149 irqno = apic_vector_to_irq[vecirq];
150 else
151 irqno = vecirq;
152
153 irq_p = apic_irq_table[irqno];
154
155 if ((irq_p == NULL) ||
156 ((irq_p->airq_mps_intr_index != RESERVE_INDEX) &&
157 ((irq_p->airq_temp_cpu == IRQ_UNBOUND) ||
158 (irq_p->airq_temp_cpu == IRQ_UNINIT)))) {
159 mutex_exit(&airq_mutex);
160 return (PSM_FAILURE);
161 }
162
163 if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) {
164
165 /* Get the (temp) cpu from apic_irq table, indexed by irq. */
166 intr_params_p->avgi_cpu_id = irq_p->airq_temp_cpu;
167
168 /* Return user bound info for intrd. */
169 if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) {
170 intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND;
171 intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND;
172 }
173 }
174
175 if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR)
176 intr_params_p->avgi_vector = irq_p->airq_vector;
177
178 if (intr_params_p->avgi_req_flags &
179 (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS))
180 /* Get number of devices from apic_irq table shared field. */
181 intr_params_p->avgi_num_devs = irq_p->airq_share;
182
183 if (intr_params_p->avgi_req_flags & PSMGI_REQ_GET_DEVS) {
184
185 intr_params_p->avgi_req_flags |= PSMGI_REQ_NUM_DEVS;
186
187 /* Some devices have NULL dip. Don't count these. */
188 if (intr_params_p->avgi_num_devs > 0) {
189 for (i = 0, av_dev = autovect[irqno].avh_link;
190 av_dev; av_dev = av_dev->av_link)
191 if (av_dev->av_vector && av_dev->av_dip)
192 i++;
193 intr_params_p->avgi_num_devs =
194 MIN(intr_params_p->avgi_num_devs, i);
195 }
196
197 /* There are no viable dips to return. */
198 if (intr_params_p->avgi_num_devs == 0)
199 intr_params_p->avgi_dip_list = NULL;
200
201 else { /* Return list of dips */
202
203 /* Allocate space in array for that number of devs. */
204 intr_params_p->avgi_dip_list = kmem_zalloc(
205 intr_params_p->avgi_num_devs *
206 sizeof (dev_info_t *),
207 KM_SLEEP);
208
209 /*
210 * Loop through the device list of the autovec table
211 * filling in the dip array.
212 *
213 * Note that the autovect table may have some special
214 * entries which contain NULL dips. These will be
215 * ignored.
216 */
217 for (i = 0, av_dev = autovect[irqno].avh_link;
218 av_dev; av_dev = av_dev->av_link)
219 if (av_dev->av_vector && av_dev->av_dip)
220 intr_params_p->avgi_dip_list[i++] =
221 av_dev->av_dip;
222 }
223 }
224
225 mutex_exit(&airq_mutex);
226
227 return (PSM_SUCCESS);
228 }
229
230
231 /*
232 * apic_pci_msi_enable_vector:
233 * Set the address/data fields in the MSI/X capability structure
234 * XXX: MSI-X support
235 */
236 /* ARGSUSED */
237 void
apic_pci_msi_enable_vector(apic_irq_t * irq_ptr,int type,int inum,int vector,int count,int target_apic_id)238 apic_pci_msi_enable_vector(apic_irq_t *irq_ptr, int type, int inum, int vector,
239 int count, int target_apic_id)
240 {
241 uint64_t msi_addr, msi_data;
242 ushort_t msi_ctrl;
243 dev_info_t *dip = irq_ptr->airq_dip;
244 int cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
245 ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(dip);
246
247 DDI_INTR_IMPLDBG((CE_CONT, "apic_pci_msi_enable_vector: dip=0x%p\n"
248 "\tdriver = %s, inum=0x%x vector=0x%x apicid=0x%x\n", (void *)dip,
249 ddi_driver_name(dip), inum, vector, target_apic_id));
250
251 ASSERT((handle != NULL) && (cap_ptr != 0));
252
253 /* MSI Address */
254 msi_addr = (MSI_ADDR_HDR |
255 (target_apic_id << MSI_ADDR_DEST_SHIFT));
256 msi_addr |= ((MSI_ADDR_RH_FIXED << MSI_ADDR_RH_SHIFT) |
257 (MSI_ADDR_DM_PHYSICAL << MSI_ADDR_DM_SHIFT));
258
259 /* MSI Data: MSI is edge triggered according to spec */
260 msi_data = ((MSI_DATA_TM_EDGE << MSI_DATA_TM_SHIFT) | vector);
261
262 DDI_INTR_IMPLDBG((CE_CONT, "apic_pci_msi_enable_vector: addr=0x%lx "
263 "data=0x%lx\n", (long)msi_addr, (long)msi_data));
264
265 if (type == DDI_INTR_TYPE_MSI) {
266 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
267
268 /* Set the bits to inform how many MSIs are enabled */
269 msi_ctrl |= ((highbit(count) -1) << PCI_MSI_MME_SHIFT);
270 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl);
271 }
272 }
273
274
275 /*
276 * apic_pci_msi_disable_mode:
277 */
278 void
apic_pci_msi_disable_mode(dev_info_t * rdip,int type)279 apic_pci_msi_disable_mode(dev_info_t *rdip, int type)
280 {
281 ushort_t msi_ctrl;
282 int cap_ptr = i_ddi_get_msi_msix_cap_ptr(rdip);
283 ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(rdip);
284
285 ASSERT((handle != NULL) && (cap_ptr != 0));
286
287 if (type == DDI_INTR_TYPE_MSI) {
288 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
289 if (!(msi_ctrl & PCI_MSI_ENABLE_BIT))
290 return;
291
292 msi_ctrl &= ~PCI_MSI_ENABLE_BIT; /* MSI disable */
293 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl);
294
295 } else if (type == DDI_INTR_TYPE_MSIX) {
296 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
297 if (msi_ctrl & PCI_MSIX_ENABLE_BIT) {
298 msi_ctrl &= ~PCI_MSIX_ENABLE_BIT;
299 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL,
300 msi_ctrl);
301 }
302 }
303 }
304
305
306 /*
307 * apic_pci_msi_enable_mode:
308 */
309 void
apic_pci_msi_enable_mode(dev_info_t * rdip,int type,int inum)310 apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum)
311 {
312 ushort_t msi_ctrl;
313 int cap_ptr = i_ddi_get_msi_msix_cap_ptr(rdip);
314 ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(rdip);
315
316 ASSERT((handle != NULL) && (cap_ptr != 0));
317
318 if (type == DDI_INTR_TYPE_MSI) {
319 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
320 if ((msi_ctrl & PCI_MSI_ENABLE_BIT))
321 return;
322
323 msi_ctrl |= PCI_MSI_ENABLE_BIT;
324 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl);
325
326 } else if (type == DDI_INTR_TYPE_MSIX) {
327 uintptr_t off;
328 uint32_t mask;
329 ddi_intr_msix_t *msix_p;
330
331 msix_p = i_ddi_get_msix(rdip);
332
333 ASSERT(msix_p != NULL);
334
335 /* Offset into "inum"th entry in the MSI-X table & clear mask */
336 off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
337 PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
338
339 mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
340
341 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, (mask & ~1));
342
343 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
344
345 if (!(msi_ctrl & PCI_MSIX_ENABLE_BIT)) {
346 msi_ctrl |= PCI_MSIX_ENABLE_BIT;
347 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL,
348 msi_ctrl);
349 }
350 }
351 }
352
353
354 /*
355 * We let the hypervisor deal with msi configutation
356 * so just stub this out.
357 */
358
359 /* ARGSUSED */
360 void
apic_pci_msi_unconfigure(dev_info_t * rdip,int type,int inum)361 apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum)
362 {
363 }
364