1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _VM_HAT_PTE_H 28*7c478bd9Sstevel@tonic-gate #define _VM_HAT_PTE_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*7c478bd9Sstevel@tonic-gate 32*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 33*7c478bd9Sstevel@tonic-gate extern "C" { 34*7c478bd9Sstevel@tonic-gate #endif 35*7c478bd9Sstevel@tonic-gate 36*7c478bd9Sstevel@tonic-gate 37*7c478bd9Sstevel@tonic-gate #include <sys/types.h> 38*7c478bd9Sstevel@tonic-gate 39*7c478bd9Sstevel@tonic-gate /* 40*7c478bd9Sstevel@tonic-gate * Defines for the bits in X86 and AMD64 Page Tables 41*7c478bd9Sstevel@tonic-gate * 42*7c478bd9Sstevel@tonic-gate * Notes: 43*7c478bd9Sstevel@tonic-gate * 44*7c478bd9Sstevel@tonic-gate * Largepages and PAT bits: 45*7c478bd9Sstevel@tonic-gate * 46*7c478bd9Sstevel@tonic-gate * bit 7 at level 0 is the PAT bit 47*7c478bd9Sstevel@tonic-gate * bit 7 above level 0 is the Pagesize bit (set for large page) 48*7c478bd9Sstevel@tonic-gate * bit 12 (when a large page) is the PAT bit 49*7c478bd9Sstevel@tonic-gate * 50*7c478bd9Sstevel@tonic-gate * In Solaris the PAT/PWT/PCD values are set up so that: 51*7c478bd9Sstevel@tonic-gate * 52*7c478bd9Sstevel@tonic-gate * PAT & PWT -> Write Protected 53*7c478bd9Sstevel@tonic-gate * PAT & PCD -> Write Combining 54*7c478bd9Sstevel@tonic-gate * PAT by itself (PWT == 0 && PCD == 0) yields uncacheable (same as PCD == 1) 55*7c478bd9Sstevel@tonic-gate * 56*7c478bd9Sstevel@tonic-gate * 57*7c478bd9Sstevel@tonic-gate * Permission bits: 58*7c478bd9Sstevel@tonic-gate * 59*7c478bd9Sstevel@tonic-gate * - PT_USER must be set in all levels for user pages 60*7c478bd9Sstevel@tonic-gate * - PT_WRITE must be set in all levels for user writable pages 61*7c478bd9Sstevel@tonic-gate * - PT_NX applies if set at any level 62*7c478bd9Sstevel@tonic-gate * 63*7c478bd9Sstevel@tonic-gate * For these, we use the "allow" settings in all tables above level 0 and only 64*7c478bd9Sstevel@tonic-gate * ever disable things in PTEs. 65*7c478bd9Sstevel@tonic-gate * 66*7c478bd9Sstevel@tonic-gate * The use of PT_GLOBAL and PT_NX depend on being enabled in processor 67*7c478bd9Sstevel@tonic-gate * control registers. Hence, we use a variable to reference these bit 68*7c478bd9Sstevel@tonic-gate * masks. During hat_kern_setup() if the feature isn't enabled we 69*7c478bd9Sstevel@tonic-gate * clear out the variables. 70*7c478bd9Sstevel@tonic-gate */ 71*7c478bd9Sstevel@tonic-gate #define PT_VALID (0x001) /* a valid translation is present */ 72*7c478bd9Sstevel@tonic-gate #define PT_WRITABLE (0x002) /* the page is writable */ 73*7c478bd9Sstevel@tonic-gate #define PT_USER (0x004) /* the page is accessible by user mode */ 74*7c478bd9Sstevel@tonic-gate #define PT_WRITETHRU (0x008) /* write back caching is disabled (non-PAT) */ 75*7c478bd9Sstevel@tonic-gate #define PT_NOCACHE (0x010) /* page is not cacheable (non-PAT) */ 76*7c478bd9Sstevel@tonic-gate #define PT_REF (0x020) /* page was referenced */ 77*7c478bd9Sstevel@tonic-gate #define PT_MOD (0x040) /* page was modified */ 78*7c478bd9Sstevel@tonic-gate #define PT_PAGESIZE (0x080) /* above level 0, indicates a large page */ 79*7c478bd9Sstevel@tonic-gate #define PT_PAT_4K (0x080) /* at level 0, used for write combining */ 80*7c478bd9Sstevel@tonic-gate #define PT_GLOBAL (0x100) /* the mapping is global */ 81*7c478bd9Sstevel@tonic-gate #define PT_SOFTWARE (0xe00) /* available for software */ 82*7c478bd9Sstevel@tonic-gate 83*7c478bd9Sstevel@tonic-gate #define PT_PAT_LARGE (0x1000) /* PAT bit for large pages */ 84*7c478bd9Sstevel@tonic-gate 85*7c478bd9Sstevel@tonic-gate #define PT_PTPBITS (PT_VALID | PT_USER | PT_WRITABLE | PT_REF) 86*7c478bd9Sstevel@tonic-gate #define PT_FLAGBITS (0xfff) /* for masking off flag bits */ 87*7c478bd9Sstevel@tonic-gate 88*7c478bd9Sstevel@tonic-gate /* 89*7c478bd9Sstevel@tonic-gate * The software bits are used by the HAT to track attributes. 90*7c478bd9Sstevel@tonic-gate * 91*7c478bd9Sstevel@tonic-gate * PT_NOSYNC - The PT_REF/PT_MOD bits are not sync'd to page_t. 92*7c478bd9Sstevel@tonic-gate * The hat will install them as always set. 93*7c478bd9Sstevel@tonic-gate * 94*7c478bd9Sstevel@tonic-gate * PT_NOCONSIST - There is no entry for this hment for this mapping. 95*7c478bd9Sstevel@tonic-gate */ 96*7c478bd9Sstevel@tonic-gate #define PT_NOSYNC (0x200) /* PTE was created with HAT_NOSYNC */ 97*7c478bd9Sstevel@tonic-gate #define PT_NOCONSIST (0x400) /* PTE was created with HAT_LOAD_NOCONSIST */ 98*7c478bd9Sstevel@tonic-gate 99*7c478bd9Sstevel@tonic-gate /* 100*7c478bd9Sstevel@tonic-gate * macros to get/set/clear the PTE fields 101*7c478bd9Sstevel@tonic-gate */ 102*7c478bd9Sstevel@tonic-gate #define PTE_SET(p, f) ((p) |= (f)) 103*7c478bd9Sstevel@tonic-gate #define PTE_CLR(p, f) ((p) &= ~(x86pte_t)(f)) 104*7c478bd9Sstevel@tonic-gate #define PTE_GET(p, f) ((p) & (f)) 105*7c478bd9Sstevel@tonic-gate 106*7c478bd9Sstevel@tonic-gate /* 107*7c478bd9Sstevel@tonic-gate * Handy macro to check if a pagetable entry or pointer is valid 108*7c478bd9Sstevel@tonic-gate */ 109*7c478bd9Sstevel@tonic-gate #define PTE_ISVALID(p) PTE_GET(p, PT_VALID) 110*7c478bd9Sstevel@tonic-gate 111*7c478bd9Sstevel@tonic-gate /* 112*7c478bd9Sstevel@tonic-gate * Does a PTE map a large page. 113*7c478bd9Sstevel@tonic-gate */ 114*7c478bd9Sstevel@tonic-gate #define PTE_IS_LGPG(p, l) ((l) > 0 && PTE_GET((p), PT_PAGESIZE)) 115*7c478bd9Sstevel@tonic-gate 116*7c478bd9Sstevel@tonic-gate /* 117*7c478bd9Sstevel@tonic-gate * does this PTE represent a page (not a pointer to another page table)? 118*7c478bd9Sstevel@tonic-gate */ 119*7c478bd9Sstevel@tonic-gate #define PTE_ISPAGE(p, l) \ 120*7c478bd9Sstevel@tonic-gate (PTE_ISVALID(p) && ((l) == 0 || PTE_GET(p, PT_PAGESIZE))) 121*7c478bd9Sstevel@tonic-gate 122*7c478bd9Sstevel@tonic-gate /* 123*7c478bd9Sstevel@tonic-gate * Handy macro to check if 2 PTE's are the same - ignores REF/MOD bits 124*7c478bd9Sstevel@tonic-gate */ 125*7c478bd9Sstevel@tonic-gate #define PTE_EQUIV(a, b) (((a) | PT_REF | PT_MOD) == ((b) | PT_REF | PT_MOD)) 126*7c478bd9Sstevel@tonic-gate 127*7c478bd9Sstevel@tonic-gate /* 128*7c478bd9Sstevel@tonic-gate * Shorthand for converting a PTE to it's pfn. 129*7c478bd9Sstevel@tonic-gate */ 130*7c478bd9Sstevel@tonic-gate #define PTE2PFN(p, l) \ 131*7c478bd9Sstevel@tonic-gate mmu_btop(PTE_GET((p), PTE_IS_LGPG((p), (l)) ? PT_PADDR_LGPG : PT_PADDR)) 132*7c478bd9Sstevel@tonic-gate 133*7c478bd9Sstevel@tonic-gate /* 134*7c478bd9Sstevel@tonic-gate * The software extraction for a single Page Table Entry will always 135*7c478bd9Sstevel@tonic-gate * be a 64 bit unsigned int. If running a non-PAE hat, the page table 136*7c478bd9Sstevel@tonic-gate * access routines know to extend/shorten it to 32 bits. 137*7c478bd9Sstevel@tonic-gate */ 138*7c478bd9Sstevel@tonic-gate typedef uint64_t x86pte_t; 139*7c478bd9Sstevel@tonic-gate typedef uint32_t x86pte32_t; 140*7c478bd9Sstevel@tonic-gate #define PT_NX (0x8000000000000000ull) 141*7c478bd9Sstevel@tonic-gate #define PT_PADDR (0x00fffffffffff000ull) 142*7c478bd9Sstevel@tonic-gate #define PT_PADDR_LGPG (0x00ffffffffffe000ull) /* phys addr for large pages */ 143*7c478bd9Sstevel@tonic-gate 144*7c478bd9Sstevel@tonic-gate /* 145*7c478bd9Sstevel@tonic-gate * Macros to create a PTP or PTE from the pfn and level 146*7c478bd9Sstevel@tonic-gate */ 147*7c478bd9Sstevel@tonic-gate #define MAKEPTP(pfn, l) \ 148*7c478bd9Sstevel@tonic-gate (((x86pte_t)(pfn) << MMU_PAGESHIFT) | mmu.ptp_bits[(l) + 1]) 149*7c478bd9Sstevel@tonic-gate #define MAKEPTE(pfn, l) \ 150*7c478bd9Sstevel@tonic-gate (((x86pte_t)(pfn) << MMU_PAGESHIFT) | mmu.pte_bits[l]) 151*7c478bd9Sstevel@tonic-gate 152*7c478bd9Sstevel@tonic-gate /* 153*7c478bd9Sstevel@tonic-gate * The idea of "level" refers to the level where the page table is used in the 154*7c478bd9Sstevel@tonic-gate * the hardware address translation steps. The level values correspond to the 155*7c478bd9Sstevel@tonic-gate * following names of tables used in AMD/Intel architecture documents: 156*7c478bd9Sstevel@tonic-gate * 157*7c478bd9Sstevel@tonic-gate * AMD/INTEL name Level # 158*7c478bd9Sstevel@tonic-gate * ---------------------- ------- 159*7c478bd9Sstevel@tonic-gate * Page Map Level 4 3 160*7c478bd9Sstevel@tonic-gate * Page Directory Pointer 2 161*7c478bd9Sstevel@tonic-gate * Page Directory 1 162*7c478bd9Sstevel@tonic-gate * Page Table 0 163*7c478bd9Sstevel@tonic-gate * 164*7c478bd9Sstevel@tonic-gate * The numbering scheme is such that the values of 0 and 1 can correspond to 165*7c478bd9Sstevel@tonic-gate * the pagesize codes used for MPSS support. For now the Maximum level at 166*7c478bd9Sstevel@tonic-gate * which you can have a large page is a constant, that may change in 167*7c478bd9Sstevel@tonic-gate * future processors. 168*7c478bd9Sstevel@tonic-gate * 169*7c478bd9Sstevel@tonic-gate * The type of "level_t" is signed so that it can be used like: 170*7c478bd9Sstevel@tonic-gate * level_t l; 171*7c478bd9Sstevel@tonic-gate * ... 172*7c478bd9Sstevel@tonic-gate * while (--l >= 0) 173*7c478bd9Sstevel@tonic-gate * ... 174*7c478bd9Sstevel@tonic-gate */ 175*7c478bd9Sstevel@tonic-gate #define MAX_NUM_LEVEL 4 176*7c478bd9Sstevel@tonic-gate #define MAX_PAGE_LEVEL 1 /* for now.. sigh */ 177*7c478bd9Sstevel@tonic-gate typedef int16_t level_t; 178*7c478bd9Sstevel@tonic-gate #define LEVEL_SHIFT(l) (mmu.level_shift[l]) 179*7c478bd9Sstevel@tonic-gate #define LEVEL_SIZE(l) (mmu.level_size[l]) 180*7c478bd9Sstevel@tonic-gate #define LEVEL_OFFSET(l) (mmu.level_offset[l]) 181*7c478bd9Sstevel@tonic-gate #define LEVEL_MASK(l) (mmu.level_mask[l]) 182*7c478bd9Sstevel@tonic-gate 183*7c478bd9Sstevel@tonic-gate /* 184*7c478bd9Sstevel@tonic-gate * Macros to: 185*7c478bd9Sstevel@tonic-gate * Check for a PFN above 4Gig and 64Gig for 32 bit PAE support 186*7c478bd9Sstevel@tonic-gate */ 187*7c478bd9Sstevel@tonic-gate #define PFN_4G (4ull * (1024 * 1024 * 1024 / MMU_PAGESIZE)) 188*7c478bd9Sstevel@tonic-gate #define PFN_64G (64ull * (1024 * 1024 * 1024 / MMU_PAGESIZE)) 189*7c478bd9Sstevel@tonic-gate #define PFN_ABOVE4G(pfn) ((pfn) >= PFN_4G) 190*7c478bd9Sstevel@tonic-gate #define PFN_ABOVE64G(pfn) ((pfn) >= PFN_64G) 191*7c478bd9Sstevel@tonic-gate 192*7c478bd9Sstevel@tonic-gate /* 193*7c478bd9Sstevel@tonic-gate * The CR3 register holds the physical address of the top level page table. 194*7c478bd9Sstevel@tonic-gate */ 195*7c478bd9Sstevel@tonic-gate #define MAKECR3(pfn) mmu_ptob(pfn) 196*7c478bd9Sstevel@tonic-gate 197*7c478bd9Sstevel@tonic-gate /* 198*7c478bd9Sstevel@tonic-gate * HAT/MMU parameters that depend on kernel mode and/or processor type 199*7c478bd9Sstevel@tonic-gate */ 200*7c478bd9Sstevel@tonic-gate struct htable; 201*7c478bd9Sstevel@tonic-gate struct hat_mmu_info { 202*7c478bd9Sstevel@tonic-gate x86pte_t pt_nx; /* either 0 or PT_NX */ 203*7c478bd9Sstevel@tonic-gate x86pte_t pt_global; /* either 0 or PT_GLOBAL */ 204*7c478bd9Sstevel@tonic-gate 205*7c478bd9Sstevel@tonic-gate pfn_t highest_pfn; 206*7c478bd9Sstevel@tonic-gate 207*7c478bd9Sstevel@tonic-gate uint_t num_level; /* number of page table levels in use */ 208*7c478bd9Sstevel@tonic-gate uint_t max_level; /* just num_level - 1 */ 209*7c478bd9Sstevel@tonic-gate uint_t max_page_level; /* maximum level at which we can map a page */ 210*7c478bd9Sstevel@tonic-gate uint_t ptes_per_table; /* # of entries in lower level page tables */ 211*7c478bd9Sstevel@tonic-gate uint_t top_level_count; /* # of entries in top most level page table */ 212*7c478bd9Sstevel@tonic-gate 213*7c478bd9Sstevel@tonic-gate uint_t hash_cnt; /* cnt of entries in htable_hash_cache */ 214*7c478bd9Sstevel@tonic-gate uint_t vlp_hash_cnt; /* cnt of entries in vlp htable_hash_cache */ 215*7c478bd9Sstevel@tonic-gate 216*7c478bd9Sstevel@tonic-gate uint_t pae_hat; /* either 0 or 1 */ 217*7c478bd9Sstevel@tonic-gate 218*7c478bd9Sstevel@tonic-gate uintptr_t hole_start; /* start of VA hole (or -1 if none) */ 219*7c478bd9Sstevel@tonic-gate uintptr_t hole_end; /* end of VA hole (or 0 if none) */ 220*7c478bd9Sstevel@tonic-gate 221*7c478bd9Sstevel@tonic-gate struct htable **kmap_htables; /* htables for segmap + 32 bit heap */ 222*7c478bd9Sstevel@tonic-gate x86pte_t *kmap_ptes; /* mapping of pagetables that map kmap */ 223*7c478bd9Sstevel@tonic-gate uintptr_t kmap_addr; /* start addr of kmap */ 224*7c478bd9Sstevel@tonic-gate uintptr_t kmap_eaddr; /* end addr of kmap */ 225*7c478bd9Sstevel@tonic-gate 226*7c478bd9Sstevel@tonic-gate uint_t pte_size; /* either 4 or 8 */ 227*7c478bd9Sstevel@tonic-gate uint_t pte_size_shift; /* either 2 or 3 */ 228*7c478bd9Sstevel@tonic-gate x86pte_t ptp_bits[MAX_NUM_LEVEL]; /* bits set for interior PTP */ 229*7c478bd9Sstevel@tonic-gate x86pte_t pte_bits[MAX_NUM_LEVEL]; /* bits set for leaf PTE */ 230*7c478bd9Sstevel@tonic-gate 231*7c478bd9Sstevel@tonic-gate /* 232*7c478bd9Sstevel@tonic-gate * The following tables are equivalent to PAGEXXXXX at different levels 233*7c478bd9Sstevel@tonic-gate * in the page table hierarchy. 234*7c478bd9Sstevel@tonic-gate */ 235*7c478bd9Sstevel@tonic-gate uint_t level_shift[MAX_NUM_LEVEL]; /* PAGESHIFT for given level */ 236*7c478bd9Sstevel@tonic-gate uintptr_t level_size[MAX_NUM_LEVEL]; /* PAGESIZE for given level */ 237*7c478bd9Sstevel@tonic-gate uintptr_t level_offset[MAX_NUM_LEVEL]; /* PAGEOFFSET for given level */ 238*7c478bd9Sstevel@tonic-gate uintptr_t level_mask[MAX_NUM_LEVEL]; /* PAGEMASK for given level */ 239*7c478bd9Sstevel@tonic-gate 240*7c478bd9Sstevel@tonic-gate uint_t tlb_entries[MAX_NUM_LEVEL]; /* tlb entries per pagesize */ 241*7c478bd9Sstevel@tonic-gate }; 242*7c478bd9Sstevel@tonic-gate 243*7c478bd9Sstevel@tonic-gate 244*7c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 245*7c478bd9Sstevel@tonic-gate /* 246*7c478bd9Sstevel@tonic-gate * The concept of a VA hole exists in AMD64. This might need to be made 247*7c478bd9Sstevel@tonic-gate * model specific eventually. 248*7c478bd9Sstevel@tonic-gate */ 249*7c478bd9Sstevel@tonic-gate #if defined(__amd64) 250*7c478bd9Sstevel@tonic-gate 251*7c478bd9Sstevel@tonic-gate #ifdef lint 252*7c478bd9Sstevel@tonic-gate #define IN_VA_HOLE(va) (__lintzero) 253*7c478bd9Sstevel@tonic-gate #else 254*7c478bd9Sstevel@tonic-gate #define IN_VA_HOLE(va) (mmu.hole_start <= (va) && (va) < mmu.hole_end) 255*7c478bd9Sstevel@tonic-gate #endif 256*7c478bd9Sstevel@tonic-gate 257*7c478bd9Sstevel@tonic-gate #define FMT_PTE "%lx" 258*7c478bd9Sstevel@tonic-gate 259*7c478bd9Sstevel@tonic-gate #elif defined(__i386) 260*7c478bd9Sstevel@tonic-gate 261*7c478bd9Sstevel@tonic-gate #ifdef lint 262*7c478bd9Sstevel@tonic-gate #define IN_VA_HOLE(va) (__lintzero) 263*7c478bd9Sstevel@tonic-gate #else 264*7c478bd9Sstevel@tonic-gate #define IN_VA_HOLE(va) (0) 265*7c478bd9Sstevel@tonic-gate #endif 266*7c478bd9Sstevel@tonic-gate 267*7c478bd9Sstevel@tonic-gate #define FMT_PTE "%llx" 268*7c478bd9Sstevel@tonic-gate 269*7c478bd9Sstevel@tonic-gate #endif 270*7c478bd9Sstevel@tonic-gate 271*7c478bd9Sstevel@tonic-gate 272*7c478bd9Sstevel@tonic-gate extern struct hat_mmu_info mmu; 273*7c478bd9Sstevel@tonic-gate 274*7c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 275*7c478bd9Sstevel@tonic-gate 276*7c478bd9Sstevel@tonic-gate 277*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 278*7c478bd9Sstevel@tonic-gate } 279*7c478bd9Sstevel@tonic-gate #endif 280*7c478bd9Sstevel@tonic-gate 281*7c478bd9Sstevel@tonic-gate #endif /* _VM_HAT_PTE_H */ 282