1c0da6274SZhi-Jun Robin Fu /* 2c0da6274SZhi-Jun Robin Fu * CDDL HEADER START 3c0da6274SZhi-Jun Robin Fu * 4c0da6274SZhi-Jun Robin Fu * The contents of this file are subject to the terms of the 5c0da6274SZhi-Jun Robin Fu * Common Development and Distribution License (the "License"). 6c0da6274SZhi-Jun Robin Fu * You may not use this file except in compliance with the License. 7c0da6274SZhi-Jun Robin Fu * 8c0da6274SZhi-Jun Robin Fu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9c0da6274SZhi-Jun Robin Fu * or http://www.opensolaris.org/os/licensing. 10c0da6274SZhi-Jun Robin Fu * See the License for the specific language governing permissions 11c0da6274SZhi-Jun Robin Fu * and limitations under the License. 12c0da6274SZhi-Jun Robin Fu * 13c0da6274SZhi-Jun Robin Fu * When distributing Covered Code, include this CDDL HEADER in each 14c0da6274SZhi-Jun Robin Fu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15c0da6274SZhi-Jun Robin Fu * If applicable, add the following below this CDDL HEADER, with the 16c0da6274SZhi-Jun Robin Fu * fields enclosed by brackets "[]" replaced with your own identifying 17c0da6274SZhi-Jun Robin Fu * information: Portions Copyright [yyyy] [name of copyright owner] 18c0da6274SZhi-Jun Robin Fu * 19c0da6274SZhi-Jun Robin Fu * CDDL HEADER END 20c0da6274SZhi-Jun Robin Fu */ 21c0da6274SZhi-Jun Robin Fu /* 22c0da6274SZhi-Jun Robin Fu * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23c0da6274SZhi-Jun Robin Fu * Use is subject to license terms. 24*6ecc4705SAndy Fiddaman * 25*6ecc4705SAndy Fiddaman * Copyright 2020 OmniOS Community Edition (OmniOSce) Association. 26*6ecc4705SAndy Fiddaman * 27c0da6274SZhi-Jun Robin Fu */ 28c0da6274SZhi-Jun Robin Fu 29c0da6274SZhi-Jun Robin Fu #ifndef _SYS_PCI_CFGACC_X86_H 30c0da6274SZhi-Jun Robin Fu #define _SYS_PCI_CFGACC_X86_H 31c0da6274SZhi-Jun Robin Fu 32c0da6274SZhi-Jun Robin Fu #ifdef __cplusplus 33c0da6274SZhi-Jun Robin Fu extern "C" { 34c0da6274SZhi-Jun Robin Fu #endif 35c0da6274SZhi-Jun Robin Fu 36c0da6274SZhi-Jun Robin Fu /* AMD's northbridges vendor-id and device-ids */ 37c0da6274SZhi-Jun Robin Fu #define AMD_NTBRDIGE_VID 0x1022 /* AMD vendor-id */ 38c0da6274SZhi-Jun Robin Fu #define AMD_HT_NTBRIDGE_DID 0x1100 /* HT Configuration */ 39c0da6274SZhi-Jun Robin Fu #define AMD_AM_NTBRIDGE_DID 0x1101 /* Address Map */ 40c0da6274SZhi-Jun Robin Fu #define AMD_DC_NTBRIDGE_DID 0x1102 /* DRAM Controller */ 41c0da6274SZhi-Jun Robin Fu #define AMD_MC_NTBRIDGE_DID 0x1103 /* Misc Controller */ 42c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_0 0x1200 43c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_1 0x1201 44c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_2 0x1202 45c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_3 0x1203 46c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_4 0x1204 47c0da6274SZhi-Jun Robin Fu 48c0da6274SZhi-Jun Robin Fu /* AMD's 8132 chipset vendor-id and device-ids */ 49c0da6274SZhi-Jun Robin Fu #define AMD_8132_BRIDGE_DID 0x7458 /* 8132 PCI-X bridge */ 50c0da6274SZhi-Jun Robin Fu #define AMD_8132_IOAPIC_DID 0x7459 /* 8132 IO APIC */ 51c0da6274SZhi-Jun Robin Fu 52c0da6274SZhi-Jun Robin Fu /* 53c0da6274SZhi-Jun Robin Fu * Check if the given device is an AMD northbridge 54c0da6274SZhi-Jun Robin Fu */ 55c0da6274SZhi-Jun Robin Fu #define IS_BAD_AMD_NTBRIDGE(vid, did) \ 56c0da6274SZhi-Jun Robin Fu (((vid) == AMD_NTBRDIGE_VID) && \ 57c0da6274SZhi-Jun Robin Fu (((did) == AMD_HT_NTBRIDGE_DID) || \ 58c0da6274SZhi-Jun Robin Fu ((did) == AMD_AM_NTBRIDGE_DID) || \ 59c0da6274SZhi-Jun Robin Fu ((did) == AMD_DC_NTBRIDGE_DID) || \ 60c0da6274SZhi-Jun Robin Fu ((did) == AMD_MC_NTBRIDGE_DID))) 61c0da6274SZhi-Jun Robin Fu 62c0da6274SZhi-Jun Robin Fu #define IS_K10_AMD_NTBRIDGE(vid, did) \ 63c0da6274SZhi-Jun Robin Fu (((vid) == AMD_NTBRDIGE_VID) && \ 64c0da6274SZhi-Jun Robin Fu (((did) == AMD_K10_NTBRIDGE_DID_0) || \ 65c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_1) || \ 66c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_2) || \ 67c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_3) || \ 68c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_4))) 69c0da6274SZhi-Jun Robin Fu 70c0da6274SZhi-Jun Robin Fu #define IS_AMD_8132_CHIP(vid, did) \ 71c0da6274SZhi-Jun Robin Fu (((vid) == AMD_NTBRDIGE_VID) && \ 72*6ecc4705SAndy Fiddaman (((did) == AMD_8132_BRIDGE_DID) || \ 73*6ecc4705SAndy Fiddaman ((did) == AMD_8132_IOAPIC_DID))) 74c0da6274SZhi-Jun Robin Fu 75c0da6274SZhi-Jun Robin Fu #define MSR_AMD_NB_MMIO_CFG_BADDR 0xc0010058 76c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ADDR_MASK 0xFFFFFFF00000ULL 77c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ENA_MASK 0x000000000001ULL 78c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ENA_ON 0x000000000001ULL 79c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ENA_OFF 0x000000000000ULL 80c0da6274SZhi-Jun Robin Fu 81c0da6274SZhi-Jun Robin Fu #ifdef __cplusplus 82c0da6274SZhi-Jun Robin Fu } 83c0da6274SZhi-Jun Robin Fu #endif 84c0da6274SZhi-Jun Robin Fu 85c0da6274SZhi-Jun Robin Fu #endif /* _SYS_PCI_CFGACC_X86_H */ 86