xref: /illumos-gate/usr/src/uts/i86pc/os/pci_orion.c (revision c88420b3)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  *
26  * Derived from pseudocode supplied by Intel.
27  */
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 /*
32  * Workaround for Intel Orion chipset bug
33  *
34  * It is intended that this code implements exactly the workaround
35  * described in the errata.  There is one exception, described below.
36  */
37 
38 #include <sys/types.h>
39 #include <sys/pci.h>
40 #include <sys/mutex.h>
41 #include <sys/pci_cfgspace_impl.h>
42 
43 #define	PCI_82454_RW_CONTROL	0x54
44 
45 static int ncDevNo;
46 
47 boolean_t
pci_is_broken_orion()48 pci_is_broken_orion()
49 {
50 	int		Num82454 = 0;
51 	boolean_t	A2B0Found = B_FALSE;
52 	boolean_t	c82454PostingEnabled = B_FALSE;
53 	uint8_t		PciReg;
54 	uint16_t	VendorID;
55 	uint16_t	DeviceID;
56 	boolean_t	A2B0WorkAroundReqd;
57 
58 	int		BusNo = 0;
59 	int		FunctionNo = 0;
60 	int		DeviceNo;
61 	uint8_t		RevisionID;
62 
63 	for (DeviceNo = 0; DeviceNo < PCI_MAX_DEVS; DeviceNo++) {
64 		VendorID = pci_mech1_getw(BusNo, DeviceNo, FunctionNo,
65 						PCI_CONF_VENID);
66 		DeviceID = pci_mech1_getw(BusNo, DeviceNo, FunctionNo,
67 						PCI_CONF_DEVID);
68 		RevisionID = pci_mech1_getb(BusNo, DeviceNo, FunctionNo,
69 						PCI_CONF_REVID);
70 		if (VendorID == 0x8086 && DeviceID == 0x84c4) {
71 			/* Found 82454 PCI Bridge */
72 			Num82454++;
73 			if (RevisionID <= 4) {
74 				A2B0Found = B_TRUE;
75 			}
76 			if (DeviceNo == (0xc8 >> 3)) {
77 				/*
78 				 * c82454 Found - determine the status of
79 				 * inbound posting.
80 				 */
81 				PciReg = pci_mech1_getb(BusNo, DeviceNo,
82 					FunctionNo, PCI_82454_RW_CONTROL);
83 				if (PciReg & 0x01) {
84 					c82454PostingEnabled = B_TRUE;
85 				}
86 			} else {
87 				/* nc82454 Found - store device no. */
88 				ncDevNo = DeviceNo;
89 			}
90 		}
91 	} /* DeviceNo */
92 	/*
93 	 * Determine if nc82454 posting is to be enabled
94 	 * and need of workaround.
95 	 *
96 	 * [[ This is a deviation from the pseudocode in the errata.
97 	 *    The errata has mismatched braces, leading to uncertainty
98 	 *    as to whether this code is inside the test for 8086/84c4.
99 	 *    The errata has this code clearly inside the DeviceNo loop.
100 	 *    This code is obviously pointless until you've at least found
101 	 *    the second 82454, and there's no need to execute it more
102 	 *    than once, so I'm moving it outside that loop to execute
103 	 *    once on completion of the scan. ]]
104 	 */
105 	if (Num82454 >= 2 && A2B0Found &&
106 	    c82454PostingEnabled) {
107 		A2B0WorkAroundReqd = B_TRUE;
108 		/* Enable inbound posting on nc82454 */
109 		PciReg = pci_mech1_getb(0, ncDevNo, 0,
110 			PCI_82454_RW_CONTROL);
111 		PciReg |= 0x01;
112 		pci_mech1_putb(0, ncDevNo, 0,
113 			PCI_82454_RW_CONTROL, PciReg);
114 	} else {
115 		A2B0WorkAroundReqd = B_FALSE;
116 	}
117 
118 	return (A2B0WorkAroundReqd);
119 }
120 
121 /*
122  * When I first read this code in the errata document, I asked "why doesn't
123  * the initial read of CFC (possibly) lead to the 'two responses' problem?"
124  *
125  * After thinking about it for a while, the answer is that we're trying to
126  * talk to the nc82454 itself.  The c82454 doesn't have the problem, so it
127  * will recognize that this request is *not* for it, and won't respond.
128  * The nc82454 will either respond or not, depending on whether it "saw"
129  * the CF8 write, and if it responds it might or might not return the
130  * right data.  That's all pretty much OK, if we're willing to assume
131  * that the only way that 84C48086 will come back is from the vendor ID/
132  * device ID registers on the nc82454.  This is probabilistic, of course,
133  * because the nc82454 *could* be pointing at a register on some device
134  * that just *happened* to have that value, but that seems unlikely.
135  */
136 static void
FuncDisableInboundPostingnc82454()137 FuncDisableInboundPostingnc82454()
138 {
139 	uint32_t	test;
140 	uint8_t		PciReg;
141 
142 	mutex_enter(&pcicfg_chipset_mutex);
143 	do {
144 		test = pci_mech1_getl(0, ncDevNo, 0, PCI_CONF_VENID);
145 	} while (test != 0x84c48086UL);
146 
147 	/*
148 	 * At this point we are guaranteed to be pointing to the nc82454 PCI
149 	 * bridge Vendor ID register.
150 	 */
151 	do {
152 		/*
153 		 * Impact of the erratum is that the configuration read will
154 		 * return the value which was last read.
155 		 * Hence read register 0x54 until the previous read value
156 		 * (VendorId/DeviceId) is not read anymore.
157 		 */
158 		test = pci_mech1_getl(0, ncDevNo, 0, PCI_82454_RW_CONTROL);
159 	} while (test == 0x84c48086UL);
160 	/*
161 	 * At this point we are guaranteed to be pointing to the PCI
162 	 * Read/Write Control Register in the nc82454 PCI Bridge.
163 	 */
164 	PciReg = pci_mech1_getb(0, ncDevNo, 0, PCI_82454_RW_CONTROL);
165 	PciReg &= ~0x01;
166 	pci_mech1_putb(0, ncDevNo, 0, PCI_82454_RW_CONTROL, PciReg);
167 }
168 
169 static void
FuncEnableInboundPostingnc82454()170 FuncEnableInboundPostingnc82454()
171 {
172 	uint8_t PciReg;
173 
174 	PciReg = pci_mech1_getb(0, ncDevNo, 0, PCI_82454_RW_CONTROL);
175 	PciReg |= 0x01;
176 	pci_mech1_putb(0, ncDevNo, 0, PCI_82454_RW_CONTROL, PciReg);
177 	mutex_exit(&pcicfg_chipset_mutex);
178 }
179 
180 uint8_t
pci_orion_getb(int bus,int device,int function,int reg)181 pci_orion_getb(int bus, int device, int function, int reg)
182 {
183 	uint8_t	val;
184 
185 	FuncDisableInboundPostingnc82454();
186 
187 	val = pci_mech1_getb(bus, device, function, reg);
188 
189 	FuncEnableInboundPostingnc82454();
190 	return (val);
191 }
192 
193 uint16_t
pci_orion_getw(int bus,int device,int function,int reg)194 pci_orion_getw(int bus, int device, int function, int reg)
195 {
196 	uint16_t val;
197 
198 	FuncDisableInboundPostingnc82454();
199 
200 	val = pci_mech1_getw(bus, device, function, reg);
201 
202 	FuncEnableInboundPostingnc82454();
203 	return (val);
204 }
205 
206 uint32_t
pci_orion_getl(int bus,int device,int function,int reg)207 pci_orion_getl(int bus, int device, int function, int reg)
208 {
209 	uint32_t	val;
210 
211 	FuncDisableInboundPostingnc82454();
212 
213 	val = pci_mech1_getl(bus, device, function, reg);
214 
215 	FuncEnableInboundPostingnc82454();
216 	return (val);
217 }
218 
219 void
pci_orion_putb(int bus,int device,int function,int reg,uint8_t val)220 pci_orion_putb(int bus, int device, int function, int reg, uint8_t val)
221 {
222 	FuncDisableInboundPostingnc82454();
223 
224 	pci_mech1_putb(bus, device, function, reg, val);
225 
226 	FuncEnableInboundPostingnc82454();
227 }
228 
229 void
pci_orion_putw(int bus,int device,int function,int reg,uint16_t val)230 pci_orion_putw(int bus, int device, int function, int reg, uint16_t val)
231 {
232 	FuncDisableInboundPostingnc82454();
233 
234 	pci_mech1_putw(bus, device, function, reg, val);
235 
236 	FuncEnableInboundPostingnc82454();
237 }
238 
239 void
pci_orion_putl(int bus,int device,int function,int reg,uint32_t val)240 pci_orion_putl(int bus, int device, int function, int reg, uint32_t val)
241 {
242 	FuncDisableInboundPostingnc82454();
243 
244 	pci_mech1_putl(bus, device, function, reg, val);
245 
246 	FuncEnableInboundPostingnc82454();
247 }
248