xref: /illumos-gate/usr/src/uts/i86pc/os/pci_mech2.c (revision 1636e047)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
57c478bd9Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
67c478bd9Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
77c478bd9Sstevel@tonic-gate  * with the License.
87c478bd9Sstevel@tonic-gate  *
97c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
107c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
117c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
127c478bd9Sstevel@tonic-gate  * and limitations under the License.
137c478bd9Sstevel@tonic-gate  *
147c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
157c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
167c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
177c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
187c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
197c478bd9Sstevel@tonic-gate  *
207c478bd9Sstevel@tonic-gate  * CDDL HEADER END
217c478bd9Sstevel@tonic-gate  */
227c478bd9Sstevel@tonic-gate /*
23c88420b3Sdmick  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
247c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
257c478bd9Sstevel@tonic-gate  */
267c478bd9Sstevel@tonic-gate 
27*1636e047SRobert Mustacchi /*
28*1636e047SRobert Mustacchi  * Copyright 2021 Oxide Computer Company
29*1636e047SRobert Mustacchi  */
307c478bd9Sstevel@tonic-gate 
317c478bd9Sstevel@tonic-gate /*
327c478bd9Sstevel@tonic-gate  * PCI Mechanism 2 primitives
337c478bd9Sstevel@tonic-gate  */
347c478bd9Sstevel@tonic-gate 
357c478bd9Sstevel@tonic-gate #include <sys/types.h>
367c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
37*1636e047SRobert Mustacchi #include <sys/pci.h>
387c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h>
39c88420b3Sdmick #include <sys/pci_cfgspace_impl.h>
407c478bd9Sstevel@tonic-gate 
417c478bd9Sstevel@tonic-gate /*
427c478bd9Sstevel@tonic-gate  * The "mechanism 2" interface only has 4 bits for device number.  To
437c478bd9Sstevel@tonic-gate  * hide this implementation detail, we return all ones for accesses to
447c478bd9Sstevel@tonic-gate  * devices 16..31.
457c478bd9Sstevel@tonic-gate  */
467c478bd9Sstevel@tonic-gate #define	PCI_MAX_DEVS_2	16
477c478bd9Sstevel@tonic-gate 
487c478bd9Sstevel@tonic-gate /*
497c478bd9Sstevel@tonic-gate  * the PCI LOCAL BUS SPECIFICATION 2.0 does not say that you need to
507c478bd9Sstevel@tonic-gate  * save the value of the register and restore them.  The Intel chip
517c478bd9Sstevel@tonic-gate  * set documentation indicates that you should.
527c478bd9Sstevel@tonic-gate  */
537c478bd9Sstevel@tonic-gate static uint8_t
pci_mech2_config_enable(uchar_t bus,uchar_t function)547c478bd9Sstevel@tonic-gate pci_mech2_config_enable(uchar_t bus, uchar_t function)
557c478bd9Sstevel@tonic-gate {
567c478bd9Sstevel@tonic-gate 	uint8_t	old;
577c478bd9Sstevel@tonic-gate 
587c478bd9Sstevel@tonic-gate 	mutex_enter(&pcicfg_mutex);
597c478bd9Sstevel@tonic-gate 	old = inb(PCI_CSE_PORT);
607c478bd9Sstevel@tonic-gate 
617c478bd9Sstevel@tonic-gate 	outb(PCI_CSE_PORT,
62*1636e047SRobert Mustacchi 	    PCI_MECH2_CONFIG_ENABLE | ((function & PCI_FUNC_MASK) << 1));
637c478bd9Sstevel@tonic-gate 	outb(PCI_FORW_PORT, bus);
647c478bd9Sstevel@tonic-gate 
657c478bd9Sstevel@tonic-gate 	return (old);
667c478bd9Sstevel@tonic-gate }
677c478bd9Sstevel@tonic-gate 
687c478bd9Sstevel@tonic-gate static void
pci_mech2_config_restore(uint8_t oldstatus)697c478bd9Sstevel@tonic-gate pci_mech2_config_restore(uint8_t oldstatus)
707c478bd9Sstevel@tonic-gate {
717c478bd9Sstevel@tonic-gate 	outb(PCI_CSE_PORT, oldstatus);
727c478bd9Sstevel@tonic-gate 	mutex_exit(&pcicfg_mutex);
737c478bd9Sstevel@tonic-gate }
747c478bd9Sstevel@tonic-gate 
757c478bd9Sstevel@tonic-gate uint8_t
pci_mech2_getb(int bus,int device,int function,int reg)767c478bd9Sstevel@tonic-gate pci_mech2_getb(int bus, int device, int function, int reg)
777c478bd9Sstevel@tonic-gate {
787c478bd9Sstevel@tonic-gate 	uint8_t tmp;
797c478bd9Sstevel@tonic-gate 	uint8_t val;
807c478bd9Sstevel@tonic-gate 
81*1636e047SRobert Mustacchi 	if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
82*1636e047SRobert Mustacchi 		return (PCI_EINVAL8);
837c478bd9Sstevel@tonic-gate 
847c478bd9Sstevel@tonic-gate 	tmp = pci_mech2_config_enable(bus, function);
857c478bd9Sstevel@tonic-gate 	val = inb(PCI_CADDR2(device, reg));
867c478bd9Sstevel@tonic-gate 	pci_mech2_config_restore(tmp);
877c478bd9Sstevel@tonic-gate 
887c478bd9Sstevel@tonic-gate 	return (val);
897c478bd9Sstevel@tonic-gate }
907c478bd9Sstevel@tonic-gate 
917c478bd9Sstevel@tonic-gate uint16_t
pci_mech2_getw(int bus,int device,int function,int reg)927c478bd9Sstevel@tonic-gate pci_mech2_getw(int bus, int device, int function, int reg)
937c478bd9Sstevel@tonic-gate {
947c478bd9Sstevel@tonic-gate 	uint8_t	tmp;
957c478bd9Sstevel@tonic-gate 	uint16_t val;
967c478bd9Sstevel@tonic-gate 
97*1636e047SRobert Mustacchi 	if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
98*1636e047SRobert Mustacchi 		return (PCI_EINVAL16);
997c478bd9Sstevel@tonic-gate 
1007c478bd9Sstevel@tonic-gate 	tmp = pci_mech2_config_enable(bus, function);
1017c478bd9Sstevel@tonic-gate 	val = inw(PCI_CADDR2(device, reg));
1027c478bd9Sstevel@tonic-gate 	pci_mech2_config_restore(tmp);
1037c478bd9Sstevel@tonic-gate 
1047c478bd9Sstevel@tonic-gate 	return (val);
1057c478bd9Sstevel@tonic-gate }
1067c478bd9Sstevel@tonic-gate 
1077c478bd9Sstevel@tonic-gate uint32_t
pci_mech2_getl(int bus,int device,int function,int reg)1087c478bd9Sstevel@tonic-gate pci_mech2_getl(int bus, int device, int function, int reg)
1097c478bd9Sstevel@tonic-gate {
1107c478bd9Sstevel@tonic-gate 	uint8_t		tmp;
1117c478bd9Sstevel@tonic-gate 	uint32_t	val;
1127c478bd9Sstevel@tonic-gate 
113*1636e047SRobert Mustacchi 	if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
114*1636e047SRobert Mustacchi 		return (PCI_EINVAL32);
1157c478bd9Sstevel@tonic-gate 
1167c478bd9Sstevel@tonic-gate 	tmp = pci_mech2_config_enable(bus, function);
1177c478bd9Sstevel@tonic-gate 	val = inl(PCI_CADDR2(device, reg));
1187c478bd9Sstevel@tonic-gate 	pci_mech2_config_restore(tmp);
1197c478bd9Sstevel@tonic-gate 
1207c478bd9Sstevel@tonic-gate 	return (val);
1217c478bd9Sstevel@tonic-gate }
1227c478bd9Sstevel@tonic-gate 
1237c478bd9Sstevel@tonic-gate void
pci_mech2_putb(int bus,int device,int function,int reg,uint8_t val)1247c478bd9Sstevel@tonic-gate pci_mech2_putb(int bus, int device, int function, int reg, uint8_t val)
1257c478bd9Sstevel@tonic-gate {
1267c478bd9Sstevel@tonic-gate 	uint8_t	tmp;
1277c478bd9Sstevel@tonic-gate 
128*1636e047SRobert Mustacchi 	if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
1297c478bd9Sstevel@tonic-gate 		return;
1307c478bd9Sstevel@tonic-gate 
1317c478bd9Sstevel@tonic-gate 	tmp = pci_mech2_config_enable(bus, function);
1327c478bd9Sstevel@tonic-gate 	outb(PCI_CADDR2(device, reg), val);
1337c478bd9Sstevel@tonic-gate 	pci_mech2_config_restore(tmp);
1347c478bd9Sstevel@tonic-gate }
1357c478bd9Sstevel@tonic-gate 
1367c478bd9Sstevel@tonic-gate void
pci_mech2_putw(int bus,int device,int function,int reg,uint16_t val)1377c478bd9Sstevel@tonic-gate pci_mech2_putw(int bus, int device, int function, int reg, uint16_t val)
1387c478bd9Sstevel@tonic-gate {
1397c478bd9Sstevel@tonic-gate 	uint8_t	tmp;
1407c478bd9Sstevel@tonic-gate 
141*1636e047SRobert Mustacchi 	if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
1427c478bd9Sstevel@tonic-gate 		return;
1437c478bd9Sstevel@tonic-gate 
1447c478bd9Sstevel@tonic-gate 	tmp = pci_mech2_config_enable(bus, function);
1457c478bd9Sstevel@tonic-gate 	outw(PCI_CADDR2(device, reg), val);
1467c478bd9Sstevel@tonic-gate 	pci_mech2_config_restore(tmp);
1477c478bd9Sstevel@tonic-gate }
1487c478bd9Sstevel@tonic-gate 
1497c478bd9Sstevel@tonic-gate void
pci_mech2_putl(int bus,int device,int function,int reg,uint32_t val)1507c478bd9Sstevel@tonic-gate pci_mech2_putl(int bus, int device, int function, int reg, uint32_t val)
1517c478bd9Sstevel@tonic-gate {
1527c478bd9Sstevel@tonic-gate 	uint8_t	tmp;
1537c478bd9Sstevel@tonic-gate 
154*1636e047SRobert Mustacchi 	if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
1557c478bd9Sstevel@tonic-gate 		return;
1567c478bd9Sstevel@tonic-gate 
1577c478bd9Sstevel@tonic-gate 	tmp = pci_mech2_config_enable(bus, function);
1587c478bd9Sstevel@tonic-gate 	outl(PCI_CADDR2(device, reg), val);
1597c478bd9Sstevel@tonic-gate 	pci_mech2_config_restore(tmp);
1607c478bd9Sstevel@tonic-gate }
161