17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 23*c88420b3Sdmick * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate /* 307c478bd9Sstevel@tonic-gate * PCI Mechanism 2 primitives 317c478bd9Sstevel@tonic-gate */ 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #include <sys/types.h> 347c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 357c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 36*c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 377c478bd9Sstevel@tonic-gate 387c478bd9Sstevel@tonic-gate /* 397c478bd9Sstevel@tonic-gate * The "mechanism 2" interface only has 4 bits for device number. To 407c478bd9Sstevel@tonic-gate * hide this implementation detail, we return all ones for accesses to 417c478bd9Sstevel@tonic-gate * devices 16..31. 427c478bd9Sstevel@tonic-gate */ 437c478bd9Sstevel@tonic-gate #define PCI_MAX_DEVS_2 16 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate /* 467c478bd9Sstevel@tonic-gate * the PCI LOCAL BUS SPECIFICATION 2.0 does not say that you need to 477c478bd9Sstevel@tonic-gate * save the value of the register and restore them. The Intel chip 487c478bd9Sstevel@tonic-gate * set documentation indicates that you should. 497c478bd9Sstevel@tonic-gate */ 507c478bd9Sstevel@tonic-gate static uint8_t 517c478bd9Sstevel@tonic-gate pci_mech2_config_enable(uchar_t bus, uchar_t function) 527c478bd9Sstevel@tonic-gate { 537c478bd9Sstevel@tonic-gate uint8_t old; 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate mutex_enter(&pcicfg_mutex); 567c478bd9Sstevel@tonic-gate old = inb(PCI_CSE_PORT); 577c478bd9Sstevel@tonic-gate 587c478bd9Sstevel@tonic-gate outb(PCI_CSE_PORT, 597c478bd9Sstevel@tonic-gate PCI_MECH2_CONFIG_ENABLE | ((function & PCI_FUNC_MASK) << 1)); 607c478bd9Sstevel@tonic-gate outb(PCI_FORW_PORT, bus); 617c478bd9Sstevel@tonic-gate 627c478bd9Sstevel@tonic-gate return (old); 637c478bd9Sstevel@tonic-gate } 647c478bd9Sstevel@tonic-gate 657c478bd9Sstevel@tonic-gate static void 667c478bd9Sstevel@tonic-gate pci_mech2_config_restore(uint8_t oldstatus) 677c478bd9Sstevel@tonic-gate { 687c478bd9Sstevel@tonic-gate outb(PCI_CSE_PORT, oldstatus); 697c478bd9Sstevel@tonic-gate mutex_exit(&pcicfg_mutex); 707c478bd9Sstevel@tonic-gate } 717c478bd9Sstevel@tonic-gate 727c478bd9Sstevel@tonic-gate uint8_t 737c478bd9Sstevel@tonic-gate pci_mech2_getb(int bus, int device, int function, int reg) 747c478bd9Sstevel@tonic-gate { 757c478bd9Sstevel@tonic-gate uint8_t tmp; 767c478bd9Sstevel@tonic-gate uint8_t val; 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate if (device >= PCI_MAX_DEVS_2) 797c478bd9Sstevel@tonic-gate return (0xff); 807c478bd9Sstevel@tonic-gate 817c478bd9Sstevel@tonic-gate tmp = pci_mech2_config_enable(bus, function); 827c478bd9Sstevel@tonic-gate val = inb(PCI_CADDR2(device, reg)); 837c478bd9Sstevel@tonic-gate pci_mech2_config_restore(tmp); 847c478bd9Sstevel@tonic-gate 857c478bd9Sstevel@tonic-gate return (val); 867c478bd9Sstevel@tonic-gate } 877c478bd9Sstevel@tonic-gate 887c478bd9Sstevel@tonic-gate uint16_t 897c478bd9Sstevel@tonic-gate pci_mech2_getw(int bus, int device, int function, int reg) 907c478bd9Sstevel@tonic-gate { 917c478bd9Sstevel@tonic-gate uint8_t tmp; 927c478bd9Sstevel@tonic-gate uint16_t val; 937c478bd9Sstevel@tonic-gate 947c478bd9Sstevel@tonic-gate if (device >= PCI_MAX_DEVS_2) 957c478bd9Sstevel@tonic-gate return (0xffff); 967c478bd9Sstevel@tonic-gate 977c478bd9Sstevel@tonic-gate tmp = pci_mech2_config_enable(bus, function); 987c478bd9Sstevel@tonic-gate val = inw(PCI_CADDR2(device, reg)); 997c478bd9Sstevel@tonic-gate pci_mech2_config_restore(tmp); 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate return (val); 1027c478bd9Sstevel@tonic-gate } 1037c478bd9Sstevel@tonic-gate 1047c478bd9Sstevel@tonic-gate uint32_t 1057c478bd9Sstevel@tonic-gate pci_mech2_getl(int bus, int device, int function, int reg) 1067c478bd9Sstevel@tonic-gate { 1077c478bd9Sstevel@tonic-gate uint8_t tmp; 1087c478bd9Sstevel@tonic-gate uint32_t val; 1097c478bd9Sstevel@tonic-gate 1107c478bd9Sstevel@tonic-gate if (device >= PCI_MAX_DEVS_2) 1117c478bd9Sstevel@tonic-gate return (0xffffffffu); 1127c478bd9Sstevel@tonic-gate 1137c478bd9Sstevel@tonic-gate tmp = pci_mech2_config_enable(bus, function); 1147c478bd9Sstevel@tonic-gate val = inl(PCI_CADDR2(device, reg)); 1157c478bd9Sstevel@tonic-gate pci_mech2_config_restore(tmp); 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate return (val); 1187c478bd9Sstevel@tonic-gate } 1197c478bd9Sstevel@tonic-gate 1207c478bd9Sstevel@tonic-gate void 1217c478bd9Sstevel@tonic-gate pci_mech2_putb(int bus, int device, int function, int reg, uint8_t val) 1227c478bd9Sstevel@tonic-gate { 1237c478bd9Sstevel@tonic-gate uint8_t tmp; 1247c478bd9Sstevel@tonic-gate 1257c478bd9Sstevel@tonic-gate if (device >= PCI_MAX_DEVS_2) 1267c478bd9Sstevel@tonic-gate return; 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate tmp = pci_mech2_config_enable(bus, function); 1297c478bd9Sstevel@tonic-gate outb(PCI_CADDR2(device, reg), val); 1307c478bd9Sstevel@tonic-gate pci_mech2_config_restore(tmp); 1317c478bd9Sstevel@tonic-gate } 1327c478bd9Sstevel@tonic-gate 1337c478bd9Sstevel@tonic-gate void 1347c478bd9Sstevel@tonic-gate pci_mech2_putw(int bus, int device, int function, int reg, uint16_t val) 1357c478bd9Sstevel@tonic-gate { 1367c478bd9Sstevel@tonic-gate uint8_t tmp; 1377c478bd9Sstevel@tonic-gate 1387c478bd9Sstevel@tonic-gate if (device >= PCI_MAX_DEVS_2) 1397c478bd9Sstevel@tonic-gate return; 1407c478bd9Sstevel@tonic-gate 1417c478bd9Sstevel@tonic-gate tmp = pci_mech2_config_enable(bus, function); 1427c478bd9Sstevel@tonic-gate outw(PCI_CADDR2(device, reg), val); 1437c478bd9Sstevel@tonic-gate pci_mech2_config_restore(tmp); 1447c478bd9Sstevel@tonic-gate } 1457c478bd9Sstevel@tonic-gate 1467c478bd9Sstevel@tonic-gate void 1477c478bd9Sstevel@tonic-gate pci_mech2_putl(int bus, int device, int function, int reg, uint32_t val) 1487c478bd9Sstevel@tonic-gate { 1497c478bd9Sstevel@tonic-gate uint8_t tmp; 1507c478bd9Sstevel@tonic-gate 1517c478bd9Sstevel@tonic-gate if (device >= PCI_MAX_DEVS_2) 1527c478bd9Sstevel@tonic-gate return; 1537c478bd9Sstevel@tonic-gate 1547c478bd9Sstevel@tonic-gate tmp = pci_mech2_config_enable(bus, function); 1557c478bd9Sstevel@tonic-gate outl(PCI_CADDR2(device, reg), val); 1567c478bd9Sstevel@tonic-gate pci_mech2_config_restore(tmp); 1577c478bd9Sstevel@tonic-gate } 158