17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5100b72f4Sandrei * Common Development and Distribution License (the "License"). 6100b72f4Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21ae115bc7Smrj 227c478bd9Sstevel@tonic-gate /* 23b9e93c10SJonathan Haslam * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #include <sys/types.h> 287c478bd9Sstevel@tonic-gate #include <sys/thread.h> 297c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 307c478bd9Sstevel@tonic-gate #include <sys/t_lock.h> 317c478bd9Sstevel@tonic-gate #include <sys/param.h> 327c478bd9Sstevel@tonic-gate #include <sys/proc.h> 337c478bd9Sstevel@tonic-gate #include <sys/disp.h> 347c478bd9Sstevel@tonic-gate #include <sys/class.h> 357c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 367c478bd9Sstevel@tonic-gate #include <sys/debug.h> 377c478bd9Sstevel@tonic-gate #include <sys/asm_linkage.h> 387c478bd9Sstevel@tonic-gate #include <sys/x_call.h> 397c478bd9Sstevel@tonic-gate #include <sys/systm.h> 407c478bd9Sstevel@tonic-gate #include <sys/var.h> 417c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 427c478bd9Sstevel@tonic-gate #include <vm/hat.h> 437c478bd9Sstevel@tonic-gate #include <vm/as.h> 447c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 45ae115bc7Smrj #include <vm/seg_kp.h> 467c478bd9Sstevel@tonic-gate #include <sys/segments.h> 477c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 487c478bd9Sstevel@tonic-gate #include <sys/stack.h> 497c478bd9Sstevel@tonic-gate #include <sys/smp_impldefs.h> 507c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 517c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 527c478bd9Sstevel@tonic-gate #include <sys/traptrace.h> 537c478bd9Sstevel@tonic-gate #include <sys/clock.h> 547c478bd9Sstevel@tonic-gate #include <sys/cpc_impl.h> 55fb2f18f8Sesaxe #include <sys/pg.h> 56fb2f18f8Sesaxe #include <sys/cmt.h> 577c478bd9Sstevel@tonic-gate #include <sys/dtrace.h> 587c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 597c478bd9Sstevel@tonic-gate #include <sys/fp.h> 607c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 61ae115bc7Smrj #include <sys/kdi_machimpl.h> 627c478bd9Sstevel@tonic-gate #include <vm/hat_i86.h> 637c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 64ef50d8c0Sesaxe #include <sys/pci_cfgspace.h> 65ae115bc7Smrj #include <sys/mach_mmu.h> 66ae115bc7Smrj #include <sys/sysmacros.h> 67843e1988Sjohnlev #if defined(__xpv) 68843e1988Sjohnlev #include <sys/hypervisor.h> 69843e1988Sjohnlev #endif 707aec1d6eScindi #include <sys/cpu_module.h> 717c478bd9Sstevel@tonic-gate 727c478bd9Sstevel@tonic-gate struct cpu cpus[1]; /* CPU data */ 737c478bd9Sstevel@tonic-gate struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 747c478bd9Sstevel@tonic-gate cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 757c478bd9Sstevel@tonic-gate 767c478bd9Sstevel@tonic-gate /* 77ae115bc7Smrj * Useful for disabling MP bring-up on a MP capable system. 787c478bd9Sstevel@tonic-gate */ 797c478bd9Sstevel@tonic-gate int use_mp = 1; 807c478bd9Sstevel@tonic-gate 8141791439Sandrei /* 82ae115bc7Smrj * to be set by a PSM to indicate what cpus 83ae115bc7Smrj * are sitting around on the system. 8441791439Sandrei */ 85ae115bc7Smrj cpuset_t mp_cpus; 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate /* 887c478bd9Sstevel@tonic-gate * This variable is used by the hat layer to decide whether or not 897c478bd9Sstevel@tonic-gate * critical sections are needed to prevent race conditions. For sun4m, 907c478bd9Sstevel@tonic-gate * this variable is set once enough MP initialization has been done in 917c478bd9Sstevel@tonic-gate * order to allow cross calls. 927c478bd9Sstevel@tonic-gate */ 93ae115bc7Smrj int flushes_require_xcalls; 94a563a037Sbholler 95a563a037Sbholler cpuset_t cpu_ready_set; /* initialized in startup() */ 967c478bd9Sstevel@tonic-gate 977c478bd9Sstevel@tonic-gate static void mp_startup(void); 987c478bd9Sstevel@tonic-gate 997c478bd9Sstevel@tonic-gate static void cpu_sep_enable(void); 1007c478bd9Sstevel@tonic-gate static void cpu_sep_disable(void); 1017c478bd9Sstevel@tonic-gate static void cpu_asysc_enable(void); 1027c478bd9Sstevel@tonic-gate static void cpu_asysc_disable(void); 1037c478bd9Sstevel@tonic-gate 1047c478bd9Sstevel@tonic-gate /* 1057c478bd9Sstevel@tonic-gate * Init CPU info - get CPU type info for processor_info system call. 1067c478bd9Sstevel@tonic-gate */ 1077c478bd9Sstevel@tonic-gate void 1087c478bd9Sstevel@tonic-gate init_cpu_info(struct cpu *cp) 1097c478bd9Sstevel@tonic-gate { 1107c478bd9Sstevel@tonic-gate processor_info_t *pi = &cp->cpu_type_info; 1117c478bd9Sstevel@tonic-gate char buf[CPU_IDSTRLEN]; 1127c478bd9Sstevel@tonic-gate 1137c478bd9Sstevel@tonic-gate /* 1147c478bd9Sstevel@tonic-gate * Get clock-frequency property for the CPU. 1157c478bd9Sstevel@tonic-gate */ 1167c478bd9Sstevel@tonic-gate pi->pi_clock = cpu_freq; 1177c478bd9Sstevel@tonic-gate 1185cff7825Smh /* 1195cff7825Smh * Current frequency in Hz. 1205cff7825Smh */ 121cf74e62bSmh cp->cpu_curr_clock = cpu_freq_hz; 1225cff7825Smh 123*37d22dc0SAnup Pemmaiah /* 124*37d22dc0SAnup Pemmaiah * Supported frequencies. 125*37d22dc0SAnup Pemmaiah */ 126*37d22dc0SAnup Pemmaiah if (cp->cpu_supp_freqs == NULL) { 127*37d22dc0SAnup Pemmaiah cpu_set_supp_freqs(cp, NULL); 128*37d22dc0SAnup Pemmaiah } 129*37d22dc0SAnup Pemmaiah 1307c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_processor_type, "i386"); 1317c478bd9Sstevel@tonic-gate if (fpu_exists) 1327c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_fputypes, "i387 compatible"); 1337c478bd9Sstevel@tonic-gate 1347c478bd9Sstevel@tonic-gate (void) cpuid_getidstr(cp, buf, sizeof (buf)); 1357c478bd9Sstevel@tonic-gate 1367c478bd9Sstevel@tonic-gate cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 1377c478bd9Sstevel@tonic-gate (void) strcpy(cp->cpu_idstr, buf); 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 1407c478bd9Sstevel@tonic-gate cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 1417c478bd9Sstevel@tonic-gate (void) strcpy(cp->cpu_brandstr, buf); 1427c478bd9Sstevel@tonic-gate } 1437c478bd9Sstevel@tonic-gate 1447c478bd9Sstevel@tonic-gate /* 1457c478bd9Sstevel@tonic-gate * Configure syscall support on this CPU. 1467c478bd9Sstevel@tonic-gate */ 1477c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 1482df1fe9cSrandyf void 1497c478bd9Sstevel@tonic-gate init_cpu_syscall(struct cpu *cp) 1507c478bd9Sstevel@tonic-gate { 1517c478bd9Sstevel@tonic-gate kpreempt_disable(); 1527c478bd9Sstevel@tonic-gate 1537c478bd9Sstevel@tonic-gate #if defined(__amd64) 154ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 1557c478bd9Sstevel@tonic-gate 1567c478bd9Sstevel@tonic-gate #if !defined(__lint) 1577c478bd9Sstevel@tonic-gate /* 1587c478bd9Sstevel@tonic-gate * The syscall instruction imposes a certain ordering on 1597c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 1607c478bd9Sstevel@tonic-gate * here. 1617c478bd9Sstevel@tonic-gate */ 1627c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 1637c478bd9Sstevel@tonic-gate ASSERT(UDS_SEL == U32CS_SEL + 8); 1647c478bd9Sstevel@tonic-gate ASSERT(UCS_SEL == U32CS_SEL + 16); 1657c478bd9Sstevel@tonic-gate #endif 1667c478bd9Sstevel@tonic-gate /* 1677c478bd9Sstevel@tonic-gate * Turn syscall/sysret extensions on. 1687c478bd9Sstevel@tonic-gate */ 1697c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate /* 1727c478bd9Sstevel@tonic-gate * Program the magic registers .. 1737c478bd9Sstevel@tonic-gate */ 174ae115bc7Smrj wrmsr(MSR_AMD_STAR, 175ae115bc7Smrj ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 1760ac7d7d8Skucharsk wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 1770ac7d7d8Skucharsk wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 1787c478bd9Sstevel@tonic-gate 1797c478bd9Sstevel@tonic-gate /* 1807c478bd9Sstevel@tonic-gate * This list of flags is masked off the incoming 1817c478bd9Sstevel@tonic-gate * %rfl when we enter the kernel. 1827c478bd9Sstevel@tonic-gate */ 1830ac7d7d8Skucharsk wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 1847c478bd9Sstevel@tonic-gate } 1857c478bd9Sstevel@tonic-gate #endif 1867c478bd9Sstevel@tonic-gate 1877c478bd9Sstevel@tonic-gate /* 1887c478bd9Sstevel@tonic-gate * On 32-bit kernels, we use sysenter/sysexit because it's too 1897c478bd9Sstevel@tonic-gate * hard to use syscall/sysret, and it is more portable anyway. 1907c478bd9Sstevel@tonic-gate * 1917c478bd9Sstevel@tonic-gate * On 64-bit kernels on Nocona machines, the 32-bit syscall 1927c478bd9Sstevel@tonic-gate * variant isn't available to 32-bit applications, but sysenter is. 1937c478bd9Sstevel@tonic-gate */ 194ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 1957c478bd9Sstevel@tonic-gate 1967c478bd9Sstevel@tonic-gate #if !defined(__lint) 1977c478bd9Sstevel@tonic-gate /* 1987c478bd9Sstevel@tonic-gate * The sysenter instruction imposes a certain ordering on 1997c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 2007c478bd9Sstevel@tonic-gate * here. See "sysenter" in Intel document 245471-012, "IA-32 2017c478bd9Sstevel@tonic-gate * Intel Architecture Software Developer's Manual Volume 2: 2027c478bd9Sstevel@tonic-gate * Instruction Set Reference" 2037c478bd9Sstevel@tonic-gate */ 2047c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 2057c478bd9Sstevel@tonic-gate 2067c478bd9Sstevel@tonic-gate ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 2077c478bd9Sstevel@tonic-gate ASSERT32(UDS_SEL == UCS_SEL + 8); 2087c478bd9Sstevel@tonic-gate 2097c478bd9Sstevel@tonic-gate ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 2107c478bd9Sstevel@tonic-gate ASSERT64(UDS_SEL == U32CS_SEL + 8); 2117c478bd9Sstevel@tonic-gate #endif 2127c478bd9Sstevel@tonic-gate 2137c478bd9Sstevel@tonic-gate cpu_sep_enable(); 2147c478bd9Sstevel@tonic-gate 2157c478bd9Sstevel@tonic-gate /* 2167c478bd9Sstevel@tonic-gate * resume() sets this value to the base of the threads stack 2177c478bd9Sstevel@tonic-gate * via a context handler. 2187c478bd9Sstevel@tonic-gate */ 219ae115bc7Smrj wrmsr(MSR_INTC_SEP_ESP, 0); 2200ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 2217c478bd9Sstevel@tonic-gate } 2227c478bd9Sstevel@tonic-gate 2237c478bd9Sstevel@tonic-gate kpreempt_enable(); 2247c478bd9Sstevel@tonic-gate } 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate /* 2277c478bd9Sstevel@tonic-gate * Multiprocessor initialization. 2287c478bd9Sstevel@tonic-gate * 2297c478bd9Sstevel@tonic-gate * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 2307c478bd9Sstevel@tonic-gate * startup and idle threads for the specified CPU. 2317c478bd9Sstevel@tonic-gate */ 232ae115bc7Smrj struct cpu * 2337c478bd9Sstevel@tonic-gate mp_startup_init(int cpun) 2347c478bd9Sstevel@tonic-gate { 2357c478bd9Sstevel@tonic-gate struct cpu *cp; 2367c478bd9Sstevel@tonic-gate kthread_id_t tp; 2377c478bd9Sstevel@tonic-gate caddr_t sp; 2387c478bd9Sstevel@tonic-gate proc_t *procp; 239843e1988Sjohnlev #if !defined(__xpv) 2405b8a6efeSbholler extern int idle_cpu_prefer_mwait; 2410e751525SEric Saxe extern void cpu_idle_mwait(); 242843e1988Sjohnlev #endif 2437c478bd9Sstevel@tonic-gate extern void idle(); 2440e751525SEric Saxe extern void cpu_idle(); 2457c478bd9Sstevel@tonic-gate 2467c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 2477c478bd9Sstevel@tonic-gate trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 2487c478bd9Sstevel@tonic-gate #endif 2497c478bd9Sstevel@tonic-gate 2507c478bd9Sstevel@tonic-gate ASSERT(cpun < NCPU && cpu[cpun] == NULL); 2517c478bd9Sstevel@tonic-gate 252ae115bc7Smrj cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 253843e1988Sjohnlev #if !defined(__xpv) 2540e751525SEric Saxe if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) { 2555b8a6efeSbholler cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 2560e751525SEric Saxe cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 2570e751525SEric Saxe } else 258843e1988Sjohnlev #endif 2590e751525SEric Saxe cp->cpu_m.mcpu_idle_cpu = cpu_idle; 260f98fbcecSbholler 2617c478bd9Sstevel@tonic-gate procp = curthread->t_procp; 2627c478bd9Sstevel@tonic-gate 2637c478bd9Sstevel@tonic-gate mutex_enter(&cpu_lock); 2647c478bd9Sstevel@tonic-gate /* 2657c478bd9Sstevel@tonic-gate * Initialize the dispatcher first. 2667c478bd9Sstevel@tonic-gate */ 2677c478bd9Sstevel@tonic-gate disp_cpu_init(cp); 2687c478bd9Sstevel@tonic-gate mutex_exit(&cpu_lock); 2697c478bd9Sstevel@tonic-gate 270affbd3ccSkchow cpu_vm_data_init(cp); 271affbd3ccSkchow 2727c478bd9Sstevel@tonic-gate /* 2737c478bd9Sstevel@tonic-gate * Allocate and initialize the startup thread for this CPU. 2747c478bd9Sstevel@tonic-gate * Interrupt and process switch stacks get allocated later 2757c478bd9Sstevel@tonic-gate * when the CPU starts running. 2767c478bd9Sstevel@tonic-gate */ 2777c478bd9Sstevel@tonic-gate tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 2787c478bd9Sstevel@tonic-gate TS_STOPPED, maxclsyspri); 2797c478bd9Sstevel@tonic-gate 2807c478bd9Sstevel@tonic-gate /* 2817c478bd9Sstevel@tonic-gate * Set state to TS_ONPROC since this thread will start running 2827c478bd9Sstevel@tonic-gate * as soon as the CPU comes online. 2837c478bd9Sstevel@tonic-gate * 2847c478bd9Sstevel@tonic-gate * All the other fields of the thread structure are setup by 2857c478bd9Sstevel@tonic-gate * thread_create(). 2867c478bd9Sstevel@tonic-gate */ 2877c478bd9Sstevel@tonic-gate THREAD_ONPROC(tp, cp); 2887c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 2897c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 2907c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 2917c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 2927c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 2937c478bd9Sstevel@tonic-gate 2947c478bd9Sstevel@tonic-gate /* 2957c478bd9Sstevel@tonic-gate * Setup thread to start in mp_startup. 2967c478bd9Sstevel@tonic-gate */ 2977c478bd9Sstevel@tonic-gate sp = tp->t_stk; 2987c478bd9Sstevel@tonic-gate tp->t_pc = (uintptr_t)mp_startup; 2997c478bd9Sstevel@tonic-gate tp->t_sp = (uintptr_t)(sp - MINFRAME); 300ae115bc7Smrj #if defined(__amd64) 301ae115bc7Smrj tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 302ae115bc7Smrj #endif 3037c478bd9Sstevel@tonic-gate 3047c478bd9Sstevel@tonic-gate cp->cpu_id = cpun; 3057c478bd9Sstevel@tonic-gate cp->cpu_self = cp; 3067c478bd9Sstevel@tonic-gate cp->cpu_thread = tp; 3077c478bd9Sstevel@tonic-gate cp->cpu_lwp = NULL; 3087c478bd9Sstevel@tonic-gate cp->cpu_dispthread = tp; 3097c478bd9Sstevel@tonic-gate cp->cpu_dispatch_pri = DISP_PRIO(tp); 3107c478bd9Sstevel@tonic-gate 311da43ceabSsethg /* 312da43ceabSsethg * cpu_base_spl must be set explicitly here to prevent any blocking 313da43ceabSsethg * operations in mp_startup from causing the spl of the cpu to drop 314da43ceabSsethg * to 0 (allowing device interrupts before we're ready) in resume(). 315da43ceabSsethg * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 316da43ceabSsethg * As an extra bit of security on DEBUG kernels, this is enforced with 317da43ceabSsethg * an assertion in mp_startup() -- before cpu_base_spl is set to its 318da43ceabSsethg * proper value. 319da43ceabSsethg */ 320da43ceabSsethg cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 321da43ceabSsethg 3227c478bd9Sstevel@tonic-gate /* 3237c478bd9Sstevel@tonic-gate * Now, initialize per-CPU idle thread for this CPU. 3247c478bd9Sstevel@tonic-gate */ 3257c478bd9Sstevel@tonic-gate tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 3267c478bd9Sstevel@tonic-gate 3277c478bd9Sstevel@tonic-gate cp->cpu_idle_thread = tp; 3287c478bd9Sstevel@tonic-gate 3297c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3307c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3317c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3327c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3337c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3347c478bd9Sstevel@tonic-gate 335394b433dSesaxe /* 336fb2f18f8Sesaxe * Bootstrap the CPU's PG data 337394b433dSesaxe */ 338fb2f18f8Sesaxe pg_cpu_bootstrap(cp); 339394b433dSesaxe 3407c478bd9Sstevel@tonic-gate /* 341ae115bc7Smrj * Perform CPC initialization on the new CPU. 3427c478bd9Sstevel@tonic-gate */ 3437c478bd9Sstevel@tonic-gate kcpc_hw_init(cp); 3447c478bd9Sstevel@tonic-gate 3457c478bd9Sstevel@tonic-gate /* 3467c478bd9Sstevel@tonic-gate * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 3477c478bd9Sstevel@tonic-gate * for each CPU. 3487c478bd9Sstevel@tonic-gate */ 3497c478bd9Sstevel@tonic-gate setup_vaddr_for_ppcopy(cp); 3507c478bd9Sstevel@tonic-gate 3517c478bd9Sstevel@tonic-gate /* 352ae115bc7Smrj * Allocate page for new GDT and initialize from current GDT. 3537c478bd9Sstevel@tonic-gate */ 354ae115bc7Smrj #if !defined(__lint) 355ae115bc7Smrj ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 356ae115bc7Smrj #endif 3570cfdb603Sjosephb cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 3580cfdb603Sjosephb bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 3597c478bd9Sstevel@tonic-gate 360ae115bc7Smrj #if defined(__i386) 3617c478bd9Sstevel@tonic-gate /* 3627c478bd9Sstevel@tonic-gate * setup kernel %gs. 3637c478bd9Sstevel@tonic-gate */ 3647c478bd9Sstevel@tonic-gate set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 3657c478bd9Sstevel@tonic-gate SEL_KPL, 0, 1); 366ae115bc7Smrj #endif 3677c478bd9Sstevel@tonic-gate 3687c478bd9Sstevel@tonic-gate /* 3697c478bd9Sstevel@tonic-gate * If we have more than one node, each cpu gets a copy of IDT 3707c478bd9Sstevel@tonic-gate * local to its node. If this is a Pentium box, we use cpu 0's 3717c478bd9Sstevel@tonic-gate * IDT. cpu 0's IDT has been made read-only to workaround the 3727c478bd9Sstevel@tonic-gate * cmpxchgl register bug 3737c478bd9Sstevel@tonic-gate */ 3747c478bd9Sstevel@tonic-gate if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 3750cfdb603Sjosephb #if !defined(__lint) 3760cfdb603Sjosephb ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 3770cfdb603Sjosephb #endif 3780cfdb603Sjosephb cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 3790cfdb603Sjosephb bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 380ae115bc7Smrj } else { 3810cfdb603Sjosephb cp->cpu_idt = CPU->cpu_idt; 3827c478bd9Sstevel@tonic-gate } 3837c478bd9Sstevel@tonic-gate 3847c478bd9Sstevel@tonic-gate /* 385ae115bc7Smrj * Get interrupt priority data from cpu 0. 3867c478bd9Sstevel@tonic-gate */ 3877c478bd9Sstevel@tonic-gate cp->cpu_pri_data = CPU->cpu_pri_data; 3887c478bd9Sstevel@tonic-gate 3897c478bd9Sstevel@tonic-gate /* 390ae115bc7Smrj * alloc space for cpuid info 3917c478bd9Sstevel@tonic-gate */ 392ae115bc7Smrj cpuid_alloc_space(cp); 3937c478bd9Sstevel@tonic-gate 3942449e17fSsherrym /* 3952449e17fSsherrym * alloc space for ucode_info 3962449e17fSsherrym */ 3972449e17fSsherrym ucode_alloc_space(cp); 3982449e17fSsherrym 399ae115bc7Smrj hat_cpu_online(cp); 4007c478bd9Sstevel@tonic-gate 4017c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 4027c478bd9Sstevel@tonic-gate /* 403ae115bc7Smrj * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 4047c478bd9Sstevel@tonic-gate */ 4057c478bd9Sstevel@tonic-gate ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 4067c478bd9Sstevel@tonic-gate ttc->ttc_next = ttc->ttc_first; 4077c478bd9Sstevel@tonic-gate ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 4087c478bd9Sstevel@tonic-gate #endif 4097c478bd9Sstevel@tonic-gate /* 4107c478bd9Sstevel@tonic-gate * Record that we have another CPU. 4117c478bd9Sstevel@tonic-gate */ 4127c478bd9Sstevel@tonic-gate mutex_enter(&cpu_lock); 4137c478bd9Sstevel@tonic-gate /* 4147c478bd9Sstevel@tonic-gate * Initialize the interrupt threads for this CPU 4157c478bd9Sstevel@tonic-gate */ 416100b72f4Sandrei cpu_intr_alloc(cp, NINTR_THREADS); 4177c478bd9Sstevel@tonic-gate /* 4187c478bd9Sstevel@tonic-gate * Add CPU to list of available CPUs. It'll be on the active list 4197c478bd9Sstevel@tonic-gate * after mp_startup(). 4207c478bd9Sstevel@tonic-gate */ 4217c478bd9Sstevel@tonic-gate cpu_add_unit(cp); 4227c478bd9Sstevel@tonic-gate mutex_exit(&cpu_lock); 423ae115bc7Smrj 424ae115bc7Smrj return (cp); 425ae115bc7Smrj } 426ae115bc7Smrj 427ae115bc7Smrj /* 428ae115bc7Smrj * Undo what was done in mp_startup_init 429ae115bc7Smrj */ 430ae115bc7Smrj static void 431ae115bc7Smrj mp_startup_fini(struct cpu *cp, int error) 432ae115bc7Smrj { 433ae115bc7Smrj mutex_enter(&cpu_lock); 434ae115bc7Smrj 435ae115bc7Smrj /* 436ae115bc7Smrj * Remove the CPU from the list of available CPUs. 437ae115bc7Smrj */ 438ae115bc7Smrj cpu_del_unit(cp->cpu_id); 439ae115bc7Smrj 440ae115bc7Smrj if (error == ETIMEDOUT) { 441ae115bc7Smrj /* 442ae115bc7Smrj * The cpu was started, but never *seemed* to run any 443ae115bc7Smrj * code in the kernel; it's probably off spinning in its 444ae115bc7Smrj * own private world, though with potential references to 445ae115bc7Smrj * our kmem-allocated IDTs and GDTs (for example). 446ae115bc7Smrj * 447ae115bc7Smrj * Worse still, it may actually wake up some time later, 448ae115bc7Smrj * so rather than guess what it might or might not do, we 449ae115bc7Smrj * leave the fundamental data structures intact. 450ae115bc7Smrj */ 451ae115bc7Smrj cp->cpu_flags = 0; 452ae115bc7Smrj mutex_exit(&cpu_lock); 453ae115bc7Smrj return; 454ae115bc7Smrj } 455ae115bc7Smrj 456ae115bc7Smrj /* 457ae115bc7Smrj * At this point, the only threads bound to this CPU should 458ae115bc7Smrj * special per-cpu threads: it's idle thread, it's pause threads, 459ae115bc7Smrj * and it's interrupt threads. Clean these up. 460ae115bc7Smrj */ 461ae115bc7Smrj cpu_destroy_bound_threads(cp); 462ae115bc7Smrj cp->cpu_idle_thread = NULL; 463ae115bc7Smrj 464ae115bc7Smrj /* 465ae115bc7Smrj * Free the interrupt stack. 466ae115bc7Smrj */ 467ae115bc7Smrj segkp_release(segkp, 468ae115bc7Smrj cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 469ae115bc7Smrj 470ae115bc7Smrj mutex_exit(&cpu_lock); 471ae115bc7Smrj 472ae115bc7Smrj #ifdef TRAPTRACE 473ae115bc7Smrj /* 474ae115bc7Smrj * Discard the trap trace buffer 475ae115bc7Smrj */ 476ae115bc7Smrj { 477ae115bc7Smrj trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 478ae115bc7Smrj 479ae115bc7Smrj kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 480ae115bc7Smrj ttc->ttc_first = NULL; 481ae115bc7Smrj } 482ae115bc7Smrj #endif 483ae115bc7Smrj 484ae115bc7Smrj hat_cpu_offline(cp); 485ae115bc7Smrj 486ae115bc7Smrj cpuid_free_space(cp); 487ae115bc7Smrj 4882449e17fSsherrym ucode_free_space(cp); 4892449e17fSsherrym 4900cfdb603Sjosephb if (cp->cpu_idt != CPU->cpu_idt) 4910cfdb603Sjosephb kmem_free(cp->cpu_idt, PAGESIZE); 4920cfdb603Sjosephb cp->cpu_idt = NULL; 493ae115bc7Smrj 4940cfdb603Sjosephb kmem_free(cp->cpu_gdt, PAGESIZE); 4950cfdb603Sjosephb cp->cpu_gdt = NULL; 496ae115bc7Smrj 497ae115bc7Smrj teardown_vaddr_for_ppcopy(cp); 498ae115bc7Smrj 499ae115bc7Smrj kcpc_hw_fini(cp); 500ae115bc7Smrj 501ae115bc7Smrj cp->cpu_dispthread = NULL; 502ae115bc7Smrj cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 503ae115bc7Smrj 504ae115bc7Smrj cpu_vm_data_destroy(cp); 505ae115bc7Smrj 506ae115bc7Smrj mutex_enter(&cpu_lock); 507ae115bc7Smrj disp_cpu_fini(cp); 508ae115bc7Smrj mutex_exit(&cpu_lock); 509ae115bc7Smrj 510843e1988Sjohnlev #if !defined(__xpv) 5115b8a6efeSbholler if (cp->cpu_m.mcpu_mwait != NULL) 5125b8a6efeSbholler cpuid_mwait_free(cp); 513843e1988Sjohnlev #endif 514ae115bc7Smrj kmem_free(cp, sizeof (*cp)); 5157c478bd9Sstevel@tonic-gate } 5167c478bd9Sstevel@tonic-gate 5177c478bd9Sstevel@tonic-gate /* 5187c478bd9Sstevel@tonic-gate * Apply workarounds for known errata, and warn about those that are absent. 5197c478bd9Sstevel@tonic-gate * 5207c478bd9Sstevel@tonic-gate * System vendors occasionally create configurations which contain different 5217c478bd9Sstevel@tonic-gate * revisions of the CPUs that are almost but not exactly the same. At the 5227c478bd9Sstevel@tonic-gate * time of writing, this meant that their clock rates were the same, their 5237c478bd9Sstevel@tonic-gate * feature sets were the same, but the required workaround were -not- 5247c478bd9Sstevel@tonic-gate * necessarily the same. So, this routine is invoked on -every- CPU soon 5257c478bd9Sstevel@tonic-gate * after starting to make sure that the resulting system contains the most 5267c478bd9Sstevel@tonic-gate * pessimal set of workarounds needed to cope with *any* of the CPUs in the 5277c478bd9Sstevel@tonic-gate * system. 5287c478bd9Sstevel@tonic-gate * 529ef50d8c0Sesaxe * workaround_errata is invoked early in mlsetup() for CPU 0, and in 530ef50d8c0Sesaxe * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 531ef50d8c0Sesaxe * to acknowledging their readiness to the master, so this routine will 532ef50d8c0Sesaxe * never be executed by multiple CPUs in parallel, thus making updates to 533ef50d8c0Sesaxe * global data safe. 534ef50d8c0Sesaxe * 5352201b277Skucharsk * These workarounds are based on Rev 3.57 of the Revision Guide for 5362201b277Skucharsk * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 5377c478bd9Sstevel@tonic-gate */ 5387c478bd9Sstevel@tonic-gate 539ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 540ae115bc7Smrj int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 541ae115bc7Smrj #endif 542ae115bc7Smrj 5437c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 5447c478bd9Sstevel@tonic-gate int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 5457c478bd9Sstevel@tonic-gate #endif 5467c478bd9Sstevel@tonic-gate 5477c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 5487c478bd9Sstevel@tonic-gate int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 5497c478bd9Sstevel@tonic-gate #endif 5507c478bd9Sstevel@tonic-gate 551ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 552ae115bc7Smrj int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 553ae115bc7Smrj #endif 554ae115bc7Smrj 5557c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 5567c478bd9Sstevel@tonic-gate int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 5577c478bd9Sstevel@tonic-gate #endif 5587c478bd9Sstevel@tonic-gate 559ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 560ae115bc7Smrj int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 561ae115bc7Smrj #endif 562ae115bc7Smrj 5637c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 5647c478bd9Sstevel@tonic-gate int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 5657c478bd9Sstevel@tonic-gate #endif 5667c478bd9Sstevel@tonic-gate 5677c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 5687c478bd9Sstevel@tonic-gate int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 5697c478bd9Sstevel@tonic-gate #endif 5707c478bd9Sstevel@tonic-gate 5717c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 5727c478bd9Sstevel@tonic-gate int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 5737c478bd9Sstevel@tonic-gate #endif 5747c478bd9Sstevel@tonic-gate 5757c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 5767c478bd9Sstevel@tonic-gate int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 5777c478bd9Sstevel@tonic-gate #endif 5787c478bd9Sstevel@tonic-gate 5792201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 5802201b277Skucharsk int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 5812201b277Skucharsk #endif 5827c478bd9Sstevel@tonic-gate 583ef50d8c0Sesaxe #if defined(OPTERON_WORKAROUND_6336786) 584ef50d8c0Sesaxe int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 585ef50d8c0Sesaxe int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 586ef50d8c0Sesaxe #endif 587ef50d8c0Sesaxe 588ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 589ee88d2b9Skchow int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 590ee88d2b9Skchow #endif 591ee88d2b9Skchow 592512cf780Skchow #if defined(OPTERON_ERRATUM_298) 593512cf780Skchow int opteron_erratum_298; 594512cf780Skchow #endif 595512cf780Skchow 596ae115bc7Smrj static void 597ae115bc7Smrj workaround_warning(cpu_t *cp, uint_t erratum) 598ae115bc7Smrj { 599ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 600ae115bc7Smrj cp->cpu_id, erratum); 601ae115bc7Smrj } 602ae115bc7Smrj 603ae115bc7Smrj static void 604ae115bc7Smrj workaround_applied(uint_t erratum) 605ae115bc7Smrj { 606ae115bc7Smrj if (erratum > 1000000) 607ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 608ae115bc7Smrj erratum); 609ae115bc7Smrj else 610ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 611ae115bc7Smrj erratum); 612ae115bc7Smrj } 613ae115bc7Smrj 614ae115bc7Smrj static void 615ae115bc7Smrj msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 616ae115bc7Smrj { 617ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 618ae115bc7Smrj cp->cpu_id, rw, msr, error); 619ae115bc7Smrj } 6207c478bd9Sstevel@tonic-gate 62192564cb1Sesaxe /* 622d2aeaf66SEric Saxe * Determine the number of nodes in a Hammer / Greyhound / Griffin family 623d2aeaf66SEric Saxe * system. 62492564cb1Sesaxe */ 62592564cb1Sesaxe static uint_t 62692564cb1Sesaxe opteron_get_nnodes(void) 62792564cb1Sesaxe { 62892564cb1Sesaxe static uint_t nnodes = 0; 62992564cb1Sesaxe 630d2aeaf66SEric Saxe if (nnodes == 0) { 63192564cb1Sesaxe #ifdef DEBUG 632d2aeaf66SEric Saxe uint_t family; 63392564cb1Sesaxe 634d2aeaf66SEric Saxe /* 635d2aeaf66SEric Saxe * This routine uses a PCI config space based mechanism 636d2aeaf66SEric Saxe * for retrieving the number of nodes in the system. 637d2aeaf66SEric Saxe * Device 24, function 0, offset 0x60 as used here is not 638d2aeaf66SEric Saxe * AMD processor architectural, and may not work on processor 639d2aeaf66SEric Saxe * families other than those listed below. 640d2aeaf66SEric Saxe * 641d2aeaf66SEric Saxe * Callers of this routine must ensure that we're running on 642d2aeaf66SEric Saxe * a processor which supports this mechanism. 643d2aeaf66SEric Saxe * The assertion below is meant to catch calls on unsupported 644d2aeaf66SEric Saxe * processors. 645d2aeaf66SEric Saxe */ 646d2aeaf66SEric Saxe family = cpuid_getfamily(CPU); 647d2aeaf66SEric Saxe ASSERT(family == 0xf || family == 0x10 || family == 0x11); 64892564cb1Sesaxe #endif /* DEBUG */ 64992564cb1Sesaxe 65092564cb1Sesaxe /* 65192564cb1Sesaxe * Obtain the number of nodes in the system from 65292564cb1Sesaxe * bits [6:4] of the Node ID register on node 0. 65392564cb1Sesaxe * 65492564cb1Sesaxe * The actual node count is NodeID[6:4] + 1 65592564cb1Sesaxe * 65692564cb1Sesaxe * The Node ID register is accessed via function 0, 65792564cb1Sesaxe * offset 0x60. Node 0 is device 24. 65892564cb1Sesaxe */ 65992564cb1Sesaxe nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 66092564cb1Sesaxe } 66192564cb1Sesaxe return (nnodes); 66292564cb1Sesaxe } 66392564cb1Sesaxe 664843e1988Sjohnlev #if defined(__xpv) 665843e1988Sjohnlev 666843e1988Sjohnlev /* 667843e1988Sjohnlev * On dom0, we can determine the number of physical cpus on the machine. 668843e1988Sjohnlev * This number is important when figuring out what workarounds are 669843e1988Sjohnlev * appropriate, so compute it now. 670843e1988Sjohnlev */ 671c7158ae9Stariq uint_t 672843e1988Sjohnlev xen_get_nphyscpus(void) 673843e1988Sjohnlev { 674843e1988Sjohnlev static uint_t nphyscpus = 0; 675843e1988Sjohnlev 676843e1988Sjohnlev ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 677843e1988Sjohnlev 678843e1988Sjohnlev if (nphyscpus == 0) { 679843e1988Sjohnlev xen_sysctl_t op; 680843e1988Sjohnlev xen_sysctl_physinfo_t *pi = &op.u.physinfo; 681843e1988Sjohnlev 682843e1988Sjohnlev op.cmd = XEN_SYSCTL_physinfo; 683843e1988Sjohnlev op.interface_version = XEN_SYSCTL_INTERFACE_VERSION; 684843e1988Sjohnlev if (HYPERVISOR_sysctl(&op) == 0) 685843e1988Sjohnlev nphyscpus = pi->threads_per_core * 686843e1988Sjohnlev pi->cores_per_socket * pi->sockets_per_node * 687843e1988Sjohnlev pi->nr_nodes; 688843e1988Sjohnlev } 689843e1988Sjohnlev return (nphyscpus); 690843e1988Sjohnlev } 691843e1988Sjohnlev #endif 692843e1988Sjohnlev 693512cf780Skchow uint_t 694512cf780Skchow do_erratum_298(struct cpu *cpu) 695512cf780Skchow { 696512cf780Skchow static int osvwrc = -3; 697512cf780Skchow extern int osvw_opteron_erratum(cpu_t *, uint_t); 698512cf780Skchow 699512cf780Skchow /* 700512cf780Skchow * L2 Eviction May Occur During Processor Operation To Set 701512cf780Skchow * Accessed or Dirty Bit. 702512cf780Skchow */ 703512cf780Skchow if (osvwrc == -3) { 704512cf780Skchow osvwrc = osvw_opteron_erratum(cpu, 298); 705512cf780Skchow } else { 706512cf780Skchow /* osvw return codes should be consistent for all cpus */ 707512cf780Skchow ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 708512cf780Skchow } 709512cf780Skchow 710512cf780Skchow switch (osvwrc) { 711512cf780Skchow case 0: /* erratum is not present: do nothing */ 712512cf780Skchow break; 713512cf780Skchow case 1: /* erratum is present: BIOS workaround applied */ 714512cf780Skchow /* 715512cf780Skchow * check if workaround is actually in place and issue warning 716512cf780Skchow * if not. 717512cf780Skchow */ 718512cf780Skchow if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 719512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 720512cf780Skchow #if defined(OPTERON_ERRATUM_298) 721512cf780Skchow opteron_erratum_298++; 722512cf780Skchow #else 723512cf780Skchow workaround_warning(cpu, 298); 724512cf780Skchow return (1); 725512cf780Skchow #endif 726512cf780Skchow } 727512cf780Skchow break; 728512cf780Skchow case -1: /* cannot determine via osvw: check cpuid */ 729512cf780Skchow if ((cpuid_opteron_erratum(cpu, 298) > 0) && 730512cf780Skchow (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 731512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 732512cf780Skchow #if defined(OPTERON_ERRATUM_298) 733512cf780Skchow opteron_erratum_298++; 734512cf780Skchow #else 735512cf780Skchow workaround_warning(cpu, 298); 736512cf780Skchow return (1); 737512cf780Skchow #endif 738512cf780Skchow } 739512cf780Skchow break; 740512cf780Skchow } 741512cf780Skchow return (0); 742512cf780Skchow } 743512cf780Skchow 7447c478bd9Sstevel@tonic-gate uint_t 7457c478bd9Sstevel@tonic-gate workaround_errata(struct cpu *cpu) 7467c478bd9Sstevel@tonic-gate { 7477c478bd9Sstevel@tonic-gate uint_t missing = 0; 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate ASSERT(cpu == CPU); 7507c478bd9Sstevel@tonic-gate 7517c478bd9Sstevel@tonic-gate /*LINTED*/ 7527c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 88) > 0) { 7537c478bd9Sstevel@tonic-gate /* 7547c478bd9Sstevel@tonic-gate * SWAPGS May Fail To Read Correct GS Base 7557c478bd9Sstevel@tonic-gate */ 7567c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_88) 7577c478bd9Sstevel@tonic-gate /* 7587c478bd9Sstevel@tonic-gate * The workaround is an mfence in the relevant assembler code 7597c478bd9Sstevel@tonic-gate */ 760ae115bc7Smrj opteron_erratum_88++; 7617c478bd9Sstevel@tonic-gate #else 762ae115bc7Smrj workaround_warning(cpu, 88); 7637c478bd9Sstevel@tonic-gate missing++; 7647c478bd9Sstevel@tonic-gate #endif 7657c478bd9Sstevel@tonic-gate } 7667c478bd9Sstevel@tonic-gate 7677c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 91) > 0) { 7687c478bd9Sstevel@tonic-gate /* 7697c478bd9Sstevel@tonic-gate * Software Prefetches May Report A Page Fault 7707c478bd9Sstevel@tonic-gate */ 7717c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 7727c478bd9Sstevel@tonic-gate /* 7737c478bd9Sstevel@tonic-gate * fix is in trap.c 7747c478bd9Sstevel@tonic-gate */ 7757c478bd9Sstevel@tonic-gate opteron_erratum_91++; 7767c478bd9Sstevel@tonic-gate #else 777ae115bc7Smrj workaround_warning(cpu, 91); 7787c478bd9Sstevel@tonic-gate missing++; 7797c478bd9Sstevel@tonic-gate #endif 7807c478bd9Sstevel@tonic-gate } 7817c478bd9Sstevel@tonic-gate 7827c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 93) > 0) { 7837c478bd9Sstevel@tonic-gate /* 7847c478bd9Sstevel@tonic-gate * RSM Auto-Halt Restart Returns to Incorrect RIP 7857c478bd9Sstevel@tonic-gate */ 7867c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 7877c478bd9Sstevel@tonic-gate /* 7887c478bd9Sstevel@tonic-gate * fix is in trap.c 7897c478bd9Sstevel@tonic-gate */ 7907c478bd9Sstevel@tonic-gate opteron_erratum_93++; 7917c478bd9Sstevel@tonic-gate #else 792ae115bc7Smrj workaround_warning(cpu, 93); 7937c478bd9Sstevel@tonic-gate missing++; 7947c478bd9Sstevel@tonic-gate #endif 7957c478bd9Sstevel@tonic-gate } 7967c478bd9Sstevel@tonic-gate 7977c478bd9Sstevel@tonic-gate /*LINTED*/ 7987c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 95) > 0) { 7997c478bd9Sstevel@tonic-gate /* 8007c478bd9Sstevel@tonic-gate * RET Instruction May Return to Incorrect EIP 8017c478bd9Sstevel@tonic-gate */ 8027c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_95) 8037c478bd9Sstevel@tonic-gate #if defined(_LP64) 8047c478bd9Sstevel@tonic-gate /* 8057c478bd9Sstevel@tonic-gate * Workaround this by ensuring that 32-bit user code and 8067c478bd9Sstevel@tonic-gate * 64-bit kernel code never occupy the same address 8077c478bd9Sstevel@tonic-gate * range mod 4G. 8087c478bd9Sstevel@tonic-gate */ 8097c478bd9Sstevel@tonic-gate if (_userlimit32 > 0xc0000000ul) 8107c478bd9Sstevel@tonic-gate *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 8117c478bd9Sstevel@tonic-gate 8127c478bd9Sstevel@tonic-gate /*LINTED*/ 8137c478bd9Sstevel@tonic-gate ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 814ae115bc7Smrj opteron_erratum_95++; 8157c478bd9Sstevel@tonic-gate #endif /* _LP64 */ 8167c478bd9Sstevel@tonic-gate #else 817ae115bc7Smrj workaround_warning(cpu, 95); 8187c478bd9Sstevel@tonic-gate missing++; 819ae115bc7Smrj #endif 8207c478bd9Sstevel@tonic-gate } 8217c478bd9Sstevel@tonic-gate 8227c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 100) > 0) { 8237c478bd9Sstevel@tonic-gate /* 8247c478bd9Sstevel@tonic-gate * Compatibility Mode Branches Transfer to Illegal Address 8257c478bd9Sstevel@tonic-gate */ 8267c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 8277c478bd9Sstevel@tonic-gate /* 8287c478bd9Sstevel@tonic-gate * fix is in trap.c 8297c478bd9Sstevel@tonic-gate */ 8307c478bd9Sstevel@tonic-gate opteron_erratum_100++; 8317c478bd9Sstevel@tonic-gate #else 832ae115bc7Smrj workaround_warning(cpu, 100); 8337c478bd9Sstevel@tonic-gate missing++; 8347c478bd9Sstevel@tonic-gate #endif 8357c478bd9Sstevel@tonic-gate } 8367c478bd9Sstevel@tonic-gate 8377c478bd9Sstevel@tonic-gate /*LINTED*/ 8387c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 108) > 0) { 8397c478bd9Sstevel@tonic-gate /* 8407c478bd9Sstevel@tonic-gate * CPUID Instruction May Return Incorrect Model Number In 8417c478bd9Sstevel@tonic-gate * Some Processors 8427c478bd9Sstevel@tonic-gate */ 8437c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_108) 8447c478bd9Sstevel@tonic-gate /* 8457c478bd9Sstevel@tonic-gate * (Our cpuid-handling code corrects the model number on 8467c478bd9Sstevel@tonic-gate * those processors) 8477c478bd9Sstevel@tonic-gate */ 8487c478bd9Sstevel@tonic-gate #else 849ae115bc7Smrj workaround_warning(cpu, 108); 8507c478bd9Sstevel@tonic-gate missing++; 8517c478bd9Sstevel@tonic-gate #endif 8527c478bd9Sstevel@tonic-gate } 8537c478bd9Sstevel@tonic-gate 8547c478bd9Sstevel@tonic-gate /*LINTED*/ 855ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 109) > 0) do { 8567c478bd9Sstevel@tonic-gate /* 8577c478bd9Sstevel@tonic-gate * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 8587c478bd9Sstevel@tonic-gate */ 8597c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 860ae115bc7Smrj /* 861ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 862ae115bc7Smrj */ 863ae115bc7Smrj uint64_t value; 864ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 865ae115bc7Smrj int err; 866ae115bc7Smrj 867ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 868ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 869ae115bc7Smrj workaround_warning(cpu, 109); 870ae115bc7Smrj missing++; 871ae115bc7Smrj } 872ae115bc7Smrj if (value == 0) 8737c478bd9Sstevel@tonic-gate opteron_erratum_109++; 8747c478bd9Sstevel@tonic-gate #else 875ae115bc7Smrj workaround_warning(cpu, 109); 8767c478bd9Sstevel@tonic-gate missing++; 8777c478bd9Sstevel@tonic-gate #endif 878ae115bc7Smrj /*CONSTANTCONDITION*/ 879ae115bc7Smrj } while (0); 880ae115bc7Smrj 8817c478bd9Sstevel@tonic-gate /*LINTED*/ 8827c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 121) > 0) { 8837c478bd9Sstevel@tonic-gate /* 8847c478bd9Sstevel@tonic-gate * Sequential Execution Across Non_Canonical Boundary Caused 8857c478bd9Sstevel@tonic-gate * Processor Hang 8867c478bd9Sstevel@tonic-gate */ 8877c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 888ae115bc7Smrj #if defined(_LP64) 8897c478bd9Sstevel@tonic-gate /* 8907c478bd9Sstevel@tonic-gate * Erratum 121 is only present in long (64 bit) mode. 8917c478bd9Sstevel@tonic-gate * Workaround is to include the page immediately before the 8927c478bd9Sstevel@tonic-gate * va hole to eliminate the possibility of system hangs due to 8937c478bd9Sstevel@tonic-gate * sequential execution across the va hole boundary. 8947c478bd9Sstevel@tonic-gate */ 895ae115bc7Smrj if (opteron_erratum_121) 896ae115bc7Smrj opteron_erratum_121++; 897ae115bc7Smrj else { 898ae115bc7Smrj if (hole_start) { 899ae115bc7Smrj hole_start -= PAGESIZE; 900ae115bc7Smrj } else { 901ae115bc7Smrj /* 902ae115bc7Smrj * hole_start not yet initialized by 903ae115bc7Smrj * mmu_init. Initialize hole_start 904ae115bc7Smrj * with value to be subtracted. 905ae115bc7Smrj */ 906ae115bc7Smrj hole_start = PAGESIZE; 9077c478bd9Sstevel@tonic-gate } 908ae115bc7Smrj opteron_erratum_121++; 9097c478bd9Sstevel@tonic-gate } 910ae115bc7Smrj #endif /* _LP64 */ 9117c478bd9Sstevel@tonic-gate #else 912ae115bc7Smrj workaround_warning(cpu, 121); 9137c478bd9Sstevel@tonic-gate missing++; 9147c478bd9Sstevel@tonic-gate #endif 9157c478bd9Sstevel@tonic-gate } 9167c478bd9Sstevel@tonic-gate 9177c478bd9Sstevel@tonic-gate /*LINTED*/ 918ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 122) > 0) do { 9197c478bd9Sstevel@tonic-gate /* 920ae115bc7Smrj * TLB Flush Filter May Cause Coherency Problem in 9217c478bd9Sstevel@tonic-gate * Multiprocessor Systems 9227c478bd9Sstevel@tonic-gate */ 9237c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 924ae115bc7Smrj uint64_t value; 925ae115bc7Smrj const uint_t msr = MSR_AMD_HWCR; 926ae115bc7Smrj int error; 927ae115bc7Smrj 9287c478bd9Sstevel@tonic-gate /* 9297c478bd9Sstevel@tonic-gate * Erratum 122 is only present in MP configurations (multi-core 9307c478bd9Sstevel@tonic-gate * or multi-processor). 9317c478bd9Sstevel@tonic-gate */ 932843e1988Sjohnlev #if defined(__xpv) 933843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 934843e1988Sjohnlev break; 935843e1988Sjohnlev if (!opteron_erratum_122 && xen_get_nphyscpus() == 1) 936843e1988Sjohnlev break; 937843e1988Sjohnlev #else 93892564cb1Sesaxe if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 939ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu) == 1) 940ae115bc7Smrj break; 941843e1988Sjohnlev #endif 942ae115bc7Smrj /* disable TLB Flush Filter */ 943ae115bc7Smrj 944ae115bc7Smrj if ((error = checked_rdmsr(msr, &value)) != 0) { 945ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 946ae115bc7Smrj workaround_warning(cpu, 122); 947ae115bc7Smrj missing++; 948ae115bc7Smrj } else { 949ae115bc7Smrj value |= (uint64_t)AMD_HWCR_FFDIS; 950ae115bc7Smrj if ((error = checked_wrmsr(msr, value)) != 0) { 951ae115bc7Smrj msr_warning(cpu, "wr", msr, error); 952ae115bc7Smrj workaround_warning(cpu, 122); 953ae115bc7Smrj missing++; 954ae115bc7Smrj } 9557c478bd9Sstevel@tonic-gate } 956ae115bc7Smrj opteron_erratum_122++; 9577c478bd9Sstevel@tonic-gate #else 958ae115bc7Smrj workaround_warning(cpu, 122); 9597c478bd9Sstevel@tonic-gate missing++; 9607c478bd9Sstevel@tonic-gate #endif 961ae115bc7Smrj /*CONSTANTCONDITION*/ 962ae115bc7Smrj } while (0); 963403c216aSkchow 9647c478bd9Sstevel@tonic-gate /*LINTED*/ 965ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 123) > 0) do { 9667c478bd9Sstevel@tonic-gate /* 9677c478bd9Sstevel@tonic-gate * Bypassed Reads May Cause Data Corruption of System Hang in 9687c478bd9Sstevel@tonic-gate * Dual Core Processors 9697c478bd9Sstevel@tonic-gate */ 970ae115bc7Smrj #if defined(OPTERON_ERRATUM_123) 971ae115bc7Smrj uint64_t value; 972ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 973ae115bc7Smrj int err; 974ae115bc7Smrj 9757c478bd9Sstevel@tonic-gate /* 9767c478bd9Sstevel@tonic-gate * Erratum 123 applies only to multi-core cpus. 9777c478bd9Sstevel@tonic-gate */ 978ae115bc7Smrj if (cpuid_get_ncpu_per_chip(cpu) < 2) 979ae115bc7Smrj break; 980843e1988Sjohnlev #if defined(__xpv) 981843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 982843e1988Sjohnlev break; 983843e1988Sjohnlev #endif 984ae115bc7Smrj /* 985ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 986ae115bc7Smrj */ 987ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 988ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 989ae115bc7Smrj workaround_warning(cpu, 123); 990ae115bc7Smrj missing++; 9917c478bd9Sstevel@tonic-gate } 992ae115bc7Smrj if (value == 0) 993ae115bc7Smrj opteron_erratum_123++; 994ae115bc7Smrj #else 995ae115bc7Smrj workaround_warning(cpu, 123); 996ae115bc7Smrj missing++; 997ae115bc7Smrj 998403c216aSkchow #endif 999ae115bc7Smrj /*CONSTANTCONDITION*/ 1000ae115bc7Smrj } while (0); 10012201b277Skucharsk 10022201b277Skucharsk /*LINTED*/ 1003ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 131) > 0) do { 10042201b277Skucharsk /* 10052201b277Skucharsk * Multiprocessor Systems with Four or More Cores May Deadlock 10062201b277Skucharsk * Waiting for a Probe Response 10072201b277Skucharsk */ 1008ae115bc7Smrj #if defined(OPTERON_ERRATUM_131) 1009ae115bc7Smrj uint64_t nbcfg; 1010ae115bc7Smrj const uint_t msr = MSR_AMD_NB_CFG; 1011ae115bc7Smrj const uint64_t wabits = 1012ae115bc7Smrj AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1013ae115bc7Smrj int error; 1014ae115bc7Smrj 10152201b277Skucharsk /* 10162201b277Skucharsk * Erratum 131 applies to any system with four or more cores. 10172201b277Skucharsk */ 1018ae115bc7Smrj if (opteron_erratum_131) 1019ae115bc7Smrj break; 1020843e1988Sjohnlev #if defined(__xpv) 1021843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1022843e1988Sjohnlev break; 1023843e1988Sjohnlev if (xen_get_nphyscpus() < 4) 1024843e1988Sjohnlev break; 1025843e1988Sjohnlev #else 102692564cb1Sesaxe if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1027ae115bc7Smrj break; 1028843e1988Sjohnlev #endif 1029ae115bc7Smrj /* 1030ae115bc7Smrj * Print a warning if neither of the workarounds for 1031ae115bc7Smrj * erratum 131 is present. 1032ae115bc7Smrj */ 1033ae115bc7Smrj if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1034ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 1035ae115bc7Smrj workaround_warning(cpu, 131); 1036ae115bc7Smrj missing++; 1037ae115bc7Smrj } else if ((nbcfg & wabits) == 0) { 1038ae115bc7Smrj opteron_erratum_131++; 1039ae115bc7Smrj } else { 1040ae115bc7Smrj /* cannot have both workarounds set */ 1041ae115bc7Smrj ASSERT((nbcfg & wabits) != wabits); 10422201b277Skucharsk } 1043ae115bc7Smrj #else 1044ae115bc7Smrj workaround_warning(cpu, 131); 1045ae115bc7Smrj missing++; 10462201b277Skucharsk #endif 1047ae115bc7Smrj /*CONSTANTCONDITION*/ 1048ae115bc7Smrj } while (0); 1049ef50d8c0Sesaxe 1050ef50d8c0Sesaxe /* 1051ae115bc7Smrj * This isn't really an erratum, but for convenience the 1052ef50d8c0Sesaxe * detection/workaround code lives here and in cpuid_opteron_erratum. 1053ef50d8c0Sesaxe */ 1054ef50d8c0Sesaxe if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1055ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1056ef50d8c0Sesaxe /* 1057ef50d8c0Sesaxe * Disable C1-Clock ramping on multi-core/multi-processor 1058ef50d8c0Sesaxe * K8 platforms to guard against TSC drift. 1059ef50d8c0Sesaxe */ 1060ef50d8c0Sesaxe if (opteron_workaround_6336786) { 1061ef50d8c0Sesaxe opteron_workaround_6336786++; 1062843e1988Sjohnlev #if defined(__xpv) 1063843e1988Sjohnlev } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1064843e1988Sjohnlev xen_get_nphyscpus() > 1) || 1065843e1988Sjohnlev opteron_workaround_6336786_UP) { 1066843e1988Sjohnlev /* 106792564cb1Sesaxe * XXPV Hmm. We can't walk the Northbridges on 1068843e1988Sjohnlev * the hypervisor; so just complain and drive 1069843e1988Sjohnlev * on. This probably needs to be fixed in 1070843e1988Sjohnlev * the hypervisor itself. 1071843e1988Sjohnlev */ 1072843e1988Sjohnlev opteron_workaround_6336786++; 1073843e1988Sjohnlev workaround_warning(cpu, 6336786); 1074843e1988Sjohnlev #else /* __xpv */ 107592564cb1Sesaxe } else if ((opteron_get_nnodes() * 1076d38257c4Sesaxe cpuid_get_ncpu_per_chip(cpu) > 1) || 1077ef50d8c0Sesaxe opteron_workaround_6336786_UP) { 107892564cb1Sesaxe 107992564cb1Sesaxe uint_t node, nnodes; 1080ae115bc7Smrj uint8_t data; 1081ae115bc7Smrj 108292564cb1Sesaxe nnodes = opteron_get_nnodes(); 108392564cb1Sesaxe for (node = 0; node < nnodes; node++) { 1084ef50d8c0Sesaxe /* 1085ef50d8c0Sesaxe * Clear PMM7[1:0] (function 3, offset 0x87) 1086ef50d8c0Sesaxe * Northbridge device is the node id + 24. 1087ef50d8c0Sesaxe */ 1088ef50d8c0Sesaxe data = pci_getb_func(0, node + 24, 3, 0x87); 1089ef50d8c0Sesaxe data &= 0xFC; 1090ef50d8c0Sesaxe pci_putb_func(0, node + 24, 3, 0x87, data); 1091ef50d8c0Sesaxe } 1092ef50d8c0Sesaxe opteron_workaround_6336786++; 1093843e1988Sjohnlev #endif /* __xpv */ 1094ef50d8c0Sesaxe } 1095ae115bc7Smrj #else 1096ae115bc7Smrj workaround_warning(cpu, 6336786); 1097ae115bc7Smrj missing++; 1098ef50d8c0Sesaxe #endif 1099ae115bc7Smrj } 1100ee88d2b9Skchow 1101ee88d2b9Skchow /*LINTED*/ 1102ee88d2b9Skchow /* 1103ee88d2b9Skchow * Mutex primitives don't work as expected. 1104ee88d2b9Skchow */ 1105ee88d2b9Skchow if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1106ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1107ee88d2b9Skchow /* 1108ae115bc7Smrj * This problem only occurs with 2 or more cores. If bit in 1109512cf780Skchow * MSR_AMD_BU_CFG set, then not applicable. The workaround 1110ee88d2b9Skchow * is to patch the semaphone routines with the lfence 1111ee88d2b9Skchow * instruction to provide necessary load memory barrier with 1112ee88d2b9Skchow * possible subsequent read-modify-write ops. 1113ee88d2b9Skchow * 1114ee88d2b9Skchow * It is too early in boot to call the patch routine so 1115ee88d2b9Skchow * set erratum variable to be done in startup_end(). 1116ee88d2b9Skchow */ 1117ee88d2b9Skchow if (opteron_workaround_6323525) { 1118ee88d2b9Skchow opteron_workaround_6323525++; 1119843e1988Sjohnlev #if defined(__xpv) 1120843e1988Sjohnlev } else if (x86_feature & X86_SSE2) { 1121843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1122843e1988Sjohnlev /* 1123843e1988Sjohnlev * XXPV Use dom0_msr here when extended 1124843e1988Sjohnlev * operations are supported? 1125843e1988Sjohnlev */ 1126843e1988Sjohnlev if (xen_get_nphyscpus() > 1) 1127843e1988Sjohnlev opteron_workaround_6323525++; 1128843e1988Sjohnlev } else { 1129843e1988Sjohnlev /* 1130843e1988Sjohnlev * We have no way to tell how many physical 1131843e1988Sjohnlev * cpus there are, or even if this processor 1132843e1988Sjohnlev * has the problem, so enable the workaround 1133843e1988Sjohnlev * unconditionally (at some performance cost). 1134843e1988Sjohnlev */ 1135843e1988Sjohnlev opteron_workaround_6323525++; 1136843e1988Sjohnlev } 1137843e1988Sjohnlev #else /* __xpv */ 113892564cb1Sesaxe } else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() * 1139ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu)) > 1)) { 114048b2bf45SKit Chow if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1141ee88d2b9Skchow opteron_workaround_6323525++; 1142843e1988Sjohnlev #endif /* __xpv */ 1143ee88d2b9Skchow } 1144ae115bc7Smrj #else 1145ae115bc7Smrj workaround_warning(cpu, 6323525); 1146ae115bc7Smrj missing++; 1147ee88d2b9Skchow #endif 1148ae115bc7Smrj } 1149ae115bc7Smrj 1150512cf780Skchow missing += do_erratum_298(cpu); 1151512cf780Skchow 1152843e1988Sjohnlev #ifdef __xpv 1153843e1988Sjohnlev return (0); 1154843e1988Sjohnlev #else 11557c478bd9Sstevel@tonic-gate return (missing); 1156843e1988Sjohnlev #endif 11577c478bd9Sstevel@tonic-gate } 11587c478bd9Sstevel@tonic-gate 11597c478bd9Sstevel@tonic-gate void 11607c478bd9Sstevel@tonic-gate workaround_errata_end() 11617c478bd9Sstevel@tonic-gate { 1162ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 1163ae115bc7Smrj if (opteron_erratum_88) 1164ae115bc7Smrj workaround_applied(88); 1165ae115bc7Smrj #endif 1166ae115bc7Smrj #if defined(OPTERON_ERRATUM_91) 1167ae115bc7Smrj if (opteron_erratum_91) 1168ae115bc7Smrj workaround_applied(91); 1169ae115bc7Smrj #endif 1170ae115bc7Smrj #if defined(OPTERON_ERRATUM_93) 1171ae115bc7Smrj if (opteron_erratum_93) 1172ae115bc7Smrj workaround_applied(93); 1173ae115bc7Smrj #endif 1174ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 1175ae115bc7Smrj if (opteron_erratum_95) 1176ae115bc7Smrj workaround_applied(95); 1177ae115bc7Smrj #endif 1178ae115bc7Smrj #if defined(OPTERON_ERRATUM_100) 1179ae115bc7Smrj if (opteron_erratum_100) 1180ae115bc7Smrj workaround_applied(100); 1181ae115bc7Smrj #endif 1182ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 1183ae115bc7Smrj if (opteron_erratum_108) 1184ae115bc7Smrj workaround_applied(108); 1185ae115bc7Smrj #endif 11867c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 11877c478bd9Sstevel@tonic-gate if (opteron_erratum_109) { 11882201b277Skucharsk cmn_err(CE_WARN, 11892201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 11902201b277Skucharsk " processor\nerratum 109 was not detected; updating your" 11912201b277Skucharsk " system's BIOS to a version\ncontaining this" 11922201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 11932201b277Skucharsk " system\noperation may occur.\n"); 11947c478bd9Sstevel@tonic-gate } 1195ae115bc7Smrj #endif 1196ae115bc7Smrj #if defined(OPTERON_ERRATUM_121) 1197ae115bc7Smrj if (opteron_erratum_121) 1198ae115bc7Smrj workaround_applied(121); 1199ae115bc7Smrj #endif 1200ae115bc7Smrj #if defined(OPTERON_ERRATUM_122) 1201ae115bc7Smrj if (opteron_erratum_122) 1202ae115bc7Smrj workaround_applied(122); 1203ae115bc7Smrj #endif 12047c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 12057c478bd9Sstevel@tonic-gate if (opteron_erratum_123) { 12062201b277Skucharsk cmn_err(CE_WARN, 12072201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12082201b277Skucharsk " processor\nerratum 123 was not detected; updating your" 12092201b277Skucharsk " system's BIOS to a version\ncontaining this" 12102201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12112201b277Skucharsk " system\noperation may occur.\n"); 12127c478bd9Sstevel@tonic-gate } 1213ae115bc7Smrj #endif 12142201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 12152201b277Skucharsk if (opteron_erratum_131) { 12162201b277Skucharsk cmn_err(CE_WARN, 12172201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12182201b277Skucharsk " processor\nerratum 131 was not detected; updating your" 12192201b277Skucharsk " system's BIOS to a version\ncontaining this" 12202201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12212201b277Skucharsk " system\noperation may occur.\n"); 12222201b277Skucharsk } 1223ae115bc7Smrj #endif 1224ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1225ae115bc7Smrj if (opteron_workaround_6336786) 1226ae115bc7Smrj workaround_applied(6336786); 1227ae115bc7Smrj #endif 1228ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1229ae115bc7Smrj if (opteron_workaround_6323525) 1230ae115bc7Smrj workaround_applied(6323525); 1231ae115bc7Smrj #endif 1232512cf780Skchow #if defined(OPTERON_ERRATUM_298) 1233512cf780Skchow if (opteron_erratum_298) { 1234512cf780Skchow cmn_err(CE_WARN, 1235512cf780Skchow "BIOS microcode patch for AMD 64/Opteron(tm)" 1236512cf780Skchow " processor\nerratum 298 was not detected; updating your" 1237512cf780Skchow " system's BIOS to a version\ncontaining this" 1238512cf780Skchow " microcode patch is HIGHLY recommended or erroneous" 1239512cf780Skchow " system\noperation may occur.\n"); 1240512cf780Skchow } 1241512cf780Skchow #endif 12427c478bd9Sstevel@tonic-gate } 12437c478bd9Sstevel@tonic-gate 1244ae115bc7Smrj static cpuset_t procset; 1245ae115bc7Smrj 1246ae115bc7Smrj /* 1247ae115bc7Smrj * Start a single cpu, assuming that the kernel context is available 1248ae115bc7Smrj * to successfully start another cpu. 1249ae115bc7Smrj * 1250ae115bc7Smrj * (For example, real mode code is mapped into the right place 1251ae115bc7Smrj * in memory and is ready to be run.) 1252ae115bc7Smrj */ 1253ae115bc7Smrj int 1254ae115bc7Smrj start_cpu(processorid_t who) 1255ae115bc7Smrj { 1256ae115bc7Smrj void *ctx; 1257ae115bc7Smrj cpu_t *cp; 1258ae115bc7Smrj int delays; 1259ae115bc7Smrj int error = 0; 1260ae115bc7Smrj 1261ae115bc7Smrj ASSERT(who != 0); 1262ae115bc7Smrj 1263ae115bc7Smrj /* 1264ae115bc7Smrj * Check if there's at least a Mbyte of kmem available 1265ae115bc7Smrj * before attempting to start the cpu. 1266ae115bc7Smrj */ 1267ae115bc7Smrj if (kmem_avail() < 1024 * 1024) { 1268ae115bc7Smrj /* 1269ae115bc7Smrj * Kick off a reap in case that helps us with 1270ae115bc7Smrj * later attempts .. 1271ae115bc7Smrj */ 1272ae115bc7Smrj kmem_reap(); 1273ae115bc7Smrj return (ENOMEM); 1274ae115bc7Smrj } 1275ae115bc7Smrj 1276ae115bc7Smrj cp = mp_startup_init(who); 1277ae115bc7Smrj if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1278ae115bc7Smrj (error = mach_cpu_start(cp, ctx)) != 0) { 1279ae115bc7Smrj 1280ae115bc7Smrj /* 1281ae115bc7Smrj * Something went wrong before we even started it 1282ae115bc7Smrj */ 1283ae115bc7Smrj if (ctx) 1284ae115bc7Smrj cmn_err(CE_WARN, 1285ae115bc7Smrj "cpu%d: failed to start error %d", 1286ae115bc7Smrj cp->cpu_id, error); 1287ae115bc7Smrj else 1288ae115bc7Smrj cmn_err(CE_WARN, 1289ae115bc7Smrj "cpu%d: failed to allocate context", cp->cpu_id); 1290ae115bc7Smrj 1291ae115bc7Smrj if (ctx) 1292ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1293ae115bc7Smrj else 1294ae115bc7Smrj error = EAGAIN; /* hmm. */ 1295ae115bc7Smrj mp_startup_fini(cp, error); 1296ae115bc7Smrj return (error); 1297ae115bc7Smrj } 1298ae115bc7Smrj 1299ae115bc7Smrj for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1300ae115bc7Smrj if (delays == 500) { 1301ae115bc7Smrj /* 1302ae115bc7Smrj * After five seconds, things are probably looking 1303ae115bc7Smrj * a bit bleak - explain the hang. 1304ae115bc7Smrj */ 1305ae115bc7Smrj cmn_err(CE_NOTE, "cpu%d: started, " 1306ae115bc7Smrj "but not running in the kernel yet", who); 1307ae115bc7Smrj } else if (delays > 2000) { 1308ae115bc7Smrj /* 1309ae115bc7Smrj * We waited at least 20 seconds, bail .. 1310ae115bc7Smrj */ 1311ae115bc7Smrj error = ETIMEDOUT; 1312ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: timed out", who); 1313ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1314ae115bc7Smrj mp_startup_fini(cp, error); 1315ae115bc7Smrj return (error); 1316ae115bc7Smrj } 1317ae115bc7Smrj 1318ae115bc7Smrj /* 1319ae115bc7Smrj * wait at least 10ms, then check again.. 1320ae115bc7Smrj */ 1321ae115bc7Smrj delay(USEC_TO_TICK_ROUNDUP(10000)); 1322ae115bc7Smrj } 1323ae115bc7Smrj 1324ae115bc7Smrj mach_cpucontext_free(cp, ctx, 0); 1325ae115bc7Smrj 1326843e1988Sjohnlev #ifndef __xpv 1327ae115bc7Smrj if (tsc_gethrtime_enable) 1328ae115bc7Smrj tsc_sync_master(who); 1329843e1988Sjohnlev #endif 1330ae115bc7Smrj 1331ae115bc7Smrj if (dtrace_cpu_init != NULL) { 1332ae115bc7Smrj /* 1333ae115bc7Smrj * DTrace CPU initialization expects cpu_lock to be held. 1334ae115bc7Smrj */ 1335ae115bc7Smrj mutex_enter(&cpu_lock); 1336ae115bc7Smrj (*dtrace_cpu_init)(who); 1337ae115bc7Smrj mutex_exit(&cpu_lock); 1338ae115bc7Smrj } 1339ae115bc7Smrj 1340ae115bc7Smrj while (!CPU_IN_SET(cpu_ready_set, who)) 1341ae115bc7Smrj delay(1); 1342ae115bc7Smrj 1343ae115bc7Smrj return (0); 1344ae115bc7Smrj } 13457c478bd9Sstevel@tonic-gate 134641791439Sandrei 13477c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 13487c478bd9Sstevel@tonic-gate void 13497c478bd9Sstevel@tonic-gate start_other_cpus(int cprboot) 13507c478bd9Sstevel@tonic-gate { 1351ae115bc7Smrj uint_t who; 1352ae115bc7Smrj uint_t skipped = 0; 1353ae115bc7Smrj uint_t bootcpuid = 0; 13547c478bd9Sstevel@tonic-gate 13557c478bd9Sstevel@tonic-gate /* 13567c478bd9Sstevel@tonic-gate * Initialize our own cpu_info. 13577c478bd9Sstevel@tonic-gate */ 13587c478bd9Sstevel@tonic-gate init_cpu_info(CPU); 13597c478bd9Sstevel@tonic-gate 136019397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 136119397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 136219397407SSherry Moore 13637c478bd9Sstevel@tonic-gate /* 13647c478bd9Sstevel@tonic-gate * Initialize our syscall handlers 13657c478bd9Sstevel@tonic-gate */ 13667c478bd9Sstevel@tonic-gate init_cpu_syscall(CPU); 13677c478bd9Sstevel@tonic-gate 1368ae115bc7Smrj /* 1369ae115bc7Smrj * Take the boot cpu out of the mp_cpus set because we know 1370ae115bc7Smrj * it's already running. Add it to the cpu_ready_set for 1371ae115bc7Smrj * precisely the same reason. 1372ae115bc7Smrj */ 1373ae115bc7Smrj CPUSET_DEL(mp_cpus, bootcpuid); 1374ae115bc7Smrj CPUSET_ADD(cpu_ready_set, bootcpuid); 1375ae115bc7Smrj 13767c478bd9Sstevel@tonic-gate /* 13777c478bd9Sstevel@tonic-gate * if only 1 cpu or not using MP, skip the rest of this 13787c478bd9Sstevel@tonic-gate */ 1379ae115bc7Smrj if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 13807c478bd9Sstevel@tonic-gate if (use_mp == 0) 13817c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?***** Not in MP mode\n"); 13827c478bd9Sstevel@tonic-gate goto done; 13837c478bd9Sstevel@tonic-gate } 13847c478bd9Sstevel@tonic-gate 13857c478bd9Sstevel@tonic-gate /* 13867c478bd9Sstevel@tonic-gate * perform such initialization as is needed 13877c478bd9Sstevel@tonic-gate * to be able to take CPUs on- and off-line. 13887c478bd9Sstevel@tonic-gate */ 13897c478bd9Sstevel@tonic-gate cpu_pause_init(); 13907c478bd9Sstevel@tonic-gate 13917c478bd9Sstevel@tonic-gate xc_init(); /* initialize processor crosscalls */ 13927c478bd9Sstevel@tonic-gate 1393ae115bc7Smrj if (mach_cpucontext_init() != 0) 13947c478bd9Sstevel@tonic-gate goto done; 13957c478bd9Sstevel@tonic-gate 13967c478bd9Sstevel@tonic-gate flushes_require_xcalls = 1; 13977c478bd9Sstevel@tonic-gate 13985205ae23Snf /* 13995205ae23Snf * We lock our affinity to the master CPU to ensure that all slave CPUs 14005205ae23Snf * do their TSC syncs with the same CPU. 14015205ae23Snf */ 14027c478bd9Sstevel@tonic-gate affinity_set(CPU_CURRENT); 14037c478bd9Sstevel@tonic-gate 14047c478bd9Sstevel@tonic-gate for (who = 0; who < NCPU; who++) { 14055205ae23Snf 140641791439Sandrei if (!CPU_IN_SET(mp_cpus, who)) 140741791439Sandrei continue; 1408ae115bc7Smrj ASSERT(who != bootcpuid); 140941791439Sandrei if (ncpus >= max_ncpus) { 141041791439Sandrei skipped = who; 14117c478bd9Sstevel@tonic-gate continue; 141241791439Sandrei } 1413ae115bc7Smrj if (start_cpu(who) != 0) 1414ae115bc7Smrj CPUSET_DEL(mp_cpus, who); 1415b9e93c10SJonathan Haslam 1416b9e93c10SJonathan Haslam mutex_enter(&cpu_lock); 1417b9e93c10SJonathan Haslam cpu_state_change_notify(who, CPU_SETUP); 1418b9e93c10SJonathan Haslam mutex_exit(&cpu_lock); 14197c478bd9Sstevel@tonic-gate } 14207c478bd9Sstevel@tonic-gate 14212449e17fSsherrym /* Free the space allocated to hold the microcode file */ 1422adc586deSMark Johnson ucode_cleanup(); 14232449e17fSsherrym 14247c478bd9Sstevel@tonic-gate affinity_clear(); 14257c478bd9Sstevel@tonic-gate 142641791439Sandrei if (skipped) { 142741791439Sandrei cmn_err(CE_NOTE, 1428ae115bc7Smrj "System detected %d cpus, but " 1429ae115bc7Smrj "only %d cpu(s) were enabled during boot.", 143041791439Sandrei skipped + 1, ncpus); 143141791439Sandrei cmn_err(CE_NOTE, 143241791439Sandrei "Use \"boot-ncpus\" parameter to enable more CPU(s). " 143341791439Sandrei "See eeprom(1M)."); 143441791439Sandrei } 143541791439Sandrei 14367c478bd9Sstevel@tonic-gate done: 14377c478bd9Sstevel@tonic-gate workaround_errata_end(); 1438ae115bc7Smrj mach_cpucontext_fini(); 14393ad553a7Sgavinm 14403ad553a7Sgavinm cmi_post_mpstartup(); 14417c478bd9Sstevel@tonic-gate } 14427c478bd9Sstevel@tonic-gate 14437c478bd9Sstevel@tonic-gate /* 14447c478bd9Sstevel@tonic-gate * Dummy functions - no i86pc platforms support dynamic cpu allocation. 14457c478bd9Sstevel@tonic-gate */ 14467c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 14477c478bd9Sstevel@tonic-gate int 14487c478bd9Sstevel@tonic-gate mp_cpu_configure(int cpuid) 14497c478bd9Sstevel@tonic-gate { 14507c478bd9Sstevel@tonic-gate return (ENOTSUP); /* not supported */ 14517c478bd9Sstevel@tonic-gate } 14527c478bd9Sstevel@tonic-gate 14537c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 14547c478bd9Sstevel@tonic-gate int 14557c478bd9Sstevel@tonic-gate mp_cpu_unconfigure(int cpuid) 14567c478bd9Sstevel@tonic-gate { 14577c478bd9Sstevel@tonic-gate return (ENOTSUP); /* not supported */ 14587c478bd9Sstevel@tonic-gate } 14597c478bd9Sstevel@tonic-gate 14607c478bd9Sstevel@tonic-gate /* 14617c478bd9Sstevel@tonic-gate * Startup function for 'other' CPUs (besides boot cpu). 1462498697c5Sdmick * Called from real_mode_start. 1463b4b46911Skchow * 1464b4b46911Skchow * WARNING: until CPU_READY is set, mp_startup and routines called by 1465b4b46911Skchow * mp_startup should not call routines (e.g. kmem_free) that could call 1466b4b46911Skchow * hat_unload which requires CPU_READY to be set. 14677c478bd9Sstevel@tonic-gate */ 14687c478bd9Sstevel@tonic-gate void 14697c478bd9Sstevel@tonic-gate mp_startup(void) 14707c478bd9Sstevel@tonic-gate { 14717c478bd9Sstevel@tonic-gate struct cpu *cp = CPU; 14727c478bd9Sstevel@tonic-gate uint_t new_x86_feature; 14730e751525SEric Saxe #ifndef __xpv 14740e751525SEric Saxe extern void cpupm_init(cpu_t *); 14750e751525SEric Saxe #endif 14767c478bd9Sstevel@tonic-gate 147724a74e86Sdmick /* 147824a74e86Sdmick * We need to get TSC on this proc synced (i.e., any delta 147924a74e86Sdmick * from cpu0 accounted for) as soon as we can, because many 148024a74e86Sdmick * many things use gethrtime/pc_gethrestime, including 148124a74e86Sdmick * interrupts, cmn_err, etc. 148224a74e86Sdmick */ 148324a74e86Sdmick 148424a74e86Sdmick /* Let cpu0 continue into tsc_sync_master() */ 148524a74e86Sdmick CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 148624a74e86Sdmick 1487843e1988Sjohnlev #ifndef __xpv 148824a74e86Sdmick if (tsc_gethrtime_enable) 148924a74e86Sdmick tsc_sync_slave(); 1490843e1988Sjohnlev #endif 149124a74e86Sdmick 1492498697c5Sdmick /* 1493498697c5Sdmick * Once this was done from assembly, but it's safer here; if 1494498697c5Sdmick * it blocks, we need to be able to swtch() to and from, and 1495498697c5Sdmick * since we get here by calling t_pc, we need to do that call 1496498697c5Sdmick * before swtch() overwrites it. 1497498697c5Sdmick */ 1498498697c5Sdmick (void) (*ap_mlsetup)(); 1499498697c5Sdmick 15007c478bd9Sstevel@tonic-gate new_x86_feature = cpuid_pass1(cp); 15017c478bd9Sstevel@tonic-gate 1502843e1988Sjohnlev #ifndef __xpv 15037c478bd9Sstevel@tonic-gate /* 15041d03c31eSjohnlev * Program this cpu's PAT 15057c478bd9Sstevel@tonic-gate */ 15061d03c31eSjohnlev if (x86_feature & X86_PAT) 15071d03c31eSjohnlev pat_sync(); 1508843e1988Sjohnlev #endif 15097c478bd9Sstevel@tonic-gate 1510ae115bc7Smrj /* 1511ae115bc7Smrj * Set up TSC_AUX to contain the cpuid for this processor 1512ae115bc7Smrj * for the rdtscp instruction. 1513ae115bc7Smrj */ 1514ae115bc7Smrj if (x86_feature & X86_TSCP) 1515ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1516ae115bc7Smrj 15177c478bd9Sstevel@tonic-gate /* 15187c478bd9Sstevel@tonic-gate * Initialize this CPU's syscall handlers 15197c478bd9Sstevel@tonic-gate */ 15207c478bd9Sstevel@tonic-gate init_cpu_syscall(cp); 15217c478bd9Sstevel@tonic-gate 15227c478bd9Sstevel@tonic-gate /* 15237c478bd9Sstevel@tonic-gate * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 15247c478bd9Sstevel@tonic-gate * highest level at which a routine is permitted to block on 15257c478bd9Sstevel@tonic-gate * an adaptive mutex (allows for cpu poke interrupt in case 15267c478bd9Sstevel@tonic-gate * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 15277c478bd9Sstevel@tonic-gate * device interrupts that may end up in the hat layer issuing cross 15287c478bd9Sstevel@tonic-gate * calls before CPU_READY is set. 15297c478bd9Sstevel@tonic-gate */ 1530ae115bc7Smrj splx(ipltospl(LOCK_LEVEL)); 1531ae115bc7Smrj sti(); 15327c478bd9Sstevel@tonic-gate 15337c478bd9Sstevel@tonic-gate /* 15347c478bd9Sstevel@tonic-gate * Do a sanity check to make sure this new CPU is a sane thing 15357c478bd9Sstevel@tonic-gate * to add to the collection of processors running this system. 15367c478bd9Sstevel@tonic-gate * 15377c478bd9Sstevel@tonic-gate * XXX Clearly this needs to get more sophisticated, if x86 15387c478bd9Sstevel@tonic-gate * systems start to get built out of heterogenous CPUs; as is 15397c478bd9Sstevel@tonic-gate * likely to happen once the number of processors in a configuration 15407c478bd9Sstevel@tonic-gate * gets large enough. 15417c478bd9Sstevel@tonic-gate */ 15427c478bd9Sstevel@tonic-gate if ((x86_feature & new_x86_feature) != x86_feature) { 15437c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?cpu%d: %b\n", 15447c478bd9Sstevel@tonic-gate cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 15457c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 15467c478bd9Sstevel@tonic-gate } 15477c478bd9Sstevel@tonic-gate 1548f98fbcecSbholler /* 1549f98fbcecSbholler * We do not support cpus with mixed monitor/mwait support if the 1550f98fbcecSbholler * boot cpu supports monitor/mwait. 1551f98fbcecSbholler */ 1552f98fbcecSbholler if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1553f98fbcecSbholler panic("unsupported mixed cpu monitor/mwait support detected"); 1554f98fbcecSbholler 15557c478bd9Sstevel@tonic-gate /* 15567c478bd9Sstevel@tonic-gate * We could be more sophisticated here, and just mark the CPU 15577c478bd9Sstevel@tonic-gate * as "faulted" but at this point we'll opt for the easier 15587c478bd9Sstevel@tonic-gate * answer of dieing horribly. Provided the boot cpu is ok, 15597c478bd9Sstevel@tonic-gate * the system can be recovered by booting with use_mp set to zero. 15607c478bd9Sstevel@tonic-gate */ 15617c478bd9Sstevel@tonic-gate if (workaround_errata(cp) != 0) 15627c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 15637c478bd9Sstevel@tonic-gate 15647c478bd9Sstevel@tonic-gate cpuid_pass2(cp); 15657c478bd9Sstevel@tonic-gate cpuid_pass3(cp); 15667c478bd9Sstevel@tonic-gate (void) cpuid_pass4(cp); 15677c478bd9Sstevel@tonic-gate 15687c478bd9Sstevel@tonic-gate init_cpu_info(cp); 15697c478bd9Sstevel@tonic-gate 15707c478bd9Sstevel@tonic-gate mutex_enter(&cpu_lock); 15717c478bd9Sstevel@tonic-gate 1572afbc4541Ssherrym cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 15735205ae23Snf 157419397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 157519397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 157619397407SSherry Moore 15775205ae23Snf if (dtrace_cpu_init != NULL) { 15785205ae23Snf (*dtrace_cpu_init)(cp->cpu_id); 15795205ae23Snf } 15805205ae23Snf 15812449e17fSsherrym /* 15822449e17fSsherrym * Fill out cpu_ucode_info. Update microcode if necessary. 15832449e17fSsherrym */ 15842449e17fSsherrym ucode_check(cp); 15852449e17fSsherrym 15867c478bd9Sstevel@tonic-gate mutex_exit(&cpu_lock); 15877c478bd9Sstevel@tonic-gate 1588e774b42bSBill Holler post_startup_cpu_fixups(); 1589e774b42bSBill Holler 1590aa7b6435Ssethg /* 1591aa7b6435Ssethg * Enable preemption here so that contention for any locks acquired 1592aa7b6435Ssethg * later in mp_startup may be preempted if the thread owning those 1593aa7b6435Ssethg * locks is continously executing on other CPUs (for example, this 1594aa7b6435Ssethg * CPU must be preemptible to allow other CPUs to pause it during their 1595aa7b6435Ssethg * startup phases). It's safe to enable preemption here because the 1596aa7b6435Ssethg * CPU state is pretty-much fully constructed. 1597aa7b6435Ssethg */ 1598aa7b6435Ssethg curthread->t_preempt = 0; 1599aa7b6435Ssethg 1600da43ceabSsethg /* The base spl should still be at LOCK LEVEL here */ 1601da43ceabSsethg ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1602da43ceabSsethg set_base_spl(); /* Restore the spl to its proper value */ 1603da43ceabSsethg 16040e751525SEric Saxe #ifndef __xpv 16050e751525SEric Saxe cpupm_init(cp); 16060e751525SEric Saxe #endif 16070e751525SEric Saxe add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 16080e751525SEric Saxe 16090e751525SEric Saxe /* 16100e751525SEric Saxe * Processor group initialization for this CPU is dependent on the 16110e751525SEric Saxe * cpuid probing, which must be done in the context of the current 16120e751525SEric Saxe * CPU, as well as the CPU's device node initialization (for ACPI). 16130e751525SEric Saxe */ 16140e751525SEric Saxe mutex_enter(&cpu_lock); 16150e751525SEric Saxe pghw_physid_create(cp); 16160e751525SEric Saxe pg_cpu_init(cp); 16170e751525SEric Saxe pg_cmt_cpu_startup(cp); 16180e751525SEric Saxe mutex_exit(&cpu_lock); 16190e751525SEric Saxe 1620afbc4541Ssherrym /* Enable interrupts */ 1621afbc4541Ssherrym (void) spl0(); 16220e751525SEric Saxe 1623afbc4541Ssherrym mutex_enter(&cpu_lock); 1624afbc4541Ssherrym cpu_enable_intr(cp); 1625afbc4541Ssherrym cpu_add_active(cp); 1626afbc4541Ssherrym mutex_exit(&cpu_lock); 1627afbc4541Ssherrym 162820c794b3Sgavinm #ifndef __xpv 162920c794b3Sgavinm { 163020c794b3Sgavinm /* 163120c794b3Sgavinm * Set up the CPU module for this CPU. This can't be done 163220c794b3Sgavinm * before this CPU is made CPU_READY, because we may (in 163320c794b3Sgavinm * heterogeneous systems) need to go load another CPU module. 163420c794b3Sgavinm * The act of attempting to load a module may trigger a 163520c794b3Sgavinm * cross-call, which will ASSERT unless this cpu is CPU_READY. 163620c794b3Sgavinm */ 163720c794b3Sgavinm cmi_hdl_t hdl; 16387aec1d6eScindi 163920c794b3Sgavinm if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1640e4b86885SCheng Sean Ye cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 164120c794b3Sgavinm if (x86_feature & X86_MCA) 164220c794b3Sgavinm cmi_mca_init(hdl); 164320c794b3Sgavinm } 164420c794b3Sgavinm } 164520c794b3Sgavinm #endif /* __xpv */ 16467aec1d6eScindi 16477c478bd9Sstevel@tonic-gate if (boothowto & RB_DEBUG) 1648ae115bc7Smrj kdi_cpu_init(); 16497c478bd9Sstevel@tonic-gate 16507c478bd9Sstevel@tonic-gate /* 16517c478bd9Sstevel@tonic-gate * Setting the bit in cpu_ready_set must be the last operation in 16527c478bd9Sstevel@tonic-gate * processor initialization; the boot CPU will continue to boot once 16537c478bd9Sstevel@tonic-gate * it sees this bit set for all active CPUs. 16547c478bd9Sstevel@tonic-gate */ 16557c478bd9Sstevel@tonic-gate CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 16567c478bd9Sstevel@tonic-gate 16577c478bd9Sstevel@tonic-gate /* 16587c478bd9Sstevel@tonic-gate * Because mp_startup() gets fired off after init() starts, we 16597c478bd9Sstevel@tonic-gate * can't use the '?' trick to do 'boot -v' printing - so we 16607c478bd9Sstevel@tonic-gate * always direct the 'cpu .. online' messages to the log. 16617c478bd9Sstevel@tonic-gate */ 16627c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 16637c478bd9Sstevel@tonic-gate cp->cpu_id); 16647c478bd9Sstevel@tonic-gate 16657c478bd9Sstevel@tonic-gate /* 16667c478bd9Sstevel@tonic-gate * Now we are done with the startup thread, so free it up. 16677c478bd9Sstevel@tonic-gate */ 16687c478bd9Sstevel@tonic-gate thread_exit(); 16697c478bd9Sstevel@tonic-gate panic("mp_startup: cannot return"); 16707c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 16717c478bd9Sstevel@tonic-gate } 16727c478bd9Sstevel@tonic-gate 16737c478bd9Sstevel@tonic-gate 16747c478bd9Sstevel@tonic-gate /* 16757c478bd9Sstevel@tonic-gate * Start CPU on user request. 16767c478bd9Sstevel@tonic-gate */ 16777c478bd9Sstevel@tonic-gate /* ARGSUSED */ 16787c478bd9Sstevel@tonic-gate int 16797c478bd9Sstevel@tonic-gate mp_cpu_start(struct cpu *cp) 16807c478bd9Sstevel@tonic-gate { 16817c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 16827c478bd9Sstevel@tonic-gate return (0); 16837c478bd9Sstevel@tonic-gate } 16847c478bd9Sstevel@tonic-gate 16857c478bd9Sstevel@tonic-gate /* 16867c478bd9Sstevel@tonic-gate * Stop CPU on user request. 16877c478bd9Sstevel@tonic-gate */ 16887c478bd9Sstevel@tonic-gate /* ARGSUSED */ 16897c478bd9Sstevel@tonic-gate int 16907c478bd9Sstevel@tonic-gate mp_cpu_stop(struct cpu *cp) 16917c478bd9Sstevel@tonic-gate { 1692d90554ebSdmick extern int cbe_psm_timer_mode; 16937c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 1694d90554ebSdmick 1695843e1988Sjohnlev #ifdef __xpv 1696843e1988Sjohnlev /* 1697843e1988Sjohnlev * We can't offline vcpu0. 1698843e1988Sjohnlev */ 1699843e1988Sjohnlev if (cp->cpu_id == 0) 1700843e1988Sjohnlev return (EBUSY); 1701843e1988Sjohnlev #endif 1702843e1988Sjohnlev 1703d90554ebSdmick /* 1704d90554ebSdmick * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1705d90554ebSdmick * can't stop it. (This is true only for machines with no TSC.) 1706d90554ebSdmick */ 1707d90554ebSdmick 1708d90554ebSdmick if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1709843e1988Sjohnlev return (EBUSY); 17107c478bd9Sstevel@tonic-gate 17117c478bd9Sstevel@tonic-gate return (0); 17127c478bd9Sstevel@tonic-gate } 17137c478bd9Sstevel@tonic-gate 17147c478bd9Sstevel@tonic-gate /* 17157c478bd9Sstevel@tonic-gate * Take the specified CPU out of participation in interrupts. 17167c478bd9Sstevel@tonic-gate */ 17177c478bd9Sstevel@tonic-gate int 17187c478bd9Sstevel@tonic-gate cpu_disable_intr(struct cpu *cp) 17197c478bd9Sstevel@tonic-gate { 17207c478bd9Sstevel@tonic-gate if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 17217c478bd9Sstevel@tonic-gate return (EBUSY); 17227c478bd9Sstevel@tonic-gate 17237c478bd9Sstevel@tonic-gate cp->cpu_flags &= ~CPU_ENABLE; 17247c478bd9Sstevel@tonic-gate return (0); 17257c478bd9Sstevel@tonic-gate } 17267c478bd9Sstevel@tonic-gate 17277c478bd9Sstevel@tonic-gate /* 17287c478bd9Sstevel@tonic-gate * Allow the specified CPU to participate in interrupts. 17297c478bd9Sstevel@tonic-gate */ 17307c478bd9Sstevel@tonic-gate void 17317c478bd9Sstevel@tonic-gate cpu_enable_intr(struct cpu *cp) 17327c478bd9Sstevel@tonic-gate { 17337c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 17347c478bd9Sstevel@tonic-gate cp->cpu_flags |= CPU_ENABLE; 17357c478bd9Sstevel@tonic-gate psm_enable_intr(cp->cpu_id); 17367c478bd9Sstevel@tonic-gate } 17377c478bd9Sstevel@tonic-gate 17387c478bd9Sstevel@tonic-gate 173920c794b3Sgavinm /*ARGSUSED*/ 17407c478bd9Sstevel@tonic-gate void 17417c478bd9Sstevel@tonic-gate mp_cpu_faulted_enter(struct cpu *cp) 17427aec1d6eScindi { 174320c794b3Sgavinm #ifndef __xpv 174420c794b3Sgavinm cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 174520c794b3Sgavinm cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 174620c794b3Sgavinm 174720c794b3Sgavinm if (hdl != NULL) { 174820c794b3Sgavinm cmi_faulted_enter(hdl); 174920c794b3Sgavinm cmi_hdl_rele(hdl); 175020c794b3Sgavinm } 175120c794b3Sgavinm #endif 17527aec1d6eScindi } 17537c478bd9Sstevel@tonic-gate 175420c794b3Sgavinm /*ARGSUSED*/ 17557c478bd9Sstevel@tonic-gate void 17567c478bd9Sstevel@tonic-gate mp_cpu_faulted_exit(struct cpu *cp) 17577aec1d6eScindi { 175820c794b3Sgavinm #ifndef __xpv 175920c794b3Sgavinm cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 176020c794b3Sgavinm cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 176120c794b3Sgavinm 176220c794b3Sgavinm if (hdl != NULL) { 176320c794b3Sgavinm cmi_faulted_exit(hdl); 176420c794b3Sgavinm cmi_hdl_rele(hdl); 176520c794b3Sgavinm } 176620c794b3Sgavinm #endif 17677aec1d6eScindi } 17687c478bd9Sstevel@tonic-gate 17697c478bd9Sstevel@tonic-gate /* 17707c478bd9Sstevel@tonic-gate * The following two routines are used as context operators on threads belonging 17717c478bd9Sstevel@tonic-gate * to processes with a private LDT (see sysi86). Due to the rarity of such 17727c478bd9Sstevel@tonic-gate * processes, these routines are currently written for best code readability and 17737c478bd9Sstevel@tonic-gate * organization rather than speed. We could avoid checking x86_feature at every 17747c478bd9Sstevel@tonic-gate * context switch by installing different context ops, depending on the 17757c478bd9Sstevel@tonic-gate * x86_feature flags, at LDT creation time -- one for each combination of fast 17767c478bd9Sstevel@tonic-gate * syscall feature flags. 17777c478bd9Sstevel@tonic-gate */ 17787c478bd9Sstevel@tonic-gate 17797c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 17807c478bd9Sstevel@tonic-gate void 17817c478bd9Sstevel@tonic-gate cpu_fast_syscall_disable(void *arg) 17827c478bd9Sstevel@tonic-gate { 1783ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 17847c478bd9Sstevel@tonic-gate cpu_sep_disable(); 1785ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 17867c478bd9Sstevel@tonic-gate cpu_asysc_disable(); 17877c478bd9Sstevel@tonic-gate } 17887c478bd9Sstevel@tonic-gate 17897c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 17907c478bd9Sstevel@tonic-gate void 17917c478bd9Sstevel@tonic-gate cpu_fast_syscall_enable(void *arg) 17927c478bd9Sstevel@tonic-gate { 1793ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 17947c478bd9Sstevel@tonic-gate cpu_sep_enable(); 1795ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 17967c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 17977c478bd9Sstevel@tonic-gate } 17987c478bd9Sstevel@tonic-gate 17997c478bd9Sstevel@tonic-gate static void 18007c478bd9Sstevel@tonic-gate cpu_sep_enable(void) 18017c478bd9Sstevel@tonic-gate { 18027c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_SEP); 18037c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 18047c478bd9Sstevel@tonic-gate 18050ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 18067c478bd9Sstevel@tonic-gate } 18077c478bd9Sstevel@tonic-gate 18087c478bd9Sstevel@tonic-gate static void 18097c478bd9Sstevel@tonic-gate cpu_sep_disable(void) 18107c478bd9Sstevel@tonic-gate { 18117c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_SEP); 18127c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 18137c478bd9Sstevel@tonic-gate 18147c478bd9Sstevel@tonic-gate /* 18157c478bd9Sstevel@tonic-gate * Setting the SYSENTER_CS_MSR register to 0 causes software executing 18167c478bd9Sstevel@tonic-gate * the sysenter or sysexit instruction to trigger a #gp fault. 18177c478bd9Sstevel@tonic-gate */ 1818ae115bc7Smrj wrmsr(MSR_INTC_SEP_CS, 0); 18197c478bd9Sstevel@tonic-gate } 18207c478bd9Sstevel@tonic-gate 18217c478bd9Sstevel@tonic-gate static void 18227c478bd9Sstevel@tonic-gate cpu_asysc_enable(void) 18237c478bd9Sstevel@tonic-gate { 18247c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_ASYSC); 18257c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 18267c478bd9Sstevel@tonic-gate 18270ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 18280ac7d7d8Skucharsk (uint64_t)(uintptr_t)AMD_EFER_SCE); 18297c478bd9Sstevel@tonic-gate } 18307c478bd9Sstevel@tonic-gate 18317c478bd9Sstevel@tonic-gate static void 18327c478bd9Sstevel@tonic-gate cpu_asysc_disable(void) 18337c478bd9Sstevel@tonic-gate { 18347c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_ASYSC); 18357c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 18367c478bd9Sstevel@tonic-gate 18377c478bd9Sstevel@tonic-gate /* 18387c478bd9Sstevel@tonic-gate * Turn off the SCE (syscall enable) bit in the EFER register. Software 18397c478bd9Sstevel@tonic-gate * executing syscall or sysret with this bit off will incur a #ud trap. 18407c478bd9Sstevel@tonic-gate */ 18410ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 18420ac7d7d8Skucharsk ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 18437c478bd9Sstevel@tonic-gate } 1844