1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2012 Gary Mills
23 *
24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 * Copyright 2019 Joyent, Inc.
27 * Copyright 2020 Oxide Computer Company
28 */
29 /*
30 * Copyright (c) 2010, Intel Corporation.
31 * All rights reserved.
32 */
33
34 #include <sys/types.h>
35 #include <sys/sysmacros.h>
36 #include <sys/disp.h>
37 #include <sys/promif.h>
38 #include <sys/clock.h>
39 #include <sys/cpuvar.h>
40 #include <sys/stack.h>
41 #include <vm/as.h>
42 #include <vm/hat.h>
43 #include <sys/reboot.h>
44 #include <sys/avintr.h>
45 #include <sys/vtrace.h>
46 #include <sys/proc.h>
47 #include <sys/thread.h>
48 #include <sys/cpupart.h>
49 #include <sys/pset.h>
50 #include <sys/copyops.h>
51 #include <sys/pg.h>
52 #include <sys/disp.h>
53 #include <sys/debug.h>
54 #include <sys/sunddi.h>
55 #include <sys/x86_archext.h>
56 #include <sys/privregs.h>
57 #include <sys/machsystm.h>
58 #include <sys/ontrap.h>
59 #include <sys/bootconf.h>
60 #include <sys/boot_console.h>
61 #include <sys/kdi_machimpl.h>
62 #include <sys/archsystm.h>
63 #include <sys/promif.h>
64 #include <sys/pci_cfgspace.h>
65 #include <sys/apic.h>
66 #include <sys/apic_common.h>
67 #include <sys/bootvfs.h>
68 #include <sys/tsc.h>
69 #include <sys/smt.h>
70 #ifdef __xpv
71 #include <sys/hypervisor.h>
72 #else
73 #include <sys/xpv_support.h>
74 #endif
75
76 /*
77 * some globals for patching the result of cpuid
78 * to solve problems w/ creative cpu vendors
79 */
80
81 extern uint32_t cpuid_feature_ecx_include;
82 extern uint32_t cpuid_feature_ecx_exclude;
83 extern uint32_t cpuid_feature_edx_include;
84 extern uint32_t cpuid_feature_edx_exclude;
85
86 nmi_action_t nmi_action = NMI_ACTION_UNSET;
87
88 /*
89 * Set console mode
90 */
91 static void
set_console_mode(uint8_t val)92 set_console_mode(uint8_t val)
93 {
94 struct bop_regs rp = {0};
95
96 rp.eax.byte.ah = 0x0;
97 rp.eax.byte.al = val;
98 rp.ebx.word.bx = 0x0;
99
100 BOP_DOINT(bootops, 0x10, &rp);
101 }
102
103
104 /*
105 * Setup routine called right before main(). Interposing this function
106 * before main() allows us to call it in a machine-independent fashion.
107 */
108 void
mlsetup(struct regs * rp)109 mlsetup(struct regs *rp)
110 {
111 u_longlong_t prop_value;
112 char prop_str[BP_MAX_STRLEN];
113 extern struct classfuncs sys_classfuncs;
114 extern disp_t cpu0_disp;
115 extern char t0stack[];
116 extern int post_fastreboot;
117 extern uint64_t plat_dr_options;
118
119 ASSERT_STACK_ALIGNED();
120
121 /*
122 * initialize cpu_self
123 */
124 cpu[0]->cpu_self = cpu[0];
125
126 #if defined(__xpv)
127 /*
128 * Point at the hypervisor's virtual cpu structure
129 */
130 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
131 #endif
132
133 /*
134 * check if we've got special bits to clear or set
135 * when checking cpu features
136 */
137
138 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
139 cpuid_feature_ecx_include = 0;
140 else
141 cpuid_feature_ecx_include = (uint32_t)prop_value;
142
143 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
144 cpuid_feature_ecx_exclude = 0;
145 else
146 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
147
148 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
149 cpuid_feature_edx_include = 0;
150 else
151 cpuid_feature_edx_include = (uint32_t)prop_value;
152
153 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
154 cpuid_feature_edx_exclude = 0;
155 else
156 cpuid_feature_edx_exclude = (uint32_t)prop_value;
157
158 #if !defined(__xpv)
159 if (bootprop_getstr("nmi", prop_str, sizeof (prop_str)) == 0) {
160 if (strcmp(prop_str, "ignore") == 0) {
161 nmi_action = NMI_ACTION_IGNORE;
162 } else if (strcmp(prop_str, "panic") == 0) {
163 nmi_action = NMI_ACTION_PANIC;
164 } else if (strcmp(prop_str, "kmdb") == 0) {
165 nmi_action = NMI_ACTION_KMDB;
166 } else {
167 prom_printf("unix: ignoring unknown nmi=%s\n",
168 prop_str);
169 }
170 }
171
172 /*
173 * Check to see if KPTI has been explicitly enabled or disabled.
174 * We have to check this before init_desctbls().
175 */
176 if (bootprop_getval("kpti", &prop_value) == 0) {
177 kpti_enable = (uint64_t)(prop_value == 1);
178 prom_printf("unix: forcing kpti to %s due to boot argument\n",
179 (kpti_enable == 1) ? "ON" : "OFF");
180 } else {
181 kpti_enable = 1;
182 }
183
184 if (bootprop_getval("pcid", &prop_value) == 0 && prop_value == 0) {
185 prom_printf("unix: forcing pcid to OFF due to boot argument\n");
186 x86_use_pcid = 0;
187 } else if (kpti_enable != 1) {
188 x86_use_pcid = 0;
189 }
190
191 /*
192 * While we don't need to check this until later, we might as well do it
193 * here.
194 */
195 if (bootprop_getstr("smt_enabled", prop_str, sizeof (prop_str)) == 0) {
196 if (strcasecmp(prop_str, "false") == 0 ||
197 strcmp(prop_str, "0") == 0)
198 smt_boot_disable = 1;
199 }
200
201 #endif
202
203 /*
204 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
205 */
206 init_desctbls();
207
208 /*
209 * Ensure that we have set the necessary feature bits before setting up
210 * PCI config space access.
211 */
212 cpuid_execpass(cpu[0], CPUID_PASS_PRELUDE, x86_featureset);
213
214 /*
215 * lgrp_init() and possibly cpuid_pass1() need PCI config
216 * space access
217 */
218 #if defined(__xpv)
219 if (DOMAIN_IS_INITDOMAIN(xen_info))
220 pci_cfgspace_init();
221 #else
222 pci_cfgspace_init();
223 /*
224 * Initialize the platform type from CPU 0 to ensure that
225 * determine_platform() is only ever called once.
226 */
227 determine_platform();
228 #endif
229
230 /*
231 * i86pc doesn't require anything in between the IDENT and BASIC passes;
232 * we assume that a BIOS has already set up any necessary cpuid feature
233 * bits, so we run both passes together here.
234 *
235 * The x86_featureset is initialized here based on the capabilities of
236 * the boot CPU. Note that if we choose to support CPUs that have
237 * different feature sets (at which point we would almost certainly want
238 * to set the feature bits to correspond to the feature minimum) this
239 * value may be altered.
240 */
241 cpuid_execpass(cpu[0], CPUID_PASS_IDENT, NULL);
242 cpuid_execpass(cpu[0], CPUID_PASS_BASIC, x86_featureset);
243
244 #if !defined(__xpv)
245 if ((get_hwenv() & HW_XEN_HVM) != 0)
246 xen_hvm_init();
247
248 /*
249 * Before we do anything with the TSCs, we need to work around
250 * Intel erratum BT81. On some CPUs, warm reset does not
251 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
252 * here. Other CPUs will clear it when we boot them later, and the
253 * resulting skew will be handled by tsc_sync_master()/_slave();
254 * note that such skew already exists and has to be handled anyway.
255 *
256 * We do this only on metal. This same problem can occur with a
257 * hypervisor that does not happen to virtualise a TSC that starts from
258 * zero, regardless of CPU type; however, we do not expect hypervisors
259 * that do not virtualise TSC that way to handle writes to TSC
260 * correctly, either.
261 */
262 if (get_hwenv() == HW_NATIVE &&
263 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
264 cpuid_getfamily(CPU) == 6 &&
265 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
266 is_x86_feature(x86_featureset, X86FSET_TSC)) {
267 (void) wrmsr(REG_TSC, 0UL);
268 }
269
270 /*
271 * Patch the tsc_read routine with appropriate set of instructions,
272 * depending on the processor family and architecure, to read the
273 * time-stamp counter while ensuring no out-of-order execution.
274 * Patch it while the kernel text is still writable.
275 *
276 * The Xen hypervisor does not correctly report whether rdtscp is
277 * supported or not, so we must assume that it is not.
278 */
279 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
280 is_x86_feature(x86_featureset, X86FSET_TSCP)) {
281 patch_tsc_read(TSC_TSCP);
282 } else if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) {
283 ASSERT(is_x86_feature(x86_featureset, X86FSET_SSE2));
284 patch_tsc_read(TSC_RDTSC_LFENCE);
285 }
286
287 #endif /* !__xpv */
288
289
290 #if !defined(__xpv)
291 patch_memops(cpuid_getvendor(CPU));
292 #endif /* !__xpv */
293
294 #if !defined(__xpv)
295 /* XXPV what, if anything, should be dorked with here under xen? */
296
297 /*
298 * While we're thinking about the TSC, let's set up %cr4 so that
299 * userland can issue rdtsc, and initialize the TSC_AUX value
300 * (the cpuid) for the rdtscp instruction on appropriately
301 * capable hardware.
302 */
303 if (is_x86_feature(x86_featureset, X86FSET_TSC))
304 setcr4(getcr4() & ~CR4_TSD);
305
306 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
307 (void) wrmsr(MSR_AMD_TSCAUX, 0);
308
309 /*
310 * Let's get the other %cr4 stuff while we're here. Note, we defer
311 * enabling CR4_SMAP until startup_end(); however, that's importantly
312 * before we start other CPUs. That ensures that it will be synced out
313 * to other CPUs.
314 */
315 if (is_x86_feature(x86_featureset, X86FSET_DE))
316 setcr4(getcr4() | CR4_DE);
317
318 if (is_x86_feature(x86_featureset, X86FSET_SMEP))
319 setcr4(getcr4() | CR4_SMEP);
320 #endif /* __xpv */
321
322 /*
323 * initialize t0
324 */
325 t0.t_stk = (caddr_t)rp - MINFRAME;
326 t0.t_stkbase = t0stack;
327 t0.t_pri = maxclsyspri - 3;
328 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
329 t0.t_procp = &p0;
330 t0.t_plockp = &p0lock.pl_lock;
331 t0.t_lwp = &lwp0;
332 t0.t_forw = &t0;
333 t0.t_back = &t0;
334 t0.t_next = &t0;
335 t0.t_prev = &t0;
336 t0.t_cpu = cpu[0];
337 t0.t_disp_queue = &cpu0_disp;
338 t0.t_bind_cpu = PBIND_NONE;
339 t0.t_bind_pset = PS_NONE;
340 t0.t_bindflag = (uchar_t)default_binding_mode;
341 t0.t_cpupart = &cp_default;
342 t0.t_clfuncs = &sys_classfuncs.thread;
343 t0.t_copyops = NULL;
344 THREAD_ONPROC(&t0, CPU);
345
346 lwp0.lwp_thread = &t0;
347 lwp0.lwp_regs = (void *)rp;
348 lwp0.lwp_procp = &p0;
349 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
350
351 p0.p_exec = NULL;
352 p0.p_stat = SRUN;
353 p0.p_flag = SSYS;
354 p0.p_tlist = &t0;
355 p0.p_stksize = 2*PAGESIZE;
356 p0.p_stkpageszc = 0;
357 p0.p_as = &kas;
358 p0.p_lockp = &p0lock;
359 p0.p_brkpageszc = 0;
360 p0.p_t1_lgrpid = LGRP_NONE;
361 p0.p_tr_lgrpid = LGRP_NONE;
362 psecflags_default(&p0.p_secflags);
363
364 sigorset(&p0.p_ignore, &ignoredefault);
365
366 CPU->cpu_thread = &t0;
367 bzero(&cpu0_disp, sizeof (disp_t));
368 CPU->cpu_disp = &cpu0_disp;
369 CPU->cpu_disp->disp_cpu = CPU;
370 CPU->cpu_dispthread = &t0;
371 CPU->cpu_idle_thread = &t0;
372 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
373 CPU->cpu_dispatch_pri = t0.t_pri;
374
375 CPU->cpu_id = 0;
376
377 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
378
379 /*
380 * Initialize thread/cpu microstate accounting
381 */
382 init_mstate(&t0, LMS_SYSTEM);
383 init_cpu_mstate(CPU, CMS_SYSTEM);
384
385 /*
386 * Initialize lists of available and active CPUs.
387 */
388 cpu_list_init(CPU);
389
390 pg_cpu_bootstrap(CPU);
391
392 /*
393 * Now that we have taken over the GDT, IDT and have initialized
394 * active CPU list it's time to inform kmdb if present.
395 */
396 if (boothowto & RB_DEBUG)
397 kdi_idt_sync();
398
399 if (BOP_GETPROPLEN(bootops, "efi-systab") < 0) {
400 /*
401 * In BIOS system, explicitly set console to text mode (0x3)
402 * if this is a boot post Fast Reboot, and the console is set
403 * to CONS_SCREEN_TEXT.
404 */
405 if (post_fastreboot &&
406 boot_console_type(NULL) == CONS_SCREEN_TEXT) {
407 set_console_mode(0x3);
408 }
409 }
410
411 /*
412 * If requested (boot -d) drop into kmdb.
413 *
414 * This must be done after cpu_list_init() on the 64-bit kernel
415 * since taking a trap requires that we re-compute gsbase based
416 * on the cpu list.
417 */
418 if (boothowto & RB_DEBUGENTER)
419 kmdb_enter();
420
421 cpu_vm_data_init(CPU);
422
423 rp->r_fp = 0; /* terminate kernel stack traces! */
424
425 prom_init("kernel", (void *)NULL);
426
427 /* User-set option overrides firmware value. */
428 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
429 plat_dr_options = (uint64_t)prop_value;
430 }
431 #if defined(__xpv)
432 /* No support of DR operations on xpv */
433 plat_dr_options = 0;
434 #else /* __xpv */
435 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
436 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
437 #endif /* __xpv */
438
439 /*
440 * Get value of "plat_dr_physmax" boot option.
441 * It overrides values calculated from MSCT or SRAT table.
442 */
443 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
444 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
445 }
446
447 /* Get value of boot_ncpus. */
448 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
449 boot_ncpus = NCPU;
450 } else {
451 boot_ncpus = (int)prop_value;
452 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
453 boot_ncpus = NCPU;
454 }
455
456 /*
457 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
458 * support CPU DR operations.
459 */
460 if (plat_dr_support_cpu() == 0) {
461 max_ncpus = boot_max_ncpus = boot_ncpus;
462 } else {
463 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
464 max_ncpus = NCPU;
465 } else {
466 max_ncpus = (int)prop_value;
467 if (max_ncpus <= 0 || max_ncpus > NCPU) {
468 max_ncpus = NCPU;
469 }
470 if (boot_ncpus > max_ncpus) {
471 boot_ncpus = max_ncpus;
472 }
473 }
474
475 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
476 boot_max_ncpus = boot_ncpus;
477 } else {
478 boot_max_ncpus = (int)prop_value;
479 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
480 boot_max_ncpus = boot_ncpus;
481 } else if (boot_max_ncpus > max_ncpus) {
482 boot_max_ncpus = max_ncpus;
483 }
484 }
485 }
486
487 /*
488 * Initialize the lgrp framework
489 */
490 lgrp_init(LGRP_INIT_STAGE1);
491
492 if (boothowto & RB_HALT) {
493 prom_printf("unix: kernel halted by -h flag\n");
494 prom_enter_mon();
495 }
496
497 ASSERT_STACK_ALIGNED();
498
499 /*
500 * Fill out cpu_ucode_info. Update microcode if necessary.
501 */
502 ucode_init();
503 ucode_check(CPU);
504 cpuid_pass_ucode(CPU, x86_featureset);
505
506 if (workaround_errata(CPU) != 0)
507 panic("critical workaround(s) missing for boot cpu");
508 }
509
510
511 void
mach_modpath(char * path,const char * filename)512 mach_modpath(char *path, const char *filename)
513 {
514 /*
515 * Construct the directory path from the filename.
516 */
517
518 int len;
519 char *p;
520 const char isastr[] = "/amd64";
521 size_t isalen = strlen(isastr);
522
523 len = strlen(SYSTEM_BOOT_PATH "/kernel");
524 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel ");
525 path += len + 1;
526
527 if ((p = strrchr(filename, '/')) == NULL)
528 return;
529
530 while (p > filename && *(p - 1) == '/')
531 p--; /* remove trailing '/' characters */
532 if (p == filename)
533 p++; /* so "/" -is- the modpath in this case */
534
535 /*
536 * Remove optional isa-dependent directory name - the module
537 * subsystem will put this back again (!)
538 */
539 len = p - filename;
540 if (len > isalen &&
541 strncmp(&filename[len - isalen], isastr, isalen) == 0)
542 p -= isalen;
543
544 /*
545 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
546 */
547 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
548 (void) strncpy(path, filename, p - filename);
549 }
550