1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright 2016 Nexenta Systems, Inc.
24  * Copyright (c) 2017 by Delphix. All rights reserved.
25  * Copyright (c) 2019, Joyent, Inc.
26  * Copyright 2020 RackTop Systems, Inc.
27  * Copyright 2020 Oxide Computer Company
28  */
29 /*
30  * Copyright (c) 2010, Intel Corporation.
31  * All rights reserved.
32  */
33 
34 /*
35  * PSMI 1.1 extensions are supported only in 2.6 and later versions.
36  * PSMI 1.2 extensions are supported only in 2.7 and later versions.
37  * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
38  * PSMI 1.5 extensions are supported in Solaris Nevada.
39  * PSMI 1.6 extensions are supported in Solaris Nevada.
40  * PSMI 1.7 extensions are supported in Solaris Nevada.
41  */
42 #define	PSMI_1_7
43 
44 #include <sys/processor.h>
45 #include <sys/time.h>
46 #include <sys/psm.h>
47 #include <sys/smp_impldefs.h>
48 #include <sys/cram.h>
49 #include <sys/acpi/acpi.h>
50 #include <sys/acpica.h>
51 #include <sys/psm_common.h>
52 #include <sys/apic.h>
53 #include <sys/apic_timer.h>
54 #include <sys/pit.h>
55 #include <sys/ddi.h>
56 #include <sys/sunddi.h>
57 #include <sys/ddi_impldefs.h>
58 #include <sys/pci.h>
59 #include <sys/promif.h>
60 #include <sys/x86_archext.h>
61 #include <sys/cpc_impl.h>
62 #include <sys/uadmin.h>
63 #include <sys/panic.h>
64 #include <sys/debug.h>
65 #include <sys/archsystm.h>
66 #include <sys/trap.h>
67 #include <sys/machsystm.h>
68 #include <sys/cpuvar.h>
69 #include <sys/rm_platter.h>
70 #include <sys/privregs.h>
71 #include <sys/cyclic.h>
72 #include <sys/note.h>
73 #include <sys/pci_intr_lib.h>
74 #include <sys/sunndi.h>
75 #include <sys/prom_debug.h>
76 #if !defined(__xpv)
77 #include <sys/hpet.h>
78 #include <sys/clock.h>
79 #endif
80 
81 /*
82  *	Local Function Prototypes
83  */
84 static int apic_handle_defconf(void);
85 static int apic_parse_mpct(caddr_t mpct, int bypass);
86 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
87 static int apic_checksum(caddr_t bptr, int len);
88 static int apic_find_bus_type(char *bus);
89 static int apic_find_bus(int busid);
90 static struct apic_io_intr *apic_find_io_intr(int irqno);
91 static int apic_find_free_irq(int start, int end);
92 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
93 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
94 static void apic_free_apic_cpus(void);
95 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
96 static int apic_acpi_enter_apicmode(void);
97 
98 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
99     int child_ipin, struct apic_io_intr **intrp);
100 int apic_find_bus_id(int bustype);
101 int apic_find_intin(uchar_t ioapic, uchar_t intin);
102 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
103 
104 int apic_debug_mps_id = 0;	/* 1 - print MPS ID strings */
105 
106 /* ACPI SCI interrupt configuration; -1 if SCI not used */
107 int apic_sci_vect = -1;
108 iflag_t apic_sci_flags;
109 
110 #if !defined(__xpv)
111 /* ACPI HPET interrupt configuration; -1 if HPET not used */
112 int apic_hpet_vect = -1;
113 iflag_t apic_hpet_flags;
114 #endif
115 
116 /*
117  * psm name pointer
118  */
119 char *psm_name;
120 
121 /* ACPI support routines */
122 static int acpi_probe(char *);
123 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
124     int *pci_irqp, iflag_t *intr_flagp);
125 
126 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
127     int ipin, int *pci_irqp, iflag_t *intr_flagp);
128 uchar_t acpi_find_ioapic(int irq);
129 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
130 
131 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
132 int apic_max_reps_clear_pending = 1000;
133 
134 int	apic_intr_policy = INTR_ROUND_ROBIN;
135 
136 int	apic_next_bind_cpu = 1; /* For round robin assignment */
137 				/* start with cpu 1 */
138 
139 /*
140  * If enabled, the distribution works as follows:
141  * On every interrupt entry, the current ipl for the CPU is set in cpu_info
142  * and the irq corresponding to the ipl is also set in the aci_current array.
143  * interrupt exit and setspl (due to soft interrupts) will cause the current
144  * ipl to be be changed. This is cache friendly as these frequently used
145  * paths write into a per cpu structure.
146  *
147  * Sampling is done by checking the structures for all CPUs and incrementing
148  * the busy field of the irq (if any) executing on each CPU and the busy field
149  * of the corresponding CPU.
150  * In periodic mode this is done on every clock interrupt.
151  * In one-shot mode, this is done thru a cyclic with an interval of
152  * apic_redistribute_sample_interval (default 10 milli sec).
153  *
154  * Every apic_sample_factor_redistribution times we sample, we do computations
155  * to decide which interrupt needs to be migrated (see comments
156  * before apic_intr_redistribute().
157  */
158 
159 /*
160  * Following 3 variables start as % and can be patched or set using an
161  * API to be defined in future. They will be scaled to
162  * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
163  * mode), or 101 in one-shot mode to stagger it away from one sec processing
164  */
165 
166 int	apic_int_busy_mark = 60;
167 int	apic_int_free_mark = 20;
168 int	apic_diff_for_redistribution = 10;
169 
170 /* sampling interval for interrupt redistribution for dynamic migration */
171 int	apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
172 
173 /*
174  * number of times we sample before deciding to redistribute interrupts
175  * for dynamic migration
176  */
177 int	apic_sample_factor_redistribution = 101;
178 
179 int	apic_redist_cpu_skip = 0;
180 int	apic_num_imbalance = 0;
181 int	apic_num_rebind = 0;
182 
183 /*
184  * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
185  * allocation of CPU ids is disabled.
186  */
187 int	apic_max_nproc = -1;
188 int	apic_nproc = 0;
189 size_t	apic_cpus_size = 0;
190 int	apic_defconf = 0;
191 int	apic_irq_translate = 0;
192 int	apic_spec_rev = 0;
193 int	apic_imcrp = 0;
194 
195 int	apic_use_acpi = 1;	/* 1 = use ACPI, 0 = don't use ACPI */
196 int	apic_use_acpi_madt_only = 0;	/* 1=ONLY use MADT from ACPI */
197 
198 /*
199  * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
200  * will be assigned (via _SRS). If it is not set, use the current
201  * irq setting (via _CRS), but only if that irq is in the set of possible
202  * irqs (returned by _PRS) for the device.
203  */
204 int	apic_unconditional_srs = 1;
205 
206 /*
207  * For interrupt link devices, if apic_prefer_crs is set when we are
208  * assigning an IRQ resource to a device, prefer the current IRQ setting
209  * over other possible irq settings under same conditions.
210  */
211 
212 int	apic_prefer_crs = 1;
213 
214 uchar_t apic_io_id[MAX_IO_APIC];
215 volatile uint32_t *apicioadr[MAX_IO_APIC];
216 uchar_t	apic_io_ver[MAX_IO_APIC];
217 uchar_t	apic_io_vectbase[MAX_IO_APIC];
218 uchar_t	apic_io_vectend[MAX_IO_APIC];
219 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
220 uint32_t apic_physaddr[MAX_IO_APIC];
221 
222 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
223 
224 /*
225  * First available slot to be used as IRQ index into the apic_irq_table
226  * for those interrupts (like MSI/X) that don't have a physical IRQ.
227  */
228 int apic_first_avail_irq  = APIC_FIRST_FREE_IRQ;
229 
230 /*
231  * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
232  * and bound elements of cpus_info and the temp_cpu element of irq_struct
233  */
234 lock_t	apic_ioapic_lock;
235 
236 int	apic_io_max = 0;	/* no. of i/o apics enabled */
237 
238 struct apic_io_intr *apic_io_intrp = NULL;
239 static	struct apic_bus	*apic_busp;
240 
241 uchar_t	apic_resv_vector[MAXIPL+1];
242 
243 char	apic_level_intr[APIC_MAX_VECTOR+1];
244 
245 uint32_t	eisa_level_intr_mask = 0;
246 	/* At least MSB will be set if EISA bus */
247 
248 int	apic_pci_bus_total = 0;
249 uchar_t	apic_single_pci_busid = 0;
250 
251 /*
252  * airq_mutex protects additions to the apic_irq_table - the first
253  * pointer and any airq_nexts off of that one. It also protects
254  * apic_max_device_irq & apic_min_device_irq. It also guarantees
255  * that share_id is unique as new ids are generated only when new
256  * irq_t structs are linked in. Once linked in the structs are never
257  * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
258  * or allocated. Note that there is a slight gap between allocating in
259  * apic_introp_xlate and programming in addspl.
260  */
261 kmutex_t	airq_mutex;
262 apic_irq_t	*apic_irq_table[APIC_MAX_VECTOR+1];
263 int		apic_max_device_irq = 0;
264 int		apic_min_device_irq = APIC_MAX_VECTOR;
265 
266 typedef struct prs_irq_list_ent {
267 	int			list_prio;
268 	int32_t			irq;
269 	iflag_t			intrflags;
270 	acpi_prs_private_t	prsprv;
271 	struct prs_irq_list_ent	*next;
272 } prs_irq_list_t;
273 
274 
275 /*
276  * ACPI variables
277  */
278 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
279 int apic_enable_acpi = 0;
280 
281 /* ACPI Multiple APIC Description Table ptr */
282 static	ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
283 
284 /* ACPI Interrupt Source Override Structure ptr */
285 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
286 int acpi_iso_cnt = 0;
287 
288 /* ACPI Non-maskable Interrupt Sources ptr */
289 static	ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
290 static	int acpi_nmi_scnt = 0;
291 static	ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
292 static	int acpi_nmi_ccnt = 0;
293 
294 static	boolean_t acpi_found_smp_config = B_FALSE;
295 
296 /*
297  * The following added to identify a software poweroff method if available.
298  */
299 
300 static struct {
301 	int	poweroff_method;
302 	char	oem_id[APIC_MPS_OEM_ID_LEN + 1];	/* MAX + 1 for NULL */
303 	char	prod_id[APIC_MPS_PROD_ID_LEN + 1];	/* MAX + 1 for NULL */
304 } apic_mps_ids[] = {
305 	{ APIC_POWEROFF_VIA_RTC,	"INTEL",	"ALDER" },   /* 4300 */
306 	{ APIC_POWEROFF_VIA_RTC,	"NCR",		"AMC" },    /* 4300 */
307 	{ APIC_POWEROFF_VIA_ASPEN_BMC,	"INTEL",	"A450NX" },  /* 4400? */
308 	{ APIC_POWEROFF_VIA_ASPEN_BMC,	"INTEL",	"AD450NX" }, /* 4400 */
309 	{ APIC_POWEROFF_VIA_ASPEN_BMC,	"INTEL",	"AC450NX" }, /* 4400R */
310 	{ APIC_POWEROFF_VIA_SITKA_BMC,	"INTEL",	"S450NX" },  /* S50  */
311 	{ APIC_POWEROFF_VIA_SITKA_BMC,	"INTEL",	"SC450NX" }  /* S50? */
312 };
313 
314 int	apic_poweroff_method = APIC_POWEROFF_NONE;
315 
316 /*
317  * Auto-configuration routines
318  */
319 
320 /*
321  * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
322  * May work with 1.1 - but not guaranteed.
323  * According to the MP Spec, the MP floating pointer structure
324  * will be searched in the order described below:
325  * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
326  * 2. Within the last kilobyte of system base memory
327  * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
328  * Once we find the right signature with proper checksum, we call
329  * either handle_defconf or parse_mpct to get all info necessary for
330  * subsequent operations.
331  */
332 int
apic_probe_common(char * modname)333 apic_probe_common(char *modname)
334 {
335 	uint32_t mpct_addr, ebda_start = 0, base_mem_end;
336 	caddr_t	biosdatap;
337 	caddr_t	mpct = NULL;
338 	caddr_t	fptr = NULL;
339 	int	i, mpct_size = 0, mapsize, retval = PSM_FAILURE;
340 	ushort_t	ebda_seg, base_mem_size;
341 	struct	apic_mpfps_hdr	*fpsp;
342 	struct	apic_mp_cnf_hdr	*hdrp;
343 	int bypass_cpu_and_ioapics_in_mptables;
344 	int acpi_user_options;
345 
346 	PRM_POINT("apic_probe_common()");
347 
348 	if (apic_forceload < 0)
349 		return (retval);
350 
351 	/*
352 	 * Remember who we are
353 	 */
354 	psm_name = modname;
355 
356 	/* Allow override for MADT-only mode */
357 	acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
358 	    "acpi-user-options", 0);
359 	apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
360 
361 	/* Allow apic_use_acpi to override MADT-only mode */
362 	if (!apic_use_acpi)
363 		apic_use_acpi_madt_only = 0;
364 
365 	PRM_POINT("acpi_probe()");
366 	retval = acpi_probe(modname);
367 	PRM_DEBUG(retval);
368 
369 	/* in UEFI system, there is no BIOS data */
370 	if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab")) {
371 		PRM_POINT("UEFI system!");
372 		goto apic_ret;
373 	}
374 
375 	/*
376 	 * mapin the bios data area 40:0
377 	 * 40:13h - two-byte location reports the base memory size
378 	 * 40:0Eh - two-byte location for the exact starting address of
379 	 *	    the EBDA segment for EISA
380 	 */
381 	PRM_POINT("psm_map_phys()");
382 	biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
383 	PRM_DEBUG(biosdatap);
384 	if (!biosdatap)
385 		goto apic_ret;
386 	fpsp = (struct apic_mpfps_hdr *)NULL;
387 	mapsize = MPFPS_RAM_WIN_LEN;
388 	/*LINTED: pointer cast may result in improper alignment */
389 	ebda_seg = *((ushort_t *)(biosdatap+0xe));
390 	PRM_DEBUG(ebda_seg);
391 	/* check the 1k of EBDA */
392 	if (ebda_seg) {
393 		ebda_start = ((uint32_t)ebda_seg) << 4;
394 		fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
395 		PRM_DEBUG(fptr);
396 		if (fptr) {
397 			if (!(fpsp =
398 			    apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
399 				psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
400 		}
401 	}
402 	/* If not in EBDA, check the last k of system base memory */
403 	PRM_DEBUG(fpsp);
404 	if (!fpsp) {
405 		/*LINTED: pointer cast may result in improper alignment */
406 		base_mem_size = *((ushort_t *)(biosdatap + 0x13));
407 
408 		if (base_mem_size > 512)
409 			base_mem_end = 639 * 1024;
410 		else
411 			base_mem_end = 511 * 1024;
412 		/* if ebda == last k of base mem, skip to check BIOS ROM */
413 		if (base_mem_end != ebda_start) {
414 
415 			fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
416 			    PROT_READ);
417 			PRM_DEBUG(fptr);
418 
419 			if (fptr) {
420 				if (!(fpsp = apic_find_fps_sig(fptr,
421 				    MPFPS_RAM_WIN_LEN)))
422 					psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
423 			}
424 		}
425 	}
426 	PRM_POINT("psm_unmap_phys()");
427 	psm_unmap_phys(biosdatap, 0x20);
428 
429 	/* If still cannot find it, check the BIOS ROM space */
430 	PRM_DEBUG(fpsp);
431 	if (!fpsp) {
432 		mapsize = MPFPS_ROM_WIN_LEN;
433 		fptr = psm_map_phys(MPFPS_ROM_WIN_START,
434 		    MPFPS_ROM_WIN_LEN, PROT_READ);
435 		PRM_DEBUG(fptr);
436 		if (fptr) {
437 			if (!(fpsp =
438 			    apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
439 				psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
440 				goto apic_ret;
441 			}
442 		}
443 	}
444 
445 	PRM_DEBUG(fptr);
446 	PRM_DEBUG(fpsp);
447 	PRM_POINT("apic_checksum()");
448 	if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
449 		PRM_POINT("psm_unmap_phys()");
450 		psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
451 		goto apic_ret;
452 	}
453 
454 	apic_spec_rev = fpsp->mpfps_spec_rev;
455 	if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
456 		PRM_POINT("psm_unmap_phys()");
457 		psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
458 		goto apic_ret;
459 	}
460 
461 	/* check IMCR is present or not */
462 	apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
463 
464 	/* check default configuration (dual CPUs) */
465 	if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
466 		PRM_POINT("psm_unmap_phys()");
467 		psm_unmap_phys(fptr, mapsize);
468 		PRM_POINT("apic_handle_defconf()");
469 		if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
470 			return (retval);
471 
472 		goto apic_ret;
473 	}
474 
475 	/* MP Configuration Table */
476 	mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
477 	PRM_DEBUG(mpct_addr);
478 
479 	psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
480 
481 	/*
482 	 * Map in enough memory for the MP Configuration Table Header.
483 	 * Use this table to read the total length of the BIOS data and
484 	 * map in all the info
485 	 */
486 	/*LINTED: pointer cast may result in improper alignment */
487 	hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
488 	    sizeof (struct apic_mp_cnf_hdr), PROT_READ);
489 	if (!hdrp)
490 		goto apic_ret;
491 
492 	/* check mp configuration table signature PCMP */
493 	if (hdrp->mpcnf_sig != 0x504d4350) {
494 		psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
495 		goto apic_ret;
496 	}
497 	mpct_size = (int)hdrp->mpcnf_tbl_length;
498 
499 	PRM_POINT("apic_set_pwroff_method_from_mpcnfhdr()");
500 	apic_set_pwroff_method_from_mpcnfhdr(hdrp);
501 
502 	psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
503 
504 	if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
505 		/* This is an ACPI machine No need for further checks */
506 		goto apic_ret;
507 	}
508 
509 	/*
510 	 * Map in the entries for this machine, ie. Processor
511 	 * Entry Tables, Bus Entry Tables, etc.
512 	 * They are in fixed order following one another
513 	 */
514 	mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
515 	if (!mpct)
516 		goto apic_ret;
517 
518 	if (apic_checksum(mpct, mpct_size) != 0)
519 		goto apic_fail1;
520 
521 	/*LINTED: pointer cast may result in improper alignment */
522 	hdrp = (struct apic_mp_cnf_hdr *)mpct;
523 	apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
524 	    APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
525 	PRM_DEBUG(hdrp);
526 	PRM_DEBUG(apicadr);
527 	if (!apicadr)
528 		goto apic_fail1;
529 
530 	/* Parse all information in the tables */
531 	bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
532 	if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
533 	    PSM_SUCCESS) {
534 		retval = PSM_SUCCESS;
535 		goto apic_ret;
536 	}
537 
538 apic_fail1:
539 	PRM_POINT("apic_fail1:");
540 	psm_unmap_phys(mpct, mpct_size);
541 	mpct = NULL;
542 
543 apic_ret:
544 	PRM_POINT("apic_ret:");
545 	if (retval == PSM_SUCCESS) {
546 		extern int apic_ioapic_method_probe();
547 
548 		PRM_POINT("apic_ioapic_method_probe()");
549 		if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS) {
550 			PRM_POINT("SUCCESS");
551 			return (PSM_SUCCESS);
552 		}
553 	}
554 
555 	for (i = 0; i < apic_io_max; i++)
556 		mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
557 	if (apic_cpus) {
558 		kmem_free(apic_cpus, apic_cpus_size);
559 		apic_cpus = NULL;
560 	}
561 	if (apicadr) {
562 		mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
563 		apicadr = NULL;
564 	}
565 	if (mpct)
566 		psm_unmap_phys(mpct, mpct_size);
567 
568 	PRM_DEBUG(retval);
569 	return (retval);
570 }
571 
572 static void
apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr * hdrp)573 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
574 {
575 	int	i;
576 
577 	for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
578 	    i++) {
579 		if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
580 		    strlen(apic_mps_ids[i].oem_id)) == 0) &&
581 		    (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
582 		    strlen(apic_mps_ids[i].prod_id)) == 0)) {
583 
584 			apic_poweroff_method = apic_mps_ids[i].poweroff_method;
585 			break;
586 		}
587 	}
588 
589 	if (apic_debug_mps_id != 0) {
590 		cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
591 		    "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
592 		    psm_name,
593 		    hdrp->mpcnf_oem_str[0],
594 		    hdrp->mpcnf_oem_str[1],
595 		    hdrp->mpcnf_oem_str[2],
596 		    hdrp->mpcnf_oem_str[3],
597 		    hdrp->mpcnf_oem_str[4],
598 		    hdrp->mpcnf_oem_str[5],
599 		    hdrp->mpcnf_oem_str[6],
600 		    hdrp->mpcnf_oem_str[7],
601 		    hdrp->mpcnf_prod_str[0],
602 		    hdrp->mpcnf_prod_str[1],
603 		    hdrp->mpcnf_prod_str[2],
604 		    hdrp->mpcnf_prod_str[3],
605 		    hdrp->mpcnf_prod_str[4],
606 		    hdrp->mpcnf_prod_str[5],
607 		    hdrp->mpcnf_prod_str[6],
608 		    hdrp->mpcnf_prod_str[7],
609 		    hdrp->mpcnf_prod_str[8],
610 		    hdrp->mpcnf_prod_str[9],
611 		    hdrp->mpcnf_prod_str[10],
612 		    hdrp->mpcnf_prod_str[11]);
613 	}
614 }
615 
616 static void
apic_free_apic_cpus(void)617 apic_free_apic_cpus(void)
618 {
619 	if (apic_cpus != NULL) {
620 		kmem_free(apic_cpus, apic_cpus_size);
621 		apic_cpus = NULL;
622 		apic_cpus_size = 0;
623 	}
624 }
625 
626 static uint32_t
acpi_get_apic_lid(void)627 acpi_get_apic_lid(void)
628 {
629 	uint32_t	id;
630 
631 	id = apic_reg_ops->apic_read(APIC_LID_REG);
632 	if (apic_mode != LOCAL_X2APIC)
633 		id >>= APIC_ID_BIT_OFFSET;
634 
635 	return (id);
636 }
637 
638 static int
acpi_probe(char * modname)639 acpi_probe(char *modname)
640 {
641 	int			i, intmax;
642 	uint32_t		id, ver;
643 	int			acpi_verboseflags = 0;
644 	int			madt_seen, madt_size;
645 	ACPI_SUBTABLE_HEADER		*ap;
646 	ACPI_MADT_LOCAL_APIC	*mpa;
647 	ACPI_MADT_LOCAL_X2APIC	*mpx2a;
648 	ACPI_MADT_IO_APIC		*mia;
649 	ACPI_MADT_IO_SAPIC		*misa;
650 	ACPI_MADT_INTERRUPT_OVERRIDE	*mio;
651 	ACPI_MADT_NMI_SOURCE		*mns;
652 	ACPI_MADT_INTERRUPT_SOURCE	*mis;
653 	ACPI_MADT_LOCAL_APIC_NMI	*mlan;
654 	ACPI_MADT_LOCAL_X2APIC_NMI	*mx2alan;
655 	ACPI_MADT_LOCAL_APIC_OVERRIDE	*mao;
656 	int			sci;
657 	iflag_t			sci_flags;
658 	volatile uint32_t	*ioapic;
659 	int			ioapic_ix;
660 	uint32_t		*local_ids;
661 	uint32_t		*proc_ids;
662 	uchar_t			hid;
663 	int			warned = 0;
664 
665 	if (!apic_use_acpi)
666 		return (PSM_FAILURE);
667 
668 	PRM_POINT("AcpiGetTable(MADT)");
669 	if (AcpiGetTable(ACPI_SIG_MADT, 1,
670 	    (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
671 		cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
672 		return (PSM_FAILURE);
673 	}
674 
675 	PRM_DEBUG((uint32_t)acpi_mapic_dtp->Address);
676 	PRM_POINT("mapin_apic()");
677 	apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
678 	    APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
679 	if (!apicadr)
680 		return (PSM_FAILURE);
681 
682 	if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
683 	    KM_NOSLEEP)) == NULL) {
684 		return (PSM_FAILURE);
685 	}
686 
687 	if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
688 	    KM_NOSLEEP)) == NULL) {
689 		kmem_free(local_ids, NCPU * sizeof (uint32_t));
690 		return (PSM_FAILURE);
691 	}
692 
693 	PRM_POINT("acpi_get_apic_lid()");
694 	local_ids[0] = acpi_get_apic_lid();
695 	PRM_DEBUG(local_ids[0]);
696 
697 	apic_nproc = 1;
698 	apic_io_max = 0;
699 
700 	ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
701 	madt_size = acpi_mapic_dtp->Header.Length;
702 	madt_seen = sizeof (*acpi_mapic_dtp);
703 
704 	PRM_DEBUG(madt_size);
705 	while (madt_seen < madt_size) {
706 		switch (ap->Type) {
707 		case ACPI_MADT_TYPE_LOCAL_APIC:
708 			mpa = (ACPI_MADT_LOCAL_APIC *) ap;
709 			if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
710 				if (mpa->Id == 255) {
711 					cmn_err(CE_WARN, "!%s: encountered "
712 					    "invalid entry in MADT: CPU %d "
713 					    "has Local APIC Id equal to 255",
714 					    psm_name, mpa->ProcessorId);
715 				}
716 				if (mpa->Id == local_ids[0]) {
717 					proc_ids[0] = mpa->ProcessorId;
718 				} else if (apic_nproc < NCPU && use_mp &&
719 				    apic_nproc < boot_ncpus) {
720 					local_ids[apic_nproc] = mpa->Id;
721 					proc_ids[apic_nproc] = mpa->ProcessorId;
722 					apic_nproc++;
723 				} else if (apic_nproc == NCPU && !warned) {
724 					cmn_err(CE_WARN, "%s: CPU limit "
725 					    "exceeded; will use %d CPUs.",
726 					    psm_name,  NCPU);
727 					warned = 1;
728 				}
729 			}
730 			break;
731 
732 		case ACPI_MADT_TYPE_IO_APIC:
733 			mia = (ACPI_MADT_IO_APIC *) ap;
734 			if (apic_io_max < MAX_IO_APIC) {
735 				ioapic_ix = apic_io_max;
736 				apic_io_id[apic_io_max] = mia->Id;
737 				apic_io_vectbase[apic_io_max] =
738 				    mia->GlobalIrqBase;
739 				apic_physaddr[apic_io_max] =
740 				    (uint32_t)mia->Address;
741 				ioapic = apicioadr[apic_io_max] =
742 				    mapin_ioapic((uint32_t)mia->Address,
743 				    APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
744 				if (!ioapic)
745 					goto cleanup;
746 				ioapic_mask_workaround[apic_io_max] =
747 				    apic_is_ioapic_AMD_813x(mia->Address);
748 				apic_io_max++;
749 			}
750 			break;
751 
752 		case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
753 			mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
754 			if (acpi_isop == NULL)
755 				acpi_isop = mio;
756 			acpi_iso_cnt++;
757 			break;
758 
759 		case ACPI_MADT_TYPE_NMI_SOURCE:
760 			/* UNIMPLEMENTED */
761 			mns = (ACPI_MADT_NMI_SOURCE *) ap;
762 			if (acpi_nmi_sp == NULL)
763 				acpi_nmi_sp = mns;
764 			acpi_nmi_scnt++;
765 
766 			cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x",
767 			    mns->GlobalIrq, mns->IntiFlags);
768 			break;
769 
770 		case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
771 			/* UNIMPLEMENTED */
772 			mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
773 			if (acpi_nmi_cp == NULL)
774 				acpi_nmi_cp = mlan;
775 			acpi_nmi_ccnt++;
776 
777 			cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d",
778 			    mlan->ProcessorId, mlan->IntiFlags,
779 			    mlan->Lint);
780 			break;
781 
782 		case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
783 			/* UNIMPLEMENTED */
784 			mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
785 			cmn_err(CE_NOTE, "!apic: address override: %lx",
786 			    (long)mao->Address);
787 			break;
788 
789 		case ACPI_MADT_TYPE_IO_SAPIC:
790 			/* UNIMPLEMENTED */
791 			misa = (ACPI_MADT_IO_SAPIC *) ap;
792 
793 			cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx",
794 			    misa->Id, misa->GlobalIrqBase,
795 			    (long)misa->Address);
796 			break;
797 
798 		case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
799 			/* UNIMPLEMENTED */
800 			mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
801 
802 			cmn_err(CE_NOTE,
803 			    "!apic: irq source: %d %d %d 0x%x %d %d",
804 			    mis->Id, mis->Eid, mis->GlobalIrq,
805 			    mis->IntiFlags, mis->Type,
806 			    mis->IoSapicVector);
807 			break;
808 
809 		case ACPI_MADT_TYPE_LOCAL_X2APIC:
810 			mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
811 
812 			if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
813 				if (mpx2a->LocalApicId == local_ids[0]) {
814 					proc_ids[0] = mpx2a->Uid;
815 				} else if (apic_nproc < NCPU && use_mp &&
816 				    apic_nproc < boot_ncpus) {
817 					local_ids[apic_nproc] =
818 					    mpx2a->LocalApicId;
819 					proc_ids[apic_nproc] = mpx2a->Uid;
820 					apic_nproc++;
821 				} else if (apic_nproc == NCPU && !warned) {
822 					cmn_err(CE_WARN, "%s: CPU limit "
823 					    "exceeded; will use %d CPUs.",
824 					    psm_name,  NCPU);
825 					warned = 1;
826 				}
827 			}
828 
829 			break;
830 
831 		case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
832 			/* UNIMPLEMENTED */
833 			mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
834 			if (mx2alan->Uid >> 8)
835 				acpi_nmi_ccnt++;
836 
837 #ifdef DEBUG
838 			cmn_err(CE_NOTE,
839 			    "!apic: local x2apic nmi: %d 0x%x %d",
840 			    mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
841 #endif
842 
843 			break;
844 
845 		case ACPI_MADT_TYPE_RESERVED:
846 		default:
847 			break;
848 		}
849 
850 		/* advance to next entry */
851 		madt_seen += ap->Length;
852 		ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
853 	}
854 
855 	PRM_DEBUG(apic_nproc);
856 	PRM_DEBUG(apic_io_max);
857 
858 	/* We found multiple enabled cpus via MADT */
859 	if ((apic_nproc > 1) && (apic_io_max > 0)) {
860 		acpi_found_smp_config = B_TRUE;
861 		cmn_err(CE_NOTE,
862 		    "!apic: Using ACPI (MADT) for SMP configuration");
863 	}
864 
865 	/*
866 	 * allocate enough space for possible hot-adding of CPUs.
867 	 * max_ncpus may be less than apic_nproc if it's set by user.
868 	 */
869 	if (plat_dr_support_cpu()) {
870 		apic_max_nproc = max_ncpus;
871 	}
872 	PRM_DEBUG(apic_max_nproc);
873 	apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
874 	if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
875 		goto cleanup;
876 
877 	/*
878 	 * ACPI doesn't provide the local apic ver, get it directly from the
879 	 * local apic
880 	 */
881 	PRM_POINT("apic_read(APIC_VERS_REG)");
882 	ver = apic_reg_ops->apic_read(APIC_VERS_REG);
883 	PRM_DEBUG(ver);
884 	PRM_DEBUG(apic_nproc);
885 	PRM_DEBUG(boot_ncpus);
886 	for (i = 0; i < apic_nproc; i++) {
887 		apic_cpus[i].aci_local_id = local_ids[i];
888 		apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
889 		apic_cpus[i].aci_processor_id = proc_ids[i];
890 		/* Only build mapping info for CPUs present at boot. */
891 		if (i < boot_ncpus) {
892 			(void) acpica_map_cpu(i, proc_ids[i]);
893 		}
894 	}
895 	PRM_POINT("acpica_map_cpu loop complete");
896 
897 	/*
898 	 * To support CPU dynamic reconfiguration, the apic CPU info structure
899 	 * for each possible CPU will be pre-allocated at boot time.
900 	 * The state for each apic CPU info structure will be assigned according
901 	 * to the following rules:
902 	 * Rule 1:
903 	 *	Slot index range: [0, min(apic_nproc, boot_ncpus))
904 	 *	State flags: 0
905 	 *	Note: cpu exists and will be configured/enabled at boot time
906 	 * Rule 2:
907 	 *	Slot index range: [boot_ncpus, apic_nproc)
908 	 *	State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
909 	 *	Note: cpu exists but won't be configured/enabled at boot time
910 	 * Rule 3:
911 	 *	Slot index range: [apic_nproc, boot_ncpus)
912 	 *	State flags: APIC_CPU_FREE
913 	 *	Note: cpu doesn't exist at boot time
914 	 * Rule 4:
915 	 *	Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
916 	 *	State flags: APIC_CPU_FREE
917 	 *	Note: cpu doesn't exist at boot time
918 	 */
919 	CPUSET_ZERO(apic_cpumask);
920 	for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
921 		CPUSET_ADD(apic_cpumask, i);
922 		apic_cpus[i].aci_status = 0;
923 	}
924 	for (i = boot_ncpus; i < apic_nproc; i++) {
925 		apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
926 	}
927 	for (i = apic_nproc; i < boot_ncpus; i++) {
928 		apic_cpus[i].aci_status = APIC_CPU_FREE;
929 	}
930 	for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
931 		apic_cpus[i].aci_status = APIC_CPU_FREE;
932 	}
933 
934 	PRM_POINT("ioapic reads");
935 	for (i = 0; i < apic_io_max; i++) {
936 		ioapic_ix = i;
937 		PRM_DEBUG(ioapic_ix);
938 
939 		/*
940 		 * need to check Sitka on the following acpi problem
941 		 * On the Sitka, the ioapic's apic_id field isn't reporting
942 		 * the actual io apic id. We have reported this problem
943 		 * to Intel. Until they fix the problem, we will get the
944 		 * actual id directly from the ioapic.
945 		 */
946 		id = ioapic_read(ioapic_ix, APIC_ID_CMD);
947 		PRM_DEBUG(id);
948 		hid = (uchar_t)(id >> 24);
949 		PRM_DEBUG(hid);
950 
951 		if (hid != apic_io_id[i]) {
952 			if (apic_io_id[i] == 0)
953 				apic_io_id[i] = hid;
954 			else { /* set ioapic id to whatever reported by ACPI */
955 				id = ((uint32_t)apic_io_id[i]) << 24;
956 				PRM_POINT("ioapic_write(ID)");
957 				ioapic_write(ioapic_ix, APIC_ID_CMD, id);
958 			}
959 		}
960 		PRM_POINT("ioapic_read(VERS)");
961 		ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
962 		apic_io_ver[i] = (uchar_t)(ver & 0xff);
963 		intmax = (ver >> 16) & 0xff;
964 		apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
965 		if (apic_first_avail_irq <= apic_io_vectend[i])
966 			apic_first_avail_irq = apic_io_vectend[i] + 1;
967 	}
968 
969 
970 	/*
971 	 * Process SCI configuration here
972 	 * An error may be returned here if
973 	 * acpi-user-options specifies legacy mode
974 	 * (no SCI, no ACPI mode)
975 	 */
976 	PRM_POINT("acpica_get_sci()");
977 	if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
978 		sci = -1;
979 
980 	/*
981 	 * Now call acpi_init() to generate namespaces
982 	 * If this fails, we don't attempt to use ACPI
983 	 * even if we were able to get a MADT above
984 	 */
985 	PRM_POINT("acpica_init()");
986 	if (acpica_init() != AE_OK) {
987 		cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
988 		goto cleanup;
989 	}
990 
991 	/*
992 	 * Call acpica_build_processor_map() now that we have
993 	 * ACPI namesspace access
994 	 */
995 	PRM_POINT("acpica_build_processor_map()");
996 	(void) acpica_build_processor_map();
997 
998 	/*
999 	 * Squirrel away the SCI and flags for later on
1000 	 * in apic_picinit() when we're ready
1001 	 */
1002 	apic_sci_vect = sci;
1003 	apic_sci_flags = sci_flags;
1004 
1005 	if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
1006 		acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
1007 
1008 	if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
1009 		acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
1010 
1011 	if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
1012 		acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
1013 
1014 	PRM_POINT("acpi_psm_init()");
1015 	if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
1016 		goto cleanup;
1017 
1018 	/* Enable ACPI APIC interrupt routing */
1019 	PRM_POINT("apic_acpi_enter_apicmode()");
1020 	if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
1021 		cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
1022 		PRM_POINT("build_reserved_irqlist()");
1023 		build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
1024 		apic_enable_acpi = 1;
1025 		if (apic_sci_vect > 0) {
1026 			PRM_POINT("acpica_set_core_feature()");
1027 			acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
1028 		}
1029 		if (apic_use_acpi_madt_only) {
1030 			cmn_err(CE_CONT,
1031 			    "?Using ACPI for CPU/IOAPIC information ONLY\n");
1032 		}
1033 
1034 #if !defined(__xpv)
1035 		/*
1036 		 * Probe ACPI for HPET information here which is used later in
1037 		 * apic_picinit().  Note that we do not need to use the HPET at
1038 		 * all on most modern systems, but if there is an actionable
1039 		 * failure message it will be logged by the routine itself.
1040 		 */
1041 		PRM_POINT("hpet_acpi_init()");
1042 		(void) hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags);
1043 #endif
1044 
1045 		kmem_free(local_ids, NCPU * sizeof (uint32_t));
1046 		kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1047 		PRM_POINT("SUCCESS");
1048 		return (PSM_SUCCESS);
1049 	}
1050 	/* if setting APIC mode failed above, we fall through to cleanup */
1051 
1052 cleanup:
1053 	cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
1054 	    acpi_found_smp_config ? "found" : "not found");
1055 	apic_free_apic_cpus();
1056 	if (apicadr != NULL) {
1057 		mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1058 		apicadr = NULL;
1059 	}
1060 	apic_max_nproc = -1;
1061 	apic_nproc = 0;
1062 	for (i = 0; i < apic_io_max; i++) {
1063 		mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
1064 		apicioadr[i] = NULL;
1065 	}
1066 	apic_io_max = 0;
1067 	acpi_isop = NULL;
1068 	acpi_iso_cnt = 0;
1069 	acpi_nmi_sp = NULL;
1070 	acpi_nmi_scnt = 0;
1071 	acpi_nmi_cp = NULL;
1072 	acpi_nmi_ccnt = 0;
1073 	acpi_found_smp_config = B_FALSE;
1074 	kmem_free(local_ids, NCPU * sizeof (uint32_t));
1075 	kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1076 	return (PSM_FAILURE);
1077 }
1078 
1079 /*
1080  * Handle default configuration. Fill in reqd global variables & tables
1081  * Fill all details as MP table does not give any more info
1082  */
1083 static int
apic_handle_defconf(void)1084 apic_handle_defconf(void)
1085 {
1086 	/* Failed to probe ACPI MADT tables, disable CPU DR. */
1087 	apic_max_nproc = -1;
1088 	apic_free_apic_cpus();
1089 	plat_dr_disable_cpu();
1090 
1091 	apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1092 	    APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1093 	apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1094 	    APIC_LOCAL_MEMLEN, PROT_READ);
1095 	apic_cpus_size = 2 * sizeof (*apic_cpus);
1096 	apic_cpus = (apic_cpus_info_t *)
1097 	    kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1098 	if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1099 		goto apic_handle_defconf_fail;
1100 	CPUSET_ONLY(apic_cpumask, 0);
1101 	CPUSET_ADD(apic_cpumask, 1);
1102 	apic_nproc = 2;
1103 	apic_cpus[0].aci_local_id = acpi_get_apic_lid();
1104 	/*
1105 	 * According to the PC+MP spec 1.1, the local ids
1106 	 * for the default configuration has to be 0 or 1
1107 	 */
1108 	if (apic_cpus[0].aci_local_id == 1)
1109 		apic_cpus[1].aci_local_id = 0;
1110 	else if (apic_cpus[0].aci_local_id == 0)
1111 		apic_cpus[1].aci_local_id = 1;
1112 	else
1113 		goto apic_handle_defconf_fail;
1114 
1115 	apic_io_id[0] = 2;
1116 	apic_io_max = 1;
1117 	if (apic_defconf >= 5) {
1118 		apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1119 		apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1120 		apic_io_ver[0] = APIC_INTEGRATED_VERS;
1121 	} else {
1122 		apic_cpus[0].aci_local_ver = 0;		/* 82489 DX */
1123 		apic_cpus[1].aci_local_ver = 0;
1124 		apic_io_ver[0] = 0;
1125 	}
1126 	if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1127 		eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1128 		    inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1129 	return (PSM_SUCCESS);
1130 
1131 apic_handle_defconf_fail:
1132 	if (apicadr)
1133 		mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1134 	if (apicioadr[0])
1135 		mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1136 	return (PSM_FAILURE);
1137 }
1138 
1139 /* Parse the entries in MP configuration table and collect info that we need */
1140 static int
apic_parse_mpct(caddr_t mpct,int bypass_cpus_and_ioapics)1141 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1142 {
1143 	struct	apic_procent	*procp;
1144 	struct	apic_bus	*busp;
1145 	struct	apic_io_entry	*ioapicp;
1146 	struct	apic_io_intr	*intrp;
1147 	int			ioapic_ix;
1148 	uint32_t		lid, id;
1149 	uchar_t			hid;
1150 	int			warned = 0;
1151 
1152 	/*LINTED: pointer cast may result in improper alignment */
1153 	procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1154 
1155 	/* No need to count cpu entries if we won't use them */
1156 	if (!bypass_cpus_and_ioapics) {
1157 
1158 		/* Find max # of CPUS and allocate structure accordingly */
1159 		apic_nproc = 0;
1160 		CPUSET_ZERO(apic_cpumask);
1161 		while (procp->proc_entry == APIC_CPU_ENTRY) {
1162 			if (procp->proc_cpuflags & CPUFLAGS_EN) {
1163 				if (apic_nproc < NCPU && use_mp &&
1164 				    apic_nproc < boot_ncpus) {
1165 					CPUSET_ADD(apic_cpumask, apic_nproc);
1166 					apic_nproc++;
1167 				} else if (apic_nproc == NCPU && !warned) {
1168 					cmn_err(CE_WARN, "%s: CPU limit "
1169 					    "exceeded; will use %d CPUs.",
1170 					    psm_name,  NCPU);
1171 					warned = 1;
1172 				}
1173 
1174 			}
1175 			procp++;
1176 		}
1177 		apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1178 		if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1179 		    kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1180 			return (PSM_FAILURE);
1181 	}
1182 
1183 	/*LINTED: pointer cast may result in improper alignment */
1184 	procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1185 
1186 	/*
1187 	 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1188 	 * if we're bypassing this information, it has already been filled
1189 	 * in by acpi_probe(), so don't overwrite it.
1190 	 */
1191 	if (!bypass_cpus_and_ioapics)
1192 		apic_nproc = 1;
1193 
1194 	while (procp->proc_entry == APIC_CPU_ENTRY) {
1195 		/* check whether the cpu exists or not */
1196 		if (!bypass_cpus_and_ioapics &&
1197 		    procp->proc_cpuflags & CPUFLAGS_EN) {
1198 			if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1199 				lid = acpi_get_apic_lid();
1200 				apic_cpus[0].aci_local_id = procp->proc_apicid;
1201 				if (apic_cpus[0].aci_local_id != lid) {
1202 					return (PSM_FAILURE);
1203 				}
1204 				apic_cpus[0].aci_local_ver =
1205 				    procp->proc_version;
1206 			} else if (apic_nproc < NCPU && use_mp &&
1207 			    apic_nproc < boot_ncpus) {
1208 				apic_cpus[apic_nproc].aci_local_id =
1209 				    procp->proc_apicid;
1210 
1211 				apic_cpus[apic_nproc].aci_local_ver =
1212 				    procp->proc_version;
1213 				apic_nproc++;
1214 
1215 			}
1216 		}
1217 		procp++;
1218 	}
1219 
1220 	/*
1221 	 * Save start of bus entries for later use.
1222 	 * Get EISA level cntrl if EISA bus is present.
1223 	 * Also get the CPI bus id for single CPI bus case
1224 	 */
1225 	apic_busp = busp = (struct apic_bus *)procp;
1226 	while (busp->bus_entry == APIC_BUS_ENTRY) {
1227 		lid = apic_find_bus_type((char *)&busp->bus_str1);
1228 		if (lid	== BUS_EISA) {
1229 			eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1230 			    inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1231 		} else if (lid == BUS_PCI) {
1232 			/*
1233 			 * apic_single_pci_busid will be used only if
1234 			 * apic_pic_bus_total is equal to 1
1235 			 */
1236 			apic_pci_bus_total++;
1237 			apic_single_pci_busid = busp->bus_id;
1238 		}
1239 		busp++;
1240 	}
1241 
1242 	ioapicp = (struct apic_io_entry *)busp;
1243 
1244 	if (!bypass_cpus_and_ioapics)
1245 		apic_io_max = 0;
1246 	do {
1247 		if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1248 			if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1249 				apic_io_id[apic_io_max] = ioapicp->io_apicid;
1250 				apic_io_ver[apic_io_max] = ioapicp->io_version;
1251 				apicioadr[apic_io_max] =
1252 				    (void *)mapin_ioapic(
1253 				    (uint32_t)ioapicp->io_apic_addr,
1254 				    APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1255 
1256 				if (!apicioadr[apic_io_max])
1257 					return (PSM_FAILURE);
1258 
1259 				ioapic_mask_workaround[apic_io_max] =
1260 				    apic_is_ioapic_AMD_813x(
1261 				    ioapicp->io_apic_addr);
1262 
1263 				ioapic_ix = apic_io_max;
1264 				id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1265 				hid = (uchar_t)(id >> 24);
1266 
1267 				if (hid != apic_io_id[apic_io_max]) {
1268 					if (apic_io_id[apic_io_max] == 0)
1269 						apic_io_id[apic_io_max] = hid;
1270 					else {
1271 						/*
1272 						 * set ioapic id to whatever
1273 						 * reported by MPS
1274 						 *
1275 						 * may not need to set index
1276 						 * again ???
1277 						 * take it out and try
1278 						 */
1279 
1280 						id = ((uint32_t)
1281 						    apic_io_id[apic_io_max]) <<
1282 						    24;
1283 
1284 						ioapic_write(ioapic_ix,
1285 						    APIC_ID_CMD, id);
1286 					}
1287 				}
1288 				apic_io_max++;
1289 			}
1290 		}
1291 		ioapicp++;
1292 	} while (ioapicp->io_entry == APIC_IO_ENTRY);
1293 
1294 	apic_io_intrp = (struct apic_io_intr *)ioapicp;
1295 
1296 	intrp = apic_io_intrp;
1297 	while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1298 		if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1299 		    (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1300 			apic_irq_translate = 1;
1301 			break;
1302 		}
1303 		intrp++;
1304 	}
1305 
1306 	return (PSM_SUCCESS);
1307 }
1308 
1309 boolean_t
apic_cpu_in_range(int cpu)1310 apic_cpu_in_range(int cpu)
1311 {
1312 	cpu &= ~IRQ_USER_BOUND;
1313 	/* Check whether cpu id is in valid range. */
1314 	if (cpu < 0 || cpu >= apic_nproc) {
1315 		return (B_FALSE);
1316 	} else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1317 		/*
1318 		 * Check whether cpuid is in valid range if CPU DR is enabled.
1319 		 */
1320 		return (B_FALSE);
1321 	} else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1322 		return (B_FALSE);
1323 	}
1324 
1325 	return (B_TRUE);
1326 }
1327 
1328 processorid_t
apic_get_next_bind_cpu(void)1329 apic_get_next_bind_cpu(void)
1330 {
1331 	int i, count;
1332 	processorid_t cpuid = 0;
1333 
1334 	for (count = 0; count < apic_nproc; count++) {
1335 		if (apic_next_bind_cpu >= apic_nproc) {
1336 			apic_next_bind_cpu = 0;
1337 		}
1338 		i = apic_next_bind_cpu++;
1339 		if (apic_cpu_in_range(i)) {
1340 			cpuid = i;
1341 			break;
1342 		}
1343 	}
1344 
1345 	return (cpuid);
1346 }
1347 
1348 uint16_t
apic_get_apic_version()1349 apic_get_apic_version()
1350 {
1351 	int i;
1352 	uchar_t min_io_apic_ver = 0;
1353 	static uint16_t version;		/* Cache as value is constant */
1354 	static boolean_t found = B_FALSE;	/* Accomodate zero version */
1355 
1356 	if (found == B_FALSE) {
1357 		found = B_TRUE;
1358 
1359 		/*
1360 		 * Don't assume all IO APICs in the system are the same.
1361 		 *
1362 		 * Set to the minimum version.
1363 		 */
1364 		for (i = 0; i < apic_io_max; i++) {
1365 			if ((apic_io_ver[i] != 0) &&
1366 			    ((min_io_apic_ver == 0) ||
1367 			    (min_io_apic_ver >= apic_io_ver[i])))
1368 				min_io_apic_ver = apic_io_ver[i];
1369 		}
1370 
1371 		/* Assume all local APICs are of the same version. */
1372 		version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1373 	}
1374 	return (version);
1375 }
1376 
1377 static struct apic_mpfps_hdr *
apic_find_fps_sig(caddr_t cptr,int len)1378 apic_find_fps_sig(caddr_t cptr, int len)
1379 {
1380 	int	i;
1381 
1382 	/* Look for the pattern "_MP_" */
1383 	for (i = 0; i < len; i += 16) {
1384 		if ((*(cptr+i) == '_') &&
1385 		    (*(cptr+i+1) == 'M') &&
1386 		    (*(cptr+i+2) == 'P') &&
1387 		    (*(cptr+i+3) == '_'))
1388 		    /*LINTED: pointer cast may result in improper alignment */
1389 			return ((struct apic_mpfps_hdr *)(cptr + i));
1390 	}
1391 	return (NULL);
1392 }
1393 
1394 static int
apic_checksum(caddr_t bptr,int len)1395 apic_checksum(caddr_t bptr, int len)
1396 {
1397 	int	i;
1398 	uchar_t	cksum;
1399 
1400 	cksum = 0;
1401 	for (i = 0; i < len; i++)
1402 		cksum += *bptr++;
1403 	return ((int)cksum);
1404 }
1405 
1406 /*
1407  * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1408  * needs special handling.  We may need to chase up the device tree,
1409  * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1410  * to find the IPIN at the root bus that relates to the IPIN on the
1411  * subsidiary bus (for ACPI or MP).  We may, however, have an entry
1412  * in the MP table or the ACPI namespace for this device itself.
1413  * We handle both cases in the search below.
1414  */
1415 /* this is the non-acpi version */
1416 int
apic_handle_pci_pci_bridge(dev_info_t * idip,int child_devno,int child_ipin,struct apic_io_intr ** intrp)1417 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1418     struct apic_io_intr **intrp)
1419 {
1420 	dev_info_t *dipp, *dip;
1421 	int pci_irq;
1422 	ddi_acc_handle_t cfg_handle;
1423 	int bridge_devno, bridge_bus;
1424 	int ipin;
1425 
1426 	dip = idip;
1427 
1428 	/*CONSTCOND*/
1429 	while (1) {
1430 		if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1431 		    (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1432 			return (-1);
1433 		if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1434 		    PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1435 		    PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1436 			pci_config_teardown(&cfg_handle);
1437 			if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1438 			    NULL) != 0)
1439 				return (-1);
1440 			/*
1441 			 * This is the rotating scheme documented in the
1442 			 * PCI-to-PCI spec.  If the PCI-to-PCI bridge is
1443 			 * behind another PCI-to-PCI bridge, then it needs
1444 			 * to keep ascending until an interrupt entry is
1445 			 * found or the root is reached.
1446 			 */
1447 			ipin = (child_devno + child_ipin) % PCI_INTD;
1448 			if (bridge_bus == 0 && apic_pci_bus_total == 1)
1449 				bridge_bus = (int)apic_single_pci_busid;
1450 			pci_irq = ((bridge_devno & 0x1f) << 2) |
1451 			    (ipin & 0x3);
1452 			if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1453 			    bridge_bus)) != NULL) {
1454 				return (pci_irq);
1455 			}
1456 			dip = dipp;
1457 			child_devno = bridge_devno;
1458 			child_ipin = ipin;
1459 		} else {
1460 			pci_config_teardown(&cfg_handle);
1461 			return (-1);
1462 		}
1463 	}
1464 	/*LINTED: function will not fall off the bottom */
1465 }
1466 
1467 uchar_t
acpi_find_ioapic(int irq)1468 acpi_find_ioapic(int irq)
1469 {
1470 	int i;
1471 
1472 	for (i = 0; i < apic_io_max; i++) {
1473 		if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1474 			return ((uchar_t)i);
1475 	}
1476 	return (0xFF);	/* shouldn't happen */
1477 }
1478 
1479 /*
1480  * See if two irqs are compatible for sharing a vector.
1481  * Currently we only support sharing of PCI devices.
1482  */
1483 static int
acpi_intr_compatible(iflag_t iflag1,iflag_t iflag2)1484 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1485 {
1486 	uint_t	level1, po1;
1487 	uint_t	level2, po2;
1488 
1489 	/* Assume active high by default */
1490 	po1 = 0;
1491 	po2 = 0;
1492 
1493 	if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1494 		return (0);
1495 
1496 	if (iflag1.intr_el == INTR_EL_CONFORM)
1497 		level1 = AV_LEVEL;
1498 	else
1499 		level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1500 
1501 	if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1502 	    (iflag1.intr_po == INTR_PO_CONFORM)))
1503 		po1 = AV_ACTIVE_LOW;
1504 
1505 	if (iflag2.intr_el == INTR_EL_CONFORM)
1506 		level2 = AV_LEVEL;
1507 	else
1508 		level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1509 
1510 	if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1511 	    (iflag2.intr_po == INTR_PO_CONFORM)))
1512 		po2 = AV_ACTIVE_LOW;
1513 
1514 	if ((level1 == level2) && (po1 == po2))
1515 		return (1);
1516 
1517 	return (0);
1518 }
1519 
1520 struct apic_io_intr *
apic_find_io_intr_w_busid(int irqno,int busid)1521 apic_find_io_intr_w_busid(int irqno, int busid)
1522 {
1523 	struct	apic_io_intr	*intrp;
1524 
1525 	/*
1526 	 * It can have more than 1 entry with same source bus IRQ,
1527 	 * but unique with the source bus id
1528 	 */
1529 	intrp = apic_io_intrp;
1530 	if (intrp != NULL) {
1531 		while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1532 			if (intrp->intr_irq == irqno &&
1533 			    intrp->intr_busid == busid &&
1534 			    intrp->intr_type == IO_INTR_INT)
1535 				return (intrp);
1536 			intrp++;
1537 		}
1538 	}
1539 	APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1540 	    "busid %x:%x\n", irqno, busid));
1541 	return ((struct apic_io_intr *)NULL);
1542 }
1543 
1544 
1545 struct mps_bus_info {
1546 	char	*bus_name;
1547 	int	bus_id;
1548 } bus_info_array[] = {
1549 	"ISA ", BUS_ISA,
1550 	"PCI ", BUS_PCI,
1551 	"EISA ", BUS_EISA,
1552 	"XPRESS", BUS_XPRESS,
1553 	"PCMCIA", BUS_PCMCIA,
1554 	"VL ", BUS_VL,
1555 	"CBUS ", BUS_CBUS,
1556 	"CBUSII", BUS_CBUSII,
1557 	"FUTURE", BUS_FUTURE,
1558 	"INTERN", BUS_INTERN,
1559 	"MBI ", BUS_MBI,
1560 	"MBII ", BUS_MBII,
1561 	"MPI ", BUS_MPI,
1562 	"MPSA ", BUS_MPSA,
1563 	"NUBUS ", BUS_NUBUS,
1564 	"TC ", BUS_TC,
1565 	"VME ", BUS_VME,
1566 	"PCI-E ", BUS_PCIE
1567 };
1568 
1569 static int
apic_find_bus_type(char * bus)1570 apic_find_bus_type(char *bus)
1571 {
1572 	int	i = 0;
1573 
1574 	for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1575 		if (strncmp(bus, bus_info_array[i].bus_name,
1576 		    strlen(bus_info_array[i].bus_name)) == 0)
1577 			return (bus_info_array[i].bus_id);
1578 	APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1579 	return (0);
1580 }
1581 
1582 static int
apic_find_bus(int busid)1583 apic_find_bus(int busid)
1584 {
1585 	struct	apic_bus	*busp;
1586 
1587 	busp = apic_busp;
1588 	while (busp->bus_entry == APIC_BUS_ENTRY) {
1589 		if (busp->bus_id == busid)
1590 			return (apic_find_bus_type((char *)&busp->bus_str1));
1591 		busp++;
1592 	}
1593 	APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1594 	return (0);
1595 }
1596 
1597 int
apic_find_bus_id(int bustype)1598 apic_find_bus_id(int bustype)
1599 {
1600 	struct	apic_bus	*busp;
1601 
1602 	busp = apic_busp;
1603 	while (busp->bus_entry == APIC_BUS_ENTRY) {
1604 		if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1605 			return (busp->bus_id);
1606 		busp++;
1607 	}
1608 	APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1609 	    bustype));
1610 	return (-1);
1611 }
1612 
1613 /*
1614  * Check if a particular irq need to be reserved for any io_intr
1615  */
1616 static struct apic_io_intr *
apic_find_io_intr(int irqno)1617 apic_find_io_intr(int irqno)
1618 {
1619 	struct	apic_io_intr	*intrp;
1620 
1621 	intrp = apic_io_intrp;
1622 	if (intrp != NULL) {
1623 		while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1624 			if (intrp->intr_irq == irqno &&
1625 			    intrp->intr_type == IO_INTR_INT)
1626 				return (intrp);
1627 			intrp++;
1628 		}
1629 	}
1630 	return ((struct apic_io_intr *)NULL);
1631 }
1632 
1633 /*
1634  * Check if the given ioapicindex intin combination has already been assigned
1635  * an irq. If so return irqno. Else -1
1636  */
1637 int
apic_find_intin(uchar_t ioapic,uchar_t intin)1638 apic_find_intin(uchar_t ioapic, uchar_t intin)
1639 {
1640 	apic_irq_t *irqptr;
1641 	int	i;
1642 
1643 	/* find ioapic and intin in the apic_irq_table[] and return the index */
1644 	for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1645 		irqptr = apic_irq_table[i];
1646 		while (irqptr) {
1647 			if ((irqptr->airq_mps_intr_index >= 0) &&
1648 			    (irqptr->airq_intin_no == intin) &&
1649 			    (irqptr->airq_ioapicindex == ioapic)) {
1650 				APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1651 				    "entry for ioapic:intin %x:%x "
1652 				    "shared interrupts ?", ioapic, intin));
1653 				return (i);
1654 			}
1655 			irqptr = irqptr->airq_next;
1656 		}
1657 	}
1658 	return (-1);
1659 }
1660 
1661 int
apic_allocate_irq(int irq)1662 apic_allocate_irq(int irq)
1663 {
1664 	int	freeirq, i;
1665 
1666 	if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) {
1667 		if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1668 		    (irq - 1))) == -1) {
1669 			/*
1670 			 * if BIOS really defines every single irq in the mps
1671 			 * table, then don't worry about conflicting with
1672 			 * them, just use any free slot in apic_irq_table
1673 			 */
1674 			for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1675 				if ((apic_irq_table[i] == NULL) ||
1676 				    apic_irq_table[i]->airq_mps_intr_index ==
1677 				    FREE_INDEX) {
1678 					freeirq = i;
1679 					break;
1680 				}
1681 			}
1682 
1683 			if (freeirq == -1) {
1684 				/* This shouldn't happen, but just in case */
1685 				cmn_err(CE_WARN, "%s: NO available IRQ",
1686 				    psm_name);
1687 				return (-1);
1688 			}
1689 		}
1690 	}
1691 
1692 	if (apic_irq_table[freeirq] == NULL) {
1693 		apic_irq_table[freeirq] =
1694 		    kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1695 		if (apic_irq_table[freeirq] == NULL) {
1696 			cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1697 			    psm_name);
1698 			return (-1);
1699 		}
1700 		apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1701 		apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1702 	}
1703 	return (freeirq);
1704 }
1705 
1706 static int
apic_find_free_irq(int start,int end)1707 apic_find_free_irq(int start, int end)
1708 {
1709 	int	i;
1710 
1711 	for (i = start; i <= end; i++)
1712 		/* Check if any I/O entry needs this IRQ */
1713 		if (apic_find_io_intr(i) == NULL) {
1714 			/* Then see if it is free */
1715 			if ((apic_irq_table[i] == NULL) ||
1716 			    (apic_irq_table[i]->airq_mps_intr_index ==
1717 			    FREE_INDEX)) {
1718 				return (i);
1719 			}
1720 		}
1721 	return (-1);
1722 }
1723 
1724 /*
1725  * compute the polarity, trigger mode and vector for programming into
1726  * the I/O apic and record in airq_rdt_entry.
1727  */
1728 void
apic_record_rdt_entry(apic_irq_t * irqptr,int irq)1729 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1730 {
1731 	int	ioapicindex, bus_type, vector;
1732 	short	intr_index;
1733 	uint_t	level, po, io_po;
1734 	struct apic_io_intr *iointrp;
1735 
1736 	intr_index = irqptr->airq_mps_intr_index;
1737 	DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1738 	    "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1739 	    (void *)irqptr->airq_dip, irqptr->airq_vector));
1740 
1741 	if (intr_index == RESERVE_INDEX) {
1742 		apic_error |= APIC_ERR_INVALID_INDEX;
1743 		return;
1744 	} else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1745 		return;
1746 	}
1747 
1748 	vector = irqptr->airq_vector;
1749 	ioapicindex = irqptr->airq_ioapicindex;
1750 	/* Assume edge triggered by default */
1751 	level = 0;
1752 	/* Assume active high by default */
1753 	po = 0;
1754 
1755 	if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1756 		ASSERT(irq < 16);
1757 		if (eisa_level_intr_mask & (1 << irq))
1758 			level = AV_LEVEL;
1759 		if (intr_index == FREE_INDEX && apic_defconf == 0)
1760 			apic_error |= APIC_ERR_INVALID_INDEX;
1761 	} else if (intr_index == ACPI_INDEX) {
1762 		bus_type = irqptr->airq_iflag.bustype;
1763 		if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1764 			if (bus_type == BUS_PCI)
1765 				level = AV_LEVEL;
1766 		} else
1767 			level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1768 			    AV_LEVEL : 0;
1769 		if (level &&
1770 		    ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1771 		    (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1772 		    bus_type == BUS_PCI)))
1773 			po = AV_ACTIVE_LOW;
1774 	} else {
1775 		iointrp = apic_io_intrp + intr_index;
1776 		bus_type = apic_find_bus(iointrp->intr_busid);
1777 		if (iointrp->intr_el == INTR_EL_CONFORM) {
1778 			if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1779 				level = AV_LEVEL;
1780 			else if (bus_type == BUS_PCI)
1781 				level = AV_LEVEL;
1782 		} else
1783 			level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1784 			    AV_LEVEL : 0;
1785 		if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1786 		    (iointrp->intr_po == INTR_PO_CONFORM &&
1787 		    bus_type == BUS_PCI)))
1788 			po = AV_ACTIVE_LOW;
1789 	}
1790 	if (level)
1791 		apic_level_intr[irq] = 1;
1792 	/*
1793 	 * The 82489DX External APIC cannot do active low polarity interrupts.
1794 	 */
1795 	if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1796 		io_po = po;
1797 	else
1798 		io_po = 0;
1799 
1800 	if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1801 		prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1802 		    "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1803 		    irqptr->airq_intin_no, level, io_po, vector,
1804 		    irqptr->airq_cpu);
1805 
1806 	irqptr->airq_rdt_entry = level|io_po|vector;
1807 }
1808 
1809 int
apic_acpi_translate_pci_irq(dev_info_t * dip,int busid,int devid,int ipin,int * pci_irqp,iflag_t * intr_flagp)1810 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1811     int ipin, int *pci_irqp, iflag_t *intr_flagp)
1812 {
1813 
1814 	int status;
1815 	acpi_psm_lnk_t acpipsmlnk;
1816 
1817 	if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1818 	    intr_flagp)) == ACPI_PSM_SUCCESS) {
1819 		APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1820 		    "from cache for device %s, instance #%d\n", psm_name,
1821 		    *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1822 		return (status);
1823 	}
1824 
1825 	bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1826 
1827 	if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1828 	    &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1829 		APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1830 		    " acpi_translate_pci_irq failed for device %s, instance"
1831 		    " #%d", psm_name, ddi_get_name(dip),
1832 		    ddi_get_instance(dip)));
1833 		return (status);
1834 	}
1835 
1836 	if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1837 		status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1838 		    intr_flagp);
1839 		if (status != ACPI_PSM_SUCCESS) {
1840 			status = acpi_get_current_irq_resource(&acpipsmlnk,
1841 			    pci_irqp, intr_flagp);
1842 		}
1843 	}
1844 
1845 	if (status == ACPI_PSM_SUCCESS) {
1846 		acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1847 		    intr_flagp, &acpipsmlnk);
1848 
1849 		APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1850 		    "new irq %d for device %s, instance #%d\n", psm_name,
1851 		    *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1852 	}
1853 
1854 	return (status);
1855 }
1856 
1857 /*
1858  * Adds an entry to the irq list passed in, and returns the new list.
1859  * Entries are added in priority order (lower numerical priorities are
1860  * placed closer to the head of the list)
1861  */
1862 static prs_irq_list_t *
acpi_insert_prs_irq_ent(prs_irq_list_t * listp,int priority,int irq,iflag_t * iflagp,acpi_prs_private_t * prsprvp)1863 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1864     iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1865 {
1866 	struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1867 
1868 	newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1869 
1870 	newent->list_prio = priority;
1871 	newent->irq = irq;
1872 	newent->intrflags = *iflagp;
1873 	newent->prsprv = *prsprvp;
1874 	/* ->next is NULL from kmem_zalloc */
1875 
1876 	/*
1877 	 * New list -- return the new entry as the list.
1878 	 */
1879 	if (listp == NULL)
1880 		return (newent);
1881 
1882 	/*
1883 	 * Save original list pointer for return (since we're not modifying
1884 	 * the head)
1885 	 */
1886 	origlistp = listp;
1887 
1888 	/*
1889 	 * Insertion sort, with entries with identical keys stored AFTER
1890 	 * existing entries (the less-than-or-equal test of priority does
1891 	 * this for us).
1892 	 */
1893 	while (listp != NULL && listp->list_prio <= priority) {
1894 		prevp = listp;
1895 		listp = listp->next;
1896 	}
1897 
1898 	newent->next = listp;
1899 
1900 	if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1901 		return (newent);
1902 	} else {
1903 		prevp->next = newent;
1904 		return (origlistp);
1905 	}
1906 }
1907 
1908 /*
1909  * Frees the list passed in, deallocating all memory and leaving *listpp
1910  * set to NULL.
1911  */
1912 static void
acpi_destroy_prs_irq_list(prs_irq_list_t ** listpp)1913 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1914 {
1915 	struct prs_irq_list_ent *nextp;
1916 
1917 	ASSERT(listpp != NULL);
1918 
1919 	while (*listpp != NULL) {
1920 		nextp = (*listpp)->next;
1921 		kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1922 		*listpp = nextp;
1923 	}
1924 }
1925 
1926 /*
1927  * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1928  * irqs returned by the link device's _PRS method.  The irqs are chosen
1929  * to minimize contention in situations where the interrupt link device
1930  * can be programmed to steer interrupts to different interrupt controller
1931  * inputs (some of which may already be in use).  The list is sorted in order
1932  * of irqs to use, with the highest priority given to interrupt controller
1933  * inputs that are not shared.   When an interrupt controller input
1934  * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1935  * returned list in the order that minimizes sharing (thereby ensuring lowest
1936  * possible latency from interrupt trigger time to ISR execution time).
1937  */
1938 static prs_irq_list_t *
apic_choose_irqs_from_prs(acpi_irqlist_t * irqlistent,dev_info_t * dip,int crs_irq)1939 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1940     int crs_irq)
1941 {
1942 	int32_t irq;
1943 	int i;
1944 	prs_irq_list_t *prsirqlistp = NULL;
1945 	iflag_t iflags;
1946 
1947 	while (irqlistent != NULL) {
1948 		irqlistent->intr_flags.bustype = BUS_PCI;
1949 
1950 		for (i = 0; i < irqlistent->num_irqs; i++) {
1951 
1952 			irq = irqlistent->irqs[i];
1953 
1954 			if (irq <= 0) {
1955 				/* invalid irq number */
1956 				continue;
1957 			}
1958 
1959 			if ((irq < 16) && (apic_reserved_irqlist[irq]))
1960 				continue;
1961 
1962 			if ((apic_irq_table[irq] == NULL) ||
1963 			    (apic_irq_table[irq]->airq_dip == dip)) {
1964 
1965 				prsirqlistp = acpi_insert_prs_irq_ent(
1966 				    prsirqlistp, 0 /* Highest priority */, irq,
1967 				    &irqlistent->intr_flags,
1968 				    &irqlistent->acpi_prs_prv);
1969 
1970 				/*
1971 				 * If we do not prefer the current irq from _CRS
1972 				 * or if we do and this irq is the same as the
1973 				 * current irq from _CRS, this is the one
1974 				 * to pick.
1975 				 */
1976 				if (!(apic_prefer_crs) || (irq == crs_irq)) {
1977 					return (prsirqlistp);
1978 				}
1979 				continue;
1980 			}
1981 
1982 			/*
1983 			 * Edge-triggered interrupts cannot be shared
1984 			 */
1985 			if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1986 				continue;
1987 
1988 			/*
1989 			 * To work around BIOSes that contain incorrect
1990 			 * interrupt polarity information in interrupt
1991 			 * descriptors returned by _PRS, we assume that
1992 			 * the polarity of the other device sharing this
1993 			 * interrupt controller input is compatible.
1994 			 * If it's not, the caller will catch it when
1995 			 * the caller invokes the link device's _CRS method
1996 			 * (after invoking its _SRS method).
1997 			 */
1998 			iflags = irqlistent->intr_flags;
1999 			iflags.intr_po =
2000 			    apic_irq_table[irq]->airq_iflag.intr_po;
2001 
2002 			if (!acpi_intr_compatible(iflags,
2003 			    apic_irq_table[irq]->airq_iflag)) {
2004 				APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
2005 				    "not compatible [%x:%x:%x !~ %x:%x:%x]",
2006 				    psm_name, irq,
2007 				    iflags.intr_po,
2008 				    iflags.intr_el,
2009 				    iflags.bustype,
2010 				    apic_irq_table[irq]->airq_iflag.intr_po,
2011 				    apic_irq_table[irq]->airq_iflag.intr_el,
2012 				    apic_irq_table[irq]->airq_iflag.bustype));
2013 				continue;
2014 			}
2015 
2016 			/*
2017 			 * If we prefer the irq from _CRS, no need
2018 			 * to search any further (and make sure
2019 			 * to add this irq with the highest priority
2020 			 * so it's tried first).
2021 			 */
2022 			if (crs_irq == irq && apic_prefer_crs) {
2023 
2024 				return (acpi_insert_prs_irq_ent(
2025 				    prsirqlistp,
2026 				    0 /* Highest priority */,
2027 				    irq, &iflags,
2028 				    &irqlistent->acpi_prs_prv));
2029 			}
2030 
2031 			/*
2032 			 * Priority is equal to the share count (lower
2033 			 * share count is higher priority). Note that
2034 			 * the intr flags passed in here are the ones we
2035 			 * changed above -- if incorrect, it will be
2036 			 * caught by the caller's _CRS flags comparison.
2037 			 */
2038 			prsirqlistp = acpi_insert_prs_irq_ent(
2039 			    prsirqlistp,
2040 			    apic_irq_table[irq]->airq_share, irq,
2041 			    &iflags, &irqlistent->acpi_prs_prv);
2042 		}
2043 
2044 		/* Go to the next irqlist entry */
2045 		irqlistent = irqlistent->next;
2046 	}
2047 
2048 	return (prsirqlistp);
2049 }
2050 
2051 /*
2052  * Configures the irq for the interrupt link device identified by
2053  * acpipsmlnkp.
2054  *
2055  * Gets the current and the list of possible irq settings for the
2056  * device. If apic_unconditional_srs is not set, and the current
2057  * resource setting is in the list of possible irq settings,
2058  * current irq resource setting is passed to the caller.
2059  *
2060  * Otherwise, picks an irq number from the list of possible irq
2061  * settings, and sets the irq of the device to this value.
2062  * If prefer_crs is set, among a set of irq numbers in the list that have
2063  * the least number of devices sharing the interrupt, we pick current irq
2064  * resource setting if it is a member of this set.
2065  *
2066  * Passes the irq number in the value pointed to by pci_irqp, and
2067  * polarity and sensitivity in the structure pointed to by dipintrflagp
2068  * to the caller.
2069  *
2070  * Note that if setting the irq resource failed, but successfuly obtained
2071  * the current irq resource settings, passes the current irq resources
2072  * and considers it a success.
2073  *
2074  * Returns:
2075  * ACPI_PSM_SUCCESS on success.
2076  *
2077  * ACPI_PSM_FAILURE if an error occured during the configuration or
2078  * if a suitable irq was not found for this device, or if setting the
2079  * irq resource and obtaining the current resource fails.
2080  *
2081  */
2082 static int
apic_acpi_irq_configure(acpi_psm_lnk_t * acpipsmlnkp,dev_info_t * dip,int * pci_irqp,iflag_t * dipintr_flagp)2083 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2084     int *pci_irqp, iflag_t *dipintr_flagp)
2085 {
2086 	int32_t irq;
2087 	int cur_irq = -1;
2088 	acpi_irqlist_t *irqlistp;
2089 	prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2090 	boolean_t found_irq = B_FALSE;
2091 
2092 	dipintr_flagp->bustype = BUS_PCI;
2093 
2094 	if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2095 	    == ACPI_PSM_FAILURE) {
2096 		APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2097 		    "or assign IRQ for device %s, instance #%d: The system was "
2098 		    "unable to get the list of potential IRQs from ACPI.",
2099 		    psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2100 
2101 		return (ACPI_PSM_FAILURE);
2102 	}
2103 
2104 	if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2105 	    dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2106 	    (cur_irq > 0)) {
2107 		/*
2108 		 * If an IRQ is set in CRS and that IRQ exists in the set
2109 		 * returned from _PRS, return that IRQ, otherwise print
2110 		 * a warning
2111 		 */
2112 
2113 		if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2114 		    == ACPI_PSM_SUCCESS) {
2115 
2116 			ASSERT(pci_irqp != NULL);
2117 			*pci_irqp = cur_irq;
2118 			acpi_free_irqlist(irqlistp);
2119 			return (ACPI_PSM_SUCCESS);
2120 		}
2121 
2122 		APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2123 		    "current irq %d for device %s, instance #%d in ACPI's "
2124 		    "list of possible irqs for this device. Picking one from "
2125 		    " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2126 		    ddi_get_instance(dip)));
2127 	}
2128 
2129 	if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2130 	    cur_irq)) == NULL) {
2131 
2132 		APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2133 		    "suitable irq from the list of possible irqs for device "
2134 		    "%s, instance #%d in ACPI's list of possible irqs",
2135 		    psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2136 
2137 		acpi_free_irqlist(irqlistp);
2138 		return (ACPI_PSM_FAILURE);
2139 	}
2140 
2141 	acpi_free_irqlist(irqlistp);
2142 
2143 	for (prs_irq_entp = prs_irq_listp;
2144 	    prs_irq_entp != NULL && found_irq == B_FALSE;
2145 	    prs_irq_entp = prs_irq_entp->next) {
2146 
2147 		acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2148 		irq = prs_irq_entp->irq;
2149 
2150 		APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2151 		    "device %s instance #%d\n", psm_name, irq,
2152 		    ddi_get_name(dip), ddi_get_instance(dip)));
2153 
2154 		if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2155 		    == ACPI_PSM_SUCCESS) {
2156 			/*
2157 			 * setting irq was successful, check to make sure CRS
2158 			 * reflects that. If CRS does not agree with what we
2159 			 * set, return the irq that was set.
2160 			 */
2161 
2162 			if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2163 			    dipintr_flagp) == ACPI_PSM_SUCCESS) {
2164 
2165 				if (cur_irq != irq)
2166 					APIC_VERBOSE_IRQ((CE_WARN,
2167 					    "!%s: IRQ resource set "
2168 					    "(irqno %d) for device %s "
2169 					    "instance #%d, differs from "
2170 					    "current setting irqno %d",
2171 					    psm_name, irq, ddi_get_name(dip),
2172 					    ddi_get_instance(dip), cur_irq));
2173 			} else {
2174 				/*
2175 				 * On at least one system, there was a bug in
2176 				 * a DSDT method called by _STA, causing _STA to
2177 				 * indicate that the link device was disabled
2178 				 * (when, in fact, it was enabled).  Since _SRS
2179 				 * succeeded, assume that _CRS is lying and use
2180 				 * the iflags from this _PRS interrupt choice.
2181 				 * If we're wrong about the flags, the polarity
2182 				 * will be incorrect and we may get an interrupt
2183 				 * storm, but there's not much else we can do
2184 				 * at this point.
2185 				 */
2186 				*dipintr_flagp = prs_irq_entp->intrflags;
2187 			}
2188 
2189 			/*
2190 			 * Return the irq that was set, and not what _CRS
2191 			 * reports, since _CRS has been seen to return
2192 			 * different IRQs than what was passed to _SRS on some
2193 			 * systems (and just not return successfully on others).
2194 			 */
2195 			cur_irq = irq;
2196 			found_irq = B_TRUE;
2197 		} else {
2198 			APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2199 			    "irq %d failed for device %s instance #%d",
2200 			    psm_name, irq, ddi_get_name(dip),
2201 			    ddi_get_instance(dip)));
2202 
2203 			if (cur_irq == -1) {
2204 				acpi_destroy_prs_irq_list(&prs_irq_listp);
2205 				return (ACPI_PSM_FAILURE);
2206 			}
2207 		}
2208 	}
2209 
2210 	acpi_destroy_prs_irq_list(&prs_irq_listp);
2211 
2212 	if (!found_irq)
2213 		return (ACPI_PSM_FAILURE);
2214 
2215 	ASSERT(pci_irqp != NULL);
2216 	*pci_irqp = cur_irq;
2217 	return (ACPI_PSM_SUCCESS);
2218 }
2219 
2220 void
ioapic_disable_redirection()2221 ioapic_disable_redirection()
2222 {
2223 	int ioapic_ix;
2224 	int intin_max;
2225 	int intin_ix;
2226 
2227 	/* Disable the I/O APIC redirection entries */
2228 	for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2229 
2230 		/* Bits 23-16 define the maximum redirection entries */
2231 		intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2232 		    & 0xff;
2233 
2234 		for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2235 			/*
2236 			 * The assumption here is that this is safe, even for
2237 			 * systems with IOAPICs that suffer from the hardware
2238 			 * erratum because all devices have been quiesced before
2239 			 * this function is called from apic_shutdown()
2240 			 * (or equivalent). If that assumption turns out to be
2241 			 * false, this mask operation can induce the same
2242 			 * erratum result we're trying to avoid.
2243 			 */
2244 			ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2245 			    AV_MASK);
2246 		}
2247 	}
2248 }
2249 
2250 /*
2251  * Looks for an IOAPIC with the specified physical address in the /ioapics
2252  * node in the device tree (created by the PCI enumerator).
2253  */
2254 static boolean_t
apic_is_ioapic_AMD_813x(uint32_t physaddr)2255 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2256 {
2257 	/*
2258 	 * Look in /ioapics, for the ioapic with
2259 	 * the physical address given
2260 	 */
2261 	dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2262 	dev_info_t *ioapic_child;
2263 	boolean_t rv = B_FALSE;
2264 	int vid, did;
2265 	uint64_t ioapic_paddr;
2266 	boolean_t done = B_FALSE;
2267 
2268 	if (ioapicsnode == NULL)
2269 		return (B_FALSE);
2270 
2271 	/* Load first child: */
2272 	ioapic_child = ddi_get_child(ioapicsnode);
2273 	while (!done && ioapic_child != 0) { /* Iterate over children */
2274 
2275 		if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2276 		    ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2277 		    != 0 && physaddr == ioapic_paddr) {
2278 
2279 			vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2280 			    DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2281 
2282 			if (vid == VENID_AMD) {
2283 
2284 				did = ddi_prop_get_int(DDI_DEV_T_ANY,
2285 				    ioapic_child, DDI_PROP_DONTPASS,
2286 				    IOAPICS_PROP_DEVID, 0);
2287 
2288 				if (did == DEVID_8131_IOAPIC ||
2289 				    did == DEVID_8132_IOAPIC) {
2290 					rv = B_TRUE;
2291 					done = B_TRUE;
2292 				}
2293 			}
2294 		}
2295 
2296 		if (!done)
2297 			ioapic_child = ddi_get_next_sibling(ioapic_child);
2298 	}
2299 
2300 	/* The ioapics node was held by ddi_find_devinfo, so release it */
2301 	ndi_rele_devi(ioapicsnode);
2302 	return (rv);
2303 }
2304 
2305 struct apic_state {
2306 	int32_t as_task_reg;
2307 	int32_t as_dest_reg;
2308 	int32_t as_format_reg;
2309 	int32_t as_local_timer;
2310 	int32_t as_pcint_vect;
2311 	int32_t as_int_vect0;
2312 	int32_t as_int_vect1;
2313 	int32_t as_err_vect;
2314 	int32_t as_init_count;
2315 	int32_t as_divide_reg;
2316 	int32_t as_spur_int_reg;
2317 	uint32_t as_ioapic_ids[MAX_IO_APIC];
2318 };
2319 
2320 
2321 static int
apic_acpi_enter_apicmode(void)2322 apic_acpi_enter_apicmode(void)
2323 {
2324 	ACPI_OBJECT_LIST	arglist;
2325 	ACPI_OBJECT		arg;
2326 	ACPI_STATUS		status;
2327 
2328 	/* Setup parameter object */
2329 	arglist.Count = 1;
2330 	arglist.Pointer = &arg;
2331 	arg.Type = ACPI_TYPE_INTEGER;
2332 	arg.Integer.Value = ACPI_APIC_MODE;
2333 
2334 	status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2335 	/*
2336 	 * Per ACPI spec - section 5.8.1 _PIC Method
2337 	 * calling the \_PIC control method is optional for the OS
2338 	 * and might not be found. It's ok to not fail in such cases.
2339 	 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2340 	 */
2341 	if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2342 		cmn_err(CE_NOTE,
2343 		    "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2344 		    ACPI_FAILURE(status));
2345 		return (PSM_FAILURE);
2346 	} else {
2347 		return (PSM_SUCCESS);
2348 	}
2349 }
2350 
2351 
2352 static void
apic_save_state(struct apic_state * sp)2353 apic_save_state(struct apic_state *sp)
2354 {
2355 	int	i, cpuid;
2356 	ulong_t	iflag;
2357 
2358 	PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2359 	/*
2360 	 * First the local APIC.
2361 	 */
2362 	sp->as_task_reg = apic_reg_ops->apic_get_pri();
2363 	sp->as_dest_reg =  apic_reg_ops->apic_read(APIC_DEST_REG);
2364 	if (apic_mode == LOCAL_APIC)
2365 		sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2366 	sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2367 	sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2368 	sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2369 	sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2370 	sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2371 	sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2372 	sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2373 	sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2374 
2375 	/*
2376 	 * If on the boot processor then save the IOAPICs' IDs
2377 	 */
2378 	if ((cpuid = psm_get_cpu_id()) == 0) {
2379 
2380 		iflag = intr_clear();
2381 		lock_set(&apic_ioapic_lock);
2382 
2383 		for (i = 0; i < apic_io_max; i++)
2384 			sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2385 
2386 		lock_clear(&apic_ioapic_lock);
2387 		intr_restore(iflag);
2388 	}
2389 
2390 	/* apic_state() is currently invoked only in Suspend/Resume */
2391 	apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2392 }
2393 
2394 static void
apic_restore_state(struct apic_state * sp)2395 apic_restore_state(struct apic_state *sp)
2396 {
2397 	int	i;
2398 	ulong_t	iflag;
2399 
2400 	/*
2401 	 * First the local APIC.
2402 	 */
2403 	apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2404 	if (apic_mode == LOCAL_APIC) {
2405 		apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2406 		apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2407 	}
2408 	apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2409 	apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2410 	apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2411 	apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2412 	apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2413 	apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2414 	apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2415 	apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2416 
2417 	/*
2418 	 * the following only needs to be done once, so we do it on the
2419 	 * boot processor, since we know that we only have one of those
2420 	 */
2421 	if (psm_get_cpu_id() == 0) {
2422 
2423 		iflag = intr_clear();
2424 		lock_set(&apic_ioapic_lock);
2425 
2426 		/* Restore IOAPICs' APIC IDs */
2427 		for (i = 0; i < apic_io_max; i++) {
2428 			ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2429 		}
2430 
2431 		lock_clear(&apic_ioapic_lock);
2432 		intr_restore(iflag);
2433 
2434 		/*
2435 		 * Reenter APIC mode before restoring LNK devices
2436 		 */
2437 		(void) apic_acpi_enter_apicmode();
2438 
2439 		/*
2440 		 * restore acpi link device mappings
2441 		 */
2442 		acpi_restore_link_devices();
2443 	}
2444 }
2445 
2446 /*
2447  * Returns 0 on success
2448  */
2449 int
apic_state(psm_state_request_t * rp)2450 apic_state(psm_state_request_t *rp)
2451 {
2452 	PMD(PMD_SX, ("apic_state "))
2453 	switch (rp->psr_cmd) {
2454 	case PSM_STATE_ALLOC:
2455 		rp->req.psm_state_req.psr_state =
2456 		    kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2457 		if (rp->req.psm_state_req.psr_state == NULL)
2458 			return (ENOMEM);
2459 		rp->req.psm_state_req.psr_state_size =
2460 		    sizeof (struct apic_state);
2461 		PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2462 		    rp->req.psm_state_req.psr_state,
2463 		    rp->req.psm_state_req.psr_state_size))
2464 		return (0);
2465 
2466 	case PSM_STATE_FREE:
2467 		kmem_free(rp->req.psm_state_req.psr_state,
2468 		    rp->req.psm_state_req.psr_state_size);
2469 		PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2470 		    rp->req.psm_state_req.psr_state,
2471 		    rp->req.psm_state_req.psr_state_size))
2472 		return (0);
2473 
2474 	case PSM_STATE_SAVE:
2475 		PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2476 		    rp->req.psm_state_req.psr_state,
2477 		    rp->req.psm_state_req.psr_state_size))
2478 		apic_save_state(rp->req.psm_state_req.psr_state);
2479 		return (0);
2480 
2481 	case PSM_STATE_RESTORE:
2482 		apic_restore_state(rp->req.psm_state_req.psr_state);
2483 		PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2484 		    rp->req.psm_state_req.psr_state,
2485 		    rp->req.psm_state_req.psr_state_size))
2486 		return (0);
2487 
2488 	default:
2489 		return (EINVAL);
2490 	}
2491 }
2492