1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 * Copyright 2018 Joyent, Inc.
29 */
30
31 /*
32 * To understand how the apix module interacts with the interrupt subsystem read
33 * the theory statement in uts/i86pc/os/intr.c.
34 */
35
36 /*
37 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
38 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
39 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
40 * PSMI 1.5 extensions are supported in Solaris Nevada.
41 * PSMI 1.6 extensions are supported in Solaris Nevada.
42 * PSMI 1.7 extensions are supported in Solaris Nevada.
43 */
44 #define PSMI_1_7
45
46 #include <sys/processor.h>
47 #include <sys/time.h>
48 #include <sys/psm.h>
49 #include <sys/smp_impldefs.h>
50 #include <sys/cram.h>
51 #include <sys/acpi/acpi.h>
52 #include <sys/acpica.h>
53 #include <sys/psm_common.h>
54 #include <sys/pit.h>
55 #include <sys/ddi.h>
56 #include <sys/sunddi.h>
57 #include <sys/ddi_impldefs.h>
58 #include <sys/pci.h>
59 #include <sys/promif.h>
60 #include <sys/x86_archext.h>
61 #include <sys/cpc_impl.h>
62 #include <sys/uadmin.h>
63 #include <sys/panic.h>
64 #include <sys/debug.h>
65 #include <sys/archsystm.h>
66 #include <sys/trap.h>
67 #include <sys/machsystm.h>
68 #include <sys/sysmacros.h>
69 #include <sys/cpuvar.h>
70 #include <sys/rm_platter.h>
71 #include <sys/privregs.h>
72 #include <sys/note.h>
73 #include <sys/pci_intr_lib.h>
74 #include <sys/spl.h>
75 #include <sys/clock.h>
76 #include <sys/cyclic.h>
77 #include <sys/dditypes.h>
78 #include <sys/sunddi.h>
79 #include <sys/x_call.h>
80 #include <sys/reboot.h>
81 #include <sys/mach_intr.h>
82 #include <sys/apix.h>
83 #include <sys/apix_irm_impl.h>
84
85 static int apix_probe();
86 static void apix_init();
87 static void apix_picinit(void);
88 static int apix_intr_enter(int, int *);
89 static void apix_intr_exit(int, int);
90 static void apix_setspl(int);
91 static int apix_disable_intr(processorid_t);
92 static void apix_enable_intr(processorid_t);
93 static int apix_get_clkvect(int);
94 static int apix_get_ipivect(int, int);
95 static void apix_post_cyclic_setup(void *);
96 static int apix_post_cpu_start();
97 static int apix_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *,
98 psm_intr_op_t, int *);
99
100 /*
101 * Helper functions for apix_intr_ops()
102 */
103 static void apix_redistribute_compute(void);
104 static int apix_get_pending(apix_vector_t *);
105 static apix_vector_t *apix_get_req_vector(ddi_intr_handle_impl_t *, ushort_t);
106 static int apix_get_intr_info(ddi_intr_handle_impl_t *, apic_get_intr_t *);
107 static char *apix_get_apic_type(void);
108 static int apix_intx_get_pending(int);
109 static void apix_intx_set_mask(int irqno);
110 static void apix_intx_clear_mask(int irqno);
111 static int apix_intx_get_shared(int irqno);
112 static void apix_intx_set_shared(int irqno, int delta);
113 static apix_vector_t *apix_intx_xlate_vector(dev_info_t *, int,
114 struct intrspec *);
115 static int apix_intx_alloc_vector(dev_info_t *, int, struct intrspec *);
116
117 extern int apic_clkinit(int);
118
119 /* IRM initialization for APIX PSM module */
120 extern void apix_irm_init(void);
121
122 extern int irm_enable;
123
124 /*
125 * Local static data
126 */
127 static struct psm_ops apix_ops = {
128 apix_probe,
129
130 apix_init,
131 apix_picinit,
132 apix_intr_enter,
133 apix_intr_exit,
134 apix_setspl,
135 apix_addspl,
136 apix_delspl,
137 apix_disable_intr,
138 apix_enable_intr,
139 NULL, /* psm_softlvl_to_irq */
140 NULL, /* psm_set_softintr */
141
142 apic_set_idlecpu,
143 apic_unset_idlecpu,
144
145 apic_clkinit,
146 apix_get_clkvect,
147 NULL, /* psm_hrtimeinit */
148 apic_gethrtime,
149
150 apic_get_next_processorid,
151 apic_cpu_start,
152 apix_post_cpu_start,
153 apic_shutdown,
154 apix_get_ipivect,
155 apic_send_ipi,
156
157 NULL, /* psm_translate_irq */
158 NULL, /* psm_notify_error */
159 NULL, /* psm_notify_func */
160 apic_timer_reprogram,
161 apic_timer_enable,
162 apic_timer_disable,
163 apix_post_cyclic_setup,
164 apic_preshutdown,
165 apix_intr_ops, /* Advanced DDI Interrupt framework */
166 apic_state, /* save, restore apic state for S3 */
167 apic_cpu_ops, /* CPU control interface. */
168
169 apic_get_pir_ipivect,
170 apic_send_pir_ipi,
171 apic_cmci_setup
172 };
173
174 struct psm_ops *psmops = &apix_ops;
175
176 static struct psm_info apix_psm_info = {
177 PSM_INFO_VER01_7, /* version */
178 PSM_OWN_EXCLUSIVE, /* ownership */
179 &apix_ops, /* operation */
180 APIX_NAME, /* machine name */
181 "apix MPv1.4 compatible",
182 };
183
184 static void *apix_hdlp;
185
186 static int apix_is_enabled = 0;
187
188 /*
189 * apix_lock is used for cpu selection and vector re-binding
190 */
191 lock_t apix_lock;
192 apix_impl_t *apixs[NCPU];
193 /*
194 * Mapping between device interrupt and the allocated vector. Indexed
195 * by major number.
196 */
197 apix_dev_vector_t **apix_dev_vector;
198 /*
199 * Mapping between device major number and cpu id. It gets used
200 * when interrupt binding policy round robin with affinity is
201 * applied. With that policy, devices with the same major number
202 * will be bound to the same CPU.
203 */
204 processorid_t *apix_major_to_cpu; /* major to cpu mapping */
205 kmutex_t apix_mutex; /* for apix_dev_vector & apix_major_to_cpu */
206
207 int apix_nipis = 16; /* Maximum number of IPIs */
208 /*
209 * Maximum number of vectors in a CPU that can be used for interrupt
210 * allocation (including IPIs and the reserved vectors).
211 */
212 int apix_cpu_nvectors = APIX_NVECTOR;
213
214 /* number of CPUs in power-on transition state */
215 static int apic_poweron_cnt = 0;
216
217 /* gcpu.h */
218
219 extern void apic_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
220 extern void apic_change_eoi();
221
222 /*
223 * This is the loadable module wrapper
224 */
225
226 int
_init(void)227 _init(void)
228 {
229 if (apic_coarse_hrtime)
230 apix_ops.psm_gethrtime = &apic_gettime;
231 return (psm_mod_init(&apix_hdlp, &apix_psm_info));
232 }
233
234 int
_fini(void)235 _fini(void)
236 {
237 return (psm_mod_fini(&apix_hdlp, &apix_psm_info));
238 }
239
240 int
_info(struct modinfo * modinfop)241 _info(struct modinfo *modinfop)
242 {
243 return (psm_mod_info(&apix_hdlp, &apix_psm_info, modinfop));
244 }
245
246 static int
apix_probe()247 apix_probe()
248 {
249 int rval;
250
251 if (apix_enable == 0)
252 return (PSM_FAILURE);
253
254 /*
255 * FIXME Temporarily disable apix module on Xen HVM platform due to
256 * known hang during boot (see #3605).
257 *
258 * Please remove when/if the issue is resolved.
259 */
260 if (get_hwenv() & HW_XEN_HVM)
261 return (PSM_FAILURE);
262
263 if (apic_local_mode() == LOCAL_X2APIC) {
264 /* x2APIC mode activated by BIOS, switch ops */
265 apic_mode = LOCAL_X2APIC;
266 apic_change_ops();
267 }
268
269 rval = apic_probe_common(apix_psm_info.p_mach_idstring);
270 if (rval == PSM_SUCCESS)
271 apix_is_enabled = 1;
272 else
273 apix_is_enabled = 0;
274 return (rval);
275 }
276
277 /*
278 * Initialize the data structures needed by pcplusmpx module.
279 * Specifically, the data structures used by addspl() and delspl()
280 * routines.
281 */
282 static void
apix_softinit()283 apix_softinit()
284 {
285 int i, *iptr;
286 apix_impl_t *hdlp;
287 int nproc;
288
289 nproc = max(apic_nproc, apic_max_nproc);
290
291 hdlp = kmem_zalloc(nproc * sizeof (apix_impl_t), KM_SLEEP);
292 for (i = 0; i < nproc; i++) {
293 apixs[i] = &hdlp[i];
294 apixs[i]->x_cpuid = i;
295 LOCK_INIT_CLEAR(&apixs[i]->x_lock);
296 }
297
298 /* cpu 0 is always up (for now) */
299 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE;
300
301 iptr = (int *)&apic_irq_table[0];
302 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
303 apic_level_intr[i] = 0;
304 *iptr++ = 0;
305 }
306 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL);
307
308 apix_dev_vector = kmem_zalloc(sizeof (apix_dev_vector_t *) * devcnt,
309 KM_SLEEP);
310
311 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) {
312 apix_major_to_cpu = kmem_zalloc(sizeof (int) * devcnt,
313 KM_SLEEP);
314 for (i = 0; i < devcnt; i++)
315 apix_major_to_cpu[i] = IRQ_UNINIT;
316 }
317
318 mutex_init(&apix_mutex, NULL, MUTEX_DEFAULT, NULL);
319 }
320
321 static int
apix_get_pending_spl(void)322 apix_get_pending_spl(void)
323 {
324 int cpuid = CPU->cpu_id;
325
326 return (bsrw_insn(apixs[cpuid]->x_intr_pending));
327 }
328
329 static uintptr_t
apix_get_intr_handler(int cpu,short vec)330 apix_get_intr_handler(int cpu, short vec)
331 {
332 apix_vector_t *apix_vector;
333
334 ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR);
335 if (cpu >= apic_nproc || vec >= APIX_NVECTOR)
336 return (0);
337
338 apix_vector = apixs[cpu]->x_vectbl[vec];
339
340 return ((uintptr_t)(apix_vector->v_autovect));
341 }
342
343 static void
apix_init()344 apix_init()
345 {
346 extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
347
348 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n"));
349
350 do_interrupt_common = apix_do_interrupt;
351 addintr = apix_add_avintr;
352 remintr = apix_rem_avintr;
353 get_pending_spl = apix_get_pending_spl;
354 get_intr_handler = apix_get_intr_handler;
355 psm_get_localapicid = apic_get_localapicid;
356 psm_get_ioapicid = apic_get_ioapicid;
357
358 apix_softinit();
359
360 apic_pir_vect = apix_get_ipivect(XC_CPUPOKE_PIL, -1);
361
362 /*
363 * Initialize IRM pool parameters
364 */
365 if (irm_enable) {
366 int i;
367 int lowest_irq;
368 int highest_irq;
369
370 /* number of CPUs present */
371 apix_irminfo.apix_ncpus = apic_nproc;
372 /* total number of entries in all of the IOAPICs present */
373 lowest_irq = apic_io_vectbase[0];
374 highest_irq = apic_io_vectend[0];
375 for (i = 1; i < apic_io_max; i++) {
376 if (apic_io_vectbase[i] < lowest_irq)
377 lowest_irq = apic_io_vectbase[i];
378 if (apic_io_vectend[i] > highest_irq)
379 highest_irq = apic_io_vectend[i];
380 }
381 apix_irminfo.apix_ioapic_max_vectors =
382 highest_irq - lowest_irq + 1;
383 /*
384 * Number of available per-CPU vectors excluding
385 * reserved vectors for Dtrace, int80, system-call,
386 * fast-trap, etc.
387 */
388 apix_irminfo.apix_per_cpu_vectors = APIX_NAVINTR -
389 APIX_SW_RESERVED_VECTORS;
390
391 /* Number of vectors (pre) allocated (SCI and HPET) */
392 apix_irminfo.apix_vectors_allocated = 0;
393 if (apic_hpet_vect != -1)
394 apix_irminfo.apix_vectors_allocated++;
395 if (apic_sci_vect != -1)
396 apix_irminfo.apix_vectors_allocated++;
397 }
398 }
399
400 static void
apix_init_intr()401 apix_init_intr()
402 {
403 processorid_t cpun = psm_get_cpu_id();
404 uint_t nlvt;
405 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
406 extern void cmi_cmci_trap(void);
407
408 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
409
410 if (apic_mode == LOCAL_APIC) {
411 /*
412 * We are running APIC in MMIO mode.
413 */
414 if (apic_flat_model) {
415 apic_reg_ops->apic_write(APIC_FORMAT_REG,
416 APIC_FLAT_MODEL);
417 } else {
418 apic_reg_ops->apic_write(APIC_FORMAT_REG,
419 APIC_CLUSTER_MODEL);
420 }
421
422 apic_reg_ops->apic_write(APIC_DEST_REG,
423 AV_HIGH_ORDER >> cpun);
424 }
425
426 if (apic_directed_EOI_supported()) {
427 /*
428 * Setting the 12th bit in the Spurious Interrupt Vector
429 * Register suppresses broadcast EOIs generated by the local
430 * APIC. The suppression of broadcast EOIs happens only when
431 * interrupts are level-triggered.
432 */
433 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
434 }
435
436 /* need to enable APIC before unmasking NMI */
437 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
438
439 /*
440 * Presence of an invalid vector with delivery mode AV_FIXED can
441 * cause an error interrupt, even if the entry is masked...so
442 * write a valid vector to LVT entries along with the mask bit
443 */
444
445 /* All APICs have timer and LINT0/1 */
446 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
447 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
448 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
449
450 /*
451 * On integrated APICs, the number of LVT entries is
452 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
453 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
454 */
455
456 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
457 nlvt = 3;
458 } else {
459 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
460 0xFF) + 1;
461 }
462
463 if (nlvt >= 5) {
464 /* Enable performance counter overflow interrupt */
465
466 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
467 apic_enable_cpcovf_intr = 0;
468 if (apic_enable_cpcovf_intr) {
469 if (apic_cpcovf_vect == 0) {
470 int ipl = APIC_PCINT_IPL;
471
472 apic_cpcovf_vect = apix_get_ipivect(ipl, -1);
473 ASSERT(apic_cpcovf_vect);
474
475 (void) add_avintr(NULL, ipl,
476 (avfunc)kcpc_hw_overflow_intr,
477 "apic pcint", apic_cpcovf_vect,
478 NULL, NULL, NULL, NULL);
479 kcpc_hw_overflow_intr_installed = 1;
480 kcpc_hw_enable_cpc_intr =
481 apic_cpcovf_mask_clear;
482 }
483 apic_reg_ops->apic_write(APIC_PCINT_VECT,
484 apic_cpcovf_vect);
485 }
486 }
487
488 if (nlvt >= 6) {
489 /* Only mask TM intr if the BIOS apparently doesn't use it */
490
491 uint32_t lvtval;
492
493 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
494 if (((lvtval & AV_MASK) == AV_MASK) ||
495 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
496 apic_reg_ops->apic_write(APIC_THERM_VECT,
497 AV_MASK|APIC_RESV_IRQ);
498 }
499 }
500
501 /* Enable error interrupt */
502
503 if (nlvt >= 4 && apic_enable_error_intr) {
504 if (apic_errvect == 0) {
505 int ipl = 0xf; /* get highest priority intr */
506 apic_errvect = apix_get_ipivect(ipl, -1);
507 ASSERT(apic_errvect);
508 /*
509 * Not PSMI compliant, but we are going to merge
510 * with ON anyway
511 */
512 (void) add_avintr(NULL, ipl,
513 (avfunc)apic_error_intr, "apic error intr",
514 apic_errvect, NULL, NULL, NULL, NULL);
515 }
516 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
517 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
518 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
519 }
520
521 /*
522 * Ensure a CMCI interrupt is allocated, regardless of whether it is
523 * enabled or not.
524 */
525 if (apic_cmci_vect == 0) {
526 const int ipl = 0x2;
527 apic_cmci_vect = apix_get_ipivect(ipl, -1);
528 ASSERT(apic_cmci_vect);
529
530 (void) add_avintr(NULL, ipl,
531 (avfunc)cmi_cmci_trap, "apic cmci intr",
532 apic_cmci_vect, NULL, NULL, NULL, NULL);
533 }
534
535 apic_reg_ops->apic_write_task_reg(0);
536 }
537
538 static void
apix_picinit(void)539 apix_picinit(void)
540 {
541 int i, j;
542 uint_t isr;
543
544 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_picinit\n"));
545
546 /*
547 * initialize interrupt remapping before apic
548 * hardware initialization
549 */
550 apic_intrmap_init(apic_mode);
551 if (apic_vt_ops == psm_vt_ops)
552 apix_mul_ioapic_method = APIC_MUL_IOAPIC_IIR;
553
554 /*
555 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
556 * bit on without clearing it with EOI. Since softint
557 * uses vector 0x20 to interrupt itself, so softint will
558 * not work on this machine. In order to fix this problem
559 * a check is made to verify all the isr bits are clear.
560 * If not, EOIs are issued to clear the bits.
561 */
562 for (i = 7; i >= 1; i--) {
563 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
564 if (isr != 0)
565 for (j = 0; ((j < 32) && (isr != 0)); j++)
566 if (isr & (1 << j)) {
567 apic_reg_ops->apic_write(
568 APIC_EOI_REG, 0);
569 isr &= ~(1 << j);
570 apic_error |= APIC_ERR_BOOT_EOI;
571 }
572 }
573
574 /* set a flag so we know we have run apic_picinit() */
575 apic_picinit_called = 1;
576 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
577 LOCK_INIT_CLEAR(&apic_ioapic_lock);
578 LOCK_INIT_CLEAR(&apic_error_lock);
579 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
580
581 picsetup(); /* initialise the 8259 */
582
583 /* add nmi handler - least priority nmi handler */
584 LOCK_INIT_CLEAR(&apic_nmi_lock);
585
586 if (!psm_add_nmintr(0, apic_nmi_intr,
587 "apix NMI handler", (caddr_t)NULL))
588 cmn_err(CE_WARN, "apix: Unable to add nmi handler");
589
590 apix_init_intr();
591
592 /* enable apic mode if imcr present */
593 if (apic_imcrp) {
594 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
595 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
596 }
597
598 ioapix_init_intr(IOAPIC_MASK);
599
600 /* setup global IRM pool if applicable */
601 if (irm_enable)
602 apix_irm_init();
603 }
604
605 static __inline__ void
apix_send_eoi(void)606 apix_send_eoi(void)
607 {
608 if (apic_mode == LOCAL_APIC)
609 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
610 else
611 X2APIC_WRITE(APIC_EOI_REG, 0);
612 }
613
614 /*
615 * platform_intr_enter
616 *
617 * Called at the beginning of the interrupt service routine, but unlike
618 * pcplusmp, does not mask interrupts. An EOI is given to the interrupt
619 * controller to enable other HW interrupts but interrupts are still
620 * masked by the IF flag.
621 *
622 * Return -1 for spurious interrupts
623 *
624 */
625 static int
apix_intr_enter(int ipl,int * vectorp)626 apix_intr_enter(int ipl, int *vectorp)
627 {
628 struct cpu *cpu = CPU;
629 uint32_t cpuid = CPU->cpu_id;
630 apic_cpus_info_t *cpu_infop;
631 uchar_t vector;
632 apix_vector_t *vecp;
633 int nipl = -1;
634
635 /*
636 * The real vector delivered is (*vectorp + 0x20), but our caller
637 * subtracts 0x20 from the vector before passing it to us.
638 * (That's why APIC_BASE_VECT is 0x20.)
639 */
640 vector = *vectorp = (uchar_t)*vectorp + APIC_BASE_VECT;
641
642 cpu_infop = &apic_cpus[cpuid];
643 if (vector == APIC_SPUR_INTR) {
644 cpu_infop->aci_spur_cnt++;
645 return (APIC_INT_SPURIOUS);
646 }
647
648 vecp = xv_vector(cpuid, vector);
649 if (vecp == NULL) {
650 if (APIX_IS_FAKE_INTR(vector))
651 nipl = apix_rebindinfo.i_pri;
652 apix_send_eoi();
653 return (nipl);
654 }
655 nipl = vecp->v_pri;
656
657 /* if interrupted by the clock, increment apic_nsec_since_boot */
658 if (vector == (apic_clkvect + APIC_BASE_VECT)) {
659 if (!apic_oneshot) {
660 /* NOTE: this is not MT aware */
661 apic_hrtime_stamp++;
662 apic_nsec_since_boot += apic_nsec_per_intr;
663 apic_hrtime_stamp++;
664 last_count_read = apic_hertz_count;
665 apix_redistribute_compute();
666 }
667
668 apix_send_eoi();
669
670 return (nipl);
671 }
672
673 ASSERT(vecp->v_state != APIX_STATE_OBSOLETED);
674
675 /* pre-EOI handling for level-triggered interrupts */
676 if (!APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method) &&
677 (vecp->v_type & APIX_TYPE_FIXED) && apic_level_intr[vecp->v_inum])
678 apix_level_intr_pre_eoi(vecp->v_inum);
679
680 /* send back EOI */
681 apix_send_eoi();
682
683 cpu_infop->aci_current[nipl] = vector;
684 if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) {
685 cpu_infop->aci_curipl = (uchar_t)nipl;
686 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
687 }
688
689 #ifdef DEBUG
690 if (vector >= APIX_IPI_MIN)
691 return (nipl); /* skip IPI */
692
693 APIC_DEBUG_BUF_PUT(vector);
694 APIC_DEBUG_BUF_PUT(vecp->v_inum);
695 APIC_DEBUG_BUF_PUT(nipl);
696 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
697 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
698 drv_usecwait(apic_stretch_interrupts);
699 #endif /* DEBUG */
700
701 return (nipl);
702 }
703
704 /*
705 * Any changes made to this function must also change X2APIC
706 * version of intr_exit.
707 */
708 static void
apix_intr_exit(int prev_ipl,int arg2)709 apix_intr_exit(int prev_ipl, int arg2)
710 {
711 int cpuid = psm_get_cpu_id();
712 apic_cpus_info_t *cpu_infop = &apic_cpus[cpuid];
713 apix_impl_t *apixp = apixs[cpuid];
714
715 UNREFERENCED_1PARAMETER(arg2);
716
717 cpu_infop->aci_curipl = (uchar_t)prev_ipl;
718 /* ISR above current pri could not be in progress */
719 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
720
721 if (apixp->x_obsoletes != NULL) {
722 if (APIX_CPU_LOCK_HELD(cpuid))
723 return;
724
725 APIX_ENTER_CPU_LOCK(cpuid);
726 (void) apix_obsolete_vector(apixp->x_obsoletes);
727 APIX_LEAVE_CPU_LOCK(cpuid);
728 }
729 }
730
731 /*
732 * The pcplusmp setspl code uses the TPR to mask all interrupts at or below the
733 * given ipl, but apix never uses the TPR and we never mask a subset of the
734 * interrupts. They are either all blocked by the IF flag or all can come in.
735 *
736 * For setspl, we mask all interrupts for XC_HI_PIL (15), otherwise, interrupts
737 * can come in if currently enabled by the IF flag. This table shows the state
738 * of the IF flag when we leave this function.
739 *
740 * curr IF | ipl == 15 ipl != 15
741 * --------+---------------------------
742 * 0 | 0 0
743 * 1 | 0 1
744 */
745 static void
apix_setspl(int ipl)746 apix_setspl(int ipl)
747 {
748 /*
749 * Interrupts at ipl above this cannot be in progress, so the following
750 * mask is ok.
751 */
752 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
753
754 if (ipl == XC_HI_PIL)
755 cli();
756 }
757
758 int
apix_addspl(int virtvec,int ipl,int min_ipl,int max_ipl)759 apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl)
760 {
761 uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
762 uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
763 apix_vector_t *vecp = xv_vector(cpuid, vector);
764
765 UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
766 ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
767
768 if (vecp->v_type == APIX_TYPE_FIXED)
769 apix_intx_set_shared(vecp->v_inum, 1);
770
771 /* There are more interrupts, so it's already been enabled */
772 if (vecp->v_share > 1)
773 return (PSM_SUCCESS);
774
775 /* return if it is not hardware interrupt */
776 if (vecp->v_type == APIX_TYPE_IPI)
777 return (PSM_SUCCESS);
778
779 /*
780 * if apix_picinit() has not been called yet, just return.
781 * At the end of apic_picinit(), we will call setup_io_intr().
782 */
783 if (!apic_picinit_called)
784 return (PSM_SUCCESS);
785
786 (void) apix_setup_io_intr(vecp);
787
788 return (PSM_SUCCESS);
789 }
790
791 int
apix_delspl(int virtvec,int ipl,int min_ipl,int max_ipl)792 apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl)
793 {
794 uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
795 uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
796 apix_vector_t *vecp = xv_vector(cpuid, vector);
797
798 UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
799 ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
800
801 if (vecp->v_type == APIX_TYPE_FIXED)
802 apix_intx_set_shared(vecp->v_inum, -1);
803
804 /* There are more interrupts */
805 if (vecp->v_share > 1)
806 return (PSM_SUCCESS);
807
808 /* return if it is not hardware interrupt */
809 if (vecp->v_type == APIX_TYPE_IPI)
810 return (PSM_SUCCESS);
811
812 if (!apic_picinit_called) {
813 cmn_err(CE_WARN, "apix: delete 0x%x before apic init",
814 virtvec);
815 return (PSM_SUCCESS);
816 }
817
818 apix_disable_vector(vecp);
819
820 return (PSM_SUCCESS);
821 }
822
823 /*
824 * Try and disable all interrupts. We just assign interrupts to other
825 * processors based on policy. If any were bound by user request, we
826 * let them continue and return failure. We do not bother to check
827 * for cache affinity while rebinding.
828 */
829 static int
apix_disable_intr(processorid_t cpun)830 apix_disable_intr(processorid_t cpun)
831 {
832 apix_impl_t *apixp = apixs[cpun];
833 apix_vector_t *vecp, *newp;
834 int bindcpu, i, hardbound = 0, errbound = 0, ret, loop, type;
835
836 lock_set(&apix_lock);
837
838 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
839 apic_cpus[cpun].aci_curipl = 0;
840
841 /* if this is for SUSPEND operation, skip rebinding */
842 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
843 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
844 vecp = apixp->x_vectbl[i];
845 if (!IS_VECT_ENABLED(vecp))
846 continue;
847
848 apix_disable_vector(vecp);
849 }
850 lock_clear(&apix_lock);
851 return (PSM_SUCCESS);
852 }
853
854 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
855 vecp = apixp->x_vectbl[i];
856 if (!IS_VECT_ENABLED(vecp))
857 continue;
858
859 if (vecp->v_flags & APIX_VECT_USER_BOUND) {
860 hardbound++;
861 continue;
862 }
863 type = vecp->v_type;
864
865 /*
866 * If there are bound interrupts on this cpu, then
867 * rebind them to other processors.
868 */
869 loop = 0;
870 do {
871 bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE);
872
873 if (type != APIX_TYPE_MSI)
874 newp = apix_set_cpu(vecp, bindcpu, &ret);
875 else
876 newp = apix_grp_set_cpu(vecp, bindcpu, &ret);
877 } while ((newp == NULL) && (loop++ < apic_nproc));
878
879 if (loop >= apic_nproc) {
880 errbound++;
881 cmn_err(CE_WARN, "apix: failed to rebind vector %x/%x",
882 vecp->v_cpuid, vecp->v_vector);
883 }
884 }
885
886 lock_clear(&apix_lock);
887
888 if (hardbound || errbound) {
889 cmn_err(CE_WARN, "Could not disable interrupts on %d"
890 "due to user bound interrupts or failed operation",
891 cpun);
892 return (PSM_FAILURE);
893 }
894
895 return (PSM_SUCCESS);
896 }
897
898 /*
899 * Bind interrupts to specified CPU
900 */
901 static void
apix_enable_intr(processorid_t cpun)902 apix_enable_intr(processorid_t cpun)
903 {
904 apix_vector_t *vecp;
905 int i, ret;
906 processorid_t n;
907
908 lock_set(&apix_lock);
909
910 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
911
912 /* interrupt enabling for system resume */
913 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
914 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
915 vecp = xv_vector(cpun, i);
916 if (!IS_VECT_ENABLED(vecp))
917 continue;
918
919 apix_enable_vector(vecp);
920 }
921 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
922 }
923
924 for (n = 0; n < apic_nproc; n++) {
925 if (!apic_cpu_in_range(n) || n == cpun ||
926 (apic_cpus[n].aci_status & APIC_CPU_INTR_ENABLE) == 0)
927 continue;
928
929 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
930 vecp = xv_vector(n, i);
931 if (!IS_VECT_ENABLED(vecp) ||
932 vecp->v_bound_cpuid != cpun)
933 continue;
934
935 if (vecp->v_type != APIX_TYPE_MSI)
936 (void) apix_set_cpu(vecp, cpun, &ret);
937 else
938 (void) apix_grp_set_cpu(vecp, cpun, &ret);
939 }
940 }
941
942 lock_clear(&apix_lock);
943 }
944
945 /*
946 * Allocate vector for IPI
947 * type == -1 indicates it is an internal request. Do not change
948 * resv_vector for these requests.
949 */
950 static int
apix_get_ipivect(int ipl,int type)951 apix_get_ipivect(int ipl, int type)
952 {
953 uchar_t vector;
954
955 if ((vector = apix_alloc_ipi(ipl)) > 0) {
956 if (type != -1)
957 apic_resv_vector[ipl] = vector;
958 return (vector);
959 }
960 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
961 return (-1); /* shouldn't happen */
962 }
963
964 static int
apix_get_clkvect(int ipl)965 apix_get_clkvect(int ipl)
966 {
967 int vector;
968
969 if ((vector = apix_get_ipivect(ipl, -1)) == -1)
970 return (-1);
971
972 apic_clkvect = vector - APIC_BASE_VECT;
973 APIC_VERBOSE(IPI, (CE_CONT, "apix: clock vector = %x\n",
974 apic_clkvect));
975 return (vector);
976 }
977
978 static int
apix_post_cpu_start()979 apix_post_cpu_start()
980 {
981 int cpun;
982 static int cpus_started = 1;
983
984 /* We know this CPU + BSP started successfully. */
985 cpus_started++;
986
987 /*
988 * On BSP we would have enabled X2APIC, if supported by processor,
989 * in acpi_probe(), but on AP we do it here.
990 *
991 * We enable X2APIC mode only if BSP is running in X2APIC & the
992 * local APIC mode of the current CPU is MMIO (xAPIC).
993 */
994 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
995 apic_local_mode() == LOCAL_APIC) {
996 apic_enable_x2apic();
997 }
998
999 /*
1000 * Switch back to x2apic IPI sending method for performance when target
1001 * CPU has entered x2apic mode.
1002 */
1003 if (apic_mode == LOCAL_X2APIC) {
1004 apic_switch_ipi_callback(B_FALSE);
1005 }
1006
1007 splx(ipltospl(LOCK_LEVEL));
1008 apix_init_intr();
1009
1010 /*
1011 * since some systems don't enable the internal cache on the non-boot
1012 * cpus, so we have to enable them here
1013 */
1014 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
1015
1016 #ifdef DEBUG
1017 APIC_AV_PENDING_SET();
1018 #else
1019 if (apic_mode == LOCAL_APIC)
1020 APIC_AV_PENDING_SET();
1021 #endif /* DEBUG */
1022
1023 /*
1024 * We may be booting, or resuming from suspend; aci_status will
1025 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
1026 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
1027 */
1028 cpun = psm_get_cpu_id();
1029 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
1030
1031 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
1032
1033 return (PSM_SUCCESS);
1034 }
1035
1036 /*
1037 * If this module needs a periodic handler for the interrupt distribution, it
1038 * can be added here. The argument to the periodic handler is not currently
1039 * used, but is reserved for future.
1040 */
1041 static void
apix_post_cyclic_setup(void * arg)1042 apix_post_cyclic_setup(void *arg)
1043 {
1044 UNREFERENCED_1PARAMETER(arg);
1045
1046 cyc_handler_t cyh;
1047 cyc_time_t cyt;
1048
1049 /* cpu_lock is held */
1050 /* set up a periodic handler for intr redistribution */
1051
1052 /*
1053 * In peridoc mode intr redistribution processing is done in
1054 * apic_intr_enter during clk intr processing
1055 */
1056 if (!apic_oneshot)
1057 return;
1058
1059 /*
1060 * Register a periodical handler for the redistribution processing.
1061 * Though we would generally prefer to use the DDI interface for
1062 * periodic handler invocation, ddi_periodic_add(9F), we are
1063 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1064 * attempt to take for us. Thus, we add our own cyclic directly:
1065 */
1066 cyh.cyh_func = (void (*)(void *))apix_redistribute_compute;
1067 cyh.cyh_arg = NULL;
1068 cyh.cyh_level = CY_LOW_LEVEL;
1069
1070 cyt.cyt_when = 0;
1071 cyt.cyt_interval = apic_redistribute_sample_interval;
1072
1073 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1074 }
1075
1076 /*
1077 * Called the first time we enable x2apic mode on this cpu.
1078 * Update some of the function pointers to use x2apic routines.
1079 */
1080 void
x2apic_update_psm()1081 x2apic_update_psm()
1082 {
1083 struct psm_ops *pops = &apix_ops;
1084
1085 ASSERT(pops != NULL);
1086
1087 /*
1088 * The pcplusmp module's version of x2apic_update_psm makes additional
1089 * changes that we do not have to make here. It needs to make those
1090 * changes because pcplusmp relies on the TPR register and the means of
1091 * addressing that changes when using the local apic versus the x2apic.
1092 * It's also worth noting that the apix driver specific function end up
1093 * being apix_foo as opposed to apic_foo and x2apic_foo.
1094 */
1095 pops->psm_send_ipi = x2apic_send_ipi;
1096 send_dirintf = pops->psm_send_ipi;
1097
1098 pops->psm_send_pir_ipi = x2apic_send_pir_ipi;
1099 psm_send_pir_ipi = pops->psm_send_pir_ipi;
1100
1101 apic_mode = LOCAL_X2APIC;
1102 apic_change_ops();
1103 }
1104
1105 /*
1106 * This function provides external interface to the nexus for all
1107 * functionalities related to the new DDI interrupt framework.
1108 *
1109 * Input:
1110 * dip - pointer to the dev_info structure of the requested device
1111 * hdlp - pointer to the internal interrupt handle structure for the
1112 * requested interrupt
1113 * intr_op - opcode for this call
1114 * result - pointer to the integer that will hold the result to be
1115 * passed back if return value is PSM_SUCCESS
1116 *
1117 * Output:
1118 * return value is either PSM_SUCCESS or PSM_FAILURE
1119 */
1120 static int
apix_intr_ops(dev_info_t * dip,ddi_intr_handle_impl_t * hdlp,psm_intr_op_t intr_op,int * result)1121 apix_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
1122 psm_intr_op_t intr_op, int *result)
1123 {
1124 int cap;
1125 apix_vector_t *vecp, *newvecp;
1126 struct intrspec *ispec, intr_spec;
1127 processorid_t target;
1128
1129 ispec = &intr_spec;
1130 ispec->intrspec_pri = hdlp->ih_pri;
1131 ispec->intrspec_vec = hdlp->ih_inum;
1132 ispec->intrspec_func = hdlp->ih_cb_func;
1133
1134 switch (intr_op) {
1135 case PSM_INTR_OP_ALLOC_VECTORS:
1136 switch (hdlp->ih_type) {
1137 case DDI_INTR_TYPE_MSI:
1138 /* allocate MSI vectors */
1139 *result = apix_alloc_msi(dip, hdlp->ih_inum,
1140 hdlp->ih_scratch1,
1141 (int)(uintptr_t)hdlp->ih_scratch2);
1142 break;
1143 case DDI_INTR_TYPE_MSIX:
1144 /* allocate MSI-X vectors */
1145 *result = apix_alloc_msix(dip, hdlp->ih_inum,
1146 hdlp->ih_scratch1,
1147 (int)(uintptr_t)hdlp->ih_scratch2);
1148 break;
1149 case DDI_INTR_TYPE_FIXED:
1150 /* allocate or share vector for fixed */
1151 if ((ihdl_plat_t *)hdlp->ih_private == NULL) {
1152 return (PSM_FAILURE);
1153 }
1154 ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp;
1155 *result = apix_intx_alloc_vector(dip, hdlp->ih_inum,
1156 ispec);
1157 break;
1158 default:
1159 return (PSM_FAILURE);
1160 }
1161 break;
1162 case PSM_INTR_OP_FREE_VECTORS:
1163 apix_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1,
1164 hdlp->ih_type);
1165 break;
1166 case PSM_INTR_OP_XLATE_VECTOR:
1167 /*
1168 * Vectors are allocated by ALLOC and freed by FREE.
1169 * XLATE finds and returns APIX_VIRTVEC_VECTOR(cpu, vector).
1170 */
1171 *result = APIX_INVALID_VECT;
1172 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1173 if (vecp != NULL) {
1174 *result = APIX_VIRTVECTOR(vecp->v_cpuid,
1175 vecp->v_vector);
1176 break;
1177 }
1178
1179 /*
1180 * No vector to device mapping exists. If this is FIXED type
1181 * then check if this IRQ is already mapped for another device
1182 * then return the vector number for it (i.e. shared IRQ case).
1183 * Otherwise, return PSM_FAILURE.
1184 */
1185 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
1186 vecp = apix_intx_xlate_vector(dip, hdlp->ih_inum,
1187 ispec);
1188 *result = (vecp == NULL) ? APIX_INVALID_VECT :
1189 APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector);
1190 }
1191 if (*result == APIX_INVALID_VECT)
1192 return (PSM_FAILURE);
1193 break;
1194 case PSM_INTR_OP_GET_PENDING:
1195 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1196 if (vecp == NULL)
1197 return (PSM_FAILURE);
1198
1199 *result = apix_get_pending(vecp);
1200 break;
1201 case PSM_INTR_OP_CLEAR_MASK:
1202 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1203 return (PSM_FAILURE);
1204
1205 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1206 if (vecp == NULL)
1207 return (PSM_FAILURE);
1208
1209 apix_intx_clear_mask(vecp->v_inum);
1210 break;
1211 case PSM_INTR_OP_SET_MASK:
1212 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1213 return (PSM_FAILURE);
1214
1215 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1216 if (vecp == NULL)
1217 return (PSM_FAILURE);
1218
1219 apix_intx_set_mask(vecp->v_inum);
1220 break;
1221 case PSM_INTR_OP_GET_SHARED:
1222 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1223 return (PSM_FAILURE);
1224
1225 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1226 if (vecp == NULL)
1227 return (PSM_FAILURE);
1228
1229 *result = apix_intx_get_shared(vecp->v_inum);
1230 break;
1231 case PSM_INTR_OP_SET_PRI:
1232 /*
1233 * Called prior to adding the interrupt handler or when
1234 * an interrupt handler is unassigned.
1235 */
1236 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1237 return (PSM_SUCCESS);
1238
1239 if (apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type) == NULL)
1240 return (PSM_FAILURE);
1241
1242 break;
1243 case PSM_INTR_OP_SET_CPU:
1244 case PSM_INTR_OP_GRP_SET_CPU:
1245 /*
1246 * The interrupt handle given here has been allocated
1247 * specifically for this command, and ih_private carries
1248 * a CPU value.
1249 */
1250 *result = EINVAL;
1251 target = (int)(intptr_t)hdlp->ih_private;
1252 if (!apic_cpu_in_range(target)) {
1253 DDI_INTR_IMPLDBG((CE_WARN,
1254 "[grp_]set_cpu: cpu out of range: %d\n", target));
1255 return (PSM_FAILURE);
1256 }
1257
1258 lock_set(&apix_lock);
1259
1260 vecp = apix_get_req_vector(hdlp, hdlp->ih_flags);
1261 if (!IS_VECT_ENABLED(vecp)) {
1262 DDI_INTR_IMPLDBG((CE_WARN,
1263 "[grp]_set_cpu: invalid vector 0x%x\n",
1264 hdlp->ih_vector));
1265 lock_clear(&apix_lock);
1266 return (PSM_FAILURE);
1267 }
1268
1269 *result = 0;
1270
1271 if (intr_op == PSM_INTR_OP_SET_CPU)
1272 newvecp = apix_set_cpu(vecp, target, result);
1273 else
1274 newvecp = apix_grp_set_cpu(vecp, target, result);
1275
1276 lock_clear(&apix_lock);
1277
1278 if (newvecp == NULL) {
1279 *result = EIO;
1280 return (PSM_FAILURE);
1281 }
1282 newvecp->v_bound_cpuid = target;
1283 hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid,
1284 newvecp->v_vector);
1285 break;
1286
1287 case PSM_INTR_OP_GET_INTR:
1288 /*
1289 * The interrupt handle given here has been allocated
1290 * specifically for this command, and ih_private carries
1291 * a pointer to a apic_get_intr_t.
1292 */
1293 if (apix_get_intr_info(hdlp, hdlp->ih_private) != PSM_SUCCESS)
1294 return (PSM_FAILURE);
1295 break;
1296
1297 case PSM_INTR_OP_CHECK_MSI:
1298 /*
1299 * Check MSI/X is supported or not at APIC level and
1300 * masked off the MSI/X bits in hdlp->ih_type if not
1301 * supported before return. If MSI/X is supported,
1302 * leave the ih_type unchanged and return.
1303 *
1304 * hdlp->ih_type passed in from the nexus has all the
1305 * interrupt types supported by the device.
1306 */
1307 if (apic_support_msi == 0) { /* uninitialized */
1308 /*
1309 * if apic_support_msi is not set, call
1310 * apic_check_msi_support() to check whether msi
1311 * is supported first
1312 */
1313 if (apic_check_msi_support() == PSM_SUCCESS)
1314 apic_support_msi = 1; /* supported */
1315 else
1316 apic_support_msi = -1; /* not-supported */
1317 }
1318 if (apic_support_msi == 1) {
1319 if (apic_msix_enable)
1320 *result = hdlp->ih_type;
1321 else
1322 *result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX;
1323 } else
1324 *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI |
1325 DDI_INTR_TYPE_MSIX);
1326 break;
1327 case PSM_INTR_OP_GET_CAP:
1328 cap = DDI_INTR_FLAG_PENDING;
1329 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1330 cap |= DDI_INTR_FLAG_MASKABLE;
1331 *result = cap;
1332 break;
1333 case PSM_INTR_OP_APIC_TYPE:
1334 ((apic_get_type_t *)(hdlp->ih_private))->avgi_type =
1335 apix_get_apic_type();
1336 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr =
1337 APIX_IPI_MIN;
1338 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu =
1339 apic_nproc;
1340 hdlp->ih_ver = apic_get_apic_version();
1341 break;
1342 case PSM_INTR_OP_SET_CAP:
1343 default:
1344 return (PSM_FAILURE);
1345 }
1346
1347 return (PSM_SUCCESS);
1348 }
1349
1350 static void
apix_cleanup_busy(void)1351 apix_cleanup_busy(void)
1352 {
1353 int i, j;
1354 apix_vector_t *vecp;
1355
1356 for (i = 0; i < apic_nproc; i++) {
1357 if (!apic_cpu_in_range(i))
1358 continue;
1359 apic_cpus[i].aci_busy = 0;
1360 for (j = APIX_AVINTR_MIN; j < APIX_AVINTR_MAX; j++) {
1361 if ((vecp = xv_vector(i, j)) != NULL)
1362 vecp->v_busy = 0;
1363 }
1364 }
1365 }
1366
1367 static void
apix_redistribute_compute(void)1368 apix_redistribute_compute(void)
1369 {
1370 int i, j, max_busy;
1371
1372 if (!apic_enable_dynamic_migration)
1373 return;
1374
1375 if (++apic_nticks == apic_sample_factor_redistribution) {
1376 /*
1377 * Time to call apic_intr_redistribute().
1378 * reset apic_nticks. This will cause max_busy
1379 * to be calculated below and if it is more than
1380 * apic_int_busy, we will do the whole thing
1381 */
1382 apic_nticks = 0;
1383 }
1384 max_busy = 0;
1385 for (i = 0; i < apic_nproc; i++) {
1386 if (!apic_cpu_in_range(i))
1387 continue;
1388 /*
1389 * Check if curipl is non zero & if ISR is in
1390 * progress
1391 */
1392 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1393 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1394
1395 int vect;
1396 apic_cpus[i].aci_busy++;
1397 vect = apic_cpus[i].aci_current[j];
1398 apixs[i]->x_vectbl[vect]->v_busy++;
1399 }
1400
1401 if (!apic_nticks &&
1402 (apic_cpus[i].aci_busy > max_busy))
1403 max_busy = apic_cpus[i].aci_busy;
1404 }
1405 if (!apic_nticks) {
1406 if (max_busy > apic_int_busy_mark) {
1407 /*
1408 * We could make the following check be
1409 * skipped > 1 in which case, we get a
1410 * redistribution at half the busy mark (due to
1411 * double interval). Need to be able to collect
1412 * more empirical data to decide if that is a
1413 * good strategy. Punt for now.
1414 */
1415 apix_cleanup_busy();
1416 apic_skipped_redistribute = 0;
1417 } else
1418 apic_skipped_redistribute++;
1419 }
1420 }
1421
1422 /*
1423 * intr_ops() service routines
1424 */
1425
1426 static int
apix_get_pending(apix_vector_t * vecp)1427 apix_get_pending(apix_vector_t *vecp)
1428 {
1429 int bit, index, irr, pending;
1430
1431 /* need to get on the bound cpu */
1432 mutex_enter(&cpu_lock);
1433 affinity_set(vecp->v_cpuid);
1434
1435 index = vecp->v_vector / 32;
1436 bit = vecp->v_vector % 32;
1437 irr = apic_reg_ops->apic_read(APIC_IRR_REG + index);
1438
1439 affinity_clear();
1440 mutex_exit(&cpu_lock);
1441
1442 pending = (irr & (1 << bit)) ? 1 : 0;
1443 if (!pending && vecp->v_type == APIX_TYPE_FIXED)
1444 pending = apix_intx_get_pending(vecp->v_inum);
1445
1446 return (pending);
1447 }
1448
1449 static apix_vector_t *
apix_get_req_vector(ddi_intr_handle_impl_t * hdlp,ushort_t flags)1450 apix_get_req_vector(ddi_intr_handle_impl_t *hdlp, ushort_t flags)
1451 {
1452 apix_vector_t *vecp;
1453 processorid_t cpuid;
1454 int32_t virt_vec = 0;
1455
1456 switch (flags & PSMGI_INTRBY_FLAGS) {
1457 case PSMGI_INTRBY_IRQ:
1458 return (apix_intx_get_vector(hdlp->ih_vector));
1459 case PSMGI_INTRBY_VEC:
1460 virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec;
1461
1462 cpuid = APIX_VIRTVEC_CPU(virt_vec);
1463 if (!apic_cpu_in_range(cpuid))
1464 return (NULL);
1465
1466 vecp = xv_vector(cpuid, APIX_VIRTVEC_VECTOR(virt_vec));
1467 break;
1468 case PSMGI_INTRBY_DEFAULT:
1469 vecp = apix_get_dev_map(hdlp->ih_dip, hdlp->ih_inum,
1470 hdlp->ih_type);
1471 break;
1472 default:
1473 return (NULL);
1474 }
1475
1476 return (vecp);
1477 }
1478
1479 static int
apix_get_intr_info(ddi_intr_handle_impl_t * hdlp,apic_get_intr_t * intr_params_p)1480 apix_get_intr_info(ddi_intr_handle_impl_t *hdlp,
1481 apic_get_intr_t *intr_params_p)
1482 {
1483 apix_vector_t *vecp;
1484 struct autovec *av_dev;
1485 int i;
1486
1487 vecp = apix_get_req_vector(hdlp, intr_params_p->avgi_req_flags);
1488 if (IS_VECT_FREE(vecp)) {
1489 intr_params_p->avgi_num_devs = 0;
1490 intr_params_p->avgi_cpu_id = 0;
1491 intr_params_p->avgi_req_flags = 0;
1492 return (PSM_SUCCESS);
1493 }
1494
1495 if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) {
1496 intr_params_p->avgi_cpu_id = vecp->v_cpuid;
1497
1498 /* Return user bound info for intrd. */
1499 if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) {
1500 intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND;
1501 intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND;
1502 }
1503 }
1504
1505 if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR)
1506 intr_params_p->avgi_vector = vecp->v_vector;
1507
1508 if (intr_params_p->avgi_req_flags &
1509 (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS))
1510 /* Get number of devices from apic_irq table shared field. */
1511 intr_params_p->avgi_num_devs = vecp->v_share;
1512
1513 if (intr_params_p->avgi_req_flags & PSMGI_REQ_GET_DEVS) {
1514
1515 intr_params_p->avgi_req_flags |= PSMGI_REQ_NUM_DEVS;
1516
1517 /* Some devices have NULL dip. Don't count these. */
1518 if (intr_params_p->avgi_num_devs > 0) {
1519 for (i = 0, av_dev = vecp->v_autovect; av_dev;
1520 av_dev = av_dev->av_link) {
1521 if (av_dev->av_vector && av_dev->av_dip)
1522 i++;
1523 }
1524 intr_params_p->avgi_num_devs =
1525 (uint8_t)MIN(intr_params_p->avgi_num_devs, i);
1526 }
1527
1528 /* There are no viable dips to return. */
1529 if (intr_params_p->avgi_num_devs == 0) {
1530 intr_params_p->avgi_dip_list = NULL;
1531
1532 } else { /* Return list of dips */
1533
1534 /* Allocate space in array for that number of devs. */
1535 intr_params_p->avgi_dip_list = kmem_zalloc(
1536 intr_params_p->avgi_num_devs *
1537 sizeof (dev_info_t *),
1538 KM_NOSLEEP);
1539 if (intr_params_p->avgi_dip_list == NULL) {
1540 DDI_INTR_IMPLDBG((CE_WARN,
1541 "apix_get_vector_intr_info: no memory"));
1542 return (PSM_FAILURE);
1543 }
1544
1545 /*
1546 * Loop through the device list of the autovec table
1547 * filling in the dip array.
1548 *
1549 * Note that the autovect table may have some special
1550 * entries which contain NULL dips. These will be
1551 * ignored.
1552 */
1553 for (i = 0, av_dev = vecp->v_autovect; av_dev;
1554 av_dev = av_dev->av_link) {
1555 if (av_dev->av_vector && av_dev->av_dip)
1556 intr_params_p->avgi_dip_list[i++] =
1557 av_dev->av_dip;
1558 }
1559 }
1560 }
1561
1562 return (PSM_SUCCESS);
1563 }
1564
1565 static char *
apix_get_apic_type(void)1566 apix_get_apic_type(void)
1567 {
1568 return (apix_psm_info.p_mach_idstring);
1569 }
1570
1571 apix_vector_t *
apix_set_cpu(apix_vector_t * vecp,int new_cpu,int * result)1572 apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1573 {
1574 apix_vector_t *newp = NULL;
1575 dev_info_t *dip;
1576 int inum, cap_ptr;
1577 ddi_acc_handle_t handle;
1578 ddi_intr_msix_t *msix_p = NULL;
1579 ushort_t msix_ctrl;
1580 uintptr_t off = 0;
1581 uint32_t mask = 0;
1582
1583 ASSERT(LOCK_HELD(&apix_lock));
1584 *result = ENXIO;
1585
1586 /* Fail if this is an MSI intr and is part of a group. */
1587 if (vecp->v_type == APIX_TYPE_MSI) {
1588 if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1)
1589 return (NULL);
1590 else
1591 return (apix_grp_set_cpu(vecp, new_cpu, result));
1592 }
1593
1594 /*
1595 * Mask MSI-X. It's unmasked when MSI-X gets enabled.
1596 */
1597 if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) {
1598 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1599 return (NULL);
1600 inum = vecp->v_devp->dv_inum;
1601
1602 handle = i_ddi_get_pci_config_handle(dip);
1603 cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1604 msix_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
1605 if ((msix_ctrl & PCI_MSIX_FUNCTION_MASK) == 0) {
1606 /*
1607 * Function is not masked, then mask "inum"th
1608 * entry in the MSI-X table
1609 */
1610 msix_p = i_ddi_get_msix(dip);
1611 off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
1612 PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
1613 mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
1614 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off,
1615 mask | 1);
1616 }
1617 }
1618
1619 *result = 0;
1620 if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL)
1621 *result = EIO;
1622
1623 /* Restore mask bit */
1624 if (msix_p != NULL)
1625 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask);
1626
1627 return (newp);
1628 }
1629
1630 /*
1631 * Set cpu for MSIs
1632 */
1633 apix_vector_t *
apix_grp_set_cpu(apix_vector_t * vecp,int new_cpu,int * result)1634 apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1635 {
1636 apix_vector_t *newp, *vp;
1637 uint32_t orig_cpu = vecp->v_cpuid;
1638 int orig_vect = vecp->v_vector;
1639 int i, num_vectors, cap_ptr, msi_mask_off = 0;
1640 uint32_t msi_pvm = 0;
1641 ushort_t msi_ctrl;
1642 ddi_acc_handle_t handle;
1643 dev_info_t *dip;
1644
1645 APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x,"
1646 " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu));
1647
1648 ASSERT(LOCK_HELD(&apix_lock));
1649
1650 *result = ENXIO;
1651
1652 if (vecp->v_type != APIX_TYPE_MSI) {
1653 DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n"));
1654 return (NULL);
1655 }
1656
1657 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1658 return (NULL);
1659
1660 num_vectors = i_ddi_intr_get_current_nintrs(dip);
1661 if ((num_vectors < 1) || ((num_vectors - 1) & orig_vect)) {
1662 APIC_VERBOSE(INTR, (CE_WARN,
1663 "set_grp: base vec not part of a grp or not aligned: "
1664 "vec:0x%x, num_vec:0x%x\n", orig_vect, num_vectors));
1665 return (NULL);
1666 }
1667
1668 if (vecp->v_inum != apix_get_min_dev_inum(dip, vecp->v_type))
1669 return (NULL);
1670
1671 *result = EIO;
1672 for (i = 1; i < num_vectors; i++) {
1673 if ((vp = xv_vector(orig_cpu, orig_vect + i)) == NULL)
1674 return (NULL);
1675 #ifdef DEBUG
1676 /*
1677 * Sanity check: CPU and dip is the same for all entries.
1678 * May be called when first msi to be enabled, at this time
1679 * add_avintr() is not called for other msi
1680 */
1681 if ((vp->v_share != 0) &&
1682 ((APIX_GET_DIP(vp) != dip) ||
1683 (vp->v_cpuid != vecp->v_cpuid))) {
1684 APIC_VERBOSE(INTR, (CE_WARN,
1685 "set_grp: cpu or dip for vec 0x%x difft than for "
1686 "vec 0x%x\n", orig_vect, orig_vect + i));
1687 APIC_VERBOSE(INTR, (CE_WARN,
1688 " cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu,
1689 vp->v_cpuid, (void *)dip,
1690 (void *)APIX_GET_DIP(vp)));
1691 return (NULL);
1692 }
1693 #endif /* DEBUG */
1694 }
1695
1696 cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1697 handle = i_ddi_get_pci_config_handle(dip);
1698 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
1699
1700 /* MSI Per vector masking is supported. */
1701 if (msi_ctrl & PCI_MSI_PVM_MASK) {
1702 if (msi_ctrl & PCI_MSI_64BIT_MASK)
1703 msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS;
1704 else
1705 msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK;
1706 msi_pvm = pci_config_get32(handle, msi_mask_off);
1707 pci_config_put32(handle, msi_mask_off, (uint32_t)-1);
1708 APIC_VERBOSE(INTR, (CE_CONT,
1709 "set_grp: pvm supported. Mask set to 0x%x\n",
1710 pci_config_get32(handle, msi_mask_off)));
1711 }
1712
1713 if ((newp = apix_rebind(vecp, new_cpu, num_vectors)) != NULL)
1714 *result = 0;
1715
1716 /* Reenable vectors if per vector masking is supported. */
1717 if (msi_ctrl & PCI_MSI_PVM_MASK) {
1718 pci_config_put32(handle, msi_mask_off, msi_pvm);
1719 APIC_VERBOSE(INTR, (CE_CONT,
1720 "set_grp: pvm supported. Mask restored to 0x%x\n",
1721 pci_config_get32(handle, msi_mask_off)));
1722 }
1723
1724 return (newp);
1725 }
1726
1727 void
apix_intx_set_vector(int irqno,uint32_t cpuid,uchar_t vector)1728 apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector)
1729 {
1730 apic_irq_t *irqp;
1731
1732 mutex_enter(&airq_mutex);
1733 irqp = apic_irq_table[irqno];
1734 irqp->airq_cpu = cpuid;
1735 irqp->airq_vector = vector;
1736 apic_record_rdt_entry(irqp, irqno);
1737 mutex_exit(&airq_mutex);
1738 }
1739
1740 apix_vector_t *
apix_intx_get_vector(int irqno)1741 apix_intx_get_vector(int irqno)
1742 {
1743 apic_irq_t *irqp;
1744 uint32_t cpuid;
1745 uchar_t vector;
1746
1747 mutex_enter(&airq_mutex);
1748 irqp = apic_irq_table[irqno & 0xff];
1749 if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
1750 mutex_exit(&airq_mutex);
1751 return (NULL);
1752 }
1753 cpuid = irqp->airq_cpu;
1754 vector = irqp->airq_vector;
1755 mutex_exit(&airq_mutex);
1756
1757 return (xv_vector(cpuid, vector));
1758 }
1759
1760 /*
1761 * Must called with interrupts disabled and apic_ioapic_lock held
1762 */
1763 void
apix_intx_enable(int irqno)1764 apix_intx_enable(int irqno)
1765 {
1766 uchar_t ioapicindex, intin;
1767 apic_irq_t *irqp = apic_irq_table[irqno];
1768 ioapic_rdt_t irdt;
1769 apic_cpus_info_t *cpu_infop;
1770 apix_vector_t *vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector);
1771
1772 ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1773
1774 ioapicindex = irqp->airq_ioapicindex;
1775 intin = irqp->airq_intin_no;
1776 cpu_infop = &apic_cpus[irqp->airq_cpu];
1777
1778 irdt.ir_lo = AV_PDEST | AV_FIXED | irqp->airq_rdt_entry;
1779 irdt.ir_hi = cpu_infop->aci_local_id;
1780
1781 apic_vt_ops->apic_intrmap_alloc_entry(&vecp->v_intrmap_private, NULL,
1782 vecp->v_type, 1, ioapicindex);
1783 apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private,
1784 (void *)&irdt, vecp->v_type, 1);
1785 apic_vt_ops->apic_intrmap_record_rdt(vecp->v_intrmap_private, &irdt);
1786
1787 /* write RDT entry high dword - destination */
1788 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin,
1789 irdt.ir_hi);
1790
1791 /* Write the vector, trigger, and polarity portion of the RDT */
1792 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin, irdt.ir_lo);
1793
1794 vecp->v_state = APIX_STATE_ENABLED;
1795
1796 APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_enable: ioapic 0x%x"
1797 " intin 0x%x rdt_low 0x%x rdt_high 0x%x\n",
1798 ioapicindex, intin, irdt.ir_lo, irdt.ir_hi));
1799 }
1800
1801 /*
1802 * Must called with interrupts disabled and apic_ioapic_lock held
1803 */
1804 void
apix_intx_disable(int irqno)1805 apix_intx_disable(int irqno)
1806 {
1807 apic_irq_t *irqp = apic_irq_table[irqno];
1808 int ioapicindex, intin;
1809
1810 ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1811 /*
1812 * The assumption here is that this is safe, even for
1813 * systems with IOAPICs that suffer from the hardware
1814 * erratum because all devices have been quiesced before
1815 * they unregister their interrupt handlers. If that
1816 * assumption turns out to be false, this mask operation
1817 * can induce the same erratum result we're trying to
1818 * avoid.
1819 */
1820 ioapicindex = irqp->airq_ioapicindex;
1821 intin = irqp->airq_intin_no;
1822 ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK);
1823
1824 APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_disable: ioapic 0x%x"
1825 " intin 0x%x\n", ioapicindex, intin));
1826 }
1827
1828 void
apix_intx_free(int irqno)1829 apix_intx_free(int irqno)
1830 {
1831 apic_irq_t *irqp;
1832
1833 mutex_enter(&airq_mutex);
1834 irqp = apic_irq_table[irqno];
1835
1836 if (IS_IRQ_FREE(irqp)) {
1837 mutex_exit(&airq_mutex);
1838 return;
1839 }
1840
1841 irqp->airq_mps_intr_index = FREE_INDEX;
1842 irqp->airq_cpu = IRQ_UNINIT;
1843 irqp->airq_vector = APIX_INVALID_VECT;
1844 mutex_exit(&airq_mutex);
1845 }
1846
1847 #ifdef DEBUG
1848 int apix_intr_deliver_timeouts = 0;
1849 int apix_intr_rirr_timeouts = 0;
1850 int apix_intr_rirr_reset_failure = 0;
1851 #endif
1852 int apix_max_reps_irr_pending = 10;
1853
1854 #define GET_RDT_BITS(ioapic, intin, bits) \
1855 (READ_IOAPIC_RDT_ENTRY_LOW_DWORD((ioapic), (intin)) & (bits))
1856 #define APIX_CHECK_IRR_DELAY drv_usectohz(5000)
1857
1858 int
apix_intx_rebind(int irqno,processorid_t cpuid,uchar_t vector)1859 apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector)
1860 {
1861 apic_irq_t *irqp = apic_irq_table[irqno];
1862 ulong_t iflag;
1863 int waited, ioapic_ix, intin_no, level, repeats, rdt_entry, masked;
1864
1865 ASSERT(irqp != NULL);
1866
1867 iflag = intr_clear();
1868 lock_set(&apic_ioapic_lock);
1869
1870 ioapic_ix = irqp->airq_ioapicindex;
1871 intin_no = irqp->airq_intin_no;
1872 level = apic_level_intr[irqno];
1873
1874 /*
1875 * Wait for the delivery status bit to be cleared. This should
1876 * be a very small amount of time.
1877 */
1878 repeats = 0;
1879 do {
1880 repeats++;
1881
1882 for (waited = 0; waited < apic_max_reps_clear_pending;
1883 waited++) {
1884 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) == 0)
1885 break;
1886 }
1887 if (!level)
1888 break;
1889
1890 /*
1891 * Mask the RDT entry for level-triggered interrupts.
1892 */
1893 irqp->airq_rdt_entry |= AV_MASK;
1894 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1895 intin_no);
1896 if ((masked = (rdt_entry & AV_MASK)) == 0) {
1897 /* Mask it */
1898 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no,
1899 AV_MASK | rdt_entry);
1900 }
1901
1902 /*
1903 * If there was a race and an interrupt was injected
1904 * just before we masked, check for that case here.
1905 * Then, unmask the RDT entry and try again. If we're
1906 * on our last try, don't unmask (because we want the
1907 * RDT entry to remain masked for the rest of the
1908 * function).
1909 */
1910 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1911 intin_no);
1912 if ((masked == 0) && ((rdt_entry & AV_PENDING) != 0) &&
1913 (repeats < apic_max_reps_clear_pending)) {
1914 /* Unmask it */
1915 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1916 intin_no, rdt_entry & ~AV_MASK);
1917 irqp->airq_rdt_entry &= ~AV_MASK;
1918 }
1919 } while ((rdt_entry & AV_PENDING) &&
1920 (repeats < apic_max_reps_clear_pending));
1921
1922 #ifdef DEBUG
1923 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) != 0)
1924 apix_intr_deliver_timeouts++;
1925 #endif
1926
1927 if (!level || !APIX_IS_MASK_RDT(apix_mul_ioapic_method))
1928 goto done;
1929
1930 /*
1931 * wait for remote IRR to be cleared for level-triggered
1932 * interrupts
1933 */
1934 repeats = 0;
1935 do {
1936 repeats++;
1937
1938 for (waited = 0; waited < apic_max_reps_clear_pending;
1939 waited++) {
1940 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR)
1941 == 0)
1942 break;
1943 }
1944
1945 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1946 lock_clear(&apic_ioapic_lock);
1947 intr_restore(iflag);
1948
1949 delay(APIX_CHECK_IRR_DELAY);
1950
1951 iflag = intr_clear();
1952 lock_set(&apic_ioapic_lock);
1953 }
1954 } while (repeats < apix_max_reps_irr_pending);
1955
1956 if (repeats >= apix_max_reps_irr_pending) {
1957 #ifdef DEBUG
1958 apix_intr_rirr_timeouts++;
1959 #endif
1960
1961 /*
1962 * If we waited and the Remote IRR bit is still not cleared,
1963 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
1964 * times for this interrupt, try the last-ditch workaround:
1965 */
1966 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1967 /*
1968 * Trying to clear the bit through normal
1969 * channels has failed. So as a last-ditch
1970 * effort, try to set the trigger mode to
1971 * edge, then to level. This has been
1972 * observed to work on many systems.
1973 */
1974 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1975 intin_no,
1976 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1977 intin_no) & ~AV_LEVEL);
1978 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1979 intin_no,
1980 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1981 intin_no) | AV_LEVEL);
1982 }
1983
1984 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1985 #ifdef DEBUG
1986 apix_intr_rirr_reset_failure++;
1987 #endif
1988 lock_clear(&apic_ioapic_lock);
1989 intr_restore(iflag);
1990 prom_printf("apix: Remote IRR still "
1991 "not clear for IOAPIC %d intin %d.\n"
1992 "\tInterrupts to this pin may cease "
1993 "functioning.\n", ioapic_ix, intin_no);
1994 return (1); /* return failure */
1995 }
1996 }
1997
1998 done:
1999 /* change apic_irq_table */
2000 lock_clear(&apic_ioapic_lock);
2001 intr_restore(iflag);
2002 apix_intx_set_vector(irqno, cpuid, vector);
2003 iflag = intr_clear();
2004 lock_set(&apic_ioapic_lock);
2005
2006 /* reprogramme IO-APIC RDT entry */
2007 apix_intx_enable(irqno);
2008
2009 lock_clear(&apic_ioapic_lock);
2010 intr_restore(iflag);
2011
2012 return (0);
2013 }
2014
2015 static int
apix_intx_get_pending(int irqno)2016 apix_intx_get_pending(int irqno)
2017 {
2018 apic_irq_t *irqp;
2019 int intin, ioapicindex, pending;
2020 ulong_t iflag;
2021
2022 mutex_enter(&airq_mutex);
2023 irqp = apic_irq_table[irqno];
2024 if (IS_IRQ_FREE(irqp)) {
2025 mutex_exit(&airq_mutex);
2026 return (0);
2027 }
2028
2029 /* check IO-APIC delivery status */
2030 intin = irqp->airq_intin_no;
2031 ioapicindex = irqp->airq_ioapicindex;
2032 mutex_exit(&airq_mutex);
2033
2034 iflag = intr_clear();
2035 lock_set(&apic_ioapic_lock);
2036
2037 pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin) &
2038 AV_PENDING) ? 1 : 0;
2039
2040 lock_clear(&apic_ioapic_lock);
2041 intr_restore(iflag);
2042
2043 return (pending);
2044 }
2045
2046 /*
2047 * This function will mask the interrupt on the I/O APIC
2048 */
2049 static void
apix_intx_set_mask(int irqno)2050 apix_intx_set_mask(int irqno)
2051 {
2052 int intin, ioapixindex, rdt_entry;
2053 ulong_t iflag;
2054 apic_irq_t *irqp;
2055
2056 mutex_enter(&airq_mutex);
2057 irqp = apic_irq_table[irqno];
2058
2059 ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2060
2061 intin = irqp->airq_intin_no;
2062 ioapixindex = irqp->airq_ioapicindex;
2063 mutex_exit(&airq_mutex);
2064
2065 iflag = intr_clear();
2066 lock_set(&apic_ioapic_lock);
2067
2068 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2069
2070 /* clear mask */
2071 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2072 (AV_MASK | rdt_entry));
2073
2074 lock_clear(&apic_ioapic_lock);
2075 intr_restore(iflag);
2076 }
2077
2078 /*
2079 * This function will clear the mask for the interrupt on the I/O APIC
2080 */
2081 static void
apix_intx_clear_mask(int irqno)2082 apix_intx_clear_mask(int irqno)
2083 {
2084 int intin, ioapixindex, rdt_entry;
2085 ulong_t iflag;
2086 apic_irq_t *irqp;
2087
2088 mutex_enter(&airq_mutex);
2089 irqp = apic_irq_table[irqno];
2090
2091 ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2092
2093 intin = irqp->airq_intin_no;
2094 ioapixindex = irqp->airq_ioapicindex;
2095 mutex_exit(&airq_mutex);
2096
2097 iflag = intr_clear();
2098 lock_set(&apic_ioapic_lock);
2099
2100 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2101
2102 /* clear mask */
2103 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2104 ((~AV_MASK) & rdt_entry));
2105
2106 lock_clear(&apic_ioapic_lock);
2107 intr_restore(iflag);
2108 }
2109
2110 /*
2111 * For level-triggered interrupt, mask the IRQ line. Mask means
2112 * new interrupts will not be delivered. The interrupt already
2113 * accepted by a local APIC is not affected
2114 */
2115 void
apix_level_intr_pre_eoi(int irq)2116 apix_level_intr_pre_eoi(int irq)
2117 {
2118 apic_irq_t *irqp = apic_irq_table[irq];
2119 int apic_ix, intin_ix;
2120
2121 if (irqp == NULL)
2122 return;
2123
2124 ASSERT(apic_level_intr[irq] == TRIGGER_MODE_LEVEL);
2125
2126 lock_set(&apic_ioapic_lock);
2127
2128 intin_ix = irqp->airq_intin_no;
2129 apic_ix = irqp->airq_ioapicindex;
2130
2131 if (irqp->airq_cpu != CPU->cpu_id) {
2132 if (!APIX_IS_MASK_RDT(apix_mul_ioapic_method))
2133 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2134 lock_clear(&apic_ioapic_lock);
2135 return;
2136 }
2137
2138 if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) {
2139 /*
2140 * This is a IOxAPIC and there is EOI register:
2141 * Change the vector to reserved unused vector, so that
2142 * the EOI from Local APIC won't clear the Remote IRR for
2143 * this level trigger interrupt. Instead, we'll manually
2144 * clear it in apix_post_hardint() after ISR handling.
2145 */
2146 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2147 (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR);
2148 } else {
2149 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2150 AV_MASK | irqp->airq_rdt_entry);
2151 }
2152
2153 lock_clear(&apic_ioapic_lock);
2154 }
2155
2156 /*
2157 * For level-triggered interrupt, unmask the IRQ line
2158 * or restore the original vector number.
2159 */
2160 void
apix_level_intr_post_dispatch(int irq)2161 apix_level_intr_post_dispatch(int irq)
2162 {
2163 apic_irq_t *irqp = apic_irq_table[irq];
2164 int apic_ix, intin_ix;
2165
2166 if (irqp == NULL)
2167 return;
2168
2169 lock_set(&apic_ioapic_lock);
2170
2171 intin_ix = irqp->airq_intin_no;
2172 apic_ix = irqp->airq_ioapicindex;
2173
2174 if (APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method)) {
2175 /*
2176 * Already sent EOI back to Local APIC.
2177 * Send EOI to IO-APIC
2178 */
2179 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2180 } else {
2181 /* clear the mask or restore the vector */
2182 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2183 irqp->airq_rdt_entry);
2184
2185 /* send EOI to IOxAPIC */
2186 if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC)
2187 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2188 }
2189
2190 lock_clear(&apic_ioapic_lock);
2191 }
2192
2193 static int
apix_intx_get_shared(int irqno)2194 apix_intx_get_shared(int irqno)
2195 {
2196 apic_irq_t *irqp;
2197 int share;
2198
2199 mutex_enter(&airq_mutex);
2200 irqp = apic_irq_table[irqno];
2201 if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
2202 mutex_exit(&airq_mutex);
2203 return (0);
2204 }
2205 share = irqp->airq_share;
2206 mutex_exit(&airq_mutex);
2207
2208 return (share);
2209 }
2210
2211 static void
apix_intx_set_shared(int irqno,int delta)2212 apix_intx_set_shared(int irqno, int delta)
2213 {
2214 apic_irq_t *irqp;
2215
2216 mutex_enter(&airq_mutex);
2217 irqp = apic_irq_table[irqno];
2218 if (IS_IRQ_FREE(irqp)) {
2219 mutex_exit(&airq_mutex);
2220 return;
2221 }
2222 irqp->airq_share += delta;
2223 mutex_exit(&airq_mutex);
2224 }
2225
2226 /*
2227 * Setup IRQ table. Return IRQ no or -1 on failure
2228 */
2229 static int
apix_intx_setup(dev_info_t * dip,int inum,int irqno,struct apic_io_intr * intrp,struct intrspec * ispec,iflag_t * iflagp)2230 apix_intx_setup(dev_info_t *dip, int inum, int irqno,
2231 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *iflagp)
2232 {
2233 int origirq = ispec->intrspec_vec;
2234 int newirq;
2235 short intr_index;
2236 uchar_t ipin, ioapic, ioapicindex;
2237 apic_irq_t *irqp;
2238
2239 UNREFERENCED_1PARAMETER(inum);
2240
2241 if (intrp != NULL) {
2242 intr_index = (short)(intrp - apic_io_intrp);
2243 ioapic = intrp->intr_destid;
2244 ipin = intrp->intr_destintin;
2245
2246 /* Find ioapicindex. If destid was ALL, we will exit with 0. */
2247 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--)
2248 if (apic_io_id[ioapicindex] == ioapic)
2249 break;
2250 ASSERT((ioapic == apic_io_id[ioapicindex]) ||
2251 (ioapic == INTR_ALL_APIC));
2252
2253 /* check whether this intin# has been used by another irqno */
2254 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1)
2255 return (newirq);
2256
2257 } else if (iflagp != NULL) { /* ACPI */
2258 intr_index = ACPI_INDEX;
2259 ioapicindex = acpi_find_ioapic(irqno);
2260 ASSERT(ioapicindex != 0xFF);
2261 ioapic = apic_io_id[ioapicindex];
2262 ipin = irqno - apic_io_vectbase[ioapicindex];
2263
2264 if (apic_irq_table[irqno] &&
2265 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) {
2266 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin &&
2267 apic_irq_table[irqno]->airq_ioapicindex ==
2268 ioapicindex);
2269 return (irqno);
2270 }
2271
2272 } else { /* default configuration */
2273 intr_index = DEFAULT_INDEX;
2274 ioapicindex = 0;
2275 ioapic = apic_io_id[ioapicindex];
2276 ipin = (uchar_t)irqno;
2277 }
2278
2279 /* allocate a new IRQ no */
2280 if ((irqp = apic_irq_table[irqno]) == NULL) {
2281 irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP);
2282 apic_irq_table[irqno] = irqp;
2283 } else {
2284 if (irqp->airq_mps_intr_index != FREE_INDEX) {
2285 newirq = apic_allocate_irq(apic_first_avail_irq);
2286 if (newirq == -1) {
2287 return (-1);
2288 }
2289 irqno = newirq;
2290 irqp = apic_irq_table[irqno];
2291 ASSERT(irqp != NULL);
2292 }
2293 }
2294 apic_max_device_irq = max(irqno, apic_max_device_irq);
2295 apic_min_device_irq = min(irqno, apic_min_device_irq);
2296
2297 irqp->airq_mps_intr_index = intr_index;
2298 irqp->airq_ioapicindex = ioapicindex;
2299 irqp->airq_intin_no = ipin;
2300 irqp->airq_dip = dip;
2301 irqp->airq_origirq = (uchar_t)origirq;
2302 if (iflagp != NULL)
2303 irqp->airq_iflag = *iflagp;
2304 irqp->airq_cpu = IRQ_UNINIT;
2305 irqp->airq_vector = 0;
2306
2307 return (irqno);
2308 }
2309
2310 /*
2311 * Setup IRQ table for non-pci devices. Return IRQ no or -1 on error
2312 */
2313 static int
apix_intx_setup_nonpci(dev_info_t * dip,int inum,int bustype,struct intrspec * ispec)2314 apix_intx_setup_nonpci(dev_info_t *dip, int inum, int bustype,
2315 struct intrspec *ispec)
2316 {
2317 int irqno = ispec->intrspec_vec;
2318 int newirq, i;
2319 iflag_t intr_flag;
2320 ACPI_SUBTABLE_HEADER *hp;
2321 ACPI_MADT_INTERRUPT_OVERRIDE *isop;
2322 struct apic_io_intr *intrp;
2323
2324 if (!apic_enable_acpi || apic_use_acpi_madt_only) {
2325 int busid;
2326
2327 if (bustype == 0)
2328 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA;
2329
2330 /* loop checking BUS_ISA/BUS_EISA */
2331 for (i = 0; i < 2; i++) {
2332 if (((busid = apic_find_bus_id(bustype)) != -1) &&
2333 ((intrp = apic_find_io_intr_w_busid(irqno, busid))
2334 != NULL)) {
2335 return (apix_intx_setup(dip, inum, irqno,
2336 intrp, ispec, NULL));
2337 }
2338 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA;
2339 }
2340
2341 /* fall back to default configuration */
2342 return (-1);
2343 }
2344
2345 /* search iso entries first */
2346 if (acpi_iso_cnt != 0) {
2347 hp = (ACPI_SUBTABLE_HEADER *)acpi_isop;
2348 i = 0;
2349 while (i < acpi_iso_cnt) {
2350 if (hp->Type == ACPI_MADT_TYPE_INTERRUPT_OVERRIDE) {
2351 isop = (ACPI_MADT_INTERRUPT_OVERRIDE *) hp;
2352 if (isop->Bus == 0 &&
2353 isop->SourceIrq == irqno) {
2354 newirq = isop->GlobalIrq;
2355 intr_flag.intr_po = isop->IntiFlags &
2356 ACPI_MADT_POLARITY_MASK;
2357 intr_flag.intr_el = (isop->IntiFlags &
2358 ACPI_MADT_TRIGGER_MASK) >> 2;
2359 intr_flag.bustype = BUS_ISA;
2360
2361 return (apix_intx_setup(dip, inum,
2362 newirq, NULL, ispec, &intr_flag));
2363 }
2364 i++;
2365 }
2366 hp = (ACPI_SUBTABLE_HEADER *)(((char *)hp) +
2367 hp->Length);
2368 }
2369 }
2370 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH;
2371 intr_flag.intr_el = INTR_EL_EDGE;
2372 intr_flag.bustype = BUS_ISA;
2373 return (apix_intx_setup(dip, inum, irqno, NULL, ispec, &intr_flag));
2374 }
2375
2376
2377 /*
2378 * Setup IRQ table for pci devices. Return IRQ no or -1 on error
2379 */
2380 static int
apix_intx_setup_pci(dev_info_t * dip,int inum,int bustype,struct intrspec * ispec)2381 apix_intx_setup_pci(dev_info_t *dip, int inum, int bustype,
2382 struct intrspec *ispec)
2383 {
2384 int busid, devid, pci_irq;
2385 ddi_acc_handle_t cfg_handle;
2386 uchar_t ipin;
2387 iflag_t intr_flag;
2388 struct apic_io_intr *intrp;
2389
2390 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0)
2391 return (-1);
2392
2393 if (busid == 0 && apic_pci_bus_total == 1)
2394 busid = (int)apic_single_pci_busid;
2395
2396 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS)
2397 return (-1);
2398 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA;
2399 pci_config_teardown(&cfg_handle);
2400
2401 if (apic_enable_acpi && !apic_use_acpi_madt_only) { /* ACPI */
2402 if (apic_acpi_translate_pci_irq(dip, busid, devid,
2403 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS)
2404 return (-1);
2405
2406 intr_flag.bustype = (uchar_t)bustype;
2407 return (apix_intx_setup(dip, inum, pci_irq, NULL, ispec,
2408 &intr_flag));
2409 }
2410
2411 /* MP configuration table */
2412 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3);
2413 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) == NULL) {
2414 pci_irq = apic_handle_pci_pci_bridge(dip, devid, ipin, &intrp);
2415 if (pci_irq == -1)
2416 return (-1);
2417 }
2418
2419 return (apix_intx_setup(dip, inum, pci_irq, intrp, ispec, NULL));
2420 }
2421
2422 /*
2423 * Translate and return IRQ no
2424 */
2425 static int
apix_intx_xlate_irq(dev_info_t * dip,int inum,struct intrspec * ispec)2426 apix_intx_xlate_irq(dev_info_t *dip, int inum, struct intrspec *ispec)
2427 {
2428 int newirq, irqno = ispec->intrspec_vec;
2429 int parent_is_pci_or_pciex = 0, child_is_pciex = 0;
2430 int bustype = 0, dev_len;
2431 char dev_type[16];
2432
2433 if (apic_defconf) {
2434 mutex_enter(&airq_mutex);
2435 goto defconf;
2436 }
2437
2438 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) {
2439 mutex_enter(&airq_mutex);
2440 goto nonpci;
2441 }
2442
2443 /*
2444 * use ddi_getlongprop_buf() instead of ddi_prop_lookup_string()
2445 * to avoid extra buffer allocation.
2446 */
2447 dev_len = sizeof (dev_type);
2448 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip),
2449 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
2450 &dev_len) == DDI_PROP_SUCCESS) {
2451 if ((strcmp(dev_type, "pci") == 0) ||
2452 (strcmp(dev_type, "pciex") == 0))
2453 parent_is_pci_or_pciex = 1;
2454 }
2455
2456 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip,
2457 DDI_PROP_DONTPASS, "compatible", (caddr_t)dev_type,
2458 &dev_len) == DDI_PROP_SUCCESS) {
2459 if (strstr(dev_type, "pciex"))
2460 child_is_pciex = 1;
2461 }
2462
2463 mutex_enter(&airq_mutex);
2464
2465 if (parent_is_pci_or_pciex) {
2466 bustype = child_is_pciex ? BUS_PCIE : BUS_PCI;
2467 newirq = apix_intx_setup_pci(dip, inum, bustype, ispec);
2468 if (newirq != -1)
2469 goto done;
2470 bustype = 0;
2471 } else if (strcmp(dev_type, "isa") == 0)
2472 bustype = BUS_ISA;
2473 else if (strcmp(dev_type, "eisa") == 0)
2474 bustype = BUS_EISA;
2475
2476 nonpci:
2477 newirq = apix_intx_setup_nonpci(dip, inum, bustype, ispec);
2478 if (newirq != -1)
2479 goto done;
2480
2481 defconf:
2482 newirq = apix_intx_setup(dip, inum, irqno, NULL, ispec, NULL);
2483 if (newirq == -1) {
2484 mutex_exit(&airq_mutex);
2485 return (-1);
2486 }
2487 done:
2488 ASSERT(apic_irq_table[newirq]);
2489 mutex_exit(&airq_mutex);
2490 return (newirq);
2491 }
2492
2493 static int
apix_intx_alloc_vector(dev_info_t * dip,int inum,struct intrspec * ispec)2494 apix_intx_alloc_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2495 {
2496 int irqno;
2497 apix_vector_t *vecp;
2498
2499 if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2500 return (0);
2501
2502 if ((vecp = apix_alloc_intx(dip, inum, irqno)) == NULL)
2503 return (0);
2504
2505 DDI_INTR_IMPLDBG((CE_CONT, "apix_intx_alloc_vector: dip=0x%p name=%s "
2506 "irqno=0x%x cpuid=%d vector=0x%x\n",
2507 (void *)dip, ddi_driver_name(dip), irqno,
2508 vecp->v_cpuid, vecp->v_vector));
2509
2510 return (1);
2511 }
2512
2513 /*
2514 * Return the vector number if the translated IRQ for this device
2515 * has a vector mapping setup. If no IRQ setup exists or no vector is
2516 * allocated to it then return 0.
2517 */
2518 static apix_vector_t *
apix_intx_xlate_vector(dev_info_t * dip,int inum,struct intrspec * ispec)2519 apix_intx_xlate_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2520 {
2521 int irqno;
2522 apix_vector_t *vecp;
2523
2524 /* get the IRQ number */
2525 if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2526 return (NULL);
2527
2528 /* get the vector number if a vector is allocated to this irqno */
2529 vecp = apix_intx_get_vector(irqno);
2530
2531 return (vecp);
2532 }
2533
2534 /*
2535 * Switch between safe and x2APIC IPI sending method.
2536 * The CPU may power on in xapic mode or x2apic mode. If the CPU needs to send
2537 * an IPI to other CPUs before entering x2APIC mode, it still needs to use the
2538 * xAPIC method. Before sending a StartIPI to the target CPU, psm_send_ipi will
2539 * be changed to apic_common_send_ipi, which detects current local APIC mode and
2540 * use the right method to send an IPI. If some CPUs fail to start up,
2541 * apic_poweron_cnt won't return to zero, so apic_common_send_ipi will always be
2542 * used. psm_send_ipi can't be simply changed back to x2apic_send_ipi if some
2543 * CPUs failed to start up because those failed CPUs may recover itself later at
2544 * unpredictable time.
2545 */
2546 void
apic_switch_ipi_callback(boolean_t enter)2547 apic_switch_ipi_callback(boolean_t enter)
2548 {
2549 ulong_t iflag;
2550 struct psm_ops *pops = psmops;
2551
2552 iflag = intr_clear();
2553 lock_set(&apic_mode_switch_lock);
2554 if (enter) {
2555 ASSERT(apic_poweron_cnt >= 0);
2556 if (apic_poweron_cnt == 0) {
2557 pops->psm_send_ipi = apic_common_send_ipi;
2558 send_dirintf = pops->psm_send_ipi;
2559 pops->psm_send_pir_ipi = apic_common_send_pir_ipi;
2560 psm_send_pir_ipi = pops->psm_send_pir_ipi;
2561 }
2562 apic_poweron_cnt++;
2563 } else {
2564 ASSERT(apic_poweron_cnt > 0);
2565 apic_poweron_cnt--;
2566 if (apic_poweron_cnt == 0) {
2567 pops->psm_send_ipi = x2apic_send_ipi;
2568 send_dirintf = pops->psm_send_ipi;
2569 pops->psm_send_pir_ipi = x2apic_send_pir_ipi;
2570 psm_send_pir_ipi = pops->psm_send_pir_ipi;
2571 }
2572 }
2573 lock_clear(&apic_mode_switch_lock);
2574 intr_restore(iflag);
2575 }
2576
2577 /* stub function */
2578 int
apix_loaded(void)2579 apix_loaded(void)
2580 {
2581 return (apix_is_enabled);
2582 }
2583