17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #ifndef _SYS_VGAREG_H 287c478bd9Sstevel@tonic-gate #define _SYS_VGAREG_H 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #ifdef __cplusplus 317c478bd9Sstevel@tonic-gate extern "C" { 327c478bd9Sstevel@tonic-gate #endif 337c478bd9Sstevel@tonic-gate 349890ff83SToomas Soome #define VGA_REG_ADDR 0x3c0 359890ff83SToomas Soome #define VGA_REG_SIZE 0x20 369890ff83SToomas Soome 379890ff83SToomas Soome #define VGA_MEM_ADDR 0xa0000 389890ff83SToomas Soome #define VGA_MEM_SIZE 0x20000 399890ff83SToomas Soome 40*8e6d016fSToomas Soome #define VGA_TEXT_COLS 80 41*8e6d016fSToomas Soome #define VGA_TEXT_ROWS 25 42*8e6d016fSToomas Soome 437c478bd9Sstevel@tonic-gate /* 447c478bd9Sstevel@tonic-gate * VGA frame buffer hardware definitions. 457c478bd9Sstevel@tonic-gate */ 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate #define VGA8_DEPTH 8 487c478bd9Sstevel@tonic-gate #define VGA8_CMAP_ENTRIES 256 497c478bd9Sstevel@tonic-gate #define VGA_TEXT_CMAP_ENTRIES 64 507c478bd9Sstevel@tonic-gate 517c478bd9Sstevel@tonic-gate /* 527c478bd9Sstevel@tonic-gate * General VGA registers 537c478bd9Sstevel@tonic-gate * These are relative to their register set, which 547c478bd9Sstevel@tonic-gate * the 3c0-3df set. 557c478bd9Sstevel@tonic-gate */ 567c478bd9Sstevel@tonic-gate #define VGA_ATR_AD 0x00 577c478bd9Sstevel@tonic-gate #define VGA_ATR_DATA 0x01 587c478bd9Sstevel@tonic-gate #define VGA_MISC_W 0x02 597c478bd9Sstevel@tonic-gate #define VGA_SEQ_ADR 0x04 607c478bd9Sstevel@tonic-gate #define VGA_SEQ_DATA 0x05 617c478bd9Sstevel@tonic-gate #define VGA_DAC_BASE 0x06 627c478bd9Sstevel@tonic-gate #define VGA_DAC_AD_MK 0x06 637c478bd9Sstevel@tonic-gate #define VGA_DAC_RD_AD 0x07 647c478bd9Sstevel@tonic-gate #define VGA_DAC_STS 0x07 657c478bd9Sstevel@tonic-gate #define VGA_DAC_WR_AD 0x08 667c478bd9Sstevel@tonic-gate #define VGA_DAC_DATA 0x09 677c478bd9Sstevel@tonic-gate #define VGA_MISC_R 0x0c 687c478bd9Sstevel@tonic-gate #define VGA_GRC_ADR 0x0e 697c478bd9Sstevel@tonic-gate #define VGA_GRC_DATA 0x0f 707c478bd9Sstevel@tonic-gate #define VGA_CRTC_ADR 0x14 717c478bd9Sstevel@tonic-gate #define VGA_CRTC_DATA 0x15 727c478bd9Sstevel@tonic-gate #define CGA_STAT 0x1a 737c478bd9Sstevel@tonic-gate 747c478bd9Sstevel@tonic-gate /* 757c478bd9Sstevel@tonic-gate * Attribute controller index bits 767c478bd9Sstevel@tonic-gate */ 777c478bd9Sstevel@tonic-gate #define VGA_ATR_ENB_PLT 0x20 787c478bd9Sstevel@tonic-gate 797c478bd9Sstevel@tonic-gate /* 807c478bd9Sstevel@tonic-gate * Miscellaneous output bits 817c478bd9Sstevel@tonic-gate */ 827c478bd9Sstevel@tonic-gate #define VGA_MISC_IOA_SEL 0x01 837c478bd9Sstevel@tonic-gate #define VGA_MISC_ENB_RAM 0x02 847c478bd9Sstevel@tonic-gate #define VGA_MISC_VCLK 0x0c 857c478bd9Sstevel@tonic-gate #define VGA_MISC_VCLK0 0x00 867c478bd9Sstevel@tonic-gate #define VGA_MISC_VCLK1 0x04 877c478bd9Sstevel@tonic-gate #define VGA_MISC_VCLK2 0x08 887c478bd9Sstevel@tonic-gate #define VGA_MISC_VCLK3 0x0c 897c478bd9Sstevel@tonic-gate #define VGA_MISC_PGSL 0x20 907c478bd9Sstevel@tonic-gate #define VGA_MISC_HSP 0x40 917c478bd9Sstevel@tonic-gate #define VGA_MISC_VSP 0x80 92*8e6d016fSToomas Soome #define VGA_MISC_IS1_VR 0x08 /* Vertical Retrace */ 93*8e6d016fSToomas Soome #define VGA_MISC_IS1_DD 0x01 /* Display Disabled */ 947c478bd9Sstevel@tonic-gate 957c478bd9Sstevel@tonic-gate /* 967c478bd9Sstevel@tonic-gate * CRT Controller registers 977c478bd9Sstevel@tonic-gate */ 987c478bd9Sstevel@tonic-gate #define VGA_CRTC_H_TOTAL 0x00 997c478bd9Sstevel@tonic-gate #define VGA_CRTC_H_D_END 0x01 1007c478bd9Sstevel@tonic-gate #define VGA_CRTC_S_H_BLNK 0x02 1017c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_BLNK 0x03 1027c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_BLNK_PUT_EHB(n) \ 1037c478bd9Sstevel@tonic-gate ((n)&0x1f) 1047c478bd9Sstevel@tonic-gate #define VGA_CRTC_S_H_SY_P 0x04 1057c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_SY_P 0x05 1067c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT 5 1077c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_SY_P_HOR_SKW 0x60 1087c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_SY_P_EHB5 7 1097c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_SY_P_PUT_HOR_SKW(skew) \ 1107c478bd9Sstevel@tonic-gate ((skew)<<VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT) 1117c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_SY_P_PUT_EHB(n) \ 1127c478bd9Sstevel@tonic-gate ((((n)>>5)&1)<<VGA_CRTC_E_H_SY_P_EHB5) 1137c478bd9Sstevel@tonic-gate #define VGA_CRTC_E_H_SY_P_PUT_EHS(n) \ 1147c478bd9Sstevel@tonic-gate ((n)&0x1f) 1157c478bd9Sstevel@tonic-gate #define VGA_CRTC_V_TOTAL 0x06 1167c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG 0x07 1177c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_VT8 0 1187c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_VDE8 1 1197c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_VRS8 2 1207c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_SVB8 3 1217c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_LCM8 4 1227c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_VT9 5 1237c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_VDE9 6 1247c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_VRS9 7 1257c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_PUT_VT(n) \ 1267c478bd9Sstevel@tonic-gate ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VT8) \ 1277c478bd9Sstevel@tonic-gate | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VT9) 1287c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_PUT_VDE(n) \ 1297c478bd9Sstevel@tonic-gate ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VDE8) \ 1307c478bd9Sstevel@tonic-gate | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VDE9) 1317c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_PUT_VRS(n) \ 1327c478bd9Sstevel@tonic-gate ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VRS8) \ 1337c478bd9Sstevel@tonic-gate | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VRS9) 1347c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_PUT_LCM(n) \ 1357c478bd9Sstevel@tonic-gate ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_LCM8) 1367c478bd9Sstevel@tonic-gate #define VGA_CRTC_OVFL_REG_PUT_SVB(n) \ 1377c478bd9Sstevel@tonic-gate ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_SVB8) 1387c478bd9Sstevel@tonic-gate #define VGA_CRTC_P_R_SCAN 0x08 1397c478bd9Sstevel@tonic-gate #define VGA_CRTC_MAX_S_LN 0x09 1407c478bd9Sstevel@tonic-gate #define VGA_CRTC_MAX_S_LN_SVB9 5 1417c478bd9Sstevel@tonic-gate #define VGA_CRTC_MAX_S_LN_LCM9 6 1427c478bd9Sstevel@tonic-gate #define VGA_CRTC_MAX_S_LN_PUT_SVB(n) \ 1437c478bd9Sstevel@tonic-gate ((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_SVB9) 1447c478bd9Sstevel@tonic-gate #define VGA_CRTC_MAX_S_LN_PUT_LCM(n) \ 1457c478bd9Sstevel@tonic-gate ((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_LCM9) 1467c478bd9Sstevel@tonic-gate #define VGA_CRTC_CSSL 0x0a 1477c478bd9Sstevel@tonic-gate #define VGA_CRTC_CESL 0x0b 1487c478bd9Sstevel@tonic-gate #define VGA_CRTC_STAH 0x0c 1497c478bd9Sstevel@tonic-gate #define VGA_CRTC_STAL 0x0d 1507c478bd9Sstevel@tonic-gate #define VGA_CRTC_CLAH 0x0e 1517c478bd9Sstevel@tonic-gate #define VGA_CRTC_CLAL 0x0f 1527c478bd9Sstevel@tonic-gate #define VGA_CRTC_VRS 0x10 1537c478bd9Sstevel@tonic-gate #define VGA_CRTC_VRE 0x11 1547c478bd9Sstevel@tonic-gate #define VGA_CRTC_VRE_LOCK 0x80 1557c478bd9Sstevel@tonic-gate #define VGA_CRTC_VRE_DIS_VINT 0x20 1567c478bd9Sstevel@tonic-gate #define VGA_CRTC_VRE_PUT_VRE(n) \ 1577c478bd9Sstevel@tonic-gate ((n)&0x0f) 1587c478bd9Sstevel@tonic-gate #define VGA_CRTC_VDE 0x12 1597c478bd9Sstevel@tonic-gate #define VGA_CRTC_SCREEN_OFFSET 0x13 1607c478bd9Sstevel@tonic-gate #define VGA_CRTC_ULL 0x14 1617c478bd9Sstevel@tonic-gate #define VGA_CRTC_SVB 0x15 1627c478bd9Sstevel@tonic-gate #define VGA_CRTC_EVB 0x16 1637c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD 0x17 1647c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD_2BK_CGA 0x01 1657c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD_4BK_HGC 0x02 1667c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD_VT_X2 0x04 1677c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD_WRD_MODE 0x08 1687c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD_ADW_16K 0x20 1697c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD_BYTE_MODE 0x40 1707c478bd9Sstevel@tonic-gate #define VGA_CRTC_CRT_MD_NO_RESET 0x80 1717c478bd9Sstevel@tonic-gate #define VGA_CRTC_LCM 0x18 1727c478bd9Sstevel@tonic-gate 1737c478bd9Sstevel@tonic-gate /* 1747c478bd9Sstevel@tonic-gate * Sequencer registers 1757c478bd9Sstevel@tonic-gate */ 1767c478bd9Sstevel@tonic-gate #define VGA_SEQ_RST_SYN 0x00 1777c478bd9Sstevel@tonic-gate #define VGA_SEQ_RST_SYN_ASYNC_RESET 0x00 1787c478bd9Sstevel@tonic-gate #define VGA_SEQ_RST_SYN_NO_ASYNC_RESET 0x01 1797c478bd9Sstevel@tonic-gate #define VGA_SEQ_RST_SYN_SYNC_RESET 0x00 1807c478bd9Sstevel@tonic-gate #define VGA_SEQ_RST_SYN_NO_SYNC_RESET 0x02 1817c478bd9Sstevel@tonic-gate #define VGA_SEQ_CLK_MODE 0x01 1827c478bd9Sstevel@tonic-gate #define VGA_SEQ_CLK_MODE_8DC 0x01 1837c478bd9Sstevel@tonic-gate #define VGA_SEQ_EN_WT_PL 0x02 1847c478bd9Sstevel@tonic-gate #define VGA_SEQ_EN_WT_PL_ALL 0x0f 185*8e6d016fSToomas Soome #define VGA_SEQ_CMS 0x03 /* Char Map Select */ 186*8e6d016fSToomas Soome #define VGA_SEQ_CMS_SAH 0x20 /* Char. A (bit 2) */ 187*8e6d016fSToomas Soome #define VGA_SEQ_CMS_SBH 0x10 /* Char. B (bit 2) */ 188*8e6d016fSToomas Soome #define VGA_SEQ_CMS_SA 0x0C /* Char. A (bit 0+1) */ 189*8e6d016fSToomas Soome #define VGA_SEQ_CMS_SB 0x03 /* Char. B (bit 0+1) */ 1907c478bd9Sstevel@tonic-gate #define VGA_SEQ_MEM_MODE 0x04 1917c478bd9Sstevel@tonic-gate #define VGA_SEQ_MEM_MODE_EXT_MEM 0x02 1927c478bd9Sstevel@tonic-gate #define VGA_SEQ_MEM_MODE_SEQ_MODE 0x04 1937c478bd9Sstevel@tonic-gate #define VGA_SEQ_MEM_MODE_CHN_4M 0x08 1947c478bd9Sstevel@tonic-gate 1957c478bd9Sstevel@tonic-gate /* 1967c478bd9Sstevel@tonic-gate * Graphics Controller 1977c478bd9Sstevel@tonic-gate */ 1987c478bd9Sstevel@tonic-gate #define VGA_GRC_SET_RST_DT 0x00 1997c478bd9Sstevel@tonic-gate #define VGA_GRC_EN_S_R_DT 0x01 2007c478bd9Sstevel@tonic-gate #define VGA_GRC_COLOR_CMP 0x02 2017c478bd9Sstevel@tonic-gate #define VGA_GRC_WT_ROP_RTC 0x03 2027c478bd9Sstevel@tonic-gate #define VGA_GRC_RD_PL_SL 0x04 2037c478bd9Sstevel@tonic-gate #define VGA_GRC_GRP_MODE 0x05 2047c478bd9Sstevel@tonic-gate #define VGA_GRC_GRP_MODE_SHF_MODE_256 0x40 2057c478bd9Sstevel@tonic-gate #define VGA_GRC_MISC_GM 0x06 2067c478bd9Sstevel@tonic-gate #define VGA_GRC_MISC_GM_GRAPH 0x01 2077c478bd9Sstevel@tonic-gate #define VGA_GRC_MISC_GM_MEM_MAP_1 0x04 2087c478bd9Sstevel@tonic-gate #define VGA_GRC_CMP_DNTC 0x07 2097c478bd9Sstevel@tonic-gate #define VGA_GRC_CMP_DNTC_ALL 0x0f 2107c478bd9Sstevel@tonic-gate #define VGA_GRC_BIT_MASK 0x08 2117c478bd9Sstevel@tonic-gate 2127c478bd9Sstevel@tonic-gate /* 2137c478bd9Sstevel@tonic-gate * Attribute controller registers 2147c478bd9Sstevel@tonic-gate */ 215*8e6d016fSToomas Soome #define VGA_ATR_PAS 0x20 /* Palette Address Source */ 216*8e6d016fSToomas Soome #define VGA_ATR_PLT_REG 0x00 /* Palette Register */ 217*8e6d016fSToomas Soome #define VGA_ATR_NUM_PLT 0x10 /* Palette Register count */ 218*8e6d016fSToomas Soome #define VGA_ATR_MODE 0x10 /* Attribute mode control */ 219*8e6d016fSToomas Soome #define VGA_ATR_MODE_GRAPH 0x01 /* Graphics enable */ 220*8e6d016fSToomas Soome #define VGA_ATR_MODE_MONO 0x02 /* Monochrome emulation */ 221*8e6d016fSToomas Soome #define VGA_ATR_MODE_9WIDE 0x04 /* Line Graphics enable */ 222*8e6d016fSToomas Soome #define VGA_ATR_MODE_BLINK 0x08 /* Blink enable */ 223*8e6d016fSToomas Soome #define VGA_ATR_MODE_PPM 0x20 /* Pixel panning mode */ 224*8e6d016fSToomas Soome #define VGA_ATR_MODE_256CLR 0x40 /* 8-bit color enable */ 225*8e6d016fSToomas Soome #define VGA_ATR_MODE_P54S 0x80 /* Palette bits 4-5 select */ 2267c478bd9Sstevel@tonic-gate #define VGA_ATR_BDR_CLR 0x11 2277c478bd9Sstevel@tonic-gate #define VGA_ATR_DISP_PLN 0x12 2287c478bd9Sstevel@tonic-gate #define VGA_ATR_DISP_PLN_ALL 0x0f 2297c478bd9Sstevel@tonic-gate #define VGA_ATR_H_PX_PAN 0x13 2307c478bd9Sstevel@tonic-gate #define VGA_ATR_PX_PADD 0x14 2317c478bd9Sstevel@tonic-gate 2327c478bd9Sstevel@tonic-gate /* 2337c478bd9Sstevel@tonic-gate * Low-memory frame buffer definitions. These are relative to the 2347c478bd9Sstevel@tonic-gate * A0000 register set. 2357c478bd9Sstevel@tonic-gate */ 2367c478bd9Sstevel@tonic-gate #define VGA_MONO_BASE 0x10000 /* Base of monochrome text */ 2377c478bd9Sstevel@tonic-gate #define VGA_COLOR_BASE 0x18000 /* Base of color text */ 2387c478bd9Sstevel@tonic-gate #define VGA_TEXT_SIZE 0x8000 /* Size of text frame buffer */ 2397c478bd9Sstevel@tonic-gate 2407c478bd9Sstevel@tonic-gate #ifdef __cplusplus 2417c478bd9Sstevel@tonic-gate } 2427c478bd9Sstevel@tonic-gate #endif 2437c478bd9Sstevel@tonic-gate 2447c478bd9Sstevel@tonic-gate #endif /* _SYS_VGAREG_H */ 245